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2.7 V to 5.5 V, <100 A, 8-/10-/12-Bit nanoDACs(R) with I2C(R)-Compatible Interface, Tiny SC70 Package
AD5602/AD5612/AD5622
FEATURES
Single 8-, 10-, 12-bit DACs, 2 LSB INL 6-lead SC70 package Micropower operation: 100 A max @ 5 V Power-down to <150 nA @ 3 V 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to 0 V with brownout detection 3 power-down functions I2C-compatible serial interface supports standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz) modes On-chip output buffer amplifier, rail-to-rail operation
FUNCTIONAL BLOCK DIAGRAM
VDD GND
POWER-ON RESET
AD5602/AD5612/AD5622
DAC REGISTER
REF(+) 8-/10-/12-BIT DAC
OUTPUT BUFFER
VOUT
INPUT CONTROL LOGIC
POWER-DOWN CONTROL LOGIC
RESISTOR NETWORK
Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators
ADDR
SCL
SDA
Figure 1.
Table 1. Related Devices
Part No. AD5601/AD5611/AD5621 Description 2.7 V to 5.5 V, <100 A, 8-, 10-, 12-bit nanoDAC with SPI(R) interface in a tiny SC70 package
GENERAL DESCRIPTION
The AD5602/AD5612/AD5622, members of the nanoDAC family, are single 8-, 10-, 12-bit buffered voltage-out DACs that operate from a single 2.7 V to 5.5 V supply, consuming <100 A at 5 V. These DACs come in tiny SC70 packages. Each DAC contains an on-chip precision output amplifier that allows railto-rail output swing to be achieved. The AD5602/AD5612/AD5622 use a 2-wire I2C-compatible serial interface that operates in standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz) modes. The references for AD5602/AD5612/AD5622 are derived from the power supply inputs to give the widest dynamic output range. Each part incorporates a power-on reset circuit that ensures the DAC output powers up to 0 V and remains there until a valid write takes place to the device. The parts contain a power-down feature that reduces the current consumption of the devices to <150 nA at 3 V and provides software-selectable output loads while in power-down mode. The parts are put into power-down mode over the serial interface. The low power consumption of the AD5602/AD5612/AD5622 in normal operation makes them ideally suited for use in portable battery-operated equipment. The typical power consumption is 0.4 mW at 5 V.
PRODUCT HIGHLIGHTS
1. 2. Available in a 6-lead SC70 package. Maximum 100 A power consumption, single-supply operation. These parts operate from a single 2.7 V to 5.5 V supply, typically consuming 0.2 mW at 3 V and 0.4 mW at 5 V, making them ideal for battery-powered applications. The on-chip output buffer amplifier allows the output of the DAC to swing rail-to-rail with a typical slew rate of 0.5 V/s. Reference derived from the power supply. Standard, fast, and high speed mode I2C interface. Designed for very low power consumption. Power-down capability. When powered down, the DAC typically consumes <150 nA at 3 V. Power-on reset and brownout detection.
3.
4. 5. 6. 7. 8.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
05446-001
APPLICATIONS
AD5602/AD5612/AD5622 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 I2C Timing Specifications............................................................ 4 Timing Diagram ........................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Terminology .................................................................................... 14 Theory of Operation ...................................................................... 15 D/A Section................................................................................. 15 Resistor String............................................................................. 15 Output Amplifier........................................................................ 15 Serial Interface ................................................................................ 16 Input Register.............................................................................. 16 Power-On Reset.......................................................................... 17 Power-Down Modes .................................................................. 17 Write Operation.......................................................................... 18 Read Operation........................................................................... 19 High Speed Mode....................................................................... 20 Applications..................................................................................... 21 Choosing a Reference as Power Supply................................... 21 Bipolar Operation....................................................................... 21 Power Supply Bypassing and Grounding................................ 21 Outline Dimensions ....................................................................... 22 Ordering Guide .......................................................................... 23
REVISION HISTORY
3/06--Rev. A to Rev. B Changes to Table 2............................................................................ 3 Updates to Outline Dimensions ................................................... 22 Changes to Ordering Guide .......................................................... 23 8/05--Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 22 6/05--Revision 0: Initial Version
Rev. B | Page 2 of 24
AD5602/AD5612/AD5622 SPECIFICATIONS
VDD = 2.7 V to 5.5 V, RL = 2 k to GND, CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
Parameter STATIC PERFORMANCE Resolution AD5602 AD5612 AD5622 Relative Accuracy 2 AD5602 AD5612 AD5622 Differential Nonlinearity2 Zero Code Error Offset Error Full-Scale Error Gain Error Zero Code Error Drift Gain Temperature Coefficient OUTPUT CHARACTERISTICS 3 Output Voltage Range Output Voltage Settling Time Slew Rate Capacitive Load Stability Output Noise Spectral Density Noise Digital-to-Analog Glitch Impulse Digital Feedthrough DC Output Impedance Short Circuit Current LOGIC INPUTS (SDA, SCL) IIN, Input Current VINL, Input Low Voltage VINH, Input High Voltage CIN, Pin Capacitance VHYST, Input Hysteresis LOGIC OUTPUTS (OPEN DRAIN) VOL, Output Low Voltage Floating-State Leakage Current Floating-State Output Capacitance Min A, B, W, Y Versions 1 Typ Max Unit Bits 8 10 12 0.5 0.5 4 2 6 1 10 10 0.037 LSB LSB LSB LSB LSB LSB mV mV mV % of FSR V/C ppm of FSR/C V s V/s pF pF nV/Hz B, Y versions B, Y versions A version B, Y versions A, W versions Guaranteed monotonic by design All 0s loaded to DAC register All 1s loaded to DAC register Test Conditions/Comments DAC output unloaded
0.5 0.063 0.5 0.0004 5 2 0 6 0.5 470 1000 120 2 5 0.2 0.5 15
VDD 10
Code 1/4 to 3/4 RL = RL = 2 k DAC code = midscale, 10 kHz DAC code = midscale, 0.1 Hz to 10 Hz bandwidth 1 LSB change around major carry
nV-s nV-s mA 1 0.3 x VDD A V V pF V V V A pF
VDD = 3 V/5 V
0.7 x VDD 2 0.1 x VDD 0.4 0.6 1 2
ISINK = 3 mA ISINK = 6 mA
Rev. B | Page 3 of 24
AD5602/AD5612/AD5622
Parameter POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V IDD (All Power-Down Modes) VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V POWER EFFICIENCY IOUT/IDD
1 2
Min 2.7
A, B, W, Y Versions 1 Typ Max 5.5 75 60 0.3 0.15 96 100 90 1 1
Unit V A A A A %
Test Conditions/Comments
DAC active and excluding load current VIH = VDD and VIL = GND VIH = VDD and VIL = GND VIH = VDD and VIL = GND VIH = VDD and VIL = GND ILOAD = 2 mA, VDD = 5 V
Temperature ranges for A, B versions: -40C to +125C, typical at 25C. Linearity calculated using a reduced code range 64 to 4032. 3 Guaranteed by design and characterization, not production tested.
I2C TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 3.4 MHz, unless otherwise noted. 1 Table 3.
Parameter fSCL 3 Conditions Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode Standard mode Fast mode
2
t1
t2
t3
t4
t5
t6
t7
Limit at TMIN, TMAX Min Max 100 400 3.4 1.7 4 0.6 60 120 4.7 1.3 160 320 250 100 10 0 3.45 0 0.9 0 70 0 150 4.7 0.6 160 4 0.6 160 4.7 1.3
Unit KHz KHz MHz MHz s s ns ns s s ns ns ns ns ns s s ns ns s s ns s s ns s s
Description Serial clock frequency
tHIGH, SCL high time
tLOW, SCL low time
tSU;DAT, data setup time
tHD;DAT, data hold time
tSU;STA, set-up time for a repeated start condition
tHD;STA, hold time (repeated) start condition
tBUF, bus free time between a stop and a start condition
Rev. B | Page 4 of 24
AD5602/AD5612/AD5622
Parameter t8 Conditions2 Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Fast mode High speed mode Limit at TMIN, TMAX Min Max 4 0.6 160 1000 300 10 80 20 160 300 300 10 80 20 160 1000 300 10 40 20 80 1000 300 80 160 300 300 40 80 50 10 Unit s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description tSU;STO, setup time for a stop condition
t9
tRDA, rise time of SDA signal
t10
tFDA, fall time of SDA signal
t11
tRCL, rise time of SCL signal
t11A
tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit
10 20
t12
tFCL, fall time of SCL signal
tSP 4
10 20 0 0
Pulse width of spike suppressed
1
See Figure 2. High speed mode timing specification applies to the AD5602-1/AD5612-1/AD5622-1 only. Standard and fast mode timing specifications apply to the AD5602-1/AD5612-1/AD5622-1 and AD5602-2/AD5612-2/AD5622-2. 2 CB refers to the capacitance on the bus line. 3 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior of the part. 4 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode.
TIMING DIAGRAM
t11
SCL
t12
t2 t6 t4 t1 t3 t5 t10
t6
t8 t9
05446-002
SDA
t7
P S S P
Figure 2. 2-Wire Serial Interface Timing Diagram
Rev. B | Page 5 of 24
AD5602/AD5612/AD5622 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 4.
Parameter VDD to GND Digital Input Voltage to GND VOUT to GND Operating Temperature Range Extended Automotive (W, Y Versions) Extended Industrial (A, B Versions) Storage Temperature Range Maximum Junction Temperature SC70 Package JA Thermal Impedance JC Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) ESD Rating -0.3 V to + 7.0 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -40C to +125C -40C to +85C -65C to +160C 150C 332C/W 120C/W 215C 220C 2.0 kV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. B | Page 6 of 24
AD5602/AD5612/AD5622 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADDR 1 SCL 2 SDA 3
4
VDD
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 Mnemonic ADDR SCL SDA VDD GND VOUT Description Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 6). Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input register. Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input register. It is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and VDD should be decoupled to GND. Ground. The ground reference point for all circuitry on the part. Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
Rev. B | Page 7 of 24
05446-003
TOP VIEW (Not to Scale)
AD5602/ AD5612/ AD5622
6
VOUT GND
5
AD5602/AD5612/AD5622 TYPICAL PERFORMANCE CHARACTERISTICS
1.0 0.8 0.6
DNL ERROR (LSB)
0.05 VDD = 5V TA = 25C 0.04 0.03 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04
05446-004
VDD = 5V TA = 25C
0.4
INL ERROR (LSB)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 500 1000 1500 2000 2500 DAC CODE 3000 3500 4000
0
200
400 600 DAC CODE
800
1000
Figure 4. Typical AD5622 Integral Nonlinearity Error
0.15 0.10 0.05
DNL ERROR (LSB)
Figure 7. Typical AD5612 Differential Nonlinearity Error
0.06 VDD = 5V TA = 25C 0.04
VDD = 5V TA = 25C
0 -0.05 -0.10 -0.15
05446-005
INL ERROR (LSB)
0.02
0
-0.02
-0.04
0
500
1000
1500
2000 2500 DAC CODE
3000
3500
4000
0
50
100 150 DAC CODE
200
250
Figure 5. Typical AD5622 Differential Nonlinearity Error
0.25 0.20 0.15 0.10
INL ERROR (LSB)
Figure 8. Typical AD5602 Integral Nonlinearity Error
0.015
VDD = 5V TA = 25C
VDD = 5V TA = 25C
0.010
0.05 0 -0.05 -0.10 -0.15 -0.20
05446-047
DNL ERROR (LSB)
0.005
0
-0.005
-0.010
0
200
400 600 DAC CODE
800
1000
0
50
100 150 DAC CODE
200
250
Figure 6. Typical AD5612 Integral Nonlinearity Error
Figure 9. Typical AD5602 Differential Nonlinearity Error
Rev. B | Page 8 of 24
05446-050
-0.25
-0.015
05446-049
-0.20
-0.06
05446-048
-0.05
AD5602/AD5612/AD5622
1 0 -1 -2 -3 -4 -5 -6
05446-006
0.5
VDD = 5V TA = 25C
TA = 25C 0.4 0.3 DNL ERROR (LSB) MAX DNL 0.2 0.1 0 -0.1 -0.2
05446-009
TUE (LSB)
MIN DNL
-7
0
500
1000
1500
2000 2500 DAC CODE
3000
3500
4000
-0.3 2.7
3.2
3.7
4.2 VDD (V)
4.7
5.2
Figure 10. Typical AD5622 Total Unadjusted Error
0.8 TA = 25C 0.6 0.4 INL ERROR (LSB) INL ERROR (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 2.7 MIN INL MAX INL
Figure 13. AD5622 DNL Error vs. Supply
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2
05446-007
MAX INL = 5V MAX INL = 3V
MIN INL = 5V MIN INL = 3V -20 0 20 40 60 TEMPERATURE (C) 80 100 120
05446-010 05446-011
3.2
3.7
4.2 VDD (V)
4.7
5.2
-0.3 -40
Figure 11. AD5622 INL Error vs. Supply
0 TA = 25C -1 -2 -3 -4 -5 -6 -7
05446-008
Figure 14. AD5622 INL Error vs. Temperature (3 V/5 V Supply)
8
MAX TUE
7 6 5 4 3
MAX TUE = 5V
TUE (LSB)
TUE (LSB)
MAX TUE = 3V
MIN TUE = 5V
MIN TUE
2 1 MIN TUE = 3V 0 -40 -20 0
-8 2.7
3.2
3.7
4.2 VDD (V)
4.7
5.2
20 40 60 TEMPERATURE (C)
80
100
120
Figure 12. AD5622 Total Unadjusted Error vs. Supply
Figure 15. AD5622 Total Unadjusted Error vs. Temperature (3 V/5 V Supply)
Rev. B | Page 9 of 24
AD5602/AD5612/AD5622
0.6 0.5 0.4 MAX DNL = 5V
DNL ERROR (LSB)
1.8 1.6 OFFSET ERROR = 3V 1.4 1.2
ERROR (mV)
0.3 0.2 0.1 0 -0.1 -0.2
05446-012
MAX DNL = 3V
1.0 0.8 0.6
MIN DNL = 5V
OFFSET ERROR = 5V 0.4 0.2
-20
0
20 40 60 TEMPERATURE (C)
80
100
120
-20
0
20 40 60 TEMPERATURE (C)
80
100
120
Figure 16. AD5622 DNL Error vs. Temperature (3 V/5 V Supply)
4 2 0
ERROR (mV)
Figure 19. Offset Error vs. Temperature (3 V/5 V Supply)
0.00025
ZERO CODE ERROR = 3V 0.00020 ZERO CODE ERROR = 5V
ERROR (%FSR)
GAIN ERROR = 3V
-2 -4 FULL-SCALE ERROR = 3V -6
0.00015 GAIN ERROR = 5V 0.00010
0.00005 -8 -10 -40 FULL-SCALE ERROR = 5V
05446-013
-20
0
20 40 60 TEMPERATURE (C)
80
100
120
-20
0
20 40 60 TEMPERATURE (C)
80
100
120
Figure 17. Zero Code/Full-Scale Error vs. Temperature (3 V/5 V Supply)
Figure 20. Gain Error vs. Temperature (3 V/5 V Supply)
1 0 -1 -2 ERROR (mV) -3 -4 -5 -6 -7
05446-014
0.10
ZERO CODE ERROR
0.09
TA = 25C
TA = 25C
0.08 0.07
IDD (A)
0.06 0.05 0.04 0.03
FULL-SCALE ERROR
0.02 0.01
3.2
3.7
4.2 VDD (V)
4.7
5.2
3.2
3.7
4.2 VDD (V)
4.7
5.2
Figure 18. Zero Code/Full-Scale Error vs. Supply Voltage
Figure 21. Supply Current vs. Supply Voltage
Rev. B | Page 10 of 24
05446-017
-8 2.7
0 2.7
05446-016
0 -40
05446-015
-0.3 -40
MIN DNL = 3V
0 -40
AD5602/AD5612/AD5622
12
0.10 0.09 0.08 0.07 0.06 VDD = 5V
10
VDD = 3V VIH = VDD VIL = GND TA = 25C
VDD = 5V VIH = VDD VIL = GND TA = 25C
8
FREQUENCY
6
IDD (A)
0.05 0.04 0.03 0.02
VDD = 3V
4
2
0.05456 0.05527
0.05599
0.05671
0.05742
0.05814
05446-018
-20
0
20 40 60 80 TEMPERATURE (C)
100
120
140
IDD (A)
Figure 22. Supply Current vs. Temperature (3 V/5 V Supply)
70 VDD = 5V 60 50 VDD = 3V 40 30 20 10 0 TA = 25C
Figure 25. IDD Histogram (3 V/5 V Supply)
0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 DAC LOADED WITH FULL-SCALE CODE VDD = 5V TA = 25C DAC LOADED WITH ZERO-SCALE CODE
IDD (A)
05446-019
VO (V)
05446-021
0 -40
0.05885 0.06648 0.06710 0.06773 0.06835 0.06897 0.06960 0.07022 0.07084 0.07147 0.07209 0.07271 0.07334 0 I (mA) 5 10 VDD VOUT = 70mV
0.01
0
0
2000
4000
6000
8000 10000 12000 14000 16000 DAC CODE
-15
-10
-5
15
Figure 23. Supply Current vs. Digital Input Code
Figure 26. Sink and Source Capability
900 800 700 600 SCL/SDA DECREASING VDD = 5V SCL/SDA INCREASING VDD = 3V SCL/SDA INCREASING VDD = 5V
VDD = 5V TA = 25C
IDD (A)
500 400 300 200 100 0 0.5 1.0 1.5
CH1
SCL/SDA DECREASING VDD = 3V
2.0 2.5 3.0 VLOGIC (V)
3.5
4.0
4.5
5.0
05446-020
0
CH2 CH1 = 1V/DIV, CH2 = 20mV/DIV, TIME BASE = 20s/DIV
Figure 24. Supply Current vs. SCL/SDA Logic Voltage
Figure 27. Power-On Reset to 0 V
Rev. B | Page 11 of 24
05446-038
05446-037
AD5602/AD5612/AD5622
CH1 VDD
VDD = 5V TA = 25C
VDD = 5V TA = 25C
CH1
CH2
CH2
VOUT
05446-039 05446-042
CH1 = 5V/DIV, CH2 = 1V/DIV, TIME BASE = 2s/DIV
CH1 = 1V/DIV, CH2 = 3V/DIV, TIME BASE = 50s/DIV
Figure 28. Exiting Power-Down Mode
2.458 2.456
CH1 VDD = 5V TA = 25C AMPLITUDE (V)
Figure 31. VOUT vs. VDD
2.454 2.452 2.450 2.448 2.446 2.444 2.442 2.440
05446-040
CH2 CH1 = 5V/DIV, CH2 = 1V/DIV, TIME BASE = 2s/DIV
2.438 2.436 0 100
VDD = 5V TA = 25C LOAD = 2k AND 220pF CODE 0x800 TO 0x7FF 10ns/SAMPLE NUMBER 200 300 SAMPLE NUMBER 400 500
05446-043
Figure 29. Full-Scale Settling Time
2.4278 2.4276
CH1 VDD = 5V TA = 25C
Figure 32. Digital-to-Analog Glitch Impulse
2.4274
AMPLITUDE (V)
VDD = 5V TA = 25C LOAD = 2k AND 220pF 10ns/SAMPLE NUMBER
2.4272 2.4270 2.4268 2.4266 2.4264 2.4262
CH2
05446-041
CH1 = 5V/DIV, CH2 = 1V/DIV, TIME BASE = 2s/DIV
0
100
200 300 SAMPLE NUMBER
400
500
Figure 30. Half-Scale Settling Time
Figure 33. Digital Feedthrough
Rev. B | Page 12 of 24
05446-044
2.4260
AD5602/AD5612/AD5622
OUTPUT NOISE SPECTRAL DENSITY (nV/ Hz)
VDD = 5V TA = 25C MIDSCALE LOADED
700 600 500 400
VDD = 5V TA = 25C UNLOADED OUTPUT
CH1
ZERO SCALE 300 200 100
05446-046
MIDSCALE FULL SCALE
05446-045
CH1 = 5V/DIV
0 100
1000 10000 FREQUENCY (Hz)
100000
Figure 34. 1/f Noise, 0.1 Hz to 10 Hz Bandwidth
Figure 35. Output Noise Spectral Density
Rev. B | Page 13 of 24
AD5602/AD5612/AD5622 TERMINOLOGY
Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 4. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 5. Zero Code Error Zero-code error is due to a combination of the offset errors in the DAC and output amplifier; it is a measure of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5602/AD5612/AD5622 because the output of the DAC cannot go below 0 V. Zero-code error is expressed in mV. A plot of zero-code error vs. temperature can be seen in Figure 17. Full-Scale Error Full-scale error is a measure of the output error when full-scale code (0xFFFF) is loaded to the DAC register; it is expressed in percent of full-scale range. Ideally, the output should be VDD - 1 LSB. A plot of full-scale error vs. temperature can be seen in Figure 17. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed as a percent of the full-scale range. Total Unadjusted Error (TUE) Total unadjusted error is a measure of the output error taking all the various errors into account. A typical TUE vs. code plot can be seen in Figure 10. Zero Code Error Drift Zero code error drift is a measure of the change in zero code error with a change in temperature. It is expressed in V/C. Gain Error Drift Gain error drift is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/C. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000) (see Figure 32). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s, and vice versa (see Figure 33).
Rev. B | Page 14 of 24
AD5602/AD5612/AD5622 THEORY OF OPERATION
D/A SECTION
The AD5602/AD5612/AD5622 DACs are fabricated on a CMOS process. The architecture consists of a string DACs followed by an output buffer amplifier. Figure 36 shows a block diagram of the DAC architecture.
VDD REF (+) DAC REGISTER RESISTOR NETWORK REF (-) OUTPUT AMPLIFIER VOUT
R
R
R
TO OUTPUT AMPLIFIER
GND
05446-022
Figure 36. DAC Architecture
R
D VOUT = V DD x n 2
where: D is the decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 255 (AD5602), 0 to 1023 (AD5612), or 0 to 4095 (AD5622). n is the bit resolution of the DAC.
Figure 37. Resistor String Structure
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0 V to VDD. It is capable of driving a load of 2 k in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 26. The slew rate is 0.5 V/s with a halfscale settling time of 5 s with the output unloaded.
RESISTOR STRING
The resistor string structure is shown in Figure 37. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.
Rev. B | Page 15 of 24
05446-023
Since the input coding to the DAC is straight binary, the ideal output voltage is given by
R
AD5602/AD5612/AD5622 SERIAL INTERFACE
The AD5602/AD5612/AD5622 have 2-wire I2C-compatible serial interfaces (refer to I2C-Bus Specification, Version 2.1, January 2000, available from Philips Semiconductor). The AD5602/AD5612/AD5622 can be connected to an I2C bus as a slave device, under the control of a master device. See Figure 2 for a timing diagram of a typical write sequence. The AD5602/AD5612/AD5622 support standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz) data transfer modes. Support is not provided for 10-bit addressing and general call addressing. The AD5602/AD5612/AD5622 each have a 7-bit slave address. The five MSBs are 00011 and the two LSBs are determined by the state of the ADDR pin. The facility to make hardwired changes to ADDR allows the user to incorporate up to three of these devices on one bus as outlined in Table 6. The 2-wire serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address. The slave address corresponding to the transmitted address responds by pulling SDA low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL.
DB15 (MSB) 0 0 PD1 PD0 D7 D6 D5 D4 D3 D2 D1 D0 X X DB0 (LSB) X X
05446-024
3.
When all data bits have been read or written, a stop condition is established. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse, and then high during the 10th clock pulse to establish a stop condition. Table 6. Device Address Selection
A1 1 0 1 A0 1 0 0
ADDR GND VDD NC (No Connection)
INPUT REGISTER
The input register is 16 bits wide. Figure 38, Figure 39, and Figure 40 illustrate the contents of the input register for each part. Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCL. The timing diagram for this operation is shown in Figure 2. The 16-bit word consists of four control bits followed by 8, 10, or 12 bits of data, depending on the device type. MSB (DB15) is loaded first. The first two bits are reserved bits that must be set to zero, the next two bits are control bits that select the mode of operation of the device (normal mode or any one of three power-down modes). See the Power-Down Modes section for a complete description. The remaining bits are left-justified DAC data bits, starting with the MSB and ending with the LSB.
2.
DATA BITS
Figure 38. AD5602 Input Register Contents
DB15 (MSB) 0 0 PD1 PD0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DB0 (LSB) X X
05446-025
DATA BITS
Figure 39. AD5612 Input Register Contents
DB15 (MSB) 0 0 PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 DB0 (LSB) D1 D0
05446-026
DATA BITS
Figure 40. AD5622 Input Register Contents
Rev. B | Page 16 of 24
AD5602/AD5612/AD5622
POWER-ON RESET
The AD5602/AD5612/AD5622 each contain a power-on reset circuit that controls the output voltage during power-up. The DAC register is filled with zeros and the output voltage is 0 V where it remains until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the DAC output while it is in the process of powering up. When both bits are set to 0, the part works normally with its usual power consumption of 100 A maximum at 5 V. However, for the three power-down modes, the supply current falls to <150 nA (at 3 V). Not only does the supply current fall, but the output stage is internally switched from the output of the amplifier to a resistor network of known values. This gives the advantage of knowing the output impedance of the part while the part is in power-down mode. There are three different options. The output is connected internally to GND through a 1 k resistor, a 100 k resistor, or it is left open-circuited (three-state). Figure 41 shows the output stage.
POWER-DOWN MODES
The AD5602/AD5612/AD5622 each contain four separate modes of operation. These modes are software-programmable by setting Bit PD1 and Bit PD0 in the control register. Table 7 shows how the state of the bits corresponds to the mode of operation of the device. Table 7. Modes of Operation
PD1 0 0 1 1 PD0 0 1 0 1 Operating Mode Normal operation Power-down (1 k load to GND) Power-down (100 k load to GND) Power-down (Three-state output)
RESISTOR STRING DAC
AMPLIFIER
VOUT
POWER-DOWN CIRCUITRY
Figure 41. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other associated linear circuitry are all shut down when the powerdown mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 14 s for VDD = 5 V and 17 s for VDD = 3 V (see Figure 28).
Rev. B | Page 17 of 24
05446-027
RESISTOR NETWORK
AD5602/AD5612/AD5622
WRITE OPERATION
When writing to the AD5602/AD5612/AD5622, the user must begin with a start command followed by an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low.
1 SCL 9
Two bytes of data are then written to the DAC, the most significant byte followed by the least significant byte as shown in Figure 39; both of these data bytes are acknowledged by the AD5602/AD5612/AD5622. A stop condition follows. The write operations for the three DACs are shown in Figure 42, Figure 43, and Figure 44.
1 9
SDA START BY MASTER
0
0
0
1
1
A1
A0
R/W ACK. BY AD5602
0
0
PD1
PD0
D7
D6
D5
D4 ACK. BY AD5602
FRAME 1 SERIAL BUS ADDRESS BYTE 9 SCL (CONTINUED) 1
FRAME 2 MOST SIGNIFICANT DATA BYTE 9
SDA (CONTINUED)
D3
D2
D1
D0
X
X
X
X
05446-028 05446-030 05446-029
ACK. BY AD5602 FRAME 3 LEAST SIGNIFICANT DATA BYTE
STOP BY MASTER
Figure 42. AD5602 Write Sequence
1 SCL 9 1 9
SDA START BY MASTER
0
0
0
1
1
A1
A0
R/W ACK. BY AD5612
0
0
PD1
PD0
D9
D8
D7
D6 ACK. BY AD5612
FRAME 1 SERIAL BUS ADDRESS BYTE 9 SCL (CONTINUED) 1
FRAME 2 MOST SIGNIFICANT DATA BYTE 9
SDA (CONTINUED)
D5
D4
D3
D2
D1
D0
X
X ACK. BY AD5612 STOP BY MASTER
FRAME 3 LEAST SIGNIFICANT DATA BYTE
Figure 43. AD5612 Write Sequence
1 SCL 9 1 9
SDA START BY MASTER
0
0
0
1
1
A1
A0
R/W ACK. BY AD5622
0
0
PD1
PD0
D11
D10
D9
D8 ACK. BY AD5622
FRAME 1 SERIAL BUS ADDRESS BYTE 9 SCL (CONTINUED) 1
FRAME 2 MOST SIGNIFICANT DATA BYTE 9
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY AD5622 STOP BY MASTER
FRAME 3 LEAST SIGNIFICANT DATA BYTE
Figure 44. AD5622 Write Sequence
Rev. B | Page 18 of 24
AD5602/AD5612/AD5622
READ OPERATION
When reading data back from the AD5602/AD5612/AD5622, the user begins with a start command followed by an address byte (R/W = 1), after which the DAC acknowledges that it is
1 SCL 9
prepared to transmit data by pulling SDA low. Two bytes of data are then read from the DAC, which are both acknowledged by the master as shown in Figure 45, Figure 46, and Figure 47. A stop condition follows.
1 9
SDA START BY MASTER
0
0
0
1
1
A1
A0
R/W ACK. BY AD5602
PD1
PD0
D7
D6
D5
D4
D3
D2 ACK. BY MASTER
FRAME 1 SERIAL BUS ADDRESS BYTE 1 SCL (CONTINUED)
FRAME 2 MOST SIGNIFICANT DATA BYTE FROM AD5602 9
SDA (CONTINUED)
D1
D0
0
0
0
0
0
0
05446-031 05446-033 05446-032
NO ACK. BY STOP BY MASTER MASTER FRAME 3 LEAST SIGNIFICANT DATA BYTE FROM AD5602
Figure 45. AD5602 Read Sequence
1 SCL 9 1 9
SDA START BY MASTER
0
0
0
1
1
A1
A0
R/W ACK. BY AD5612
PD1
PD0
D9
D8
D7
D6
D5
D4
FRAME 1 SERIAL BUS ADDRESS BYTE 1 SCL (CONTINUED)
ACK. BY MASTER FRAME 2 MOST SIGNIFICANT DATA BYTE FROM AD5612 9
SDA (CONTINUED)
D3
D2
D1
D0
0
0
0
0 NO ACK. BY STOP BY MASTER MASTER
FRAME 3 LEAST SIGNIFICANT DATA BYTE FROM AD5612
Figure 46. AD5612 Read Sequence
1 SCL 9 1 9
SDA START BY MASTER
0
0
0
1
1
A1
A0
R/W ACK. BY AD5622
PD1
PD0
D11
D10
D9
D8
D7
D6
FRAME 1 SERIAL BUS ADDRESS BYTE 1 SCL (CONTINUED)
ACK. BY MASTER FRAME 2 MOST SIGNIFICANT DATA BYTE FROM AD5622 9
SDA (CONTINUED)
D5
D4
D3
D2
D1
D0
0
0 NO ACK. BY STOP BY MASTER MASTER
FRAME 3 LEAST SIGNIFICANT DATA BYTE FROM AD5622
Figure 47. AD5622 Read Sequence
Rev. B | Page 19 of 24
AD5602/AD5612/AD5622
HIGH SPEED MODE
High speed mode communication commences after the master addresses all devices connected to the bus with the Master Code 00001XXX to indicate that a high speed mode transfer is to begin. No device connected to the bus is permitted to acknowledge the high speed master code, therefore, the code is
1 SCL FAST MODE 9
followed by a no acknowledge. The master must then issue a repeated start followed by the device address. The selected device then acknowledges its address. All devices continue to operate in high speed mode until the master issues a stop condition. When the stop condition is issued, the devices return to standard/fast mode.
1 HIGH-SPEED MODE 9
SDA START BY MASTER
0
0
0
0
1
X
X
X NACK. SR
0
0
0
1
1
A1
A0
R/W
05446-034
ACK. BY AD56x2 SERIAL BUS ADDRESS BYTE
HS-MODE MASTER CODE
Figure 48. Placing the AD5602/AD5612/AD5622 into High Speed Mode
Rev. B | Page 20 of 24
AD5602/AD5612/AD5622 APPLICATIONS
CHOOSING A REFERENCE AS POWER SUPPLY
The AD5602/AD5612/AD5622 come in tiny SC70 packages with less than 100 A supply current, thereby making the choice of reference dependent upon the application requirement. For space-saving applications, the ADR425 is available in an SC70 package with excellent drift at 3ppm/C. It also provides very good noise performance at 3.4 V p-p in the 0.1 Hz to 10 Hz range. Because the supply current required by the AD5602/AD5612/ AD5622 DACs is extremely low, they are ideal for low supply applications. The ADR293 voltage reference is recommended in this case. This requires 15 A of quiescent current and can therefore drive multiple DACs in the one system, if required.
7V
With VDD = 5 V, R1 = R2 = 10 k
10 x D VO = -5 V n 2
This is an output voltage range of 5 V with 0x000 corresponding to a -5 V output, and 0xFFF corresponding to a +5 V output.
R2 10k R1 10k +5V
+5V
AD820/ OP295 VDD 10F 0.1F
5V OUT
AD5602/ AD5612/ AD5622
VOUT -5V
05446-036
SDA SCL
ADR425
5V
Figure 50. Bipolar Operation with the AD5602/AD5612/AD5622
POWER SUPPLY BYPASSING AND GROUNDING
AD5602/ AD5612/ AD5622
VOUT = 0V TO 5V
05446-035
SCL SDA
Figure 49. ADR425 as Power Supply
Examples of some recommended precision references for use as supplies to the AD5602/AD5612/AD5622 are shown in Table 8. Table 8. Recommended Precision References
Part No. ADR435 ADR425 ADR02 ADR395 Initial Accuracy (mV max) 6 6 5 6 Temperature Drift (ppm/C max) 3 3 3 25 0.1 Hz to 10 Hz Noise (V p-p typ) 3.4 3.4 15 5
When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5602/ AD5612/AD5622 should have separate analog and digital sections, each having its own area of the board. If the AD5602, AD5612, or AD5622 is in a system where other devices require an AGND to DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5602/AD5612/AD5622. The power supply to the AD5602/AD5612/AD5622 should be bypassed with 10 F and 0.1 F capacitors. The capacitors should be physically as close as possible to the device with the 0.1 F capacitor ideally right up against the device. The 10 F capacitors are the tantalum bead type. It is important that the 0.1 F capacitor has low effective series resistance (ESR) and effective series inductance (ESI), such as common ceramic types. This 0.1 F capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, the microstrip technique is not always possible with a 2-layer board.
BIPOLAR OPERATION
The AD5602/AD5612/AD5622 have been designed for singlesupply operation, but a bipolar output range is also possible using the circuit in Figure 50. The circuit in Figure 50 gives an output voltage range of 5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. The output voltage for any input code can be calculated as
D R1 + R2 R2 VO = VDD x n x - VDD x 2 R1 R1
where: D represents the input code in decimal. n represents the bit resolution of the DAC.
Rev. B | Page 21 of 24
AD5602/AD5612/AD5622 OUTLINE DIMENSIONS
2.20 2.00 1.80 2.40 2.10 1.80 1.35 1.25 1.15 PIN 1 1.30 BSC 1.00 0.90 0.70 0.65 BSC 1.10 0.80 0.40 0.10 0.46 0.36 0.26
6 1 5 2 4 3
0.10 MAX
0.30 0.15 0.10 COPLANARITY
SEATING PLANE
0.22 0.08
COMPLIANT TO JEDEC STANDARDS MO-203-AB
Figure 51. 6-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-6) Dimensions shown in millimeters
Rev. B | Page 22 of 24
AD5602/AD5612/AD5622
ORDERING GUIDE
Model AD5602YKSZ-1500RL71 AD5602YKSZ-1REEL71 AD5602BKSZ-2500RL71 AD5602BKSZ-2REEL71 AD5602YKSZ-2500RL71 AD5602YKSZ-2REEL71 AD5612YKSZ-1500RL71 AD5612YKSZ-1REEL71 AD5612BKSZ-2500RL71 AD5612BKSZ-2REEL71 AD5612AKSZ-2500RL71 AD5612AKSZ-2REEL71 AD5612YKSZ-2500RL71 AD5612YKSZ-2REEL71 AD5622YKSZ-1500RL71 AD5622YKSZ-1REEL71 AD5622BKSZ-2500RL71 AD5622BKSZ-2REEL71 AD5622YKSZ-2500RL71 AD5622YKSZ-2REEL71 AD5622WKSZ-1500RL71 AD5622WKSZ-1REEL71 AD5622AKSZ-2500RL71 AD5622AKSZ-2REEL71
1
INL (max) 0.5 LSB 0.5 LSB 0.5 LSB 0.5 LSB 0.5 LSB 0.5 LSB 0.5 LSB 0.5 LSB 0.5 LSB 0.5 LSB 4 LSB 4 LSB 0.5 LSB 0.5 LSB 2 LSB 2 LSB 2 LSB 2 LSB 2 LSB 2 LSB 6 LSB 6 LSB 6 LSB 6 LSB
I2C Interface Modes Supported Standard, fast and high speed Standard, fast and high speed Standard, fast Standard, fast Standard, fast Standard, fast Standard, fast, and high speed Standard, fast, and high speed Standard, fast Standard, fast Standard, fast Standard, fast Standard, fast Standard, fast Standard, fast, and high speed Standard, fast, and high speed Standard, fast Standard, fast Standard, fast Standard, fast Standard, fast, and high speed Standard, fast, and high speed Standard, fast Standard, fast
Temperature Range -40C to +125C -40C to +125C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +85C -40C to +85C
Power Supply Range 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V 2.7 V to 5.5 V
Package Option KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6
Package Description 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70 6-Lead SC70
Branding D5W D5W D5X D5X D5Y D5Y D5T D5T D5U D5U D60 D60 D5S D5S D5M D5M D5N D5N D5P D5P D5Q D5Q D5R D5R
Z = Pb-free part.
Rev. B | Page 23 of 24
AD5602/AD5612/AD5622
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05446-0-3/06(B)
Rev. B | Page 24 of 24

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