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Preliminary Data Sheet July 2000
LU5X34F Quad Gigabit Ethernet Transceiver
Overview
The LU5X34F is a low-cost, low-power quad transceiver. It is used for data transmission over fiber or coaxial media in conformance with IEEE * 802.3z Gigabit Ethernet specification and Fibre Channel ANSI X3T11 at 1.0 Gbits/s and 1.25 Gbits/s. Each of the four transceivers independently provides complete serialize/deserialize (SERDES) and transmit and receive functions. The device is available in a 217-pin PBGA package. The transmitter section accepts TTL compatible data at the 10-bit parallel input port. The parallel input data is latched on the rising edge of TXCLKx. It also accepts the low-speed, TTL compatible system clock, REFCLK, and uses this clock to synthesize the internal high-speed serial bit clock. The serialized data is then available at the differential PECL outputs, terminated in 50 or 75 to drive either an optical transmitter or coaxial media. The receive section receives high-speed serial data at its differential PECL input port. This data is fed to the digital clock recovery section, which generates a recovered clock and retimes the data. The retimed data is deserialized and presented as 10-bit parallel data on the output port. A divided-down version of the recovered clock, synchronous with parallel data bytes, is also available as a TTL compatible output. The receive section recognizes the comma character and aligns the comma-containing byte on the word boundary, when ENCDET = 1.
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100 MHz--125 MHz differential or single-ended reference clock. 10-bit parallel, TTL-compatible I/O interface. 8-bit/10-bit encoded data. High-speed comma character recognition (K28.1, K28.5, K28.7) for latency-sensitive applications and alignment to word boundary. Two 50 MHz--62.5 MHz receive-byte clocks. Single analog PLL design requires no external components for the frequency synthesizer. Novel digital data lock in receiver avoids the need for multiple analog PLLs. Expandable beyond four serializer/deserializers. PECL high-speed interface I/O for use with optical transceiver or coaxial copper media. Requires one external resistor for PECL output reference-level definition. Low-power digital CMOS technology. Less than 2 W total power dissipation per quad transceiver. 3.3 V 5% power supply. 0 C--70 C ambient temperature. Stand-alone transceiver product. Transceiver macrocell template. Available in 217-pin PBGA package.
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Features
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Designed to operate in Ethernet, fibre channel, Firewire , or backplane applications. Operationally compliant to IEEE 802.3z Gigabit Ethernet specification. Operationally compliant to Fibre Channel ANSI X3T11. Provides FC-0 services at 1.0 Gbits/s-- 1.25 Gbits/s (10-bit encoded data rate).
* IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. ANSI is a registered trademark of American National Standards Institute. FireWire is a registered trademark of Apple Computer, Inc.
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LU5X34F Quad Gigabit Ethernet Transceiver
Preliminary Data Sheet July 2000
Table of Contents
Contents Page Table Page
Overview ....................................................................1 Features.....................................................................1 Functional Description ...............................................3 Transmitter Section .................................................3 Receiver Section .....................................................3 Lock to Reference ...................................................3 Byte Alignment ........................................................4 Parallel Output Port.................................................4 Loopback Mode Operation......................................4 Powerup Sequence.................................................5 Device Reset...........................................................5 Sleep Mode .............................................................5 Block Diagrams .......................................................6 Block Diagrams (continued) ....................................7 Input/Output Information ............................................8 Electrical Specifications ...........................................14 Transmitter ............................................................14 Receiver ................................................................14 Receiver (continued) .............................................15 Timing Characteristics .............................................16 Serial Timing .........................................................16 Receiver Section Timing .......................................17 Receiver Port Timing.............................................17 Transmitter Section Timing ...................................18 Application Section ..................................................19 Test Modes ..............................................................22 Outline Diagram .......................................................24 217-pin PBGA .......................................................24 Ordering Information ................................................25
Table 1. Receive Circuit Operating Modes ............. 3 Table 2. Definition of Bit Transmission/Reception Order .................................................................... 4 Table 3a. Pinout--Channel A I/O............................9 Table 3b. Pinout--Channel B I/O.......................... 10 Table 3c. Pinout--Channel C I/O.......................... 11 Table 3d. Pinout--Channel D I/O ......................... 12 Table 3e. Pinout--Common I/O ............................ 13 Table 3f. Pinout--Power I/O ................................. 13 Table 4. Reference Clock Specifications (REFCLK and REFCLKN) .................................. 14 Table 5. PLL Specifications .................................. 14 Table 6. Output Jitter at 1.0 Gbit/s--1.25 Gbits/s Data Rate ........................................................... 14 Table 7. Input Data Rate ....................................... 14 Table 8. Data Lock Characteristics ....................... 14 Table 9. Power Dissipation ................................... 15 Table 10. dc Electrical Specifications ................... 15 Table 11. Absolute Maximum Ratings .................. 15 Table 12. Serial Output Timing Levels .................. 16 Table 13. Serial Input Interface Timing ................ 16 Table 14. Receiver Parallel Port Timing ............... 17 Table 15. Transmitter Timing at Parallel Interface 18 Table 16. External Resistor Value vs. Differential Output Level Viewing ......................................... 20 Table 17. External Resistor Value vs. Differential Output Level Viewing ......................................... 21 Table 18. Test Modes ........................................... 22
Figure
Page
Figure 1. LU5X34F Quad Gigabit Ethernet Transceiver Block Diagram ........................................................ 6 Figure 2. LU5X34F Single-Channel Transceiver Functional Diagram ........................................................ 7 Figure 3. Pin Designations (Top View) ..................... 8 Figure 4. Serial Interface Timing............................. 16 Figure 5. Receiver Section Timing .......................... 17 Figure 6. Receiver Port Timing ............................... 17 Figure 7. Parallel Interface Transmit Timing ........... 18 Figure 8. Reference Clock Connections with SingleEnded and Differential Sources............................ 19 Figure 9. Typical Termination for a Single-Channel, High-Speed Serial Transmit-and-Receive Port in a 50 Backplane Application ................................. 20 Figure 10. Typical Termination for a Single-Channel, High-Speed Serial Transmit Port Interfacing a 5 V GBIC Transceiver ................................................. 21
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Lucent Technologies Inc.
Preliminary Data Sheet July 2000
LU5X34F Quad Gigabit Ethernet Transceiver
Receiver Section
Each of the quad receiver circuits recovers clock from and retimes the serial input data. The data is input to the receiver on differential PECL buffers. External termination resistors are supplied by the user in accordance with ANSI standard, X3T11. The serial differential inputs, HDINP and HDINN, are ac-coupled to the device and internally biased to the PECL input common-mode range center. See Figure 9 for the typical application and termination of the transmission lines. The receiver data-retiming circuit uses a digital timing recovery loop that compares the phase of the input data to multiple phases of the on-device VCO in the transmit section. One of the phases is chosen to retime the receive data. A digital low-pass filter is used in the timing recovery loop to reject jitter from the data input. A novel phase interpolation circuit permits the retiming clock's phase to be stepped with fine resolution for precise alignment of the sampling clock within the data eye. Use of this digital data locking scheme for each receiver advantageously avoids the use of multiple analog phase-lock loops on-device that can potentially injection lock to one another. Additionally, the digital data locking loop maintains precise loop dynamics, hence, the jitter transfer function is process and temperature independent.
Functional Description
The LU5X34F transceiver provides for data transmission over fiber or coaxial media at 1.0 Gbits/s to 1.25 Gbits/s. The block diagram of the quad transceiver is shown in Figure 1 and the four-channel application pinout for the 217-pin PBGA package is given in Figure 3 and Table 3.
Transmitter Section
The transmitter accepts 8b/10b encoded bits in 10-bit parallel form and converts to serial format for up to 1.25 Gbits/s transmission. The serial nonreturn to zero (NRZ) bits are then shifted out of the device at a maximum rate of 1.25 Gbits/s. Internally, the device uses two parallel shift registers that operate at half rate (i.e., a maximum of 625 MHz) for reduced power consumption. The two shift registers drive the PECL output buffer in an interleaved manner to construct the 1.25 Gbits/s output data stream. The typical transmit-and-receive, high-speed I/O interfacing for a single-channel backplane application is shown in Figure 9. The transmit shift register and other circuits are driven with clocks generated from a 500 MHz--625 MHz internal clock. This internal clock is sourced from a voltagecontrolled oscillator (VCO) that is locked to the external reference of 100 MHz--125 MHz. The internal transmit phase- lock loop multiplies the frequency of the input reference clock by a factor of 5, and controls the transmit jitter bandwidth with appropriate design of the jitter transfer function. The transmit phase-lock loop generates multiple clock phases that are all used by each of the four receiver circuits. The clock phases are derived from the transmit VCO.
Lock to Reference
The receive circuit has two modes of operation: lock to reference, and lock to data with retiming. When no data or invalid data is present on the HDINP and HDINN input pins, the user can program the device to ignore the input data by setting LCKREFN equal to logic 0. In this mode, neither the PECL input buffer nor the RX parallel data bus toggles. In normal operation, the LCKREFN is a logic 1 and the receiver attempts to lock to the incoming data. If the input data is invalid or outside the nominal frequency range, the receive digital PLL will simply ramp the phase of the output clock until it locks to data.
Table 1. Receive Circuit Operating Modes* Mode LCKREFN = 1 (normal operation) LCKREFN = 0 Lock to Reference Not applicable. Lock to clock, output data does not toggle. Disable PECL input buffer. Lock to Receive Data Continually attempts to lock to data. Not applicable.
* REFCLK requirements are given in Table 4, and receive PLL specifications are given in Table 5.
Lucent Technologies Inc.
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LU5X34F Quad Gigabit Ethernet Transceiver
Preliminary Data Sheet July 2000
Parallel Output Port
Timing for the parallel output data and the 50 MHz to 62.5 MHz receive-byte clock is given in Table 14. Two low data rate receive-byte clocks are available as TTL compatible outputs during use of the parallel output port in 10-bit mode. RXCLK1 is the receive byte clock used by the protocol device to register bytes 0 and 2. RXCLK0 is the receive-byte clock used by the protocol device to register bytes 1 and 3, and it is 180 degrees out of phase with RXCLK1. Both RXCLK1 and RXCLK0 can be stretched during byte alignment but not truncated or slivered. The maximum allowable frequency of these two clocks under all circumstances, excluding start-up, will not exceed 80 MHz. The startup time is specified as 1 ms.
Functional Description (continued)
Byte Alignment
When ENCDET = 1, the LU5X34F recognizes the comma character and aligns this 10-bit character to the word boundary, bits RX[0:9]. COMDET =1 when the parallel output word contains a byte-aligned comma character. The COMDET flag will continue to pulse a logic 1 whenever a byte-aligned comma character is at the parallel output port, independent of ENCDET. When ENCDET = 0, there are two possible scenarios depending upon when the comma character is received. 1. If byte alignment had been previously achieved when ENCDET had been a logic 1, the COMDET flag will continue to pulse a logic 1 whenever a byte-aligned comma character is at the parallel output port. If a comma character occurs that is not on the word boundary, no attempt will be made to align this comma character and the COMDET flag will remain at a logic 0. 2. If byte alignment had not been previously achieved when ENCDET had been a logic 1, then the first (and only the first) comma character received will be aligned to the word boundary. COMDET will pulse when the comma character is aligned to the word boundary.
Loopback Mode Operation
A control signal input, EWRAP, selects between two possible sets of inputs: normal data (HDINP, HDINN) or internal loopback data. When EWRAP = 1, the serial output ports, HDOUTP and HDOUTN, remain active. The serial transmit data prior to the PECL output driver is directed to the data recovery circuit, where clock is recovered and data is resynchronized to the recovered clock. Retimed data and clock then go to the serial-toparallel converter.
Table 2. Definition of Bit Transmission/Reception Order* Serial Transmit/ Receive Rate TXX[9:0] RXX[9:0] RXX[0] bit received first at serial inputs HDINXP HDINXN ,
1.0 Gbits/s to 1.25 Gbits/s TXX[0] bit serially transmitted first at HDOUTXP, HDOUTXN
* Lower case X signifies channel A, B, C, or D.
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Lucent Technologies Inc.
Preliminary Data Sheet July 2000
LU5X34F Quad Gigabit Ethernet Transceiver
Sleep Mode
The LU5X34F has a sleep mode that is activated by enabling LPWR. In this mode, a divided-down version of the REFCLK is used to refresh the dynamic circuits within the transceiver. The PLL is powered down in this mode also. LCKREFN can also be activated to reduce the power even further. Note that complete powerdown for IDDQ testing is not supported due to the dynamic logic used in the high-speed sections of the transceiver. The lock-in sequence timing is needed when coming out of sleep mode.
Functional Description (continued)
Powerup Sequence
The power ramp time for the LU5X34F is specified at VDD > 2.7 V within 20 s of start-up. Once 2.7 V is reached, the device is held in reset for 15 s--70 s. The REFCLK must be active and within specification at this point and remain active while the device is powered up, unless in Reset. When signals RESET, BYPPLL, and LPWR are all low, the following start-up sequence occurs: 1. 0 s--32 s, the analog PLL is held at minimum frequency to allow dc bias to settle. 2. 32 s--262 s, the analog PLL has locked-in and receiver analog circuits start to lock-in. 3. 262 s--326 s, the receiver analog circuits are locked; receiver starts to lock onto incoming data. 4. After 358 s, the receiver is locked onto incoming data and can be viewed at the parallel output ports. The comma-detect circuit is enabled at this point, allowing byte alignment if ENCDET = 1. If LCKREFN goes low after the 358 s, the receiver will sit idle. When LCKREFN goes high, the receiver will be locked onto data after 2 s.
Device Reset
The RESETN input to the device is active-low. When activated with a pulse duration of 1 s, the RESETN signal globally resets the device and the following is performed: 1. The single analog PLL is forced to operate at the minimum frequency possible for its VCO. The PLL will not be locked in this condition. 2. The HDOUTP HDOUTN outputs are forced to a , PECL logic 0. 3. The deserializer clocks, but input data at HDINP, HDINN is ignored and the RX[9:0] signals remain in their previous state. 4. The phase interpolation/selection circuits are deactivated and the selected phase is reset. 5. The receiver digital low-pass filter in the DPLL is reset. Normally, a reset is not necessary for correct operation, although a reset can aid rapid lock-in of the internal PLL circuitry. This active-low pin is internally pulled high.
Lucent Technologies Inc.
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LU5X34F Quad Gigabit Ethernet Transceiver
Preliminary Data Sheet July 2000
Functional Description (continued)
Block Diagrams
LCKREFN[A:D] COMDET[A:D] ENCDET[A:D]
LPWR
RESET
EWRAP[A:D]
TXCLK[A:D]*
OLREF OLRVS
HDINAP HDINAN HDOUTAP HDOUTAN HDINBP HDINBN HDOUTBP HDOUTBN
2 2 TRANSCEIVER A
RXA[9:0] TXA[9:0]
2 2 TRANSCEIVER B
RXB[9:0] TXB[9:0] TEST[5:1] LDST[A:D] BYPPLL RXCLK0[A:D] RXCLK1[A:D]
TEST CIRCUITS REFCLK REFCLKN 2 ANALOG PLL
HDINCP HDINCN HDOUTCP HDOUTCN HDINDP HDINDN HDOUTDP HDOUTDN
2 2 TRANSCEIVER C
RXC[9:0] TXC[9:0]
2 2 TRANSCEIVER D
RXD[9:0] TXD[9:0]
5-8808(F)
* Synchronous with REFCLK(N).
Figure 1. LU5X34F Quad Gigabit Ethernet Transceiver Block Diagram
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Lucent Technologies Inc.
Preliminary Data Sheet July 2000
LU5X34F Quad Gigabit Ethernet Transceiver
Functional Description (continued)
Block Diagrams (continued)
OLREF OLRVS
TX[9:0]
DATA IN SERIALIZER SERIAL DATA OUT PECL
HDOUTP
REFCLK
LOAD
HDOUTN
TEST[5:1] / LDST BYPPLL ANALOG PLL GLOBAL CONTROL RESETN LPWR ENCDET EWRAP
DESERIALIZER PHASE SELECT/ INTERPOLATION
HDINP DIGITAL LOW-PASS FILTER PHASE DETECTOR PECL HDINN
RX[9:0] RXCLK0 RXCLK1 COMDET DATA RETIMING, SERIAL-TO-PARALLEL CONVERSION AND COMMA DETECTION SERIAL DATA IN
5-8809(F).a
Figure 2. LU5X34F Single-Channel Transceiver Functional Diagram
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LU5X34F Quad Gigabit Ethernet Transceiver
Preliminary Data Sheet July 2000
Input/Output Information
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1
RXB7
RXB6
RXB2
EWRAPA
LCKREFA
LCKREFB
TEST2
TEST4
BYPPLL
REFCLK
ENCDETC
ENCDETD
LCKREFD
TXC1
TXC5
TXC5
N/C
2
RXB8
VSS
RXB5
RXB1
ENCDETA
EWRAPB
RESETN
TEST3
TEST5
REFCLKN
LDSTC
LDSTD
TXC0
TXC4
TXC8
VSS
TXCLKC
3
RXCLK0B
RXB9
VSS
RXB4
N/C
LDSTA
ENCDETB
TEST1
LPWR
EWRAPC
LPBKD
N/C
TXC3
TXC7
VSS
N/C
N/C
4
TXB9
RXCLK1B
COMDETB
VSS
RXB3
RXB0
LDSTB
VDD
VSS
VDD
LCKREFC
TXC2
TXC6
VSS
RXCLK1C
COMDETC
RXC7
5
TXB6
TXB8
N/C
VDD
RXCLK0C
RXC8
RXC6
RXC4
6
TXB4
TXB5
TXB7
TXCLKB
RXC9
RXC5
RXC3
RXC0
7
TXB0
TXB1
TXB3
TXB2
RXC1
RXC2
N/C
TXD1
8
RXA1
RXA0
N/C
VDD
VSS
VSS
VSS
VDD
TXD0
TXD2
TXD3
9
RXA3
RXA4
RXA2
VSS
VSS
VSS
VSS
VSS
TXD6
TXD4
TXD5
10
RXA5
RXA6
RXA8
VDD
VSS
VSS
VSS
VDD
TXD10
TXD8
TXD7
11
RXA7
RXA9
RXCLK0A
N/C
N/C
RXCLK1D
TXCLKD
N/C
12
COMDETA
RXCLK1A
TXCLKA
TXA7
RXD6
RXD9
N/C
RXCLK0D
13
N/C
VDD
TXA8
TXA4
RXD2
RXD5
RXD8
COMDETD
14
TXA9
TXA6
TXA3
VSST
HDINAN
HDOUTAP
HDOUTBP
VDDR
VSST
VDDR
VSSRC
N/C
VDDTD
VSS
RXD1
RXD4
RXD7
15
TXA5
TXA2
VSST
HDINAP
HDOUTAN
HDINBP
HDOUTBN
VSSP
VREG
VSSRC
VDDTC
HDOUTCP
HDINDP
HDOUTDN
VSS
RXD0
RXD3
16
TXA1
VSST
VSSRA
VDDTA
VSSRB
VSSRB
VDDTB
VDDP
N/C
OLREF
HDINCP
HDOUTCN
VDDTC
HDINDN
HDOUTDP
VSS
N/C
17
TXA0
N/C
VSSRA
VDDTA
HDINBN
VDDTB
VDDP
VSSP
N/C
OLRVS
N/C
HDINCN
N/C
VSSRD
VSSRD
VDDTD
N/C
Figure 3. Pin Designations (Top View)
5-8880(F)
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Lucent Technologies Inc.
Preliminary Data Sheet July 2000
LU5X34F Quad Gigabit Ethernet Transceiver
Input/Output Information (continued)
Table 3a. Pinout--Channel A I/O Name TXA9 TXA8 TXA7 TXA6 TXA5 TXA4 TXA3 TXA2 TXA1 TXA0 RXA9 RXA8 RXA7 RXA6 RXA5 RXA4 RXA3 RXA2 RXA1 RXA0 TXCLKA Pin A14 C13 D12 B14 A15 D13 C14 B15 A16 A17 B11 C10 A11 B10 A10 B9 A9 C9 A8 B8 C12 I/O Input Level TTL/ CMOS Description Channel A, Transmit Data [9:0]. Parallel input bits [9:0], one 10-bit, 8b/10b encoded data byte, clocked-in on the rising edge of TXCLKA. TXA0 is the LSB.
Output
TTL/ CMOS
Channel A, Receive Data [9:0]. Parallel output bits [9:0], one 10-bit data type, clockedout on the alternate rising edge of RXCLK0A, RXCLK1A. RXA0 is the LSB.
Input
TTL/ CMOS TTL/ CMOS TTL/ CMOS TTL/ CMOS TTL/ CMOS TTL/ CMOS TTL/ CMOS PECL PECL TTL/ CMOS
Transmit Clock (100 MHz--125 MHz). Used to latch TXA[9:0] data into the LU5X34F. Synchronous with REFCLK(N) Channel A, Receive Byte-Align Clock 0. Channel A, Receive Byte-Align Clock 1. Channel A, Enable Comma Detect A. Channel A, Byte-Aligned Comma A. Channel A, Loopback at Serial I/O A. Channel A, Lock Receiver to Clock. Channel A, Differential Serial Inputs. Channel A, Differential Serial Outputs. Channel A, Load Test[5:1] Inputs.
RXCLK0A RXCLK1A ENCDETA COMDETA EWRAPA LCKREFNA HDINAP , HDINAN HDOUTAP , HDOUTAN LDSTA
C11 B12 E2 A12 D1 E1 D15, E14 F14, E15 F3
Output Output Input Output Input Input Input Output Input
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LU5X34F Quad Gigabit Ethernet Transceiver
Preliminary Data Sheet July 2000
Input/Output Information (continued)
Table 3b. Pinout--Channel B I/O Name TXB9 TXB8 TXB7 TXB6 TXB5 TXB4 TXB3 TXB2 TXB1 TXB0 RXB9 RXB8 RXB7 RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXB0 TXCLKB Pin A4 B5 C6 A5 B6 A6 C7 D7 B7 A7 B3 A2 A1 B1 C2 D3 E4 C1 D2 F4 D6 I/O Input Level TTL/ CMOS Description Channel B, Transmit Data [9:0]. Parallel input bits [9:0], one 10-bit, 8b/10b encoded data byte, clocked-in on the rising edge of TXCLKB. TXB0 is the LSB.
Output
TTL/ CMOS
Channel B, Receive Data [9:0]. Parallel output bits [9:0], one 10-bit data type, clockedout on the alternate rising edge of RXCLK0B, RXCLK1B. RXB0 is the LSB.
Input
TTL/ CMOS TTL/ CMOS TTL/ CMOS TTL/ CMOS TTL/ CMOS TTL/ CMOS TTL/ CMOS PECL PECL TTL/ CMOS
RXCLK0B RXCLK1B ENCDETB COMDETB EWRAPB LCKREFNB HDINBP , HDINBN HDOUTBP , HDOUTBN LDSTB
A3 B4 G3 C4 F2 F1 F15, E17 G14, G15 G4
Output Output Input Output Input Input Input Output Input
Transmit Clock (100 MHz--125 MHz). Used to latch TXB[9:0] data into the LU5X34F. Synchronous with REFCLK(N) Channel B, Byte-Align Clock 0. Channel B, Byte-Align Clock 1. Channel B, Enable Comma Detect. Channel B, Byte-Aligned Comma. Channel B, Loopback at Serial I/O. Channel B, Lock Receiver to Clock. Channel B, Differential Serial Inputs. Channel B, Differential Serial Outputs. Channel B, Load TEST[5:1] inputs.
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Lucent Technologies Inc.
Preliminary Data Sheet July 2000
LU5X34F Quad Gigabit Ethernet Transceiver
Input/Output Information (continued)
Table 3c. Pinout--Channel C I/O Name TXC9 TXC8 TXC7 TXC6 TXC5 TXC4 TXC3 TXC2 TXC1 TXC0 RXC9 RXC8 RXC7 RXC6 RXC5 RXC4 RXC3 RXC2 RXC1 RXC0 TXCLKC Pin T1 R2 P3 N4 R1 P2 N3 M4 P1 N2 P6 R5 U4 T5 R6 U5 T6 R7 P7 U6 U2 I/O Input Level TTL/ CMOS Description Channel C, Transmit Data [9:0]. Parallel input bits [9:0], one 10-bit, 8b/10b encoded data byte, clocked in on the rising edge of TXCLKC. TXC0 is the LSB.
Output
TTL/ CMOS
Channel C, Receive Data [9:0]. Parallel output bits [9:0], one 10-bit data type, clockedout on the alternate rising edge of RXCLK0C, RXCLK1C. RXC0 is the LSB.
Input
TTL/ CMOS TTL/ CMOS TTL/ CMOS TTL/ CMOS TTL/ CMOS TTL/ CMOS TTL/ CMOS PECL PECL TTL/ CMOS
RXCLK0C RXCLK1C ENCDETC COMDETC EWRAPC LCKREFNC HDINCP , HDINCN HDOUTCP , HDOUTCN LDSTC
P5 R4 L1 T4 K3 L4 L16, M17 M15, M16 L2
Output Output Input Output Input Input Input Output Input
Transmit Clock (100 MHz--125 MHz). Used to latch TXC[9:0] data into the LU5X34F. Synchronous with REFCLK(N) Channel C, Byte-Align Clock 0. Channel C, Byte-Align Clock 1. Channel C, Enable-Comma Detect. Channel C, Byte-Aligned Comma. Channel C, Loopback at Serial I/O. Channel C, Lock Receiver to Clock. Channel C, Differential Serial Inputs. Channel C, Differential Serial Outputs. Channel C, Load Test[5:1] Inputs.
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LU5X34F Quad Gigabit Ethernet Transceiver
Preliminary Data Sheet July 2000
Input/Output Information (continued)
Table 3d. Pinout--Channel D I/O Name TXD9 TXD8 TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0 RXD9 RXD8 RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 TXCLKD Pin R10 T10 U10 R10 U9 T9 U8 T8 U7 R8 R12 T13 U14 P12 R13 T14 U15 P13 R14 T15 T11 I/O Input Level TTL/ CMOS Description Channel D, Transmit Data [9:0]. Parallel input bits [9:0], one 10-bit, 8b/10b encoded data byte, clocked-in on the rising edge of TXCLKD. TXD0 is the LSB.
Output
TTL/ CMOS
Channel D, Receive Data [9:0]. Parallel output bits [9:0], one 10-bit data type, clockedout on the alternate rising edge of RXCLK0D, RXCLK1D. RXD0 is the LSB.
Input
TTL/ CMOS TTL/ CMOS TTL/ CMOS TTL/ CMOS TTL/ CMOS TTL/ CMOS TTL/ CMOS PECL PECL TTL/ CMOS
RXCLK0D RXCLK1D ENCDETD COMDETD EWRAPD LCKREFND HDINDP , HDINDN HDOUTDP, HDOUTDN LDSTD
U12 R11 M1 U13 L3 N1 N15, P16 R16, P15 M2
Output Output Input Output Input Input Input Output Input
Transmit Clock (100 MHz--125 MHz). Used to latch TXD[9:0] data into the LU5X34F. Synchronous with REFCLK(N) Channel D, Byte-Align Clock 0. Channel D, Byte-Align Clock 1. Channel D, Enable Comma Detect. Channel D, Byte-Aligned Comma. Channel D, Loopback at Serial I/O. Channel D, Lock Receiver to Clock. Channel D, Differential Serial Inputs. Channel D, Differential Serial Outputs. Channel D, Load Test[5:1] Inputs.
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Lucent Technologies Inc.
Preliminary Data Sheet July 2000
LU5X34F Quad Gigabit Ethernet Transceiver
Input/Output Information (continued)
Table 3e. Pinout--Common I/O Name OLREF OLRVS LPWR RESETN TEST5* TEST4* TEST3* TEST2* TEST1* BYPPLL REFCLK, REFCLKN Pin K16 K17 J3 G2 J2 H1 H2 G1 H3 J1 K1, K2 I/O Input/ Output Input/ Output Input Input Input/ Output Input Input Input Input Input Input Level Analog Analog TTL/ CMOS TTL/ CMOS TTL/ CMOS TTL/ CMOS TTL/ CMOS TTL/ CMOS TTL/ CMOS TTL/ CMOS PECL or TTL/ CMOS Description PECL Level Set Resistor Terminal 1. PECL Level Set Resistor Terminal 2. Device Low-Power Mode. Device Reset (Active-Low). Global Test Control Input/Output. Local Test Control Input. Local Test Control Input. Local Test Control Input. Local Test Control Input. Test Control, PLL Bypass Mode. Reference Clock Input (100 MHz--125 MHz). Used by the transmitter PLL to generate the 1.0 Gbits/s-- 1.25 Gbits/s serial data; has a +100 ppm tolerance requirement.
* For related information, see Table 18, Test Modes.
Table 3f. Pinout--Power I/O Name VDD VDDP VDDTX VDDR VSS VSSP VSST VSSRX Pin D5, D8, D10, B13, H4, K4, P8, P10 G17, H16 D16, D17, F17, G16, L15, N16, N14, T17, H14, K14 B2, C3, D4, D9, H8, H9, H10, J4, J8, J9, J10, K8, K9, K10, P4, P9, P14, R3, R15, T2, T16 H15, H17 B16, C15, D14, J14 C16, C17, E16, F16, K15, L14, P17, R17 Description Device Digital Power. PLL Power. High-Speed Analog Transmitter Power. High-Speed Analog Receiver Power. Device Digital Ground. PLL Ground. High-Speed Analog Transmitter Ground. High-Speed Analog Receiver Ground.
Lucent Technologies Inc.
13
LU5X34F Quad Gigabit Ethernet Transceiver
Preliminary Data Sheet July 2000
Electrical Specifications
Transmitter
Table 4. Reference Clock Specifications (REFCLK and REFCLKN) Parameter Frequency Range Frequency Tolerance Duty Cycle* Rise Time (PECL) Fall Time (PECL) Rise Time (TTL/CMOS) Fall Time (TTL/CMOS) In-band Jitter, 1 Gbit/s--1.25 Gbits/s Out-of-Band Jitter
* Measured at 50% amplitude point.
Min 100 -100 40 -- -- -- -- -- --
Max 125 100 60 0.8 0.8 1.5 1.5 30 50
Unit MHz ppm % ns ns ns ns psp-p psp-p
Table 5. PLL Specifications Parameter Bandwidth Jitter Peaking Lock Time Min -- -- -- Typ 1.5 0.5 -- Max -- -- 230 Unit MHz dB s
Table 6. Output Jitter at 1.0 Gbit/s--1.25 Gbits/s Data Rate Parameter Deterministic Random Total Min -- -- -- Max 0.08 0.12 0.2 Unit UIp-p UIp-p UIp-p
Receiver
Table 7. Input Data Rate Parameter Frequency Range Frequency Tolerance with REFCLK Table 8. Data Lock Characteristics Parameter Bandwidth* Jitter Peaking* Lock Time*
* Data pattern: 101010 . . . . Data pattern: 1111100000 . . . .
Min 1.0 -100
Max 1.25 100
Unit Gbits/s ppm
Min 0.3 -- --
Typ -- 0.5 --
Max 1* -- 2
Unit MHz dB s
14
Lucent Technologies Inc.
Preliminary Data Sheet July 2000
LU5X34F Quad Gigabit Ethernet Transceiver
Electrical Specifications (continued)
Receiver (continued)
Table 9. Power Dissipation * Parameter Power Package Thermal Resistance Sleep Mode (LPWR) Min -- TBD -- Typ -- -- TBD Max 2.0 TBD -- Unit W C/W mW
* Depending on application (PCB layout), etc.
Table 10. dc Electrical Specifications* Parameter Supply Voltage Output Low Output High Input Low Input High Diff. PECL Output Diff. PECL Input Symbol VDD, VDDP VOL VOH VIL VIH Condition -- -- -- -- -- Load, as in Figure 9. Source configuration, as in Figure 9. Min 3.135 0 2.4 0 2.0 800 400 Typ 3.3 -- -- -- -- -- -- Max 3.465 0.6 VDD 0.8 VDD -- 1600 Unit V V V V V mV mV
* Depending on application (PCB layout), etc.
Table 11. Absolute Maximum Ratings Parameter Supply Voltage TTL High Input Voltage PECL Output Current Junction Operating Temperature Storage Temperature Min 3.135 3.0 -- 0 -65 Typ 3.3 -- -- -- -- Max 3.465 3.6 16 125 150 Unit V V mA C C
Lucent Technologies Inc.
15
LU5X34F Quad Gigabit Ethernet Transceiver
Preliminary Data Sheet July 2000
Timing Characteristics
Serial Timing
Table 12. Serial Output Timing Levels Description Rise Time 20%--80% Fall Time 80%--20% Common Mode Differential Swing Load (See Table 16) Min 0.17 0.17 VDD/2 - 0.1 0.8 50 Typ 0.2 0.2 VDD/2 -- -- Max 0.22 0.22 VDD/2 + 0.1 1.6 75 Unit ns ns V Vp-p
DWIN VDIFF
tF/tR
5-8813(F)
Figure 4. Serial Interface Timing Table 13. Serial Input Interface Timing Description Rise Time (tR) Fall Time (tF) Differential Swing (VDIFF) Source Impedance Data Eye Opening Min 150 150 0.4 50 320 Max 225 225 1.6 75 -- Unit ps ps mVp-p ps
16
Lucent Technologies Inc.
Preliminary Data Sheet July 2000
LU5X34F Quad Gigabit Ethernet Transceiver
Timing Characteristics (continued)
Receiver Section Timing
HDNIP K28.5 RECOVERED CLOCK (INTERNAL) D7.2 D0.0 D1.0
RXCLK1
RXCLK0
RX[9:0]
K28.5
D7.2
COMDET
Figure 5. Receiver Section Timing
5-8813 (F)
Receiver Port Timing
RXCLK PERIOD RXCLK1 LOW RXCLK1 RXCLK1 HIGH
RXCLK0 tSKEW
RX tS
RX0 tH
RX1
RX2 tS
RX3 tH
5-8814(F)
Figure 6. Receiver Port Timing Table 14. Receiver Parallel Port Timing Symbol -- -- -- tR/F tR/F tS tH tSKEW
* 1.25 Gbits/s. 0.5 pF load.
Parameter RXCLK[1:0] Frequency* RXCLK[1:0] Low RXCLK[1:0] High RXCLK[1:0] (0.4 V to 2.6 V) Data Output (0.4 V to 2.6 V) Setup Time Hold Time Skew
Min -- 7.0 7.0 0.2 0.2 3.0 2.0 --
Max 62.5 9.0 9.0 0.5 0.5 -- -- 1.0
Units MHz ns ns ns ns ns ns ns
Lucent Technologies Inc.
17
LU5X34F Quad Gigabit Ethernet Transceiver
Preliminary Data Sheet July 2000
Timing Characteristics (continued)
Transmitter Section Timing
TXCLK*
TX[9:0]
155 155
126 126
375 375
34A
SERIALIZED DATA
SYNTHESIZED CLOCK
5-8815(F)
* Synchronous with REFCLK(N).
Figure 7. Parallel Interface Transmit Timing Table 15. Transmitter Timing at Parallel Interface Description Data Setup Data Hold Rise Time Fall Time Min 2 2 -- -- Max -- -- 1 1 Unit ns ns ns ns Conditions With positive edge TXCLK With positive edge TXCLK -- --
18
Lucent Technologies Inc.
Preliminary Data Sheet July 2000
LU5X34F Quad Gigabit Ethernet Transceiver
Application Section
BIAS REFCLK CLOCK SOURCE INTERNAL CLOCK REFCLKN 1.0 nF BIAS LU5X34F
SINGLE-ENDED CLOCK SOURCE
BIAS REFCLK CLOCK SOURCE REFCLKN INTERNAL CLOCK
BIAS LU5X34F DIFFERENTIAL CLOCK SOURCE
5-8013(F)
Figure 8. Reference Clock Connections with Single-Ended and Differential Sources
Lucent Technologies Inc.
19
LU5X34F Quad Gigabit Ethernet Transceiver
Preliminary Data Sheet July 2000
Application Section (continued)
10 HDOUTP ZO = 50 0.01 F HDINP
50 RXX[9:0] TXX[9:0] TRANSMIT LU5X34F 50 TXCLK HDOUTN 10 0.01 F ZO = 50 HDINN 100 0.1 F RXCLKX1 RXCLKX0 RECEIVE LU5X34F
OLREF
OLRVS
*
5-8811(F).c
* External resistor connected between OLREF and OLRVS. See Table 16 for external resistor value. Damping resistor, maximum = 10 .
Figure 9. Typical Termination for a Single-Channel, High-Speed Serial Transmit-and-Receive Port in a 50 Backplane Application Table 16. External Resistor Value vs. Differential Output Level Viewing Resistor Value () 7.5 k/11.25 k 5 k/7.5 k 4 k/6 k Termination Impedance () 50/75 Differential Output Voltage (V) 0.8 1.2 1.6
20
Lucent Technologies Inc.
Preliminary Data Sheet July 2000
LU5X34F Quad Gigabit Ethernet Transceiver
Application Section (continued)
68 10 HDOUTP ZO = 50 0.01 F TX(+)
50
191
TXA[9:0]
TRANSMIT LU5X34F 0.1 F 50 191 ZO = 50 HDOUTN 10 0.01 F 68 OLREF OLRVS 5V
TRANSMIT GBIC
REFCLK
TX(-)
*
5-8811(F)b
* External resistor connected between OLREF and OLRVS. See Table 17 for resistor value vs. termination impedance and output swing. Damping resistor, maximum = 10 .
Figure 10. Typical Termination for a Single-Channel, High-Speed Serial Transmit Port Interfacing a 5 V GBIC Transceiver Table 17. External Resistor Value vs. Differential Output Level Viewing Resistor Value () 7.5 k/11.25 k 5 k/7.5 k 4 k/6 k 50/75 Termination Impedance () Differential Output Voltage (V) 0.8 1.2 1.6
Lucent Technologies Inc.
21
LU5X34F Quad Gigabit Ethernet Transceiver
Preliminary Data Sheet July 2000
Test Modes
Note: Test modes are intended for manufacture test only and are not guaranteed to be operational. They may be modified or eliminated without prior notice. The device has per-channel test modes as well as global test modes. The bypass PLL, BYPPLL, is a global test input because it modifies the operation of the analog PLL. Test bits TEST[4:1] generally operate in the localized mode. The LDST[A:D] inputs are enable signals that permit the TEST[4:1] signals to be injected into a particular channel. For example, if LDSTA = 1, the TEST[4:1] signals directly control the test modes in the A channel. Once LDSTA = 0, the previous values of TEST[4:1] are held for the A channel. The TEST[4:1] signals control the four channels (A, B, C, D) via level sense latches that are gated with the LDST[A:D] inputs. TEST[5] is a global test pin used for both injection of signals as well as for monitoring points within the device. Table 18. Test Modes Global BYPPLL 0 0 0 TEST1 1 1 1 Local Test Configuration TEST2 1 1 1 TEST3 1 1 0 TEST4 1 0 1 Global TEST5 X Output X Normal operation. Analog PLL feedback signal viewed at TEST5 pin. Transceiver operates normally except RX[9:0] output is from digital filter, not the serial data. Transceiver operates normally except RX[9:0] output is from digital filter and the analog PLL feedback signal is viewed at TEST5 pin. Digital filter forced to count. Pulses applied at TEST4 increment accumulator; pulses at TEST5 decrement accumulator. RX[9:0] output is from digital filter, not the serial data. Digital filter forced to count. Pulses applied at TEST4 increment accumulator; pulses at TEST5 decrement accumulator. Parallel loopback. TX[9:0] = RX[9:0]. RX[9:0] remains active. Parallel loopback. TX[9:0] = RX[9:0] and analog PLL feedback signal viewed at TEST5 pin. RX[9:0] remains active. RX[9:0] output is from digital filter, not the serial data. Receive channel is held in reset. BYPPLL overrides this reset. RX[9:0] output is from digital filter, not the serial data. Receive channel is held in reset. BYPPLL overrides this reset. Analog PLL feedback signal viewed at TEST5 pin Operation
0
1
1
0
0
Output
0
1
0
1
P
P
0
1
0
0
P
P
0 0
0 0
1 1
1 1
1 0
X Output
0
0
1
0
1
X
0
0
1
0
0
Output
22
Lucent Technologies Inc.
Preliminary Data Sheet July 2000
LU5X34F Quad Gigabit Ethernet Transceiver
Test Modes (continued)
Table 18. Test Modes (continued) Global BYPPLL 0 TEST1 0 Local Test Configuration TEST2 0 TEST3 1 TEST4 0 Global TEST5 Output Transmitter is held in reset. BYPPLL overrides this reset. Analog PLL feedback signal viewed at TEST5 pin. Transmitter and receiver are held in reset. RX[9:0] output is from digital filter, not the serial data. Transmitter and receiver are held in reset. RX[9:0] output is from digital filter, not the serial data. Analog PLL feedback signal viewed at TEST5 pin. Analog PLL is bypassed for low speed functional test. A low-speed clock is input to TEST4, and a quadrature clock is applied to TEST5. Frequency of clocks is 5X REFCLK, but here REFCLK is lowered to about 1 MHz. Analog PLL is bypassed for low-speed functional test. A low-speed clock is input to TEST4, and a quadrature clock is applied to TEST5. Frequency of clocks is 5X REFCLK, but here REFCLK is lowered to about 1 MHz. RX[9:0] output is from digital filter, not the serial data. OPERATION
0
0
0
0
1
X
0
0
0
0
0
Output
1
X
X
1
C-0
C-90
1
X
X
0
C-0
C-90
Lucent Technologies Inc.
23
LU5X34F Quad Gigabit Ethernet Transceiver
Preliminary Data Sheet July 2000
Outline Diagram
217-pin PBGA
Dimensions are in millimeters.
23.00 0.20 A1 BALL IDENTIFIER ZONE +0.70 19.50 -0.00
+0.70 19.50 -0.00 23.00 0.20
MOLD COMPOUND PWB
0.36 0.04
1.17 0.05
2.13 0.19 SEATING PLANE 0.20
0.60 0.10
SOLDER BALL
16 SPACES @ 1.27 = 20.32
U T R P N M L K J H G F E D C B A
0.75 0.15
16 SPACES @ 1.27 = 20.32
A1 BALL CORNER
12
34567
8 9 10 11 12 13 14 15 16 17
5-6562 (F)
24
Lucent Technologies Inc.
Preliminary Data Sheet July 2000
LU5X34F Quad Gigabit Ethernet Transceiver
Ordering Information
Device Code LU5X34F Comcode 108497850 Package 217-pin PBGA Temperature 0 C--70 C
Lucent Technologies Inc.
25
LU5X34F Quad Gigabit Ethernet Transceiver
Preliminary Data Sheet July 2000
For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 325, FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
Copyright (c) 2000 Lucent Technologies Inc. All Rights Reserved
July 2000 DS00-351LAN (Replaces DS00-007LAN)

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