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IDT74LVCR16952A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O
* Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * CMOS power levels (0.4 W typ. static) * All inputs, outputs, and I/O are 5V tolerant * Supports hot insertion * Available in TSSOP package
IDT74LVCR16952A
FEATURES:
DESCRIPTION:
DRIVE FEATURES: APPLICATIONS:
* Balanced Output Drivers: 12mA * Low switching noise
* 5V and 3.3V mixed voltage systems * Data communication and telecommunication systems
This 16-bit registered transceiver is built using advanced dual metal CMOS technology. This high-speed, low power device is organized as two independent 8-bit D-type registered transceivers with separate input and output control for independent control of data flow in either direction. For example, the A-to-B Enable (CEAB) must be LOW to enter data from the A port. CLKAB controls the clocking function. When CLKAB toggles from LOWto-HIGH, the data present on the A port will be clocked into the register. OEAB performs the output enable function on the B port. Data flow from the B port to A port is similar but requires using CEBA, CLKBA, and OEBA inputs. Full 16-bit operation is achieved by tying the control pins of the independent transceivers together. All pins can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVCR162952A has series resistors in the device output structure which will significantly reduce line noise when used with light loads.This driver has been developed to drive 12mA at the designated threshold levels.
FUNCTIONAL BLOCK DIAGRAM
54 1CEBA 1CLKBA 1OEAB 3 1CEAB 1CLKAB 2 2CEAB 2CLKAB 27 55 1 2OEAB 26 2CEBA 2CLKBA 30 28 31
56 1OEBA 2OEBA
29
1A1
5
C CE D C CE D
52
2A1 1B1
15
C CE D C CE D
42
2B1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
(c) 2004 Integrated Device Technology, Inc.
JANUARY 2004
DSC-4484/2
IDT74LVCR16952A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1 OEAB 1CLKAB 1 CEAB
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND -0.5 to +6.5 -65 to +150 -50 to +50 -50 100
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1 OEBA 1 CLKBA 1 CEBA
Unit V C mA mA mA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
TSTG IOUT IIK IOK ICC ISS
GND
1A1 1A2
GND
1B1 1B2
VCC
1A3 1A4 1A5
VCC
1B3 1B4 1B5
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
GND
1A6 1A7 1A8 2A1 2A2 2A3
GND
1B6 1B7 1B8 2B1 2B2 2B3
PIN DESCRIPTION
Pin Names xOEAB xOEBA xCEAB xCEBA xCLKAB xCLKBA xAx xBx Description A-to-B Output Enable Inputs (Active LOW) B-to-A Output Enable Inputs (Active LOW) A-to-B Clock Enable Inputs (Active LOW) B-to-A Clock Enable Inputs (Active LOW) A-to-B Clock Inputs B-to-A Clock Inputs A-to-B Data Inputs or B-to-A 3-State Outputs B-to-A Data Inputs or A-to-B 3-State Outputs
GND
2A4 2A5 2A6
GND
2B4 2B5 2B6
VCC
2A7 2A8
VCC
2B7 2B8
GND
2CEAB 2CLKAB 2 OEAB
GND
2CEBA 2CLKBA 2OEBA
FUNCTION TABLE(1,2)
Inputs xCEAB xCLKAB X L X xOEAB L L L L H xAx X X L H X H X L L Outputs xBx B(3) B(3) L H Z
TSSOP TOP VIEW
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 4.5 6.5 6.5 Max. 6 8 8 Unit pF pF pF
X
NOTE: 1. As applicable to the device type.
NOTES: 1. A-to-B data flow is shown: B-to-A data flow is similar but uses xCEBA, xCLKBA, and xOEBA. 2. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance = LOW-to-HIGH Transition 3. Output level of B before the indicated steady-state input conditions were established.
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IDT74LVCR16952A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL IOFF VIK VH ICCL ICCH ICCZ ICC High Impedance Output Current (3-State Output pins) Input/Output Power Off Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 0V, VIN or VO 5.5V VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC -- -- -- -- -- -- -- -0.7 100 -- -- -- 50 -1.2 -- 10 10 500 A V mV A VCC = 3.6V VO = 0 to 5.5V -- -- 10 A Parameter Input HIGH Voltage Level Input LOW Voltage Level Input Leakage Current VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VI = 0 to 5.5V Test Conditions Min. 1.7 2 -- -- -- Typ.(1) -- -- -- -- -- Max. -- -- 0.7 0.8 5 A V Unit V
Quiescent Power Supply Current Variation
3.6 VIN 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND
A
NOTES: 1. Typical values are at VCC = 3.3V, +25C ambient. 2. This applies in the disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.7V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 4mA IOH = - 6mA IOH = - 4mA IOH = - 8mA IOH = - 6mA IOH = - 12mA IOL = 0.1mA IOL = 4mA IOL = 6mA IOL = 4mA IOL = 8mA IOL = 6mA IOL = 12mA Min. VCC - 0.2 1.9 1.7 2.2 2 2.4 2 -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- 0.2 0.4 0.55 0.4 0.6 0.55 0.8 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
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IDT74LVCR16952A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, VCC = 3.3V 0.3V, TA = 25C
Symbol CPD CPD Parameter Power Dissipation Capacitance per Transceiver Outputs enabled Power Dissipation Capacitance per Transceiver Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.7V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tSU tH tW tSK(o) Parameter Propagation Delay xCLKAB, xCLKBA to xBx, xAx Output Enable Time xOEBA, xOEAB to xAx, xBx Output Disable Time xOEBA, xOEAB to xAx, xBx Set-up Time, HIGH or LOW xAx, xBx before xCLKAB, xCLKBA Hold Time, HIGH or LOW xAx, xBx after xCLKAB, xCLKBA Set-up Time, HIGH or LOW xCEAB, xCEBA before xCLKAB, xCLKBA Hold Time, HIGH or LOW xCEAB, xCEBA after xCLKAB, xCLKBA Pulse Width HIGH or LOW, xCLKAB or xCLKBA Output Skew(2) 3 -- -- -- 3 -- -- 500 ns ps 2 -- 2 -- ns 1.8 -- 1.4 -- ns 1.5 -- 1.5 -- ns 2.5 -- 2.5 -- ns 1.5 7.5 1.5 6.5 ns 1.5 8 1.5 7 ns Min. 2 Max. 7.6 VCC = 3.3V 0.3V Min. 2 Max. 6.6 Unit ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction.
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IDT74LVCR16952A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50 6 2.7 1.5 300 300 50 VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 Unit V V V mV mV pF
OPPOSITE PHASE INPUT TRANSITION SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH tPHL tPHL VIH VT 0V VOH VT VOL VIH VT 0V
LVC Link
Propagation Delay
VCC 500 Pulse (1, 2) Generator VIN D.U.T. RT 500 CL
LVC Link
VLOAD Open GND CONTROL INPUT
ENABLE
DISABLE
tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V
tPLZ
VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
LVC Link
VOUT
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
tSU
tH
tREM
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
LVC Link
INPUT
tPLH1
tPHL1
VIH VT 0V VOH VT VOL VOH VT VOL
Set-up, Hold, and Release Times
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE VT
LVC Link
VT
OUTPUT 1
tSK (x)
tSK (x)
OUTPUT 2 tPLH2 tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Pulse Width
LVC Link
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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IDT74LVCR16952A 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
X LVC IDT XX Bus-Hold Temp. Range XX Family XX XXXX Device Type Package
PA
Thin Shrink Small Outline Package
952A 16-Bit Registered Transceiver with 3-State Outputs R16 Blank 74 Double-Density, 12mA No Bus-hold -40C to +85C
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for Tech Support: logichelp@idt.com (408) 654-6459
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