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HT82V14
14-Bit CCD/CIS Analog Signal Processor
Features
* * * * * * *
Low power CMOS : 350 mW 9 ADC clock latency for digital data output 14-bit 6 MSPS A/D converter 3-channel correlated double sampler 1~6 programmable gain Input clamp circuitry for CDS-mode Internal/external circuitfor CIS
* * * * * * *
Internal/external voltage reference Internal MUX for channel operation 1 or 3-channel operation Pixel-rate or line-rate switch operation Programmable 3-wire serial interface +5V digital I/O compatibility 28-pin SOP/SOJ package
General Description
The HT82V14 is a complete analog signal processor for CCD imaging applications. It features a 3-channel architecture designed to sample and condition the outputs of the trilinear color CCD arrays. Each channel consists of an input clamp, Correlated Double Sampler (CDS), offset DAC and Programmable Gain Amplifier (PGA), multiplexed to a high performance 14-bit A/D converter. The CDS amplifiers may be disabled for use with sensors such as Contact Image Sensors (CIS) and CMOS active pixel sensors, which do not require CDS. The 14-bit digital output is multiplexed into an 8-bit output word that is accessed using two read cycles. The internal registers are programmed through a 3-wire serial interface, which provides gain, offset, and operating mode adjustments.
Block Diagram
OFFSET REFT CML REF OE
V o lta g e R e fe r e n c e R IN G IN B IN CLP CLP CLP CDS + + + 3 8 b its DAC O ffs e t CDS CDS VGA VGA VGA 3 2 b its C o a rs e G a in C o n fig R e g is te r 3 5 b its F in e G a in MUX P ix e l R a te G u a ra n te e PGA 1 4 - b it ADC C o n tro l P o rt D13~D0 SC LK CS SDATA
CDSCLK1
CDSCLK2
AD CCLK
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HT82V14
Pin Assignment
CDSCLK1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CDSCLK2 AD CCLK OE DRVDD DRVSS D 1 3 /D 5 D 1 2 /D 4 D 1 1 /D 3 D 1 0 /D 2 D 9 /D 1 D 8 /D 0 D7 D6 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS R IN OFFSET G IN CML B IN REFT REF AVSS AVDD SLO AD SC LK SDATA
H T82V14 2 8 S O P /S O J
Pin Description
Pin No. 1 2 3 4 5 6 14~7 15 16 17 18, 27 19, 28 20 21 22 23 24 25 26 Pin Name CDSCLK1 CDSCLK2 ADCCLK OE DRVDD DRVSS D0~D13 SDATA SCLK CS AVSS AVDD REF REFT BIN CML GIN OFFSET RIN I/O DI DI DI DI 3/4 3/4 DO DIO DI DI 3/4 3/4 AO AO AI AO AI AO AI Description CDS reset clock pulse input CDS data clock pulse input A/D sample clock input for 3-channels mode Output enable Digital driver power Digital driver ground Digital data output Serial data input/output Clock input for serial interface Chip select Analog ground +5V analog supply Reference decoupling Reference decoupling Analog Input, blue Internal reference output Analog Input, green CIS reference decoupling Analog input, red
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Absolute Maximum Ratings
Supply Voltage .............................-0.3V to 5.5V Input Voltage ................VSS-0.3V to VDD+0.3V Storage Temperature ......................0C to 70C Operating Temperature ...............25C to 50C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Electrical Characteristics
Symbol Parameter Test Conditions VDD 5V10% 5V10% 5V10% 5V10% 5V10% Conditions 3/4 3/4 3/4 3/4 3/4 Min. Typ. Max. Unit
Conversion Rate 3-channel Mode with CDS 1-channel Mode with CDS A/D Converter Resolution Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Analog Inputs Full-scale Input Range Input Limits Input Capacitance Input Current Amplifiers Coarse Gain Range Coarse Gain Resolution PGA Gain Range PGA Gain Resolution Offset Range Offset Resolution 5V10% 5V10% 5V10% 5V10% 5V10% 5V10% 3/4 3/4 3/4 3/4 3/4 3/4 1 3/4 1 3/4 -200 3/4 3/4 2 3/4 5 3/4 8 3 3/4 2 3/4 200 3/4 V/V Bits V/V Bits mV Bits 5V10% 5V10% 5V10% 5V10% 3/4 3/4 3/4 3/4 3/4 AVDD-0.3 3/4 3/4 4 3/4 TBD TBD 3/4 AVDD+0.3 3/4 3/4 Vp-p V pF mA 3/4 3/4 -0.5 14 4.5 3/4 3/4 3/4 1.2 BIT LSB LSB 3/4 3/4 3/4 3/4 6 5 MSPS MSPS
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Symbol Power Supplies AVDD DRVDD Power Consumption Power Consumption Digital Specifications Symbol Logic Inputs VIH VIL IIH IIL CIN VOH VOH VOL VOL COUT High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance High Level Output Voltage High Level Output Voltage Low Level Output Voltage Low Level Output Voltage Output Capacitance 3.3V~5V 3.3V~5V 3.3V~5V 3.3V~5V 3.3V~5V 3/4 3/4 3/4 3/4 3/4 2.0 3/4 3/4 3/4 3/4 4.5 2.4 3/4 3/4 3/4 3/4 3/4 10 10 10 4.9 3/4 3/4 3/4 5 3/4 0.8 3/4 3/4 3/4 3/4 3/4 0.1 0.4 3/4 V V mA mA pF V V V V pF Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit 5V10% 3/4 3/4 350 3/4 mW 5V10% 5V10% 3/4 3/4 4.75 4.75 3/4 3/4 5.25 5.25 V V Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit
Logic Outputs 3.3V~5V IOH=50mA 3.3V~5V IOH=0.5mA 3.3V~5V IOL=-50mA 3.3V~5V IOL=-0.6mA 3.3V~5V 3/4
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Timing Diagrams
Timing Mode A B C D Mode A
P ix e l n A n a lo g In p u t tA
D
Sensor Mode CDS CDS CIS/SHA CIS/SHA
Channel Mode 3-channel internally-defined and pixel-rate mux (00) 1-channel internally-defined mux (01) 3-channel internally-defined and pixel-rate mux (00) 1-channel internally-defined mux (01)
P ix e l n + 1 tA
D
tC CDSCLK1
1A
tC
1C2A
tC
2C1A
tC
RA
tC CDSCLK2
2A
tN AD CCLK R G tC
P
VP
tS
TL1
tN R
VP
B
G
B
R G
B
D13~D0
R (n -4 ) D13~D6
R (n -4 ) D5~D0
G (n -4 ) D13~D6
G (n -4 ) D5~D0
B (n -4 ) D13~D6
B (n -4 ) D5~D0
R (n -3 ) D13~D6
R (n -3 ) D5~D0
G (n -3 ) D13~D6
G (n -3 ) D5~D0
B (n -3 ) D13~D6
B (n -3 ) D5~D0
R (n -2 ) D13~D6
R (n -2 ) D5~D0
Note: DATA timing from pixel to pixel is decided by the first rising edge of ADCCLK when CDSCLK2 is from high to low. Mode B
P ix e l n A n a lo g In p u t tA
D
P ix e l n + 1
P ix e l n + 2
tA
D
tC CDSCLK1
1B
tC
1C2B
tC
2C1B
tC
RB
tC
2B
CDSCLK2
D13~D0
D (n -1 0 ) D13~D6
D (n -1 0 ) D5~D0
D (n -9 ) D13~D6
D (n -9 ) D5~D0
D (n -8 ) D13~D6
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HT82V14
Mode C
A n a lo g In p u t P ix e l n P ix e l n + 1 P ix e l n + 2
tC CDSCLK2 tN AD CCLK
VP
1A
tA
D
tC
RA
tS B
TL
R G tC
P
B
R G
B
D13~D0
B (n -4 ) D13~D6
B (n -4 ) D5~D0
R (n -3 ) D13~D6
R (n -3 ) D5~D0
G (n -3 ) D13~D6
G (n -3 ) D5~D0
B (n -3 ) D13~D6
B (n -3 ) D5~D0
R (n -2 ) D13~D6
R (n -2 ) D5~D0
G (n -2 ) D13~D6
G (n -2 ) D5~D0
B (n -2 ) D13~D6
B (n -2 ) D5~D0
Mode D
P ix e l n A n a lo g In p u t tA
D
P ix e l n + 1
P ix e l n + 2
P ix e l n + 3
P ix e l n + 4
P ix e l n + 5
P ix e l n + 6
tS CDSCLK1 D13~D0
D (n -1 0 ) D13~D6
TL1
tS
TL1
tC
RB
D (n -1 0 ) D5~D0
D (n -9 ) D13~D6
D (n -9 ) D5~D0
D (n -8 ) D13~D6
D (n -8 ) D5~D0
D (n -7 ) D13~D6
D (n -7 ) D5~D0
D (n -6 ) D13~D6
D (n -6 ) D5~D0
D (n -5 ) D13~D6
D (n -5 ) D5~D0
D (n -4 ) D13~D6
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HT82V14
Interface Timing
SDATA SC LK tL
S
R /W b
tD
H
A2
A1
A0
tD
S
D7
D6
D5
D4
D3
D2
D1
D0
tL
H
CS
I/O write operation timing
SDATA SC LK tL
S
R /W b
tD
H
A2
A1
A0
tD
S
D7
tR
D6
DV
D5
D4
D3
D2
D1
D0
tL
H
CS
I/O read operation timing
*C L K tO
D
tO
D
D13~D0 tH
Z
tE
DV
OE N o te : * C L K : M o d e A ,C re fe re n c e A D C C L K M o d e B r e fe r e n c e fr o m th e v is in g e d g e o f C D S C L K 1 to th e fa llin g e d g e o f C D S C L K 2 M o d e D re fe re n c e C D S C L K 1
Digital output timing
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Analog Timing Specification Symbol tCRA tCRB tC1A tC1B tC2A tC2B tC2C1A tC2C1B tC1C2A tC1C2B tCP tSTL1 tAD tNVP Parameter 3-channel Conversion Rate 1-channel Conversion Rate CDSCLK1 Pulse Width CDSCLK1 Pulse Width CDSCLK2 Pulse Width CDSCLK2 Pulse Width CDSCLK2 Falling to CDSCLK1 Rising CDSCLK2 Falling to CDSCLK1 Rising CDSCLK1 Falling to CDSCLK2 Rising CDSCLK1 Falling to CDSCLK2 Rising ADCCLK Period 3-Channel Settling Time Aperture Delay Non-overlapping Space Min. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Typ. 500 200 50 50 50 50 85 80 20 20 166 80 10 5 Max. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Digital Timing Specification Symbol Data Output tOD tEDV tHZ Output Delay 3-state to Data Valid Output Enable High to 3-state Latency Interface Timing tDS tDH tLS tLH tRDV Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Read Data Valid Time 3/4 3/4 3/4 3/4 3/4 5 5 5 5 3 3/4 3/4 3/4 3/4 3/4 ns ns ns ns ns 3/4 15 5 3/4 25 3/4 3/4 9 3/4 3/4 3/4 3/4 ns ns ns ADCCLK Cycles Parameter Min. Typ. Max. Unit
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Register Overview A2 0 0 0 0 1 1 1 1 Bit 7 6 5 4 3 2 1 0 A1 0 0 1 1 0 0 1 1 Function A0 0 1 0 1 0 1 0 1 Configuration Register Red Gain Register Green Gain Register Blue Gain Register Red Offset Register Green Offset Register Blue Offset Register Color Index Register Register
* Configuration register
Sensor mode Sensor mode Clamp mode Clamp mode External VREF Channel mode Channel mode External CIS reference
* Description of configuration register
7 0 0 1 1 5 0 0 1 1 2 0 0
6 0 1 0 1 4 0 1 0 1 1 0 1
Mode CDS CIS SHA Reserved Mode Reserved Pixel Clamp No Clamp Reserved Mode 0 1 For CCD
Function For CIS dark reference: 1.4V For CIS dark reference: 0V Function For CDS pixel-by-pixel clamp For CDS reset reference<5V Function 3-channel pixel-rate mux 1-channel for internal define
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Gain registers for R, G and B Bit 7 6 5 4 3 2 1 0 LSB of Fine Gain (PGA) Note: VGA: Variable Gain Amplifier, formula: gain=1+ x where x=0~3 1.5 PGA: Programmable Gain Amplifier (PGA): specifies R, G, B sequence by color index register, x where x=0~31 formula: gain=1+ 31 Offset registers for R, G and B Bit 7 6 5 4 3 2 1 0 LSB of Offset word Note: Offset range from -200mV to +200mV, 8-bit, 256 levels; (00.....0) equal to -200mV, (100.....0) equal to 0mV, and (11.....1) equal to +198.4mV. Color index register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reserved Reserved Reserve Index for 3 channel mode Index for 3 channel mode Index for 3 channel mode Index for 1 channel mode Index for 1 channel mode Function MSB of Offset word Function MSB of Coarse Gain (VGA) LSB of Coarse Gain (VGA) Reserved MSB of Fine Gain (PGA)
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HT82V14
* Truth table for 1 channel index mode
Bit1 0 0 1 1 Bit4 0 0 0 0 1 1 1 1
Bit0 0 1 0 1 Bit3 0 0 1 1 0 0 1 1 R channel G channel B channel Reserved Bit2 0 1 0 1 0 1 0 1 R(R)G(R)B R(R)B(R)G G(R)R(R)B G(R)B(R)R B(R)R(R)G B(R)G(R)R Reserved Reserved
* Truth table for 3 channel index mode
Application Circuits
1 2 3 4 0 .1 m F 6 7 8 9 10 11 12 13 14 5 CDSCLK1 CDSCLK2 AD CCLK OE DRVDD DRVSS D 1 3 /D 5 D 1 2 /D 4 D 1 1 /D 3 D 1 0 /D 2 D 9 /D 1 D 8 /D 0 D7 D6 AVDD AVSS R IN OFFSET G IN CML B IN REFT REF AVSS AVDD SLO AD SC LK SDATA 28 27 26 25 24 22 21 20 19 18 17 16 15 10mF 0 .1 m F 0 .1 m F 0 .1 m F 2 3 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F
0 .1 m F
H T82V14
Note: Decoupling capacitor of RIN, GIN, BIN may change its value from 300pF to 0.1mF depending on the system environment.
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HT82V14
Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright O 2000 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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