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S71AL016D based MCPs
Stacked Multi-Chip Product (MCP) Flash Memory and RAM 16 Megabit (1 M x 16-bit) CMOS 3.0 Volt-only Flash Memory and 2 Megabit (128K x 16-bit) Static RAM/ Pseudo Static RAM Distinctive Characteristics
MCP Features
Power supply voltage of 2.7 to 3.1 volt High performance -- 70 ns Packages -- 7 x 9 x 1.2 mm 56 ball FBGA Operating Temperature -- -25C to +85C (Wireless)
ADVANCE INFORMATION
General Description
The S71AL series is a product line of stacked Multi-Chip Product (MCP) packages and consists of: One S29AL Flash memory die pSRAM or SRAM The products covered by this document are listed in the table below: Flash Memory Density 16Mb SRAM Density 2Mb S71AL016D02
Publication Number S71AL016D_02_04_00
Revision A
Amendment 1
Issue Date November 11, 2004
Preliminary
Product Selector Guide
16 Mb Flash Memory
Device-Model# S71AL016D02-TF S71AL016D02-BF S71AL016D02-T7 S71AL016D02-B7 Flash Access time (ns) 70 70 70 70 SRAM density 2 M SRAM 2 M SRAM 2 M SRAM 2 M SRAM (p)SRAM Access time (ns) 70 70 70 70 SRAM type SRAM2 SRAM2 SRAM1 SRAM1 Package TLC056 TLC056 TLC056 TLC056
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S71AL016D based MCPs
S71AL016D_02_04_00_A1 November 11, 2004
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Information
TABLE OF CONTENTS
S71AL016D based MCPs
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
MCP Features ........................................................................................................ 1
Write Operation Status . . . . . . . . . . . . . . . . . . . . 34
DQ7: Data# Polling ............................................................................................ 34
Figure 5. Data# Polling Algorithm ........................................ 35
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2
16 Mb Flash Memory .............................................................................................2
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .8 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . .9 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 10
TLC056--56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7 mm Package ............................................................................................... 10
RY/BY#: Ready/Busy# ....................................................................................... 35 DQ6: Toggle Bit I ............................................................................................... 36 DQ2: Toggle Bit II .............................................................................................. 36 Reading Toggle Bits DQ6/DQ2 ..................................................................... 37
Figure 6. Toggle Bit Algorithm ............................................. 38
DQ5: Exceeded Timing Limits ........................................................................ 38 DQ3: Sector Erase Timer ................................................................................ 39
Table 10. Write Operation Status ......................................... 39 Figure 7. Maximum Negative Overshoot Waveform ................ 40 Figure 8. Maximum Positive Overshoot Waveform.................. 40
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents).................................................. 42 Figure 10. Typical ICC1 vs. Frequency ................................... 43 Figure 11. Test Setup......................................................... 44 Table 11. Test Specifications ............................................... 44 Figure 12. Input Waveforms and Measurement Levels ............ 45
S29AL016D
General Description 12
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 1. S29AL016D Device Bus Operations .......................... 15
Read Operations .................................................................................................46
Figure 13. Read Operations Timings..................................... 46
Word/Byte Configuration .................................................................................15 Requirements for Reading Array Data ..........................................................15 Writing Commands/Command Sequences ................................................. 16 Program and Erase Operation Status ........................................................... 16 Standby Mode ....................................................................................................... 16 Automatic Sleep Mode .......................................................................................17 RESET#: Hardware Reset Pin ..........................................................................17 Output Disable Mode .........................................................................................17
Table 2. Sector Address Tables (Top Boot Device) ................. 18 Table 3. Sector Address Tables (Bottom Boot Device) ............ 19
Hardware Reset (RESET#) .............................................................................. 47
Figure 14. RESET# Timings................................................. 47
Word/Byte Configuration (BYTE#) ...........................................................48
Figure 15. BYTE# Timings for Read Operations...................... 48 Figure 16. BYTE# Timings for Write Operations ..................... 49
Erase/Program Operations ..............................................................................50
Figure 17. Program Operation Timings ................................. 51 Figure 18. Chip/Sector Erase Operation Timings .................... 52 Figure 19. Data# Polling Timings (During Embedded Algorithms).. 53 Figure 20. Toggle Bit Timings (During Embedded Algorithms).. 53 Figure 21. DQ2 vs. DQ6 for Erase and Erase Suspend Operations . 54 Figure 22. Temporary Sector Unprotect/Timing Diagram......... 54 Figure 23. Sector Protect/Unprotect Timing Diagram .............. 55 Figure 24. Alternate CE# Controlled Write Operation Timings .. 57
Autoselect Mode ................................................................................................ 20
Table 4. S29AL016D Autoselect Codes (High Voltage Method) . 20
Sector Protection/Unprotection ................................................................... 20 Temporary Sector Unprotect ......................................................................... 21
Figure 1. Temporary Sector Unprotect Operation.................... 21 Figure 2. In-System Sector Protect/Unprotect Algorithms ........ 22
Common Flash Memory Interface (CFI) . . . . . . .23
Table 5. Table 6. Table 7. Table 8. CFI Query Identification String ................................ 23 System Interface String ......................................... 24 Device Geometry Definition .................................... 24 Primary Vendor-Specific Extended Query ................. 25
TSOP and BGA Pin Capacitance . . . . . . . . . . . . 58
2Mbit Type 1 SRAM
Common Features . . . . . . . . . . . . . . . . . . . . . . . . 59 Functional Description . . . . . . . . . . . . . . . . . . . . . 60 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 These parameters are verified in device characterization and are not 100% tested. . . . . . 60 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 60 Operating Characteristics (Over Specified Temperature Range) . . . . . . . . . . . . . . . . . . . . . . . 61 Timing Test Conditions . . . . . . . . . . . . . . . . . . . . 62 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 2. Timing of Read Cycle (CE# = OE# = VIL, WE# = CE2= VIH) ................................................................................. 64 Figure 3. Timing Waveform of Read Cycle (WE# = VIH) .......... 64 Figure 4. Timing Waveform of Write Cycle (WE# Control) ....... 65 Figure 5. Timing Waveform of Write Cycle (CE1# Control) ...... 65 Figure 1. Power Savings with Page Mode (WE# = VIH) ........... 62
Hardware Data Protection ..............................................................................25 Low VCC Write Inhibit ..................................................................................25 Write Pulse "Glitch" Protection ................................................................25 Logical Inhibit .................................................................................................. 26 Power-Up Write Inhibit ............................................................................... 26 Reading Array Data ............................................................................................27 Reset Command ..................................................................................................27 Autoselect Command Sequence ....................................................................27 Word/Byte Program Command Sequence ................................................ 28 Unlock Bypass Command Sequence ........................................................ 28
Figure 3. Program Operation................................................ 29
Chip Erase Command Sequence ................................................................... 29 Sector Erase Command Sequence ................................................................ 30 Erase Suspend/Erase Resume Commands ....................................................31
Figure 4. Erase Operation.................................................... 32
Command Definitions ........................................................................................33
Table 9. S29AL016D Command Definitions ........................... 33
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2Mbit Type 2 SRAM
Common Features . . . . . . . . . . . . . . . . . . . . . . . . 66 Functional Description . . . . . . . . . . . . . . . . . . . . . 66 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . 66
Operating Range ..................................................................................................67 Product Portfolio ................................................................................................67 Electrical Characteristics ..................................................................................67
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . 71
Figure 3. Read Cycle 1 (Address Transition Controlled) ........... Figure 4. Read Cycle 2 (OE# Controlled)............................... Figure 5. Write Cycle 1 (WE# Controlled).............................. Figure 6. Write Cycle 2 (CE# Controlled) .............................. Figure 7. Write Cycle 3 (WE# Controlled, OE# LOW) .............. Figure 8. Write Cycle 4 (BHE#/BLE# Controlled, OE# Low) ..... 71 71 72 73 73 74
Typical DC and AC Parameters . . . . . . . . . . . . . 74
Figure 9. Operating Current vs. Supply Voltage ..................... 74 Figure 10. Standby Current vs. Supply Voltage...................... 74 Figure 11. Access Time vs. Supply Voltage............................ 75
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 AC Test Loads and Waveforms . . . . . . . . . . . . . 68
Figure 1. AC Test Loads and Waveforms................................ 68
Data Retention Characteristics (Over the Operation Range) . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 2. Data Retention Waveform ...................................... 69
Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 1. Truth Table ........................................................... 75
Switching Characteristics . . . . . . . . . . . . . . . . . . 70
Revision Summary
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Preliminary
MCP Block Diagram
VCCf
VCC CE#f
RST#f Flash 1 Shared Address OE# WE# VSS RY/BY# A19-A0
VCCS
DQ15 to DQ0
VCC A16-A0 pSRAM/SRAM
IO15-IO0 CE1#s UB# LB# CE2s CE1# UB# LB# CE2
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Preliminary
Connection Diagram
56-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)
A2 A7 B1 A3 C1 A2 D1 A1 E1 A0 F1 CE1#f G1 CE1#s B2 A6 C2 A5 D2 A4 E2 VSS F2 OE# G2 DQ0 H2 DQ8
A3 LB# B3 UB# C3 A18 D3 A17 E3 DQ1 F3 DQ9 G3 DQ10 H3 DQ2
A4 RFU B4 RST#f C4 RY/BY#
A5 WE# B5 CE2s C5 RFU
A6 A8 B6 A19 C6 A9 D6 A10 E6 DQ6
A7 A11 B7 A12 C7 A13 D7 A14 E7 RFU F7 DQ15 G7 DQ7 H7 DQ14 B8
Legend
Flash only
A15 C8 RFU D8 RFU E8 A16 F8 RFU G8 VSS
RAM only
Reserved for Future Use
F4 DQ3 G4 VCCf H4 DQ11
F5 DQ4 G5 VCCs H5 RFU
F6 DQ13 G6 DQ12 H6 DQ5
MCP S71AL016D02
Flash Only Address A19-A17
Shared Addresses A16-A0
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Preliminary
Pin Description
A16-A0 A19-A17 DQ15-DQ0 CE1#f CE1#s CE2s OE# WE# RY/BY# UB# LB# RST#f VCCf = = = = = = = = = = = = = 17 Address Inputs (Common) 3 Address Inputs (Flash) 16 Data Inputs/Outputs (Common) Chip Enable 1 (Flash) Chip Enable 1 (SRAM) Chip Enable 2 (SRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Output (Flash) Upper Byte Control (SRAM) Lower Byte Control (SRAM) Hardware Reset Pin, Active Low (Flash) Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) pSRAM Power Supply Device Ground (Common) Pin Not Connected Internally Reserved for Future Use
VCCs VSS NC RFU
= = = =
Logic Symbol
20 A19-A0 16 CE# CE1#s CE2s OE# WE# RST#f UB# LB# RY/BY# DQ15-DQ0
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Preliminary
Ordering Information
The order number is formed by a valid combinations of the following: S71AL 016 D 02 BA W T F 0
PACKING TYPE 0 = Tray 2 = 7" Tape and Reel 3 = 13" Tape and Reel MODEL NUMBER See the Valid Combinations table. BOOT TYPE T = Top Boot B = Bottom Boot TEMPERATURE RANGE W = Wireless (-25C to +85C) PACKAGE TYPE BA = Fine-pitch BGA Lead (Pb)-free compliant package BF = Fine-pitch BGA Lead (Pb)-free package SRAM DENSITY 02 = 2Mb SRAM PROCESS TECHNOLOGY D = 200 nm, Floating Gate Technology FLASH DENSITY 016 = 16Mb PRODUCT FAMILY S71AL Multi-chip Product (MCP) 3.0-volt Flash Memory and RAM
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Preliminary
Valid Combinations
S71AL016D Valid Combinations Base Ordering Part Number S71AL016D02 S71AL016D02 S71AL016D02 S71AL016D02 BAW BFW Package & Temperature Package Modifier/ Model Number TF BF T7 B7 0, 2, 3 (Note 1) 70 Packing Type Speed Options (ns) (p)SRAM Type/Access Time (ns) SRAM2/ 70 SRAM2 / 70 SRAM1 / 70 SRAM1 / 70 Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Package Marking (Note 2)
Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading "S" and packing type designator from ordering part number.
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Preliminary
Physical Dimensions
TLC056--56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7 mm Package
D
0.15 C (2X)
8 7 6
A
D1 eD
SE 7 E1
E eE
5 4 3 2 1
INDEX MARK PIN A1 CORNER 10
H
G
F
E
D
CB
A
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW
0.20 C
A A2 A1
6
C
0.08 C
SIDE VIEW b
56X
0.15 M C A B 0.08 M C
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n b eE eD SD / SE 0.35 TLC 056 N/A 9.00 mm x 7.00 mm PACKAGE MIN --0.20 0.81 NOM ------9.00 BSC. 7.00 BSC. 5.60 BSC. 5.60 BSC. 8 8 56 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. A1,A8,D4,D5,E4,E5,H1,H8 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3348 \ 16-038.22a
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S29AL016D
16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory Datasheet Distinctive Characteristics
Architectural Advantages
Single power supply operation
-- Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications
ADVANCE INFORMATION
Performance Characteristics
High performance
-- Access times as fast as 70 ns
Manufactured on 200nm process technology
-- Fully compatible with 0.23 m Am29LV160D and MBM29LV160E devices
Ultra low power consumption (typical values at 5 MHz)
-- 200 nA Automatic Sleep mode current -- 200 nA standby mode current -- 9 mA read current -- 20 mA program/erase current
Flexible sector architecture
-- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirtyone 64 Kbyte sectors (byte mode) -- One 8 Kword, two 4 Kword, one 16 Kword, and thirtyone 32 Kword sectors (word mode)
Sector Protection features
-- A hardware method of locking a sector to prevent any program or erase operations within that sector -- Sectors can be locked in-system or via programming equipment -- Temporary Sector Unprotect feature allows code changes in previously locked sectors
Cycling endurance: 1,000,000 cycles per sector typical Data retention: 20 years typical
Software Features
CFI (Common Flash Interface) compliant
-- Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices
Unlock Bypass Program Command
-- Reduces overall programming time when issuing multiple program command sequences
Erase Suspend/Erase Resume
-- Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
Top or bottom boot block configurations available Compatibility with JEDEC standards
-- Pinout and software compatible with single-power supply Flash -- Superior inadvertent write protection
Data# Polling and toggle bits
-- Provides a software method of detecting program or erase operation completion
Hardware Features
Ready/Busy# pin (RY/BY#)
-- Provides a hardware method of detecting program or erase cycle completion
Hardware reset pin (RESET#)
-- Hardware method to reset the device to reading array data
Publication Number S29AL016D_00
Revision A
Amendment 1
Issue Date August 4, 2004
Advance
Information
General Description
The S29AL016D is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The device is offered in 48-ball FBGA, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15-DQ0; the byte-wide (x8) data appears on DQ7-DQ0. This device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. A 12.0 V VPP or 5.0 VCC are not required for write or erase operations. The device can also be programmed in standard EPROM programmers. The device offers access times of 70 ns and 90 ns allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The S29AL016D is entirely command set compatible with the JEDEC singlepower-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm--an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm--an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.
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The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. Spansion's Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fo wl e r -Nordheim tunneling. The data is programmed using hot electron injection.
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Product Selector Guide
Family Part Number Speed Option Voltage Range: VCC = 2.7-3.6 V S29AL016D 70 70 70 30 90 90 90 35
Max access time, ns (tACC) Max CE# access time, ns (tCE) Max OE# access time, ns (tOE) Note: See "AC Characteristics" for full specifications.
Block Diagram
RY/BY#
VCC VSS Sector Switches Erase Voltage Generator Input/Output Buffers
DQ0-DQ15 (A-1)
RESET#
WE# BYTE#
State Control Command Register
PGM Voltage Generator Chip Enable Output Enable Logic STB Data Latch
CE# OE#
STB VCC Detector Address Latch
Y-Decoder
Y-Gating
Timer
X-Decoder
Cell Matrix
A0-A19
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Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
Table 1.
S29AL016D Device Bus Operations
DQ8-DQ15 Addresses (Note 1) AIN AIN X X X Sector Address, A6 = L, A1 = H, A0 = L Sector Address, A6 = H, A1 = H, A0 = L AIN DQ0- DQ7 DOUT DIN High-Z High-Z High-Z DIN BYTE# = VIH DOUT DIN High-Z High-Z High-Z X BYTE# = VIL DQ8-DQ14 = High-Z, DQ15 = A-1 High-Z High-Z High-Z X
Operation Read Write Standby Output Disable Reset Sector Protect (Note 2)
CE# L L VCC 0.3 V L X L
OE# WE# RESET# L H X H X H H L X H X L H H VCC 0.3 V H L VID
Sector Unprotect (Note 2) Temporary Sector Unprotect Legend:
L X
H X
L X
VID VID
DIN DIN
X DIN
X High-Z
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.5 V, X = Don't Care, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL). 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the "Sector Protection/Unprotection" section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15-DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic `1', the device is in word configuration, DQ15-DQ0 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic `0', the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/ O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control
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and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data" for more information. Refer to the AC Read Operations table for timing specifications and to Figure 13 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to "Word/Byte Configuration" for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The "Word/Byte Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A "sector address" consists of the address bits required to uniquely select a sector. The "Command Definitions" section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7-DQ0. Standard read cycle timings apply in this mode. Refer to the "Autoselect Mode" and "Autoselect Command Sequence" sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7-DQ0. Standard read cycle timings and ICC read specifications apply. Refer to "Write Operation Status" for more information, and to "AC Characteristics" for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and
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the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. In the DC Characteristics table, ICC3 and ICC4 represents the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the system drives the RESET# pin to VIL for at least a period of tRP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/ BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.
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Table 2.
Sector Address Tables (Top Boot Device)
Sector Size (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 32/16 8/4 8/4 16/8 Address Range (in hexadecimal) Byte Mode (x8) 000000-00FFFF 010000-01FFFF 020000-02FFFF 030000-03FFFF 040000-04FFFF 050000-05FFFF 060000-06FFFF 070000-07FFFF 080000-08FFFF 090000-09FFFF 0A0000-0AFFFF 0B0000-0BFFFF 0C0000-0CFFFF 0D0000-0DFFFF 0E0000-0EFFFF 0F0000-0FFFFF 100000-10FFFF 110000-11FFFF 120000-12FFFF 130000-13FFFF 140000-14FFFF 150000-15FFFF 160000-16FFFF 170000-17FFFF 180000-18FFFF 190000-19FFFF 1A0000-1AFFFF 1B0000-1BFFFF 1C0000-1CFFFF 1D0000-1DFFFF 1E0000-1EFFFF 1F0000-1F7FFF 1F8000-1F9FFF 1FA000-1FBFFF 1FC000-1FFFFF Word Mode (x16) 00000-07FFF 08000-0FFFF 10000-17FFF 18000-1FFFF 20000-27FFF 28000-2FFFF 30000-37FFF 38000-3FFFF 40000-47FFF 48000-4FFFF 50000-57FFF 58000-5FFFF 60000-67FFF 68000-6FFFF 70000-77FFF 78000-7FFFF 80000-87FFF 88000-8FFFF 90000-97FFF 98000-9FFFF A0000-A7FFF A8000-AFFFF B0000-B7FFF B8000-BFFFF C0000-C7FFF C8000-CFFFF D0000-D7FFF D8000-DFFFF E0000-E7FFF E8000-EFFFF F0000-F7FFF F8000-FBFFF FC000-FCFFF FD000-FDFFF FE000-FFFFF
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34
A19 A18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
A17 A16 A15 A14 A13 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1
A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X
Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See "Word/Byte Configuration" section.
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Table 3.
Sector Address Tables (Bottom Boot Device)
Sector Size (Kbytes/ Kwords) 16/8 8/4 8/4 32/16 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 Address Range (in hexadecimal) Byte Mode (x8) 000000-003FFF 004000-005FFF 006000-007FFF 008000-00FFFF 010000-01FFFF 020000-02FFFF 030000-03FFFF 040000-04FFFF 050000-05FFFF 060000-06FFFF 070000-07FFFF 080000-08FFFF 090000-09FFFF 0A0000-0AFFFF 0B0000-0BFFFF 0C0000-0CFFFF 0D0000-0DFFFF 0E0000-0EFFFF 0F0000-0FFFFF 100000-10FFFF 110000-11FFFF 120000-12FFFF 130000-13FFFF 140000-14FFFF 150000-15FFFF 160000-16FFFF 170000-17FFFF 180000-18FFFF 190000-19FFFF 1A0000-1AFFFF 1B0000-1BFFFF 1C0000-1CFFFF 1D0000-1DFFFF 1E0000-1EFFFF 1F0000-1FFFFF Word Mode (x16) 00000-01FFF 02000-02FFF 03000-03FFF 04000-07FFF 08000-0FFFF 10000-17FFF 18000-1FFFF 20000-27FFF 28000-2FFFF 30000-37FFF 38000-3FFFF 40000-47FFF 48000-4FFFF 50000-57FFF 58000-5FFFF 60000-67FFF 68000-6FFFF 70000-77FFF 78000-7FFFF 80000-87FFF 88000-8FFFF 90000-97FFF 98000-9FFFF A0000-A7FFF A8000-AFFFF B0000-B7FFF B8000-BFFFF C0000-C7FFF C8000-CFFFF D0000-D7FFF D8000-DFFFF E0000-E7FFF E8000-EFFFF F0000-F7FFF F8000-FFFFF
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34
A19 A18 A17 A16 A15 A14 A13 A12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
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Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See the "Word/Byte Configuration" section.
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Table 4. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Tables 2 and 3). Table 4 shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 9. This method does not require VID. See "Command Definitions" for details on using the autoselect mode.
Table 4.
S29AL016D Autoselect Codes (High Voltage Method)
A19 A11 to to OE# WE# A12 A10 L L L L L H H H H H X X VID X L L L H X X VID X L L L H X X A8 to A7 X A3 to A2 L DQ8 to DQ15 X 22h X 22h X X DQ7 to DQ0 01h C4h C4h 49h 49h 01h (protected) 00h (unprotected)
Description
Mode
CE# L L L L L
A9 VID
A6 L
A1 L
A0 L
Manufacturer ID: Spansion Device ID: S29AL016D (Top Boot Block) Device ID: S29AL016D (Bottom Boot Block) Word Byte Word Byte
Sector Protection Verification
L
L
H
SA
X
VID
X
L
L
H
L X
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care.
Note: The autoselect codes may also be accessed in-system via command sequences. See Table 9.
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. The device is shipped with all sectors unprotected. Spansion offers the option of programming and protecting sectors at its factory prior to shipping the device through Spansion's ExpressFlashTM Service. Contact a Spansion representative for details.
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It is possible to determine whether a sector is protected or unprotected. See "Autoselect Mode" for details. Sector protection/unprotection can be implemented via two methods. The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 23 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is compatible with programmer routines written for earlier 3.0 volt-only Spansion flash devices. Details on this method are provided in a supplement, publication number 21468. Contact a Spansion representative to request a copy.
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. shows the algorithm, and Figure 22 shows the timing diagrams, for this feature.
START
RESET# = VID (Note 1) Perform Erase or Program Operations
RESET# = VIH
Temporary Sector Unprotect Completed (Note 2)
Notes: 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again.
Figure 1.
Temporary Sector Unprotect Operation
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START PLSCNT = 1 RESET# = VID Wait 4 s Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address
START PLSCNT = 1 RESET# = VID Wait 4 s
Temporary Sector Unprotect Mode
No
First Write Cycle = 60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A7-A0 = 00000010 Wait 100 s Verify Sector Protect: Write 40h to sector address with A7-A0 = 00000010 Read from sector address with A7-A0 = 00000010 No
First Write Cycle = 60h? Yes All sectors protected? Yes Set up first sector address
No
Temporary Sector Unprotect Mode
Sector Unprotect: Write 60h to sector address with A7-A0 = 01000010 Reset PLSCNT = 1 Wait 1.2 ms Verify Sector Unprotect: Write 40h to sector address with A7-A0 = 00000010
Increment PLSCNT
No No PLSCNT = 25? Yes Remove VID from RESET# Data = 01h?
Increment PLSCNT
Yes
No Yes No
Read from sector address with A7-A0 = 00000010 Set up next sector address
Protect another sector? No Remove VID from RESET#
PLSCNT = 1000? Yes Remove VID from RESET#
Data = 00h? Yes
Write reset command
Sector Protect complete Write reset command Device failed
Last sector verified? Yes Remove VID from RESET#
No
Write reset command Sector Unprotect complete
Sector Protect complete
Sector Protect Algorithm
Write reset command Device failed Sector Unprotect complete
Sector Unprotect Algorithm
Figure 2. 22 In-System Sector Protect/Unprotect Algorithms S29AL016D S29AL016D_00_A1_E August 4, 2004
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Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 5-8. In word mode, the upper address bits (A7- MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 5-8. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/products/nvd/ overview/cfi.html. Alternatively, contact a Spansion representative for copies of these documents.
Table 5.
Addresses (Word Mode) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Addresses (Byte Mode) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h
CFI Query Identification String
Description Query Unique ASCII string "QRY"
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
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Table 6.
Addresses (Word Mode) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Addresses (Byte Mode) 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch Data 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h
System Interface String
Description VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 7.
Addresses (Word Mode) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Addresses (Byte Mode) 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h Data 0015h 0002h 0000h 0000h 0000h 0004h 0000h 0000h 0040h 0000h 0001h 0000h 0020h 0000h 0000h 0000h 0080h 0000h 001Eh 0000h 0000h 0001h
Device Geometry Definition
Description Device Size = 2 byte
N
Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
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Table 8.
Addresses (Word Mode) 40h 41h 42h 43h 44h 45h 46h 47h 48h Addresses (Byte Mode) 80h 82h 84h 86h 88h 8Ah 8Ch 8Eh 90h
Primary Vendor-Specific Extended Query
Data Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock 0 = Required, 1 = Not Required Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 01 = 29F040 mode, 02 = 29F016 mode, 03 = 29F400 mode, 04 = 29LV800A mode Simultaneous Operation 00 = Not Supported, 01 = Supported Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
0050h 0052h 0049h 0031h 0030h 0000h 0002h 0001h 0001h
49h
92h
0004h
4Ah 4Bh 4Ch
94h 96h 98h
0000h 0000h 0000h
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 9 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
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Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up.
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Command Definitions
Writing specific address and data commands or sequences into the command register initiates device operations. Table 9 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the "AC Characteristics" section.
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See "Erase Suspend/Erase Resume Commands" for more information on this mode. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the "Reset Command" section, next. See also "Requirements for Reading Array Data" in the "Device Bus Operations" section for more information. The Read Operations table provides the read parameters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don't care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected.
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Table 9 shows the address and data requirements. This method is an alternative to that shown in Table 4, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Tables 2 and 3 for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data.
Word/Byte Program Command Sequence
The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 9 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See "Write Operation Status" for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set DQ5 to "1," or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Only erase operations can convert a "0" to a "1".
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 9 shows the requirements for the command sequence.
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During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don't care for both cycles. The device then returns to reading array data. Figure 3 illustrates the algorithm for the program operation. See the Erase/Program Operations table in "AC Characteristics" for parameters, and to Figure 17 for timing diagrams.
START
Write Program Command Sequence
Embedded Program algorithm in progress
Data Poll from System
Verify Data?
No
Yes No
Increment Address
Last Address?
Yes Programming Completed
NOTE: See Table 9 for program command sequence.
Figure 3.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 9 shows the address and data requirements for the chip erase command sequence.
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Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See "Write Operation Status" for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in "AC Characteristics" for parameters, and to Figure 18 for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table 9 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the "DQ3: Sector Erase Timer" section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to "Write Operation Status" for information on these status bits.) Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and to Figure 18 for timing diagrams.
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Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are "don't-cares" when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See "Write Operation Status" for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" for more information. The system must write the Erase Resume command (address bits are "don't care") to exit the erase suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing.
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START
Write Erase Command Sequence (Notes 1, 2)
Data Poll to Erasing Bank from System
Embedded Erase algorithm in progress
No
Data = FFh?
Yes Erasure Completed
Notes: 1. See Table 9 for erase command sequence. 2. See "DQ3: Sector Erase Timer" for more information.
Figure 4.
Erase Operation
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Command Definitions
Table 9.
Command Sequence (Note 1) Read (Note 6) Reset (Note 7) Cycles First Addr RA XXX 555 AAA 555 AAA 555 AAA 555 4 Byte Word Byte Word Byte Word Byte 1 4 3 2 2 Word Byte Word Byte 6 6 1 1 AAA 55 AA 555 AAA 555 AAA XXX XXX 555 AAA 555 AAA XXX XXX 98 AA AA A0 90 AA AA B0 30 2AA 555 2AA 555 PA XXX 2AA 555 2AA 555 55 55 PD F0 55 55 555 AAA 555 AAA 80 80 555 AAA 555 AAA AA AA 2AA 555 2AA 555 55 55 555 AAA SA 10 30 555 AAA 555 AAA A0 20 PA PD AA 555 Data RD F0 AA AA AA 2AA 555 2AA 555 2AA 555 2AA 55 AAA 55 55 55 555 AAA 555 AAA 555 AAA 555 90 90 90 90 X00 X01 X02 X01 X02 (SA) X02 (SA) X04 01 22C4 C4 2249 49 XX00 XX01 00 01
S29AL016D Command Definitions
Bus Cycles (Notes 2-5) Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data
1 1 Word Byte Word Byte Word Byte Word 4 4 4
Autoselect (Note 8)
1. 2. 3. 4. 5. 6. 7. 8. 9.
Manufacturer ID
Device ID, Top Boot Block Device ID, Bottom Boot Block Sector Protect Verify (Note 9)
CFI Query (Note 10) Program Unlock Bypass
Unlock Bypass Program (Note 11) Unlock Bypass Reset (Note 12) Chip Erase Sector Erase Erase Suspend (Note 13) Erase Resume (Note 14)
Legend:
X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19-A12 uniquely select any sector.
Note:
See Table 1 for description of bus operations. All values are in hexadecimal. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. Data bits DQ15-DQ8 are don't cares for unlock and command cycles. Address bits A19-A11 are don't cares for unlock and command cycles, unless SA or PA required. No unlock or command cycles required when reading array data. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). The fourth cycle of the autoselect command sequence is a read cycle. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more information.
10. Command is valid when device is ready to read array data or when device is in autoselect mode. 11. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 12. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. F0 is also acceptable. 13. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 14. The Erase Resume command is valid only during the Erase Suspend mode.
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Write Operation Status
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 10 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then the device returns to reading array data. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to "1"; prior to this, the device outputs the "complement," or "0." The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7-DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (OE#) is asserted low. Figure 19, Data# Polling Timings (During Embedded Algorithms), in the "AC Characteristics" section illustrates this. Table 10 shows the outputs for Data# Polling on DQ7. Figure 6 shows the Data# Polling algorithm.
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START
Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No No
DQ5 = 1?
Yes Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No FAIL PASS
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because
Figure 5.
Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC.
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If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 10 shows the outputs for RY/BY#. Figures 13, 14, 17 and 18 shows RY/BY# for read, reset, program, and erase operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on "DQ7: Data# Polling"). If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 10 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section "Reading Toggle Bits DQ6/DQ2" explains the algorithm. Figure 20 in the "AC Characteristics" section shows the toggle bit timing diagrams. Figure 21 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on "DQ2: Toggle Bit II".
DQ2: Toggle Bit II
The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 10 to compare outputs for DQ2 and DQ6.
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Figure 6 shows the toggle bit algorithm in flowchart form, and the section "Reading Toggle Bits DQ6/DQ2" explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 20 shows the toggle bit timing diagram. Figure 21 shows the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6).
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START
Read Byte (DQ7-DQ0) Address =VA Read Byte (DQ7-DQ0) Address =VA
(Note 1)
Toggle Bit = Toggle? Yes
No
No
DQ5 = 1?
Yes Read Byte Twice (DQ7-DQ0) Address = VA
(Notes 1,2)
Toggle Bit = Toggle?
No
Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete
Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to "1". See text.
Figure 6.
Toggle Bit Algorithm
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1." This is a failure condition that indicates the program or erase cycle was not successfully completed.
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The DQ5 failure condition may appear if the system tries to program a "1" to a location that is previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a "1." Under both these conditions, the system must issue the reset command to return the device to reading array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from "0" to "1." The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 s. See also the "Sector Erase Command Sequence" section. After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is "1", the internally controlled erase cycle has begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0", the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 10 shows the outputs for DQ3.
Table 10.
Operation Standard Mode Erase Suspend Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Erase Suspended Sector Reading within Non-Erase Suspended Sector Erase-Suspend-Program
Write Operation Status
DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 2) No toggle Toggle Toggle Data N/A RY/BY# 0 0 1 1 0
DQ7 (Note 2) DQ7# 0 1 Data DQ7#
Notes: 1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See "DQ5: Exceeded Timing Limits" for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
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Absolute Maximum Ratings
Storage Temperature Plastic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Temperature with Power Applied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +125C Voltage with Respect to Ground VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to +4.0 V A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . . -0.5 V to +12.5 V All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC+0.5 V Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8. 2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
20 ns +0.8 V -0.5 V -2.0 V 20 ns
20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns
20 ns
Figure 7. Maximum Negative Overshoot Waveform
Figure 8.
Maximum Positive Overshoot Waveform
Operating Ranges
Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C VCC Supply Voltages VCC for standard voltage range . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
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DC Characteristics
CMOS Compatible
Parameter ILI ILIT ILO Description Input Load Current A9 Input Load Current Output Leakage Current Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; A9 = 12.5 V VOUT = VSS to VCC, VCC = VCC max 10 MHz CE# = VIL, OE# = VIH, Byte Mode ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH, Word Mode VCC Active Write Current (Notes 2, 3, 5) 5 MHz 1 MHz 10 MHz 5 MHz 1 MHz ICC2 ICC3 ICC4 ICC5 VIL VIH VID VOL VOH1 VOH2 VLKO CE# = VIL, OE# = VIH 15 9 2 18 9 2 20 0.2 0.2 0.2 -0.5 0.7 x VCC VCC = 3.3 V IOL = 4.0 mA, VCC = VCC min IOH = -2.0 mA, VCC = VCC min IOH = -100 A, VCC = VCC min 2.4 VCC-0.4 2.3 2.5 11.5 Min Typ Max 1.0 35 1.0 30 16 4 35 16 4 35 5 5 5 0.8 VCC + 0.3 12.5 0.45 mA A A A V V V V V V V mA Unit A A A
VCC Standby Current (Notes 2, 4) CE#, RESET# = VCC0.3 V VCC Standby Current During Reset RESET# = VSS 0.3 V (Notes 2, 4) Automatic Sleep Mode (Notes 2, 4, 6) Input Low Voltage Input High Voltage Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage (Note 4) VIH = VCC 0.3 V; VIL = VSS 0.3 V
Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. At extended temperature range (>+85C), typical current is 5 A and maximum current is 10 A. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 6. Not 100% tested.
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DC Characteristics (continued)
Zero Power Flash
25 Supply Current in mA 20 15 10 5 0 0 500 1000 1500 2000 Time in ns
Note: Addresses are switching at 1 MHz
2500
3000
3500
4000
Figure 9.
ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
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10 3.6 V 2.7 V 6
8 Supply Current in mA
4
2
0 1 2 3 Frequency in MHz
Note: T = 25 C
4
5
Figure 10.
Typical ICC1 vs. Frequency
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Test Conditions
3.3 V 2.7 k
Device Under Test CL 6.2 k
Note: Diodes are IN3064 or equivalent
Figure 11. Table 11.
Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels
Test Setup
Test Specifications
70 90 1 TTL gate 30 5 0.0 or VCC 0.5 VCC 0.5 VCC 100 pF ns V V V Unit
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Key to Switching Waveforms
WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS
VCC 0.0 V
Input
0.5 VCC
Measurement Level
0.5 VCC
Output
Figure 12.
Input Waveforms and Measurement Levels
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AC Characteristics
Read Operations
Parameter JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ Std tRC tACC tCE tOE tDF tDF tOEH Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Note 1) Output Enable to Output High Z (Note 1) Read Output Enable Hold Time (Note 1) Toggle and Data# Polling Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) CE# = VIL OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Min Min Min Speed Options 70 70 70 70 30 25 25 0 10 0 90 90 90 90 35 30 30 Unit ns ns ns ns ns ns ns ns ns
tAXQX
tOH
Notes: 1. Not 100% tested. 2. See Figure 11 and Table 11 for test specifications.
tRC Addresses CE# tOE tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tDF Addresses Stable tACC
OE#
0V
Figure 13.
Read Operations Timings
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AC Characteristics
Hardware Reset (RESET#)
Parameter JEDEC Std tREADY tREADY tRP tRH tRPD tRB Description RESET# Pin Low (During Embedded Algorithms) to Read or Write (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read or Write (See Note) RESET# Pulse Width RESET# High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Test Setup Max Max Min Min Min Min All Speed Options 20 500 500 50 20 0 Unit s ns ns ns s ns
Note: Not 100% tested.
RY/BY#
CE#, OE# tRH RESET# tRP tReady
Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
tReady RY/BY# tRB CE#, OE#
RESET# tRP
Figure 14.
RESET# Timings
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AC Characteristics
Word/Byte Configuration (BYTE#)
Parameter JEDEC Std tELFL/tELFH tFLQZ tFHQV Description CE# to BYTE# Switching Low or High BYTE# Switching Low to Output HIGH Z BYTE# Switching High to Output Active CE# Max Max Min 25 70 Speed Options 70 5 30 90 90 Unit ns ns ns
OE#
BYTE# tELFL
BYTE# Switching from word to byte mode
DQ0-DQ14
Data Output (DQ0-DQ14) DQ15 Output tFLQZ
Data Output (DQ0-DQ7) Address Input
DQ15/A-1
tELFH BYTE# BYTE# Switching from byte to word mode
DQ0-DQ14
Data Output (DQ0-DQ7) Address Input tFHQV
Data Output (DQ0-DQ14) DQ15 Output
DQ15/A-1
Figure 15.
BYTE# Timings for Read Operations
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S29AL016D_00_A1_E August 4, 2004
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Information
CE# The falling edge of the last WE# signal WE#
BYTE#
tSET (tAS)
tHOLD (tAH)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 16.
BYTE# Timings for Write Operations
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Information
AC Characteristics
Erase/Program Operations
Parameter JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tELWL tWHEH tWLWH tWHWL tWHWH1 tWHWH2 Std tWC tAS tAH tDS tDH tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH2 tVCS tRB tBUSY
Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information.
Speed Options Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Programming Operation (Note 2) Sector Erase Operation (Note 2) VCC Setup Time (Note 1) Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay Byte Word Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Min Min Max 35 30 5 7 0.7 50 0 90 45 35 0 0 0 0 35 70 70 0 45 45 90 90 Unit ns ns ns ns ns ns ns ns ns ns s sec s ns ns
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S29AL016D
S29AL016D_00_A1_E August 4, 2004
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Information
AC Characteristics
Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# Status DOUT tRB tWPH tWHWH1 PA PA Read Status Data (last two cycles)
tCH
A0h
VCC tVCS
Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode.
Figure 17.
Program Operation Timings
August 4, 2004 S29AL016D_00_A1_E
S29AL016D
51
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Information
AC Characteristics
Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA
555h for chip erase
Read Status Data
VA tAH
VA
CE#
OE# tWP WE# tCS tDS
tCH
tWPH
tWHWH2
tDH Data 55h 30h
10 for Chip Erase Status DOUT
tBUSY RY/BY# tVCS VCC
tRB
Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status"). 2. Illustration shows device in word mode.
Figure 18.
Chip/Sector Erase Operation Timings
52
S29AL016D
S29AL016D_00_A1_E August 4, 2004
Advance
Information
AC Characteristics
tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7
High Z
VA
VA
tOE tDF
Complement
Complement
True
Valid Data
High Z
DQ6-DQ0 tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 19.
Data# Polling Timings (During Embedded Algorithms)
tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ6/DQ2 tBUSY RY/BY#
High Z
VA
VA
VA
tOE tDF
Valid Status (first read)
Valid Status (second read)
Valid Status (stops toggling)
Valid Data
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last
status read cycle, and array data read cycle.
Figure 20.
Toggle Bit Timings (During Embedded Algorithms)
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S29AL016D
53
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Information
AC Characteristics
Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 21.
DQ2 vs. DQ6 for Erase and Erase Suspend Operations
Temporary Sector Unprotect
Parameter JEDEC Std tVIDR tRSP Description VID Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect Min Min All Speed Options 500 4 Unit ns s
Note: Not 100% tested.
12 V
RESET# 0 or 3 V tVIDR Program or Erase Command Sequence CE# tVIDR
WE# tRSP RY/BY#
Figure 22.
Temporary Sector Unprotect/Timing Diagram
54
S29AL016D
S29AL016D_00_A1_E August 4, 2004
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Information
AC Characteristics
VID VIH
RESET#
SA, A6, A1, A0
Valid* Sector Group Protect/Unprotect
Valid* Verify 40h
Valid*
Data 1 s CE#
60h
60h
Status
Sector Group Protect: 150 s Sector Group Unprotect: 15 ms
WE#
OE#
Note:
For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 23.
Sector Protect/Unprotect Timing Diagram
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Information
AC Characteristics
Alternate CE# Controlled Erase/Program Operations
Parameter JEDEC tAVAV tAVEL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH2 Std tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2 Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Programming Operation (Note 2) Sector Erase Operation (Note 2) Byte Word Min Min Min Min Min Min Min Min Min Min Typ Typ Typ 35 30 5 7 0.7 45 35 0 0 0 0 35 Speed Options 70 70 0 45 45 90 90 Unit ns ns ns ns ns ns ns ns ns ns s sec
Notes: 1. Not 100% tested. 2. See the "Erase and Programming Performance" section for more information.
56
S29AL016D
S29AL016D_00_A1_E August 4, 2004
Advance
Information
AC Characteristics
555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase
Data# Polling PA
Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH
A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase
tAS tAH
tWHWH1 or 2
tBUSY
DQ7#
DOUT
RESET#
RY/BY#
Notes: 1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device. 2. Figure indicates the last two bus cycles of the command sequence. 3. Word mode address used as an example.
Figure 24.
Alternate CE# Controlled Write Operation Timings
August 4, 2004 S29AL016D_00_A1_E
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Information
Erase and Programming Performance
Parameter Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Chip Programming Time (Note 3) Byte Mode Word Mode Typ (Note 1) 0.7 25 5 7 11 7.2 150 210 33 21.6 Max (Note 2) 10 Unit s s s s s s Excludes system level overhead (Note 5) Comments Excludes 00h programming prior to erasure (Note 4)
Notes: 1. Typical program and erase times assume the following conditions: 25C, VCC = 3.0 V, 100,000 cycles, checkerboard data pattern. 2. Under worst case conditions of 90C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 9 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 100,000 cycles per sector.
TSOP and BGA Pin Capacitance
Parameter Symbol CIN Parameter Description Input Capacitance Test Setup VIN = 0 Package TSOP BGA TSOP BGA TSOP BGA Typ 6 4.2 8.5 5.4 7.5 3.9 Max 7.5 5.0 12 6.5 9 4.7 Unit pF pF pF pF pF pF
COUT
Output Capacitance
VOUT = 0
CIN2
Control Pin Capacitance
VIN = 0
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
58
S29AL016D
S29AL016D_00_A1_E August 4, 2004
Preliminary
2Mbit Type 1 SRAM
Common Features
Single Wide Power Supply Range 2.3 to 3.6 Volts Very low standby current 2.0A at 3.0V (Typical) Very low operating current 2.0mA at 3.0V and 1s (Typical) Very low Page Mode operating current 0.8mA at 3.0V and 1s (Typical) Simple memory control Dual Chip Enables (CE1# and CE2) Byte control for independent byte operation Output Enable (OE#) for memory expansion Low voltage data retention VCC = 1.8V Very fast output enable access time 30ns OE# access time Automatic power down to standby mode TTL compatible three-state output driver Tested wafers
August 4, 2004 SRAM_Type01_03A0
2Mbit Type 1 SRAM
59
Preliminary
Functional Description
CE# H X L L L L CE2 X L H H H H WE# X X X L H H OE# X X X X (Note 3) L H UB# X X H L (Note 1) L (Note 1) L (Note 1) LB# X X H L (Note 1) L (Note 1) L (Note 1) IO0~15 (Note 1) High-Z High-Z High-Z Data In Data Out High-Z Mode Standby (Note 2) Standby (Note 2) Standby Write (Note 3) Read Active Power Standby Standby Standby Active Active Active
Notes: 1. When UB# and LB# are in select mode (low), I/O0 - I/O15 are affected as shown. When only LB# is in the select mode, only I/O0 - I/O7 are affected as shown. When UB# is in the select mode only I/O8 - I/O15 are affected as shown. 2. When the device is in standby mode, control inputs (WE#, OE#, UB#, and LB#), address inputs and data input/outputs are internally isolated from any external influence and disabled from exerting any influence externally. 3. When WE# is invoked, the OE# input is internally disabled and has no effect on the circuit.
Capacitance
Item Input Capacitance I/O Capacitance Symbol CIN CI/O Test Condition VIN = 0V, f = 1 MHz, TA = 25C VIN = 0V, f = 1 MHz, TA = 25C Min Max 8 8 Unit pF pF
Note: These parameters are verified in device characterization and are not 100% tested.
Absolute Maximum Ratings
Item Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Power Dissipation Storage Temperature Operating Temperature Soldering Temperature and Time Symbol VIN,VOUT VCC PD TSTG TA TSOLDER Ratings -0.3 to VCC + 0.3 -0.3 to 4.5V 500 -40 to 125 -40 to 85 240C, 10sec (Lead only) Unit V V W C C C
Note: Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
60
2Mbit Type 1 SRAM
SRAM_Type01_03A0 August 4, 2004
Preliminary
Operating Characteristics (Over Specified Temperature Range)
Item Supply Voltage Data Retention Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Read/Write Operating Supply Current at 1 s Cycle Time (Note 2) Read/Write Operating Supply Current at 70 ns Cycle Time (Note 2) Page Mode Operating Supply Current at 70ns Cycle Time (Note 2) (Figure 1) Read/Write Quiescent Operating Supply Current (Note 3) Maximum Standby Current (Note 3) Maximum Data Retention Current (Note 3) Symbol VCC VDR VIH VIL VOH VOL ILI ILO ICC1 ICC2 ICC3 ICC4 ISB1 IDR IOH = 0.2mA IOL = -0.2mA VIN = 0 to VCC OE# = VIH or Chip Disabled VCC = 3.6 V, VIN = VIH or VIL Chip Enabled, IOUT = 0 VCC = 3.6 V, VIN = VIH or VIL Chip Enabled, IOUT = 0 VCC = 3.6 V, VIN = VIH or VIL Chip Enabled, IOUT = 0 VCC = 3.6 V, VIN=VIH or VIL Chip Enabled, IOUT = 0, f = 0 VIN = VCC or 0V Chip Disabled tA = 85C, VCC = 3.6 V VCC = 1.8V, VIN = VCC or 0 Chip Disabled, tA= 85C 2.0 2.0 12.0 4.0 3.0 20.0 10.0 Chip Disabled (Note 3) Test Conditions Min 2.3 1.8 1.8 -0.3 VCC - 0.2 0.2 0.5 0.5 4.0 16.0 mA A Type (Note1) 3.0 Max 3.6 3.6 VCC + 0.3 0.6 V Unit
Notes: 1. Typical values are measured at VCC = VCC Typ., TA = 25C and is not 100% tested. 2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. 3. This device assumes a standby mode if the chip is disabled (CE1# high or CE2 low). In order to achieve low standby current all inputs must be within 0.2 volts of either VCC or VSS.
August 4, 2004 SRAM_Type01_03A0
2Mbit Type 1 SRAM
61
Preliminary
Page Address (A4 -A16)
Open page ...
Word Address (A0 -A3)
Word 1
Word 2
Word 16
CE1# CE2
OE# LB#, UB#
Figure 1. Power Savings with Page Mode (WE# = VIH)
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power saving feature. The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant bits and addressing the 16 words within the open page, power is reduced to the page mode value which is considerably lower than standard operating currents for low power SRAMs.
Timing Test Conditions
Item Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Output Load Operating Temperature 0.1VCC to 0.9 VCC 5ns 0.5 VCC CL = 30pF -40 to +85C
62
2Mbit Type 1 SRAM
SRAM_Type01_03A0 August 4, 2004
Preliminary
Timing
2.3 - 3.6 V Item Read Cycle Time Address Access Time Chip Enable to Valid Output Output Enable to Valid Output Byte Select to Valid Output Chip Enable to Low-Z output Output Enable to Low-Z Output Byte Select to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Byte Select Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Enable to End of Write Address Valid to End of Write Byte Select to End of Write Write Pulse Width Address Setup Time Write Recovery Time Write to High-Z Output Data to Write Time Overlap Data Hold from Write Time End Write to Low-Z Output Symbol tRC tAA tCO tOE tLB, tUB tLZ tOLZ tLBLZ, tUBLZ tHZ tOHZ tLBHZ, tUBHZ tOH tWC tCW tAW tLBW, tUBW tWP tAS tWR tWHZ tDW tDH tOW 40 0 10 10 5 10 0 0 0 10 70 50 50 50 40 0 0 20 20 20 20 ns Min 70 70 70 35 70 Max Units
August 4, 2004 SRAM_Type01_03A0
2Mbit Type 1 SRAM
63
Preliminary
Timing Diagrams
tRC Address tAA tOH
Data Out
Previous Data Valid
Data Valid
Figure 2.
Timing of Read Cycle (CE# = OE# = VIL, WE# = CE2= VIH)
tRC Address
tAA
tHZ
CE1# tCO CE2 tLZ tOE
OE#
tOHZ
tOLZ tLB, tUB LB#, UB# tLBLZ, tUBLZ Data Out High-Z
Figure 3.
tLBHZ, tUBHZ
Data Valid
Timing Waveform of Read Cycle (WE# = VIH)
64
2Mbit Type 1 SRAM
SRAM_Type01_03A0 August 4, 2004
Preliminary
tWC Address tAW CE1# tCW CE2 tLBW, t UBW LB#, UB# tAS WE# tDW Data In High-Z tWHZ High-Z
Figure 4. Timing Waveform of Write Cycle (WE# Control)
tWR
tWP
tDH
Dat Valid a tOW
Data Out
tWC Address
tAW CE1# (for CE2 Control, use inverted signal) LB#, UB# tWP
WE#
tWR
tCW tAS tLBW, tUBW
tDW Data In tLZ Data Out
Figure 5. August 4, 2004 SRAM_Type01_03A0
tDH
Data Valid
tWHZ
High-Z
Timing Waveform of Write Cycle (CE1# Control) 2Mbit Type 1 SRAM 65
Preliminary
2Mbit Type 2 SRAM
128K x 16 Static RAM Common Features
High Speed -- 55ns and 70ns availability Ultra-low active power -- Typical active current: 1.5 mA @ f = 1MHz -- Typical active current: 7 mA @ f = fmax (70ns speed) Low standby power Easy memory expansion with CE and OE features Automatic power-down when deselected CMOS for optimum speed/power
Functional Description
The 2Mbit Type 2 SRAM is a family of high-performance CMOS static RAMs organized as 128K words by 16 bits. These devices feature advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBLTM) in portable applications such as cellular telephones. The devices also have an automatic power-down feature that significantly reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE# High). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE# High), outputs are disabled (OE# High), both Byte High Enable and Byte Low Enable are disabled (BHE#, BLE# High), or during a write operation (CE# Low, and WE# Low). Writing to the device is accomplished by taking Chip Enable (CE#) and Write Enable (WE#) inputs Low. If Byte Low Enable (BLE#) is Low, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE#) is Low, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE#) and Output Enable (OE#) Low while forcing the Write Enable (WE#) High. If Byte Low Enable (BLE#) is Low, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE#) is Low, then data from memory will appear on I/O8 to I/O15. See Table 1 for a complete description of read and write modes.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . . -55C to +125C Supply Voltage to Ground Potential . . . . . . . . . . . . . . -0.5V to VCCmax + 0.5V DC Voltage Applied to Outputs in High-Z State (note 2) . . -0.5V to VCC + 0.5V DC Input Voltage (note 2) . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC + 0.5V Output Current into Outputs (Low). . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
66
2Mbit Type 2 SRAM
SRAM_Type04_04A0 August 4, 2004
Preliminary
Operating Range
Range Industrial Ambient Temperature -40C to +85C VCC 2.7V to 3.3V
Product Portfolio
Power Dissipation (Industrial) Operating, ICC VCC Range VCC (min) 2.7V VCC (typ.) (note 2) 3.0V VCC (max) 3.3V Speed 55 ns 70 ns f = 1 MHz Typ. (note 2) 1.5 mA 1.5 mA Max 3 mA 3 mA f = fmax Typ. (note 2) 12 mA 7 mA Max 25 mA 15 mA Standby (ISB2) Typ. (note 2) 2 A Max 10 A
Notes: 1. VIL(min.) = -2.0V for pulse durations less than 20 ns. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C.
Electrical Characteristics
Voltage Range 2.7V - 3.3V Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VO < VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz VCC = 3.3V IOUT = 0 mA CMOS Levels Test Conditions IOH = -1.0 mA IOL = 2.1mA VCC = 2.7V VCC = 2.7V 2.2 -0.3 -1 -1 7 1.5 Min. 2.4 0.4 VCC + 0.3V 0.8 +1 +1 15 3 A V Typ. (note 1) Max Unit
mA
ISB1
Automatic CE Power-Down Current--CMOS Inputs
CE# VCC - 0.2V VIN VCC - 0.2V or VIN 0.2V, f = fmax (Address and Data Only), f=0 (OE#, WE#, BHE# and BLE#) CE# VCC - 0.2V VIN VCC - 0.2V or VIN 0.2V, f = 0, VCC = 3.3V
2
10
A
ISB2
Automatic CE Power-Down Current--CMOS Inputs
Notes: 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C.
August 4, 2004 SRAM_Type04_04A0
2Mbit Type 2 SRAM
67
Preliminary
Capacitance
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Condition TA = 25C, f = 1 MHz, VCC = VCC(typ.) Max 6 8 Unit pF
Note: Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 R1
ALL INPUT PULSES VCC Typ GND Rise Time: 1 V/ns 10% 90% 90% 10% Fall Time: 1 V/ns
Equivalent to:
THE VENIN EQUIVALENT RTH VTH
OUTPUT
Figure 1.
Parameters R1 R2 RTH VTH 2.5V 16.6 15.4 8 1.20
AC Test Loads and Waveforms
3.0V 1.105 1.550 0.645 1.75 3.3V 1.216 1.374 0.645 1.75 Volts K Ohms Unit
Data Retention Characteristics (Over the Operation Range)
Parameter VDR ICCDR tCDR (note 2) tR (note 3) Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = 1.5V CE# VCC - 0.2V 0 tRC Conditions Min. 1.5 1 Typ (note 1) Max. VCCMAX 4 Unit V A ns
Notes: 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C. 2. Tested initially and after any design or process changes that may affect these parameters. 3. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 ms or stable at VCC(min.) > 100 ms.
68
2Mbit Type 2 SRAM
SRAM_Type04_04A0 August 4, 2004
Preliminary
VCC CE# or
VCC(min)
tCDR
DATA RETENTION MODE VDR > 1.5 V
VCC(min)
tR
BHE#.BLE#
Figure 2.
Data Retention Waveform
Note: BHE#.BLE# is the AND of both BHE# and BLE#. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE# and BLE#.
August 4, 2004 SRAM_Type04_04A0
2Mbit Type 2 SRAM
69
Preliminary
Switching Characteristics
Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE (note 3) tHZBE Read Cycle Time Address to Data Valid Data Hold from Address Change CE# Low to Data Valid OE# Low to Data Valid OE# Low to Low Z (note 2) OE# High to High Z (note 2, 4) CE# Low to Low Z (note 2) CE# High to High Z (note 2, 4) CE# Low to Power-Up CE# High to Power-Down BHE# / BLE# Low to Data Valid BHE# / BLE# Low to Low Z (note 2) BHE# / BLE# High to High Z (note 2, 4) 5 20 0 55 55 5 25 10 20 0 70 70 5 20 10 25 10 55 25 5 25 ns 55 55 10 70 35 70 70 Description 55 ns Min Max 70 ns Min Max Unit
Write Cycle (note 5) tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write Cycle Time CE# Low to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE# Pulse Width BHE# / BLE# Pulse Width Data Set-Up to Write End Data Hold from Write End WE# Low to High Z (note 2, 4) WE# High to Low Z (note 2) 5 55 45 45 0 0 45 50 25 0 20 5 70 60 60 0 0 50 60 30 0 25 ns
Notes: 1. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.) /2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 2. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 3. If both byte enables are toggled together this value is 10ns. 4. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 5. The internal write time of the memory is defined by the overlap of WE#, CE# = VIL, BHE# and/or BLE# = VIL. All signals must be Active to initiate a write, and any of these signals can terminate a write by going Inactive. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
70
2Mbit Type 2 SRAM
SRAM_Type04_04A0 August 4, 2004
Preliminary
Switching Waveforms
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Figure 3.
Read Cycle 1 (Address Transition Controlled)
Notes: 1. Device is continuously selected. OE#, CE# = VIL, BHE#, BLE# = VIL. 2. WE# is High for read cycle.
ADDRESS
CE# tACE OE#
tDOE
t RC t PD tHZCE
t HZOE
BHE#/BLE#
tLZOE tLZOE
tHZBE tLZBE DATA OUT tDBE DATA VALID HIGH IMPEDANCE
HIGH IMPEDANCE tLZCE
VCC SUPPLY CURRENT
tPU 50% 50%
ICC ISB
Figure 4.
Notes: 1. WE# is High for read cycle.
Read Cycle 2 (OE# Controlled)
2. Address valid prior to or coincident with CE#, BHE#, BLE# transition Low.
August 4, 2004 SRAM_Type04_04A0
2Mbit Type 2 SRAM
71
Preliminary
tWC ADDRESS tS C E CE# tAW tSA WE# tPWE tHA
BHE#/BLE#
tBW
OE# tSD DATA I/O NOTE 4 tHZOE DATA IN VALID tHD
Figure 5.
Write Cycle 1 (WE# Controlled)
Notes: 1. The internal write time of the memory is defined by the overlap of WE#, CE# = VIL, BHE# and/or BLE# = VIL. All signals must be Active to initiate a write, and any of these signals can terminate a write by going Inactive. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 2. Data I/O is high-impedance if OE# = VIH. 3. If CE# goes High simultaneously with WE# High, the output remains in a high-impedance state. 4. During this period, the I/Os are in output state and input signals should not be applied.
72
2Mbit Type 2 SRAM
SRAM_Type04_04A0 August 4, 2004
Preliminary
tWC ADDRESS tSCE CE#
tSA
tAW tPWE
tHA
WE#
BHE#/BLE#
tBW
OE# tSD DATA I/O NOTE 4 t HZOE DATA IN VALID tHD
Figure 6.
Write Cycle 2 (CE# Controlled)
Notes: 1. The internal write time of the memory is defined by the overlap of WE#, CE# = VIL, BHE# and/or BLE# = VIL. All signals must be Active to initiate a write, and any of these signals can terminate a write by going Inactive. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 2. Data I/O is high-impedance if OE# = VIH. 3. If CE# goes High simultaneously with WE# High, the output remains in a high-impedance state. 4. During this period, the I/Os are in output state and input signals should not be applied.
tWC ADDRESS tS C E CE# t BW
BHE#/BLE# tAW tSA WE#
tHA tPWE
tSD DATAI/O NOTE 2 tHZWE DATA IN VALID
tH D
tLZWE
Figure 7.
Write Cycle 3 (WE# Controlled, OE# LOW)
Notes: 1. If CE# goes High simultaneously with WE# High, the output remains in a high-impedance state. 2. During this period, the I/Os are in output state and input signals should not be applied.
August 4, 2004 SRAM_Type04_04A0
2Mbit Type 2 SRAM
73
Preliminary
tWC ADDRESS
CE# tS C E tAW BHE#/BLE# t SA WE# tPWE tSD DATA I/O NOTE 2 DATAIN VALID tHD tBW tHA
Figure 8.
Write Cycle 4 (BHE#/BLE# Controlled, OE# Low)
Notes: 1. If CE# goes High simultaneously with WE# High, the output remains in a high-impedance state. 2. During this period, the I/Os are in output state and input signals should not be applied.
Typical DC and AC Parameters
14.0 12.0 ICC (mA) 10.0 8.0 6.0 4.0 (f = 1 MHz) 0.0 3.0 2.7 3.3 SUPPLY VOLTAGE (V) 2.0 MoBL (f = max 70ns) f, (f = max, 55ns) f
Figure 9.
Operating Current vs. Supply Voltage
12.0 ISB (m A) 10.0 MoBL 8.0 6.0 4.0 2.0 0 2.7 3.0 3.3 SUPPLY VOLTAGE (V)
Figure 10. 74
Standby Current vs. Supply Voltage 2Mbit Type 2 SRAM SRAM_Type04_04A0 August 4, 2004
Preliminary
60 50 40 T AA (ns) 30 20 10 0
MoBL
2.7
3.0
3.3
SUPPLY VOLTAGE (V)
Figure 11.
Access Time vs. Supply Voltage
Truth Table
Table 1.
CE# H L L L L L L L L L L WE# OE# BHE# X X H H H H H H L L L X X L L L H H H X X X X H L H L L H L L H L BLE# X H L L H L L H L L H High-Z High-Z Data Out (I/OO-I/O15) Data Out (I/OO-I/O7); I/O8-I/O15 in High Z Data Out (I/O8-I/O15); I/O0-I/O7 in High Z High-Z High-Z High-Z Data In (I/OO-I/O15) Data In (I/OO-I/O7); I/O8-I/O15 in High Z Data In (I/O8-I/O15); I/O0-I/O7 in High Z
Truth Table
Mode Deselect/Power-Down Output Disabled Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Active (ICC) Power Standby (ISB)
Inputs / Outputs
August 4, 2004 SRAM_Type04_04A0
2Mbit Type 2 SRAM
75
Advance
Information
Revision Summary
Revision A (September 27, 2004)
Initial release.
Revision A+1 (November 11, 2004)
Deleted parameter "tOES" at page 50,56. Changed the symbol of " tLBZ, tUBZ" to " tLBLZ, tUBLZ" at page 63.
Trademarks and Notice The contents of this document are subject to change without notice.This document may contain information on a SpansionTM product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable ( i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. The contents of this document are subject to change without notice.This document may contain information on a SpansionTM product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2004 Spansion LLC. All rights reserved. SpansionTM, the SpansionTM logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
76
Revision Summary
S71AL016D_02_04_00_A0 November 11, 2004

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