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M68AW511A
4 Mbit (512K x8) 3.0V Asynchronous SRAM
FEATURES SUMMARY

SUPPLY VOLTAGE: 2.7 to 3.6V 512K x 8 bits SRAM with OUTPUT ENABLE EQUAL CYCLE and ACCESS TIMES: 55ns LOW STANDBY CURRENT LOW VCC DATA RETENTION: 1.5V TRI-STATE COMMON I/O LOW ACTIVE and STANDBY POWER
Figure 1. Packages
32
1
TSOP32 Type II (NC)
SO32 (MC)
September 2004
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M68AW511A
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Table 1. Figure 3. Figure 4. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 TSOP and SO Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 6. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 5. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 7. Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.. . . . . . . . . . . . . 11 Figure 9. Chip Enable Controlled, Standby Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 7. Read and Standby Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 10.Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 11.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 8. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 12.Low VCC Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 9. Low VCC Data Retention Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 13.TSOP 32 Type II - 32 lead Plastic Thin Small Outline Type II, Package Outline . . . . . . 17 Table 10. TSOP32 Type II - 32 lead Plastic Thin Small Outline Type II, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 14.SO32 - 32 lead Plastic Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 11. SO32 - 32 lead Plastic Small Outline, Package Mechanical Data. . . . . . . . . . . . . . . . . . 18 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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M68AW511A
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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M68AW511A
SUMMARY DESCRIPTION
The M68AW511A is a 4 Mbit (4,194,304 bit) CMOS SRAM, organized as 524,288 words by 8 bits. The device features fully static operation requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7 to 3.6V supply. This device has an automatic power-down feature, reducing the power consumption by over 99% when deselected. The M68AW511A is available in two different packages: 32-lead TSOP Type II and 32-lead SO.
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A18 DQ0-DQ7 Address Inputs Data Input/Output Chip Enable Output Enable Write Enable Supply Voltage Ground
VCC
E G
19 A0-A18
8 DQ0-DQ7
W VCC
W E G
M68AW511A
VSS
VSS
AI05445c
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M68AW511A
Figure 3. TSOP and SO Connections
A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1
32
8 9
M68AW511A
25 24
16
17
AI05446c
VCC A15 A18 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
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M68AW511A
Figure 4. Block Diagram
A18 ROW DECODER A8 MEMORY ARRAY
VCC VSS
DQ7
I/O CIRCUITS COLUMN DECODER
DQ0
A0 E W
A7
G
AI05916
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M68AW511A
OPERATION
The M68AW511A has a Chip Enable power down feature which invokes an automatic standby mode whenever Chip Enable is de-asserted (E = High). An Output Enable (G) signal provides a high speed tri-state control, allowing fast read/write cyRead Mode The M68AW511A is in the Read mode whenever Write Enable (W) is High with Output Enable (G) Low, and Chip Enable (E) is asserted. This provides access to data from eight of the 4,194,304 locations in the static memory array, specified by the 19 address inputs. Valid data will be available at the eight output pins within tAVQV after the last Write Mode The M68AW511A is in the Write mode whenever the W and E pins are Low. Either the Chip Enable input (E) or the Write Enable input (W) must be deasserted during Address transitions for subsequent write cycles. Write begins with the concurrence of Chip Enable being active with W low. Therefore, address setup time is referenced to Write Enable and Chip Enable as tAVWL and tAVEH respectively, and is determined by the latter occurring edge. cles to be achieved with the common I/O data bus. Operational modes are determined by device control inputs W and E as summarized in the Operating Modes table (Table 2).
stable address, providing G is Low and E is Low. If Chip Enable or Output Enable access times are not met, data access will be measured from the limiting parameter (t ELQV or tGLQV) rather than the address. Data out may be indeterminate at tELQX and tGLQX, but data lines will always be valid at tAVQV.
The Write cycle can be terminated by the earlier rising edge of E, or W. if the Output is enabled (E = Low and G = Low), then W will return the outputs to high impedance within t WLQZ of its falling edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable, or for t DVEH before the rising edge of E, whichever occurs first, and remain valid for tWHDX or tEHDX.
Table 2. Operating Modes
Operation Output Disabled Read Write Deselect
Note: X = VIH or VIL.
E VIL VIL VIL VIH
W X VIH VIL X
G VIH VIL X X
DQ0-DQ7 Hi-Z Data Output Data Input Hi-Z
Power Active (ICC) Active (ICC) Active (ICC) Standby (ISB)
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M68AW511A
MAXIMUM RATING
Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 3. Absolute Maximum Ratings
Symbol IO (1) TA TSTG VCC VIO (2) PD Output Current Ambient Operating Temperature Storage Temperature Supply Voltage Input or Output Voltage Power Dissipation Parameter Value 20 -55 to 125 -65 to 150 -0.5 to 4.6 -0.5 to VCC +0.5 1 Unit mA C C V V W
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. One output at a time, not to exceed 1 second of duration. 2. Up to a maximum operating VCC of 3.6V only.
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M68AW511A
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Parameter VCC Supply Voltage Range 1 Ambient Operating Temperature Range 6 Load Capacitance (CL) Output Circuit Protection Resistance (R1) Load Resistance (R2) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages Input and Output Transition Timing Ref. Voltages -40 to 85C 30pF 3.0k 3.1k 1ns/V 0 to VCC VCC/2 VOL = 0.3VCC; VOH = 0.7VCC M68AW511A 2.7 to 3.6V 0 to 70C
Figure 5. AC Measurement I/O Waveform
Figure 6. AC Measurement Load Circuit
VCC
I/O Timing Reference Voltage VCC VCC/2 0V DEVICE UNDER TEST CL R2 0.7VCC 0.3VCC
AI04831
R1
OUT
I/O Transition Timing Reference Voltage VCC
0V
CL includes JIG capacitance
AI03853
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M68AW511A
Table 5. Capacitance
Symbol CIN COUT Parameter(1,2) Input Capacitance on all pins (except DQ) Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 8 Unit pF pF
Note: 1. Sampled only, not 100% tested. 2. At TA = 25C, f = 1MHz, VCC = 3.0V.
Table 6. DC Characteristics
Symbol ICC1 (1,2) ICC2 (3) ILI ILO (4) ISB VIH VIL VOH VOL
Note: 1. 2. 3. 4.
Parameter Operating Supply Current Operating Supply Current Input Leakage Current Output Leakage Current Standby Supply Current CMOS Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage
Test Condition VCC = 3.6V, f = 1/tAVAV, IOUT = 0mA VCC = 3.6V, f = 1MHz, IOUT = 0mA 0V VIN VCC 0V VOUT VCC VCC = 3.6V, E VCC - 0.2V, f=0
Min
Typ
Max 30 5
Unit mA mA A A A V V V
-1 -1 5 2.2 -0.3
1 1 10 VCC + 0.3 0.6
IOH = -1mA IOL = 2.1mA
2.4 0.4
V
Average AC current, cycling at tAVAV minimum. E = VIL, VIN = V IH or VIL. E 0.2V, VIN 0.2V or VIN V CC - 0.2V. Output disable.
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M68AW511A
Figure 7. Address Controlled, Read Mode AC Waveforms
tAVAV A0-A18 tAVQV VALID tAXQX
DQ0-DQ7
DATA VALID
AI03034
Note: E = Low, G = Low, W = High.
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV A0-A18 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 VALID
AI03035
VALID tAXQX tEHQZ
tGHQZ
Note: Write Enable (W) = High.
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M68AW511A
Figure 9. Chip Enable Controlled, Standby Mode AC Waveforms
E ICC1 ICC2 tPU 50% tPD
AI03036
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M68AW511A
Table 7. Read and Standby Mode AC Characteristics
M68AW511A Symbol tAVAV tAVQV tAXQX (1) tEHQZ (2,3) tELQV tELQX (1) tGHQZ (2,3) tGLQV tGLQX (1) tPD tPU Read Cycle Time Address Valid to Output Valid Data hold from Address change Chip Enable High to Output Hi-Z Chip Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable High to Output Hi-Z Output Enable Low to Output Valid Output Enable Low to Output Transition Chip Enable High to Power Down Chip Enable Low to Power Up Parameter 55 Min Max Min Max Max Min Max Max Min Max Min 55 55 5 20 55 5 20 25 5 55 0 70 70 70 5 25 70 5 25 35 5 70 0 ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. Test conditions assume transition timing reference level = 0.3VCC or 0.7VCC. 2. At any given temperature and voltage condition, tEHQZ is less than t ELQX and tGHQZ is less than t GLQX for any given device. 3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
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M68AW511A
Figure 10. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A18 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI03037
tWHAX
tWHQX
Figure 11. Chip Enable Controlled, Write AC Waveforms
tAVAV A0-A18 VALID tAVEH tAVEL E tWLEH W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI05914
tELEH
tEHAX
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M68AW511A
Table 8. Write Mode AC Characteristics
M68AW511A Symbol tAVAV tAVEH tAVEL tAVWH tAVWL tDVEH tDVWH tEHAX tEHDX tELEH tELWH tWHAX tWHDX tWHQX (1) tWLEH tWLQZ (1,2) tWLWH Write Cycle Time Address Valid to Chip Enable High Address Valid to Chip Enable Low Address Valid to Write Enable High Address Valid to Write Enable Low Input Valid to Chip Enable High Input Valid to Write Enable High Chip Enable High to Address Transition Chip Enable High to Input Transition Chip Enable Low to Chip Enable High Chip Enable Low to Write Enable High Write Enable High to Address Transition Write Enable High to Input Transition Write Enable High to Output Transition Write Enable Low to Chip Enable High Write Enable Low to Output Hi-Z Write Enable Low to Write Enable High Parameter 55 Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min Max Min 55 45 0 45 0 25 25 0 0 45 45 0 0 5 45 20 45 70 70 60 0 60 0 30 30 0 0 60 60 0 0 5 60 25 60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: 1. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tWLQZ is less than tWHQX for any given device.
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M68AW511A
Figure 12. Low VCC Data Retention AC Waveforms
DATA RETENTION MODE 3.6V VCC 2.7V VDR > 1.5V tCDR E VDR - 0.2V E tR
AI05447
Table 9. Low VCC Data Retention Characteristics
Symbol Parameter Test Condition VCC = 1.5V, E VCC - 0.2V, f = 0 (3) 0 tAVAV E VCC - 0.2V, f = 0 1.5 Min Typ 4.5 Max 9 Unit A ns ns V ICCDR (1) Supply Current (Data Retention) tCDR (1,2) Chip Disable to Power Down tR (2) VDR (1) Operation Recovery Time Supply Voltage (Data Retention)
Note: 1. All other Inputs at V IH VCC -0.2V or VIL 0.2V. 2. Tested initially and after any design or process may affect these parameters. t AVAV is Read cycle time. 3. No input may exceed VCC +0.2V.
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M68AW511A
PACKAGE MECHANICAL
Figure 13. TSOP 32 Type II - 32 lead Plastic Thin Small Outline Type II, Package Outline
D
N
E1
E
1
N/2
b
e
A
A2 C A1 CP L
TSOP-e
Note: Drawing is not to scale.
Table 10. TSOP32 Type II - 32 lead Plastic Thin Small Outline Type II, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b C CP D e E E1 L N 1.27 20.82 - 11.56 10.03 0.40 0 32 0.05 0.95 0.30 0.12 Min Max 1.20 0.15 1.05 0.52 0.21 0.10 21.08 - 11.96 10.29 0.60 5 0.050 0.820 - 0.455 0.395 0.016 0 32 0.002 0.037 0.012 0.005 Typ Min Max 0.047 0.006 0.041 0.020 0.008 0.004 0.830 - 0.471 0.405 0.024 5 inches
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M68AW511A
Figure 14. SO32 - 32 lead Plastic Small Outline, Package Outline
D
16 1
E
E1
17
32
A2 B SO-C e A1 CP
A C L1 L
Note: Drawing is not to scale.
Table 11. SO32 - 32 lead Plastic Small Outline, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B C D E E1 e L L1 CP 1.27 0.10 2.57 0.36 0.15 20.14 11.18 13.87 - 0.58 1.19 2.82 0.51 0.30 20.75 11.43 14.38 - 0.99 1.60 0.10 0.050 Min Max 3.00 0.004 0.101 0.014 0.006 0.793 0.440 0.546 - 0.023 0.047 0.111 0.020 0.012 0.817 0.450 0.566 - 0.039 0.063 0.004 Typ Min Max 0.118 inches
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M68AW511A
PART NUMBERING
Table 12. Ordering Information Scheme
Example: Device Type M68 Mode A = Asynchronous Operating Voltage W = 2.7 to 3.6V Array Organization 511 = 4 Mbit (512K x8) Option 1 A = 1 Chip Enable Option 2 L = L-Die M = M-Die Speed Class 55 = 55ns 70 = 70ns Package NC = TSOP32 Type II MC = SO32 Operative Temperature 1 = 0 to 70C 6 = -40 to 85C Shipping T = Tape & Reel Packing M68AW511 A L 55 NC 6 T
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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M68AW511A
REVISION HISTORY
Table 13. Document Revision History
Date August 2001 27-Sep-2001 Version 1.0 2.0 First Issue. 55ns speed class replaces 70ns. From Preliminary Data to Data Sheet. 70ns speed class added. Temperature Range 1 (0 to 70C) added. Block Diagram clarified (Figure 4). Operating and AC Measurement Conditions table clarified (Table 4). AC Measurement Load Circuit clarified (Figure 6). DC Characteristics table clarified (Table 6). Write, Read and Standby Mode AC Characteristics tables clarified (Table 8 and 7). Chip Enable Controlled, Write AC Waveforms clarified (Figure 11). Low VCC Data Retention AC Waveforms and Characteristics clarified (Figure 12 and Table 9). SO32 package added. Read and Standby Mode AC Characteristics table clarified (Table 7). Low VCC Data Retention AC Waveforms and Characteristics clarified (Figure 12 and Table 9). DC Characteristics Table clarified (Table 6). Write Mode AC Characteristics Table clarified (Table 8). Minor changes. Load Capacitance (CL) changed from 100pF to 30pF (Table 4). New part number added. Commercial code modified. Correction to wording in Operating Modes table. Document structure modified: - Chapter OPERATION moved before chapter MAXIMUM RATING. - AC Characteristics Tables and waveforms moved to the DC/AC PARAMETERS section. tPU ad tPD updated in Table 7. Revision Details
27-Feb-2002
3.0
01-Mar-2002 25-Mar-2002
4.0 5.0
26-Apr-2002 17-Jun-2002 09-Sep-2002 02-Oct-2002 09-Oct-2002 12-Jun-2003
6.0 6.1 6.2 6.3 6.4 6.5
24-Sep-2004
7.0
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M68AW511A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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