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EM MICROELECTRONIC - MARIN SA
EM6125
Digitally programmable 65 and 81 multiplex rate LCD Controller and Driver
Features
Slim IC for COG, COF and COB technologies 2 I C & Serial bus interface Internal display data RAM 2 digitally programmable multiplex rates : 81 rows x 102 columns 65 rows x 118 columns LCD supply voltage internally generated and digitally programmable from 3V to 11V Low operating current consumption: 120A (typ) No external components needed except one VLCD capacitor On chip 4 intermediate bias voltages generation Oscillator for LCD refresh (no external components required) High noise immunity on inputs Row and column drivers mirroring for COG or COF connections flexibility Partial display mode with 17 active rows for current consumption reduction Sleep mode for a nearly null current consumption Wide VDD supply voltage from 1.8V to 5V. Wide temperature range: -40C to +85C
Typical Applications
Mobile phones Smart cards Automotive displays Portable, battery operated products Balances and scales, utility meters Typical Operating Configuration
40 row drivers 41 row drivers 102 columns outputs
EM6125
VLCD SCL SDA RES Vss1 Vss2 VDD1 VDD2 VHV
Figure 1
Pin Configuration
Description
The EM6125 is a bit map controller and driver for full dot matrix monochrome STN LCD displays. The driving capability is 81 rows x 102 columns (10 rows of characters + one row of icons) or 65 rows x 118 columns (8 rows of characters + one row of icons). There is a one to one relation between LCD pixels and bits of the Display Data RAM. The EM6125 is extremely low power consumption LCD controller and driver product. The typical current consumption is about 120A with no external component except the capacitor connected to VLCD. One important feature on EM6125 is the partial display mode, which enables important current consumption reduction. With this function selected, only 17 rows remain active, needed VLCD decreases and the commutation frequencies of row and column drivers are also decreased. These three effects of partial display mode reduce drastically current consumption.
Figure 2
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EM6125
Features Description Typical Applications Typical Operating Configuration Pin Configuration 1 Absolute Maximum Ratings 2 Handling Procedures 3 Operating Conditions 4 Electrical Characteristics 5 Timing Characteristics 5.1 Timing Waveforms 6 Block diagram 7 Pin description 8 Functional description 8.1 Selection of interface type 8.2 Serial interface 2 8.3 I C interface 8.3.1 Start and stop conditions 8.3.2 Bit transfer 8.3.3 Acknowledge 2 8.4 I C protocol 8.4.1 Write mode 8.4.2 Read Mode (RW = 1) 8.5 Display Data RAM 8.5.1 DDRAM description 8.5.2 DDRAM addressing 8.6 Initialization of EM6125 8.7 Description of instructions 8.7.1 Initialization 0 8.7.1.1 Mux Mode 8.7.1.2 TC[1:0] 8.7.1.3 Inv. Row 8.7.1.4 MX 8.7.1.5 Blank 8.7.1.6 Checker 8.7.1.7 Inv. Video 8.7.2 Initialization 1 8.7.2.1 X[6:0] 8.7.2.2 V 8.7.3 Initialization 2 8.7.3.1 Y[3:0] 8.7.3.2 Vlcd Dischg. 8.7.3.3 DEC 8.7.3.4 LSB 8.7.4 Initialization 3 8.7.4.1 Vlcd Level[7:0] 8.7.5 Initialization 4 8.7.5.1 Mult[1:0] 8.7.5.2 Partial Display 8.7.5.3 First Row PD[3:0]
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EM6125
8.7.5.4 Sleep 8.7.6 Test 0 to 3 8.8 LCD outputs 8.9 LCD refresh frequency 8.10 VLCD depending on VHV 8.11 LCD driver waveforms 8.11.1 Partial Display 9 Typical Application 10 Pad location 11 Ordering Information 12 Updates 29 29 30 31 31 32 34 35 39 42 43
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EM6125
1 Absolute Maximum Rating s
Parameter Supply voltage range Supply voltage range Supply voltage range All input voltages Voltages at S0 to S184 Storage temperature range Electrostatic discharge max. to MIL-STD-883C method 3015 Maximum soldering conditions Symbol VDD1,2 VHV VLCD VLOGIC VDISPLAY TSTO VESD TSMAX Conditions -0.3V to +6V -0.3V to +6V VHV-0.3V to +12V -0.3V to VDD1,2+0.3V -0.3V to VLCD + 0.3V -65C to +150 C 1000V 250C x 10 s
2 Handling Procedures
This device has built-in protection against high static voltages or electric fields; however, anti-static precautions should be taken as for any other CMOS components. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range.
3 Operating Conditions
Parameter Operating temperature Logic supply voltage High voltage generator supply voltage LCD supply voltage Symbol TA VDD1,2 VHV VLCD Min. -40 1.8 2.4 * 3 Typ. Max. +85 5.5 5.5 11 C V V V
2.5 2.5 8
Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified electrical characteristics may affect device reliability or cause malfunction.
* Lower VHV voltage is possible until the required VLCD voltage is reached.
4 Electrical Characteristics
VSS1,2 = 0V, VDD1 = VDD2 = 1.8V, VHV = 2.4V, unless otherwise specified. TA = -40C to +85 C unless otherwise specified. Minimum required capacitor: 1F on VLCD, 100nF on VDD1,2 and VHV. Parameter Symbol Test conditions Min. Typ. Max. Units Supply Current Sleep mode Sleep mode Normal LCD refresh mode Normal LCD refresh mode Partial LCD refresh mode Control Input Signals Input leakage Input capacitance Low level input voltage High level input voltage LCD Outputs Internally generated LCD supply voltage IDD IHV IDD IHV IHV IIN CIN VIL VIH Sleep = 1 Sleep = 1 (note 1) (note 2) (note 3) Vi = Vss1 or VDD1 -1 8 0.3xVDD1 0.7xVDD1 VLCD 00000000b VLCD 10001110b VLCD step between 2 consecutive programmed VLCD Level V bias tolerance VLCD step V bias tol. (note 5) -80 3.02 8.02 35.2 80 10 0.5 15 124 50 nA 21 180 87 1 A A A A A pF V V V V mV mV
Note 1: Measured on VDD1 + VDD2, all outputs open, SDA and SCL at VSS, RES at VDD1, multiplex rate 81, x5 voltage multiplier, VLCD = 10001110b, DDRAM loaded with checker pattern Note 2: Measured on VHV, same conditions as (note 1). Note 3: Measured on VHV, all outputs open, SDA and SCL at VSS, RES at VDD1, partial display mode, x 2 voltage multiplier, VLCD = 00101011b, DDRAM loaded with checker pattern. Note 4: With internal voltage multiplier, the maximum VLCD voltage depends on VHV, programmed voltage multiplier and display load. Note 5: V1, V2, V3 and V4 bias levels measured with VLCD = 7V, on 1 LCD row driver output and 1 LCD column driver output, multiplex rate 81, TA = 25 C, load = 10A.
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EM6125
5 Timing Characteristics
VSS1,2 = 0V, VDD1 = VDD2 = 1.8V, VHV = 2.4V, TA = -40C to +85 C unless otherwise specified. Parameter Internal frame frequency for LCD refresh Minimum reset pulse width I2C timing characteristics SCL frequency SCL low period SCL high period SDA setup time SDA hold time SCL and SDA rise time SCL and SDA fall time Setup time for a repeated start condition Hold time for a start condition Setup time for a stop condition Spike width on SCL and SDA Time before a new transmission can start Capacitive bus line load Serial bus timing characteristics SCL frequency SCL low period SCL high period SDA setup time SDA hold time SCL rise time SCL fall time CS setup time CS hold time Time before a new transmission can start, CS minimum high time. Note 1: Measured on pad FR. fSER tCL tCH tDS tDH tCR tCF tSUCS tHDCS tBUFCS 10 130 70 70 130 20 50 200 200 4 MHz ns ns ns ns ns ns ns ns ns fI2C tLOW tHIGH tSUDAT tHDDAT tR tF tSUSTA tHDSTA tSUSTO tSW tBUF Cb 100 400 20 20 20 20 350 100 10 20 200 200 1600 kHz ns ns ns ns ns ns ns ns ns ns ns pF Symbol fFR tRW Test conditions (note 1) 70 Min. Typ. 75 x mux Max. Units Hz ns
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EM6125
VSS1,2 = 0V, VDD1 = VDD2 = 2.5V, VHV = 2.4V, TA = -40C to +85 C unless otherwise specified. Parameter Minimum reset pulse width I2C timing characteristics SCL frequency SCL low period SCL high period SDA setup time SDA hold time SCL and SDA rise time SCL and SDA fall time Setup time for a repeated start condition Hold time for a start condition Setup time for a stop condition Spike width on SCL and SDA Time before a new transmission can start Capacitive bus line load Serial bus timing characteristics SCL frequency SCL low period SCL high period SDA setup time SDA hold time SCL rise time SCL fall time CS setup time CS hold time Time before a new transmission can start, CS minimum high time. fSCL tCL tCH tDS tDH tCR tCF tSUCS tHDCS tBUFCS 10 80 50 50 80 15 40 200 200 5.2 MHz ns ns ns ns ns ns ns ns ns fSCL tLOW tHIGH tSUDAT tHDDAT tR tF tSUSTA tHDSTA tSUSTO tSW tBUF Cb 40 400 20 20 20 10 190 60 10 20 200 200 2100 kHz ns ns ns ns ns ns ns ns ns ns ns pF Symbol tRW Test conditions Min. 50 Typ. Max. Units
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5.1 Timing Waveforms
SDA
SCL
Data line stable, data valid
Change of data allowed
Figure 3: I2C 1 bit transfer
SDA
SCL S P
Start condition
Stop condition
Figure 4: I2C start and stop conditions
SDA By transmitter Not Acknowledge SDA By receiver
Acknowledge
SCL S
1
2
8
9
Start condition Clock pulse for acknowledgement
Figure 5: Acknowledgement on the I2C bus
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EM6125
SDA tBUF tLOW SCL tHIGH tHDSTA tr tHDDAT tSUDAT tf
SDA
tSUSTA
tSUSTO
Figure 6: I2C timing diagram.
Data stable, data valid Change of data allowed
SDA
SDA sampled on SCL falling edge
SCL
Data input setup time
Data input hold time
Data input setup time
Data input hold time
Figure 7: Serial interface, 1 bit transfer.
tDH tDS
SDA
tCL SCL tCH tcr tSUCS
tcf
tBUFCS tHDCS
CS
Figure 8: Serial interface timing diagram.
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EM6125
6 Block diagram
S0 to S183
VHV
Voltage Multiplier Intermediate voltages generation
LCD levels selection
VLCD 1 uF external capacitor
Internal Oscillator 81 bits sequenceur
Gating
Blank, Video, Checker
001000...000 VDD1 DB7 to DB0 VDD2 VSS RES I2C / serial 3 wires interface
Display Data RAM 1x118 8x(8x118) 2x(8x102) y-address x-address x-address and y-address generator
SDA
SCL
CS
I
Figure 9: Block diagram.
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EM6125
7 Pin description
Symbol S0 to S183 S0 to S32 and S151 to S183 S33 to S40 and S143 to S150 S41 to S142 VHV VDD1,2 VSS1,2 I RES CS FR TEST SDA SCL VLCD Pad Type Output Output Output Output Positive power supply Positive power supply Ground power supply Input Input Input Input/output Input/output Input/output Input Positive power supply Description LCD driver outputs LCD row driver outputs S0 = S184 LCD row driver outputs when multiplex rate 81 is selected LCD column driver outputs when multiplex rate 65 is selected LCD column driver outputs Supply voltage for internal voltage multiplier Supply voltage for logical and analog parts Ground power supply Interface protocol selection input External reset input, active low Chip select input Frame frequency input/output Test Serial data input Serial clock LCD supply voltage
Table 1: Pin description
S0 to S183: VHV: VDD1,2:
Connected to LCD electrodes, it should be left open if not used. S0 and S183 are internally connected together. Supply voltage for internal voltage multiplier, it could be a different voltage value than for VDD1,2. Logic and analog power supplies. VDD1 and VDD2 are not connected inside EM6125 but have to be connected outside to the same potential. For chip on glass application, it is advised to keep VDD1 and VDD2 separated until their connection to 1 F capacitor. Ground supply for logic and high voltage generator. VSS1 is connected to substrate. Same precautions than for VDD1,2 should be taken to connect these pads. Selects the chosen interface protocol. For chip on glass applications, it can be directly connected to VSS1 or VDD1 on glass. External reset, a reset cycle must be applied at power on (reset at low level when power on). Active low chip select, when serial interface is used it enables data transfer. If I C is used, it must be connected at VSS1 or VDD1 pads. Outputs LCD refresh frame frequency, used for test. It must be left open. Test pad, it must be left open. Serial data input used for I C interface as for 3 wires serial interface. Serial clock input used to latch SDA for I C interface as for 3 wires serial interface. LCD voltage supply (generation of LCD waveforms applied to S0 to S183). It is normally internally generated from VHV supply voltage. 1 F capacitor is required between VLCD and VSS. External power supply is also possible; in this configuration VLCD must be programmed at its lower value and VHV connected to VSS2.
2 2 2
VSS1,2: I: RES: CS: FR: TEST: SDA: SCL: VLCD:
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8 Functional description
8.1 Selection of interface type There are two different serial interfaces available on EM6125. Selection depends on logical value applied on pad I. If I = 0, serial interface is selected: 3 wires with Chip Select CS, Serial Clock SCL and Serial Data SDA. 2 If I = 1, I C protocol is selected: 2 wires with Serial Clock SCL and Serial Data SDA. CS must be connected to VSS or VDD1.
I 0 1
Interface 3 wires serial interface 2 IC
Table 2: Interface selection
8.2 Serial interface The serial interface consists of 3 wires: Chip Select CS, Serial Clock SCL and Serial Data SDA. The information is exchanged byte-wide and is shifted serially in the LCD driver at SCL fall edge.
SDA
Data sampled on SCL fall edge
SCL
Data stable, data valid
Change of data allowed
Figure 10: Serial interface, 1 bit transfer
Transfer of data is unidirectional from micro controller to EM6125. When CS is activated at low level the communication is enabled and must stay low for the rest of the transaction. Data transfer begins with one control byte. This control bytes is transferred MSB first, it consists in:
MSB LSB
C0
DC Test[2] Test[1] Test[0]
Ini[2]
Ini[1]
Ini[0]
C0 is the continuation bit: If C0 = 1, the control byte is followed by 1 data byte only, the next byte is a new control byte. If C0 = 0, all the following bytes are data bytes until data transfer is stopped. DC selects data bytes or command bytes to be send after the control byte: If DC = 1, the following data byte(s) is (are) written in the Display Data RAM. First data byte is stored at the address specified by the x-address and y-address pointers. Data pointers are automatically updated for each byte written in the DDRAM (see DDRAM description). IF DC = 0, the following data byte is a command byte. It enables initialization of functions (multiplex rate, number of voltage multiplier stages, VLCD programming, partial display settings...).
Bits ini2, ini1 and ini0 select the initialization register to be set by the following command byte (see Table 4: EM6125 instructions).
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EM6125
CS start stop
Control Byte C0 = 1 DC = 0
Data Byte Command byte
Control Byte C0 = 1 DC = 1
Data Byte DDRAM Data byte
Control Byte C0 = 0 DC = 1
Data Byte DDRAM Data byte n bytes
2n bytes
2n bytes
Figure 11: serial interface protocol
Data byte is transferred with MSB bit first, LSB bit last:
MSB LSB
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
If CS goes high during a byte transfer, this byte is invalid but all previously transmitted data are valid. While CS is high the serial interface is kept in reset that means internal interface counter and disables data transfer. To prevent transmission errors, CS should be at high level when transfer is stopped.
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EM6125
8.3 I C interface The EM6125 can be interfaced with a slave I C protocol (see description I2C protocol). The I C bus consists in 2 wires: SCL (Serial Clock Line) and SDA (Serial Data Line). Both lines must be connected to VDD1,2 via a pull up resistor. EM6125 pad SCL is input, pad SDA is bi-directional with pull down open drain. EM6125 supports initialization and RAM write and status read access. 8.3.1 Start and stop conditions Data transfer begins by a falling edge on SDA when SCL is at high level, this is the start condition (S), initiated by the I C bus master. It is stopped with a rising edge on SDA and SCL at high level, this is the stop condition (P) (see Figure 4: I2C start and stop conditions). 8.3.2 Bit transfer One data bit is transferred during each SCL pulse. The data on the SDA line must remain stable during the high period of SCL pulses, as any changes at this time would be interpreted as start or stop conditions. Data is always transferred with MSB first. 8.3.3 Acknowledge After a start condition, data bits are transferred to EM6125. Each byte is followed by an acknowledge bit: the transmitter let the SDA line high (no pull down) and generates a high SCL pulse; if transfer concerns the EM6125 slave receiver and has performed correctly, it generates a low SDA level (pull down activated). SDA remains stable during the high period of the acknowledge related SCL pulse. After acknowledge, EM6125 let SDA line free, enabling the transmitter to continue transfer or to generate a stop condition. 8.4 I C protocol The EM6125 has a slave address, coded on 7 bits: 0000000. After a start condition, the slave address + RW bit must be send first. If the slave address does not match with the EM6125 ones there is no acknowledge from LCD driver and the following data transfer will not affect the chip. If the slave address corresponds to EM6125 slave address, it will acknowledge (pull SDA down to logical low level) and data transfer is enabled. The 8th bit RW sets the chip in write mode or read status mode, it is read for data transfer. 8.4.1 Write mode If RW = 0, EM6125 is accessed by the micro controller. Data transfer bytes can be either control bytes or data bytes. Data transfer always begins with a control byte (described in fig.1). It sets bits C0, DC, ini2, ini1 and ini0. C0 is the continuation bit: If C0 = 1, the control byte is followed by 1 data byte only, the next byte is a new control byte. If C0 = 0, all the following bytes are data bytes until data transfer is stopped. DC selects data bytes or command bytes to be send after the control byte: If DC = 1, the following data byte(s) is (are) written in the Display Data RAM. First data byte is stored at the address specified by the x-address and y-address pointers. Data pointers are automatically updated for each byte written in the DDRAM (see DDRAM description). IF DC = 0, the following data byte is a command byte. It enables initialization of functions (multiplex rate, number of voltage multiplier stages, VLCD programming, partial display settings...).
2 2 2 2 2
Bits ini2, ini1 and ini0 select the initialization register to be set by the following command byte (see Table 4: EM6125 instructions).
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EM6125
8.4.2 Read Mode (RW = 1) EM6125 will output one status byte after slave address. This status byte consists in 8 initialization bits previously set by command bytes or the reset cycle (see Table 4: EM6125 instructions).
First byte send:
MSB
0 0 0 0 0 0 0 RW
Control Byte:
LSB MSB
Data Byte:
LSB
C0
DC Test[2]Test[1]Test[0] Ini[2] Ini[1] Ini[0]
A
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
A
EM6125 Slave Address
W rite mode:
Acknowledge from EM 6125 Acknowledge from EM 6125 Acknowledge from EM6125 Acknowledge from EM6125 Acknowledge from EM6125
S
0
0
0
0
0
0
0
0
A
1
Control Byte
A
Data Byte
A
0
Control Byte
A
Data Byte
A
P
Slave Address
2n 0 bytes C0
W rite M ode
1 byte C0
n 0 bytes
Read mode:
Acknowledge from EM6125
S 0 0 0 0 0 0 0 1 A 1
Acknowledge from master
A P
Status Byte
Slave Address
Figure 12: I2C protocol description
8.5 Display Data RAM The EM6125 contains a RAM, which stores the display data; there is a one to one correspondence between the bit stored in the RAM and one LCD pixel. 8.5.1 DDRAM description DDRAM consists in: 1 bank of 118 bits (row 0) 8 banks of 118 bytes (rows 1 to 64) 2 banks of 102 bytes (rows 65 to 80) DDRAM is read row by row for display refresh. Each row corresponds to one pad, which is activated when the corresponding row is read. DDRAM is accessed via the interface. Bytes are stored at the column specified by x-address pointer and the bank specified by y-address pointer. These pointers are set by the corresponding instruction "Initialization 1" and "Initialization 2" and are automatically incremented or decrement after each byte written in the DDRAM (see DDRAM addressing and Table 5: Internal functions after reset.) For bank 0 only data byte 7 (DB7) is stored in row 0, DB6 to DB0 are not used. For bank 1 to 10 (y-address = 1 to 10), DBX is stored at row ((8 x y-address)-X).
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EM6125
If Mux Mode = 0, the DDRAM provides a 65 rows and 118 columns matrix. Bank 9 and 10 are not used for display refresh, the cells can not be addressed.
0
- - - - - - - - - - - - - - - - - - - - - - - x-address - - - - - - - - - - - - - - - - - - - - - - -
117
0
Bank 0
DB7 DB7 DB7 DB7 DB7 DB7 DB6 DB6 DB6 DB5 DB5 DB5
DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB6 DB6 DB6 DB6 DB5 DB5 DB5 DB5 DB4 DB4 DB4 DB4 DB3 DB3 DB3 DB3 DB2 DB2 DB2 DB2 DB1 DB1 DB1 DB1 DB0 DB0 DB0 DB0
DB7 DB7 DB7 DB7 DB7 DB7 DB6 DB6 DB6 DB5 DB5 DB5 DB4 DB4 DB4 DB3 DB3 DB3 DB2 DB2 DB2 DB1 DB1 DB1 DB0 DB0 DB0
DB7 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB7 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB7 DB7 DB7 DB7 DB7 DB7 DB6 DB6 DB6 DB5 DB5 DB5 DB4 DB4 DB4 DB3 DB3 DB3 DB2 DB2 DB2 DB1 DB1 DB1 DB0 DB0 DB0
DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB7 DB6 DB6 DB6 DB6 DB5 DB5 DB5 DB5 DB4 DB4 DB4 DB4 DB3 DB3 DB3 DB3 DB2 DB2 DB2 DB2 DB1 DB1 DB1 DB1 DB0 DB0 DB0 DB0
DB7 DB7 DB7 DB7 DB7 DB7 DB6 DB6 DB6 DB5 DB5 DB5 DB4 DB4 DB4 DB3 DB3 DB3 DB2 DB2 DB2 DB1 DB1 DB1 DB0 DB0 DB0
Bank 1
DB4 DB4 DB4 DB3 DB3 DB3 DB2 DB2 DB2 DB1 DB1 DB1 DB0 DB0 DB0
Row 0 Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Row 8 Row 9 Row 10
DB7 DB7 DB7 DB6 DB6 DB6 DB5 DB5 DB5
DB7 DB7 DB7 DB7 DB6 DB6 DB6 DB6 DB5 DB5 DB5 DB5 DB4 DB4 DB4 DB4 DB3 DB3 DB3 DB3 DB2 DB2 DB2 DB2 DB1 DB1 DB1 DB1 DB0 DB0 DB0 DB0
DB7 DB7 DB7 DB6 DB6 DB6 DB5 DB5 DB5 DB4 DB4 DB4 DB3 DB3 DB3 DB2 DB2 DB2 DB1 DB1 DB1 DB0 DB0 DB0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB7 DB7 DB7 DB6 DB6 DB6 DB5 DB5 DB5 DB4 DB4 DB4 DB3 DB3 DB3 DB2 DB2 DB2 DB1 DB1 DB1 DB0 DB0 DB0
DB7 DB7 DB7 DB7 DB6 DB6 DB6 DB6 DB5 DB5 DB5 DB5 DB4 DB4 DB4 DB4 DB3 DB3 DB3 DB3 DB2 DB2 DB2 DB2 DB1 DB1 DB1 DB1 DB0 DB0 DB0 DB0
DB7 DB7 DB7 DB6 DB6 DB6 DB5 DB5 DB5 DB4 DB4 DB4 DB3 DB3 DB3 DB2 DB2 DB2 DB1 DB1 DB1 DB0 DB0 DB0
8
Bank 8
DB4 DB4 DB4 DB3 DB3 DB3 DB2 DB2 DB2 DB1 DB1 DB1 DB0 DB0 DB0
Row 55 Row 56 Row 57 Row 58 Row 59 Row 60 Row 61 Row 62 Row 63 Row 64
Bank 9
Rows not used
Bank 10
Rows not used
Figure 13: DDRAM description with Mux Mode = 0 and LSB = 0
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EM6125
If Mux Mode = 1, the DDRAM provides a 81 rows and 102 columns matrix. 8 columns on the left + 8 columns on the right are not used for display refresh, the cells can not be addressed.
0
- - - - x-address - - - -
101
Columns not used 0 Bank 0
DB7 DB7 DB6 DB5 DB7 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Columns not used Row 0 Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Row 8 Row 9 Row 10
Bank 1
DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5
Bank 8
DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5
Bank 9
DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5
10
Bank 10
DB4 DB3 DB2 DB1 DB0
Row 55 Row 56 Row 57 Row 58 Row 59 Row 60 Row 61 Row 62 Row 63 Row 64 Row 65 Row 66 Row 67 Row 68 Row 69 Row 70 Row 71 Row 72 Row 73 Row 74 Row 75 Row 76 Row 77 Row 78 Row 79 Row 80
Figure 14: DDRAM description with Mux Mode = 1 and LSB = 0
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EM6125
If Mux Mode = 1 and LSB=1.
0
- - - - x-address - - - -
101
Columns not used 0 Bank 0
DB0 DB0 DB1 DB2 DB0 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
Columns not used Row 0 Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Row 8 Row 9 Row 10
Bank 1
DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2
Bank 8
DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2
Bank 9
DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2
10
Bank 10
DB3 DB4 DB5 DB6 DB7
Row 55 Row 56 Row 57 Row 58 Row 59 Row 60 Row 61 Row 62 Row 63 Row 64 Row 65 Row 66 Row 67 Row 68 Row 69 Row 70 Row 71 Row 72 Row 73 Row 74 Row 75 Row 76 Row 77 Row 78 Row 79 Row 80
Figure 15: DDRAM description with Mux Mode = 1 and LSB = 1
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8.5.2 DDRAM addressing The x-address and the y-address pointers are used to address RAM cells. They are set by instructions "initialization 1" and "initialization 2". As EM6125 offers 2 digitally programmable multiplex rates, number of row drivers and number of column drivers are not fixed. As DDRAM is an image of LCD display, address ranges also depend on multiplex rate (Mux Mode): If Mux Mode = 0: If Mux Mode = 1: 0 x-address 117 0 y-address 8 0 x-address 101 0 y-address 10
Addresses outside these ranges are not allowed. There are three functions that affects the pointers: DEC, V and MX. They are set by instructions "initialization 1" and "initialization 2" (see Table 4: EM6125 instructions). Instruction DEC increment or decrement x-address: If DEC = 0, x-address increments after each byte written to the RAM. After the last x-address, x-address wraps around to 0 and y-address increments. If DEC = 1, x-address decrements after each byte written to the RAM. After x-address=0, x-address wraps around to the higher x-address for the select mux mode and y-address increments. DEC allows write to the RAM in two ways right and left easily. Instruction V horizontal or vertical mode addressing: If V = 0 (horizontal mode addressing), x-address increments or decrements after each byte written to the RAM. After the last x-address, x-address wraps around to 0 or to the higher x-address and y-address increments. If V = 1 (vertical mode addressing), y-address increments after each byte written to the RAM. After the last yaddress, y-address wraps around to 0 and x-address increments or decrements. Instruction MX mirrored the DDRAM columns: If MX = 0, x-address 0000000b corresponds to DDRAM column 0. If MX = 1, x-address 0000000b corresponds to DDRAM column 117 or 101. The table below represents the next address select after pointers are in the last allowed address: Mux Mode 0 1 0 1 DEC 0 0 1 1 Last allowed address x-address y-address 117 8 101 10 0 8 0 10
Table 3
Next address x-address y-address 0 0 0 0 117 0 101 0
The following tables represent the way that the pointers x-address and y-address are working according with the setting of the instructions Mux Mode, V, MX and DEC.
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Mux Mode = 0, V = 0, DEC =0, MX = 0:
0 0 1 2 | y -a d d re ss | 6 7 8 Pad S33 Pad S150 1 2 3 -x-a d d re ss --11 4 115 116 117
Figure 16
Mux Mode = 0, V = 0, DEC =1, MX = 0:
0 0 1 2 | y -a d d re ss | 6 7 8 Pad S33 Pad S150 1 2 3 -x-a d d re ss --11 4 115 116 117
Figure 17
Mux Mode = 1, V = 0, DEC =0, MX = 0:
0 0 1 2 | y -a d d re ss | 8 9 10 Pad S41 Pad S142 1 2 3 -x-a d d re ss --98 99 100 101
Figure 18
Mux Mode = 1, V = 0, DEC =1, MX = 0:
0 0 1 2 | y -a d d re ss | 8 9 10 Pad S41 Pad S142 1 2 3 -x-a d d re ss --98 99 100 101
Figure 19
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Mux Mode = 0, V = 1, DEC =0,MX = 0:
0 0 1 2 | y -a d d re s s | 6 7 8 Pad S33 Pad S150 1 2 3 -x -a d d re s s --114 115 116 117
Figure 20
Mux Mode = 0, V = 1, DEC =1,MX = 0:
0 0 1 2 | y -a d d re s s | 6 7 8 Pad S33 Pad S150 1 2 3 -x -a d d re s s --114 115 116 117
Figure 21
Mux Mode = 1, V = 1, DEC =0, MX = 0:
0 0 1 2 | y -a d d re s s | 8 9 10 Pad S41 Pad S142 1 2 3 -x -a d d re s s --98 99 100 101
Figure 22
Mux Mode = 1, V = 1, DEC =1, MX = 0:
0 0 1 2 | y -a d d re s s | 8 9 10 Pad S41 Pad S142 1 2 3 -x -a d d re s s --98 99 100 101
Figure 23
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Mux Mode = 0, V = 0, DEC =0, MX = 1:
117 0 1 2 | y -a d d re s s | 6 7 8 Pad S33 Pad S150 116 115 114 -x -a d d re s s --3 2 1 0
Figure 24
Mux Mode = 0, V = 0, DEC =1, MX = 1:
117 0 1 2 | y -a d d re s s | 6 7 8 Pad S33 Pad S150 116 115 114 -x -a d d re s s --3 2 1 0
Figure 25
Mux Mode = 1, V = 0, DEC =0, MX = 1:
101 0 1 2 | y -a d d re s s | 8 9 10 Pad S41 Pad S142 100 99 98 -x -a d d re s s --3 2 1 0
Figure 26
Mux Mode = 1, V = 0, DEC =1, MX = 1:
101 0 1 2 | y -a d d re s s | 8 9 10 Pad S41 Pad S142 100 99 98 -x -a d d re s s --3 2 1 0
Figure 27
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Mux Mode = 0, V = 1, DEC =0,MX = 1:
117 0 1 2 | y -a d d re s s | 6 7 8 Pad S33 Pad S150 116 115 114 -x -a d d re s s --3 2 1 0
Figure 28
Mux Mode = 0, V = 1, DEC =1,MX = 1:
117 0 1 2 | y -a d d re s s | 6 7 8 Pad S33 Pad S150 116 115 114 -x -a d d re s s --3 2 1 0
Figure 29
Mux Mode = 1, V = 1, DEC =0, MX = 1:
101 0 1 2 | y -a d d re s s | 8 9 10 Pad S41 Pad S142 100 99 98 -x -a d d re s s --3 2 1 0
Figure 30
Mux Mode = 1, V = 1, DEC =1, MX = 1:
101 0 1 2 | y -a d d re s s | 8 9 10 Pad S41 Pad S142 100 99 98 -x -a d d re s s --3 2 1 0
Figure 31
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8.6 Initialization of EM6125 Data loaded in EM6125 can be divided in two parts: The bits stored in the DDRAM, which are corresponding to LCD pixels. The command bits, which are used to set functions of the LCD controller. The way of addressing these bits is described in table below:
Control Byte Instruction
Mux Mode X[6] TC [1] X[5] TC [0] X[4] Inv. Row X[3] Inv. Video V
Control Byte Description
Initialization 0 Initialization 1
0 0
1 1
0 0
0 0
0 0
0 0
0 0
0 0
0 1
MX X[2]
Blank Checker X[1] Vlcd Dischg Vlcd Level [2] First Row PD [1] 0 0 0 0 X[0]
Set functions Set column adress for DDRAM write access and vertical/horizontal addressing Set bank adress for DDRAM write access, increment /decrement pointer and LSB/MSB mode Programming the internally generated LCD voltage supply VLCD Number of voltage multiplier stages Partial display parameters Sleep mode Byte test 0, all bits must be set to 0 Byte test 1, all bits must be set to 0 Byte test 2, all bits must be set to 0 Byte test 3, all bits must be set to 0 Write data byte to the Display Data Ram Read Status Byte from EM6125 Status Byte = initialization 0 using I C interface
2
Initialization 2
0
1
0
0
0
0
0
1
0
Y[3] Vlcd Level [7] Mult [1] 0 0 0 0
Y[2] Vlcd Level [6] Mult [0] 0 0 0 0
Y[1] Vlcd Level [5]
Partial Display
Y[0] Vlcd Level [4] First Row PD [3] 0 0 0 0
0 Vlcd Level [3] First Row PD [2] 0 0 0 0
DEC Vlcd Level [1] First Row PD [0] 0 0 0 0
LSB Vlcd Level [0] Sleep
Initialization 3
0
1
0
0
0
0
0
1
1
Initialization 4 Test 0 Test 1 Test 2 Test 3 Write 1 byte in DDRAM Read 1 byte in initialization
0
1
0
0
0
0
1
0
0
0 0 0 0
1 1 1 1
0 0 0 0
1 1 1 1
0 0 1 1
0 1 0 1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0
1/0
1
0
0
0
0
0
0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
-
-
-
-
-
-
-
-
Mux Mode
TC [1]
TC [0]
Inv. Row
MX
Blank Checker
Inv. Video
Table 4: EM6125 instructions
Bits of instructions from Table 4 and active levels and state after reset: Bits Mux Mode TC[1:0] Inv. Row. MX Blank Checker Inv. Video X[6:0] V Y[3:0] VLCD Dischg DEC LSB VLCD Level[7:0] Mult[1:0] Partial Display First RowPD[3:0] Sleep 0 1 Multiplex rate 65 Multiplex rate 81 Select VLCD Temperature Coefficient Normal row drivers Mirrored row drivers Normal column drivers Mirrored column drivers Display DDRAM content LCD blanked (all OFF) Display DDRAM content LCD = checker board LCD = DDRAM LCD = NOT (DDRAM) x-address pointer. Selects DDRAM columns to be accessed Horizontal addressing Vertical addressing y-address pointer. Selects DDRAM bank to be accessed Normal Mode Discharge Capacitor x-address pointer incremented x-address pointer decrement DB7 copied to the higher row of the DB0 copied to the higher row of the selected bank selected bank Program the required LCD supply voltage Number of voltage multiplier stages Mux Mode multiplex rate 17 LCD rows active only Position of first active row when partial display mode Normal mode No LCD pixel active, low power consumption
Table 5: Internal functions after reset. Copyright 2001, EM Microelectronic-Marin SA 23 www.emmicroelectronic.com
State after reset 0 00b 0 0 0 0 0 0000000b 0 0000b 0b 0 0 00000000b 00b 0 0000b 0
EM6125
8.7 Description of instructions 8.7.1 Initialization 0 8.7.1.1 Mux Mode Set the multiplex rate. Mux Mode Multiplex rate (number of row drivers) Row drivers Number of column drivers Column drivers Bias system 0 65 S0 S32 S151 S182 118 S33 S150 1/9 Table 6 1 81 S0 S40 S143 S182 102 S41 S142 1/10
The bias system sets the voltages V1, V2, V3 and V4 applied to row and column drivers. Assuming these voltages comes from a resistive divider, we have:
VLCD
R V1 R V2 nR V3 R V4 R VSS
The value of the corresponding bias system is: V1/ VLCD = 1/(n+4). It is chosen to optimize the value of the RMS voltage applied to a LCD pixel ON divided by the RMS voltage applied to a LCD pixel OFF: (VON)RMS/(VOFF)RMS. This condition leads to: 1 =1 (n + 4) (1 + MultiplexRate ) bias systems 1/5 for multiplex rate 17 (partial display mode) bias systems 1/9 for multiplex rate 65 bias systems = 1/10 for multiplex rate 81
8.7.1.2 TC[1:0] It sets the VLCD temperature compensation. 4 temperature coefficients are available for the internally generated voltage supply VLCD. One of these coefficients is chosen depending one the LCD crystal needs. The temperature coefficient is proportional to VLCD.
VLCD Temperature Coefficients
8.800
TC[1] 0 0 1 1
TC[0] 0 1 0 1
Table 7
VLCD Temperature coefficient (mV/C) 0 -0.39 x VLCD -0.86 x VLCD -1.34 x VLCD
8.600
8.400
8.200
8.000
7.800
7.600
7.400 -20 -10 0 10 20 30 40 50 60 70
Temperature [C]
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8.7.1.3 Inv. Row Row driver pads can be mirrored to give more flexibility for LCD interconnects. This function acts on the row driver that is activated when a given DDRAM row is read: it becomes active with no need of rewriting the RAM (see Table 8 and Figure 34: LCD output pads configuration depending on Mux Mode, Inv. Row and MX). Read data when Inv. Row=0:
0 0 1 2 | y -a d d re ss | | | 8 or 10 1 2 3 -x -a d dr e s s ----101 or 117
Figure 32
Read data when Inv. Row=1:
0 0 1 2 | y -a d d re ss | | | 8 or 10 1 2 3 -x -a d dr e s s ----101 or 117
Figure 33
In v . R o w M ux M ode S0 S1 S32 S33 S34 S35 S36 S37 S38 S39 S40 S 4 1 to S 1 4 2 S 143 S 144 S 145 S 146 S 147 S 148 S 149 S 150 S 151 S 152 S 182 S 183 = S 0
0 0 Row 0 Row 1 R ow 32 x -a d d re e s s x -a d d re e s s x -a d d re e s s x -a d d re e s s x -a d d re e s s x -a d d re e s s x -a d d re e s s x -a d d re e s s x -a d d re e s s x -a d d re e s s x -a d d re e s s x -a d d re e s s x -a d d re e s s x -a d d re e s s x -a d d re e s s x -a d d re e s s R ow 64 R ow 63 R ow 33 Row 0 = = = = = = = =
1 0 Row 64 Row 63 Row 32 0 1 2 3 4 5 6 7
0 1 Row 0 Row 1 Row Row Row Row Row Row Row Row Row Row Row Row Row Row Row Row Row Row Row 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71
1 1 R ow 80 R ow 79 Row Row Row Row Row Row Row Row Row Row Row Row Row Row Row Row Row Row Row 48 47 46 45 44 43 42 41 40 0 1 2 3 4 5 6 7 8 9
= = = = = = = =
x -a d d re e s s = 8 to x -a d d re e s s = 1 0 9 110 111 112 113 114 115 116 117 Row 0 Row 1 Row 31 Row 64
x -a d d re e s s = 0 to x -a d d re e s s = 1 0 1
Row 41 Row 0
R ow 39 R ow 80
Table 8
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EM6125
8.7.1.4 MX Column driver pads can also be mirrored to give more flexibility for LCD interconnects. This function change the x-address pointer to reverse columns of the DDRAM accessed during a write cycle: a rewrite cycle is required to observe changes on outputs (see Figure 34: LCD output pads configuration depending on Mux Mode, Inv. Row and MX) Table 9 shows how the DDRAM is connected to LCD output pads, depending on bits Mux Mode, MX and Inv. Row.
MX Mux Mode S0 0 0 Row 0 1 0 0 1 Row 0 1 1
S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 to S139 S140 S141 S142 S143 S144 S145 S146 S147 S148 S149 S150 S151
Row 32 x-address = 0 x-address = 1 x-address = 2 x-address = 3 x-address = 4 x-address = 5 x-address = 6 x-address = 7 x-address = 8 x-address = 9 x-address = 10 x-address =11 to x-address =106 x-address x-address x-address x-address x-address x-address x-address x-address x-address x-address x-address = = = = = = = = = = = 107 108 109 110 111 112 113 114 115 116 117 Row 64 x-address = 117 x-address = 116 x-address = 115 x-address = 114 x-address = 113 x-address = 112 x-address = 111 x-address = 110 x-address = 109 x-address = 108 x-address = 107 x-address =106 to x-address =11 x-address = 10 x-address = 9 x-address = 8 x-address = 7 x-address = 6 x-address = 5 x-address = 4 x-address = 3 x-address = 2 x-address = 1 x-address = 0
Row Row Row Row Row Row Row Row Row x-address = 0 x-address = 1 x-address = 2 x-address =3 to x-address = 98 x-address = 99 x-address = 100 x-address = 101 Row Row Row Row Row Row Row Row Row
32 33 34 35 36 37 38 39 40 x-address = 101 x-address = 100 x-address = 99 x-address = 98 to x-address = 3 x-address = 2 x-address = 1 x-address = 0 80 79 78 77 76 75 74 73 72
S182 S183 = S0
Table 9: Relation between LCD output pads and row and columns of DDRAM
Row 33 Row 0
Row 41 Row 0
The combination of Mux Mode, Inv. Row and MX gives the following figures (next page) of output pads. 8.7.1.5 Blank Sets all the LCD pixels OFF. Every row drivers and column drivers are at VSS level. DDRAM content is not affected by this instruction. 8.7.1.6 Checker Sets all the LCD pixels in a checker mode, LCD displays alternately ON and OFF pixels. DDRAM content is not affected by this instruction. 8.7.1.7 Inv. Video Sets an inverse video mode. If Inv. Video = 0, a logical 1 level stored in the DDRAM leads to a "ON" pixel displayed the LCD. If Inv. Video = 1, a logical 1 level stored in the DDRAM leads to a "OFF" pixel displayed the LCD. DDRAM content is not affected by this instruction.
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EM6125
Row 53 x-addr=106
x-addr=106 Row 11 x-addr=11 Row 53
Row 33 Row 0
Row 31 Row 64
Row 33 Row 0
Mux Mode = 0
Mux Mode = 0
Mux Mode = 0
Inv. Row = 0
Inv. Row = 1
Inv. Row = 0
MX. = 0
MX. = 0
MX = 1
Row 0
Row 64
Row 0
x-addr=11 Row 21
x-addr=11 Row 43
x-addr=106 Row 21
Row 61 x-addr=98 x-addr=98
Row 19 x-addr=4
Row 61
Row 41 Row 0
Row 39 Row 80
Row 41 Row 0
Mux Mode = 1
Mux Mode = 1
Mux Mode = 1
Inv. Row = 0
Inv. Row = 1
Inv. Row = 0
MX = 0
MX = 0
MX = 1
Row 0
Row 80
Row 0
x-addr=3 Row 21
x-addr=3 Row 59
x-addr=98 Row 21
Figure 34: LCD output pads configuration depending on Mux Mode, Inv. Row and MX
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8.7.2 Initialization 1 8.7.2.1 X[6:0] These 7 bits set the x-address pointer of the DDRAM. Data are written in column "x-address" with: X[6] = MSB, X[0] = LSB. As the number of column drivers depends on the chosen multiplex rate, the DDRAM x-address pointer should also satisfy the following relationships: If Mux Mode = 0 then 0 x-address 1110101b. (117). If Mux Mode = 1 then 0 x-address 1100101b. (101). 8.7.2.2 V Vertical addressing: If V = 0, DDRAM x-address pointer is incremented or decrement after each data byte send. If V = 1, DDRAM y-address pointer is incremented or decrement after each data byte send. 8.7.3 Initialization 2 8.7.3.1 Y[3:0] These 4 bits set the y-address pointer of the DDRAM. Data are written in bank "y-address" with Y[3]= MSB, Y[0]= LSB. As the multiplex rate is digitally programmable, the DDRAM y-address pointer should also satisfy the following relationships: If Mux Mode = 0 then 0 y-address 1000b. If Mux Mode = 1 then 0 y-address 1010b. 8.7.3.2 Vlcd Dischg. VLCD Discharge works to discharge the capacitor connected to PAD VLCD. This operation becomes necessary when programming Partial Display Mode. In this case, a lower VLCD is required than the voltage used for normal mux 65 or 81 operation, the display at beginning of partial mode operation could be completely `ON' until VLCD is low enough. To avoid this, an internal pull down helps the VLCD voltage to come down and hence reach the new optimum value in a short time. This pull down is on until bit `Vlcd Dischg' is at 1L. Typical use of `Vlcd Dischg' command:
Normal mux 65 or mux 81 mode VLCD = 8V
Blank = 1 Partial Display = 1 VLCD_Level = 2Bh (4.5V) VLCD Dischg = 1
T 30ms, depending on VLCD capacitor
VLCD Dischg = 0 Blank = 0
Using this command with external power supply on VLCD can damage the IC. 8.7.3.3 DEC H controls the DDRAM writing direction: If DEC = 0 then x-address pointer increments after each byte written to the DDRAM. If DEC = 1 then x-address pointer decrements after each byte written to the DDRAM. 8.7.3.4 LSB This instruction change the bytes send to the DDRAM before writing them. For instance, for bank 1 we have: If LSB = 0 then DB7 is written on Row 1. If LSB = 1 then DB0 is written on Row 1 (see Figure 14 and Figure 15). 8.7.4 Initialization 3
8.7.4.1 Vlcd Level[7:0] Set the internally generated voltage level. These 8 bits generate integer "VLCD Level", VLCD Level [7] = MSB, VLCD Level [0] = LSB. VLCD is given by the following formula:
VLCD = 3.02 + 0.0352 x VLCD _Level
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8.7.5 Initialization 4 8.7.5.1 Mult[1:0] Set the internal voltage multiplier factor. These bits should be chosen depending on the VHV supply voltage level, the desired VLCD voltage and the current consumption due to LCD load. If low VLCD is required, for instance when partial display mode is enabled, lower voltage multiplier range can be used, leading in current consumption reduction (improved voltage multiplier efficiency). Mult1 0 0 1 1 Mult0 0 1 0 1
Table 10
Voltage multiplier
x2 x3 x4 x5
8.7.5.2 Partial Display Set the partial display configuration of the driver (multiplex ratio 17). In this configuration, 17 rows only are active: The row which corresponds to RAM address 0. 16 other rows, first one is defined by First Row PD [3:0]. Partial Display 0 1 Multiplex rate 65 or 81 (depending on Mux Mode) 17
Table 11
8.7.5.3 First Row PD[3:0] Partial display mode yields to a LCD with 2 banks activated only. Row 0 is always active, it could be used to drive icons. The 16 other active rows are chosen from 64 or 80 row as shown on table: Mux Mode 0 or 1 First Row PD[3] 0 0 0 0 0 0 0 0 1 First Row PD[2] 0 0 0 0 1 1 1 1 0 First Row PD[1] 0 0 1 1 0 0 1 1 0 First Row PD[0] 0 1 0 1 0 1 0 1 0 First active row (DDRAM) Row 1 Row 9 Row 17 Row 25 Row 33 Row 41 Row 49 Row 57 Row 65
Table 12
Last active row (DDRAM) Row 16 Row 24 Row 32 Row 40 Row 48 Row 56 Row 64 Row 72 Row 80
Activated banks 0,1,2 0,2,3 0,3,4 0,4,5 0,5,6 0,6,7 0,7,8 0,8,9 0,9,10
1
If Mux Mode = 0, 0 First_Row PD [3:0] 0110b. If Mux Mode = 1, 0 First_Row PD [3:0] 1000b. Values for "First_Row PD [3:0]" outside these ranges are not allowed. 8.7.5.4 Sleep This function stops all functionality, internal oscillator and voltage multiplier are off, and LCD is blanked. It yields to a very low current consumption with leakage currents only. 8.7.6 Test 0 to 3 All bits must be set to 0 (see example in typical application page 35).
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8.8 LCD outputs The LCD output pads are connected to LCD electrodes, signals and voltages are optimized for the best LCD contrast and a null DC component of voltage applied to LCD pixels. Table 13 gives bias voltages referring to VLCD.
Multiplex Rate
VLCD
V1
V2
V3
V4
VSS
n
1
ae1o 1- c e n +1
0.90
ae2o 1- c / e n +1
0.80
2 n +1
0.20
1 n +1
0.10
0
81 (Mux Mode = 1)
1
0
65 (Mux Mode = 0)
1
0.89
0.78
0.22
0.11
0
17 (Partial Display = 1)
1
0.80
0.60
0.40
0.20
0
Table 13: Values of intermediate bias voltages
Table 14 gives values of VLCD in reference to RMS voltage applied to a pixel OFF and the contrast achieved between a ON pixel and a OFF pixel. These values correspond to bias voltages described on Table 13.
Programmed multiplex rate
LCD Bias configuration
VLCD VOFF (RMS)
VON (RMS) VOFF (RMS)
81
6 levels
n ( n + 1)2 = 7.500 2( n - 1) n ( n + 1)2 = 6.847 2( n - 1)
n ( n + 1)2 = 4.162 2( n - 1)
n +1 = 1.118 n -1 n +1 = 1.133 n -1 n +1 = 1.281 n -1
65
6 levels
17
6 levels
Table 14: Required LCD supply voltage and achieved LCD contrast
VLCD gives the required VLCD voltage supply. We VOFF (RMS) can observe that the Partial Display mode decreases VLCD, leading to lower power consumption. Current consumption is also decreased because lower VLCD leads to choose fewer stages for voltage multiplier and the efficiency is improved. The chosen LCD gives the value of VOFF (RMS) and the value of
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8.9 LCD refresh frequency LCD refresh frequency depends on an internal RC oscillator. Pad FR outputs this frequency multiplied by the multiplex rate. Following figures display typical variations depending on VDD power supply and temperature.
FR=f(VDD) @25C
77
76
75
74
73 1.8 2.3 2.8 3.3 3.8 4.3 4.8
VDD
LCD refresh frequency depending on temperature
85
83
81
79
77
75
73
71
69
67
65 -20 -10 0 10 20 30 40 50 60 70
Temperature [C]
8.10 VLCD depending on VHV
VLCD (VHV)
8.1
8.09
8.08
8.07
8.06
8.05
8.04
8.03
8.02
8.01
8 2.4 2.9 3.4 3.9 4.4 4.9
VHV [V]
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8.11 LCD driver waveforms Row and Column Multiplexing Waveform EM6125 (81)
frame n
VLCD V1 V2
frame n+1
Vstate1 (t)
Row 1
Vstate2 (t)
Row 1
V3 V4 VSS
VLCD V1 V2
Row 2
V3 V4 VSS
Row 2
VLCD V1 V2
Col 0
V3 V4 VSS
Col 0
Col 1
VLCD V1 V2
Col 1
V3 V4 VSS
VLCD V2 - VSS
Vstate1 (t) = Col1 (t) - Row1 (t)
VLCD - V1 0V V2 - V1 V3 - V4 0V VSS - V4
Vstate1 (t)
V3 - VLCD -VLCD
VLCD V2 - VSS
Vstate2 (t) = Col1 (t) - Row2 (t)
VLCD - V1 0V V2 - V1 V3 - V4 0V VSS - V4
Vstate2 (t)
V3 - VLCD -VLCD
0 1 2 3 4 5 6 7 8...
...80 0 1 2 3 4 5 6 7 8...
...80
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EM6125
Row and Column Multiplexing Waveform EM6125 (65)
frame n
VLCD V1 V2
frame n+1
Vstate1 (t)
Row 1
Vstate2 (t)
Row 1
V3 V4 VSS
VLCD V1 V2
Row 2
V3 V4 VSS
Row 2
VLCD V1 V2
Col 1
V3 V4 VSS
Col 1
Col 2
VLCD V1 V2
Col 2
V3 V4 VSS
VLCD V2 - VSS
Vstate1 (t) = Col1 (t) - Row1 (t)
VLCD - V1 0V V2 - V1 V3 - V4 0V VSS - V4
Vstate1 (t)
V3 - VLCD -VLCD
VLCD V2 - VSS
Vstate2 (t) = Col2 (t) - Row2 (t)
VLCD - V1 0V V2 - V1 V3 - V4 0V VSS - V4
Vstate2 (t)
V3 - VLCD -VLCD
0 1 2 3 4 5 6 7 8...
...64 0 1 2 3 4 5 6 7 8...
...64
Figure 36 Copyright 2001, EM Microelectronic-Marin SA 33 www.emmicroelectronic.com
EM6125
8.11.1 Partial Display Row and Column Multiplexing Waveform EM6125 (17)
frame n
VLCD V1 V2
frame n+1
Vstate1 (t)
Row 1
Vstate2 (t)
Row 1
V3 V4 VSS
VLCD V1 V2
Row 2
V3 V4 VSS
Row 2
VLCD V1
Col 0
V2 V3 V4 VSS
Col 0
Col 1
VLCD V1
Col 1
V2 V3 V4 VSS
VLCD
V2 - VSS
Vstate1 (t)
VLCD - V1 0V V2 - V1 V3 - V4 0V VSS - V4
Vstate1 (t) = Col1 (t) - Row1 (t)
V3 - VLCD VLCD -VLCD V2 - VSS
Vstate2 (t)
VLCD - V1 0V V2 - V1 V3 - V4 0V VSS - V4
Vstate2 (t) = Col1 (t) - Row2 (t)
V3 - VLCD
-VLCD 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 160 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Figure 37 Copyright 2001, EM Microelectronic-Marin SA 34 www.emmicroelectronic.com
EM6125
9 Typical Application
This example gives typical programming steps for EM6125 with I C interface, for serial interface, start and stop conditions should be replaced by CS at 0L and CS at 1L. LCD display is connected as described on Figure 38:
2
Example
Liquid Cristal Display 81 row x 102 columns
41 rows
102 columns 40 rows
Col 2 Col 0 Row 40
Col 99 Col 101 Row 80
EM6125
Row 21 Row 61
Figure 38: Connection between EM6125 and LCD for the application example
Step 1 2 3 4 5
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Comment Power on Reset I2C start condition x 1 x 0 x 0 x 0 x 0 x 0 x 0 0 0 EM6125 slave address + write mode Control byte for initialization 0 Data byte = initialization 0 Multiplex Rate = 81 Vlcd Temperature Coefficient = -0.39 x Vlcd (mV/C) No row or column mirroring No blank, Checker or Video functions. Control byte for initialization 3 Data byte = initialization 3 Programmed Vlcd_level = 10001110b (8Eh=142) Vlcd = 3.02 + 142*0.0352 = 8.02V Control byte for initialization 4 Data byte = initialization 4 x 5 Voltage Multiplier No partial display mode. No sleep mode Control byte for test 0 bits test must be set to 0L Control byte for test 1 bits test must be set to 0L Control byte for test 2 bits test must be set to 0L Control byte for test 3 bits test must be set to 0L
35
Display Undefined Blank Blank Blank Blank
A reset cycle must always follow the power on
6
1
0
1
0
0
0
0
0
Blank
7 8 9 10 11 12 13 14 15 16 17 18
1 1 1 1 1 0 1 0 1 0 1 0
0 0 0 1 0 0 0 0 0 0 0 0
0 0 0 0 1 0 1 0 1 0 1 0
0 0 0 0 0 0 0 0 1 0 1 0
0 1 0 0 0 0 1 0 0 0 1 0
0 1 1 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0
Blank Blank Blank Undefined
Undefined
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EM6125
Step DB7 0 19 DB6 1 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0 Comment Last control byte DDRAM write selected Fisrt DDRAM byte stored at x-address = 0, y-address = 0 Horizontal addressing is selected (state after reset) Only DB7 is stored at row 0 of DDRAM, column 0 Display Undefined
20
0
x
x
x
x
x
x
x
21 to 121
0
x
x
x
x
x
x
x
Only DB7 is stored at row 0, columns 1 to 101
122
0
0
0
0
0
0
0
0
DB7 to DB0 are stored at column 0, rows 1 to 8
123
1
1
1
1
1
1
1
0
DB7 to DB0 are stored at column 1, rows 1 to 8
124
1
0
0
1
0
0
1
0
DB7 to DB0 are stored at column 2, rows 1 to 8
125
1
0
0
1
0
0
1
0
DB7 to DB0 are stored at column 3, rows 1 to 8
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EM6125
Step DB7 1 126 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 0 Comment DB7 to DB0 are stored at column 4, rows 1 to 8 Display
127 to 229
0
0
0
0
0
0
0
0
DB7 to DB0 are stored at column 5 to 101, rows 1 to 8 column 0 to 5, rows 9 to 16
230 231 232 233 234 235 236 to 325
0 1 0 0 0 1 0
0 1 1 0 1 1 0
0 1 0 1 0 1 0
0 1 0 0 0 1 0
0 1 0 0 0 1 0
0 1 0 0 0 1 0
0 1 0 0 0 1 0
0 0 0 0 0 0 0
Write letter M
DB7 to DB0 are stored at column 12 to 101, rows 9 to 16
326 327 328 329 330 331 332 333 334 335 336 337 338
I2C stop condition + new start condition x 1 0 1 0 0 0 1 1 1 0 x x 0 0 0 0 0 1 0 0 0 1 x x 0 0 0 0 0 1 0 0 0 0 x x 0 1 0 1 0 1 1 1 1 0 x x 0 1 0 0 0 1 0 0 0 1 x x 0 0 0 0 0 1 0 0 0 1 x x 0 0 1 0 0 0 1 1 1 0 x 0 1 0 0 0 0 0 0 0 0 0 x Continuation... EM6125 slave address + write mode Control byte for initialization 1 x-address = 12 , Horizontal mode addressing Control byte for initialization 2 y-address = 1 Write 6
Unchanged Unchanged Unchanged Unchanged Unchanged Unchanged
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EM6125
Step DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Comment I2C start condition 1 2 3 4 5 6 7 8 9 10 x 1 1 1 0 1 0 1 1 x 0 0 0 0 0 0 0 1 x 0 1 0 1 0 0 0 1 x 0 0 0 0 0 0 0 0 x 0 0 0 1 0 0 0 0 x 0 1 0 0 0 1 1 0 x 0 0 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 EM6125 slave address + write mode Control byte for initialization 0 Blank = 1 Control byte for initialization 3 Vlcd_level = 2Bh Control byte for initialization 2 Vlcd_Dischg = 1 Control byte for initialization 4 Partial display on banks: 0, 1 and 2 Wait 30 ms Control byte for initialization 32 Vlcd_Dischg = 0 Control byte for initialization 0 Blank = 0 Partial display on banks: 0, 1 and 2 Display Previously set Unchanged Unchanged All pixels OFF All pixels OFF All pixels OFF All pixels OFF All pixels OFF All pixels OFF All pixels OFF
11 12 13 14
1 0 1 1
0 0 0 0
0 0 0 1
0 0 0 0
0 0 0 0
0 0 0 0
1 0 0 0
0 0 0 0
All pixels OFF All pixels OFF All pixels OFF
15
1
0
0
0
0
1
0
0
Control byte for initialization 4
16
1
1
1
0
0
0
1
0
Partial display on banks: 0, 2 and 3
Remark: This typical application example shows a LCD display `ON' before the DDRAM is completely written, parts of the LCD are undefined as DDRAM data is random at power on. However, blank function can remain active until DDRAM is completed to avoid randomly ON or OFF pixels to appear on the LCD.
Copyright 2001, EM Microelectronic-Marin SA
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EM6125
10 Pad location
Figure 39
Mechanical Dimensions: Minimum pad pitch Bump size pads from S[0] to S[183] Bump size interface pads Bump hardness Wafer thickness Chip Size Typical value 70 50 x 100 x 17.5 102 x 102 x 17.5 50 380 7775 x 2175 Unit m m m Vickers m m
90 m
30 m
90 m
30 m
y center
30 m 30 m
90 m
y center
30 m
90 m
x center
x center
MARK 1 : x = - 61, y = 209
MARK 2 : x = 7397, y = 209
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EM6125
Pad VHV VHV VDD2 VDD2 VDD1 VDD1 VSS2 VSS2 VSS1 VSS1 VSS1 VSS1 I CS RES FR TEST SDA SCL VLCD VLCD VLCD VLCD S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 Serial number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 x 5543 5383 5223 5063 4903 4743 4583 4423 4263 4103 3943 3783 3623 3463 3303 3143 2913 2683 2453 2271 2111 1951 1791 1545 1475 1405 1335 1265 1195 1125 1055 985 915 845 775 705 635 565 495 425 355 285 215 145 75 0 0 0 0 0 0 0 0 0 y 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 362 432 502 572 642 712 782 852 922 Pad S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 S81 S82 S83 S84 Serial number 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 x 0 0 0 0 0 0 0 0 0 0 0 0 0 342 412 482 552 622 692 762 832 902 972 1042 1112 1182 1252 1322 1392 1462 1532 1602 1672 1742 1812 1882 1952 2022 2092 2162 2232 2302 2372 2442 2512 2582 2652 2722 2792 2862 2932 3002 3072 3142 y 992 1062 1132 1202 1272 1342 1412 1482 1552 1622 1692 1762 1832 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785
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EM6125
Pad S85 S86 S87 S88 S89 S90 S91 S92 S93 S94 S95 S96 S97 S98 S99 S100 S101 S102 S103 S104 S105 S106 S107 S108 S109 S110 S111 S112 S113 S114 S115 S116 S117 S118 S119 S120 S121 S122 S123 S124 S125 S126 S127 S128 S129 S130 S131 S132 S133 S134 Serial number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 x 3212 3282 3352 3422 3492 3562 3632 3702 3772 3842 3912 3982 4052 4122 4192 4262 4332 4402 4472 4542 4612 4682 4752 4822 4892 4962 5032 5102 5172 5242 5312 5382 5452 5522 5592 5662 5732 5802 5872 5942 6012 6082 6152 6222 6292 6362 6432 6502 6572 6642 y 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 1785 Pad S135 S136 S137 S138 S139 S140 S141 S142 S143 S144 S145 S146 S147 S148 S149 S150 S151 S152 S153 S154 S155 S156 S157 S158 S159 S160 S161 S162 S163 S164 S165 S166 S167 S168 S169 S170 S171 S172 S173 S174 S175 S176 S177 S178 S179 S180 S181 S182 S183 Serial number 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 x 6712 6782 6852 6922 6992 7334 7334 7334 7334 7334 7334 7334 7334 7334 7334 7334 7334 7334 7334 7334 7334 7334 7334 7334 7334 7334 7334 7259 7189 7119 7049 6979 6909 6839 6769 6699 6629 6559 6489 6419 6349 6279 6209 6139 6069 5999 5929 5859 5789 y 1785 1785 1785 1785 1785 1832 1762 1692 1622 1552 1482 1412 1342 1272 1202 1132 1062 992 922 852 782 712 642 572 502 432 362 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28
Table 15: Pad location.
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EM6125
11 Ordering Information
When ordering please specify the complete part number and package. Part Number Die Form & Thickness Bumping EM6125WS27 Sawn Wafer, 27mils No bumps EM6125WP15 Waffle pack, 15mils No bumps EM6125WP15E Waffle pack, 15mils Gold Bumps Other delivery form might be available upon request and for a minimum order quantity. Please contact EM sales.
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EM6125
12 Updates
Date ,Name Version 22.11.01 02.04.02 Chapter concerned All 8.5.1 Fig13,14,15 Old Version (Text, Figure, etc.) First version Row 17 Row 18 New Version (Text, Figure, etc.) Row 9 Row10
EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version.
(c) EM Microelectronic-Marin SA, 04/02, Rev. B/454 Copyright 2001, EM Microelectronic-Marin SA 43 www.emmicroelectronic.com

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