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T48C510
MARC4 - 4-bit MTP Universal Microcontroller
The T48C510 is an Multi Time Programmable (MTP) microcontroller which is pin and functionally compatible to the Atmel Wireless & Microcontrollers' M44C510E mask programmable microcontroller. It contains EEPROM, RAM, up to 34 digital I/O pins, up to 10 maskable external interrupt sources, 4 maskable internal interrupts, a watchdog timer, interval timer, 2 x 8-bit multifunction timer/counter module and a versatile software configurable on-chip system clock module.
Features / Benefits
D Programmable system clock with prescaler and five different clock sources: - Up to 8-MHz crystal oscillator (system clock) - 32-kHz crystal oscillator - RC-oscillator fully integrated - RC-oscillator with external resistor adjustment - External clock input D Wide supply-voltage range (2.4 V to 6.2 V) D Very low halt current D 4 KByte program EEPROM, 256 x 4-bit RAM D 8 hard- and software interrupt priority levels D Up to 10 external and 4 internal interrupts, bitwise maskable with programmable priority level D Up to 34 I/O lines
TE SCLIN OSCIN OSCOUT AVDD VSS NRST VDD TIM1
D I/O ports - bitwise configurable with combined interrupt handling (for serial I/O applications) D 2 x 8-bit multifunction timer/counters D Coded reset and watchdog timer D Power-on reset and "brown out" function D Various power-down modes D Efficient, hardware-controlled interrupt handling D High-level programming language in qFORTH D Comprehensive library of useful routines D Windows 95/NT based development and programmer tools
Config. EEPROM
Test Sleep
System clock
Real time clock
Master reset
EEPROM
4K x 8 bit
RAM
256 x 4 bit
Timer/ counter Watch- dog Prescaler Timer 1 Timer 0 Melody & buzzer
MARC4
4-bit CPU core
I/O bus
I/O I/O
4 4 4
I/O I/O
4
I/O
Interrupt & reset
4
I/O
Interrupt
4
I/O I/O
Interrupt
4 2
I/O
4
PM
Port 0 Port 1 Port 5 Port 7
Port A
Port B
Port C
Port 6
Port 4
16536
Figure 1. Block diagram
Rev. A2, 26-Feb-01
1 (61)
Preliminary Information
T48C510
Ordering Information
Extended Type Number T48C510 - ILS T48C510 - ILQ
BP70 BP71
Package SSO44 SSO44
OSCIN AVDD SCLIN BPC3 BPC2 BPB3 BPB2 BPB1 BPB0 BP72 BP73 BP61 BP60
Remarks Stick Taped and reeled
OSCOUT NRST BPA0 BPA1 25 BPA2 21 BP11 24 BPA3 BP10 22 23
44
43
42
41
40
PM
39
38
37
36
35
34
33
32
31
30
29
28 17
27 BPC0 18
T48C510
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BPC1 16
19 BP13
26
V SS BP53
TIM1
BP52
BP51
BP50
BP43
BP42
BP41
BP40
BP03
BP02
BP01
BP00
Figure 2. Pin connections SSO44-package Table 1 Pin description
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VDD VSS Power supply voltage +2.4 V to +6.2 V Circuit ground AVDD Analog power supply voltage +2.4 V to +6.2 V BP00 - BP03 BP10 - BP13 BP50 - BP53 BP70 - BP73 4 I/O lines of Port 0 - automatic nibblewise configurable / programmer interface 4 I/O lines of Port 1 - automatic nibblewise configurable 4 I/O lines of high current Port 5 - bitwise configurable 4 I/O lines of high current Port 7 - bitwise configurable BPA0 - BPA3 4 I/O lines of Port A - bitwise configurable, as inputs to a port monitor module and optional coded reset inputs 4 I/O lines of Port B - bitwise configurable I/O and as inputs to a port monitor module 4 I/O lines of Port C - bitwise configurable I/O 2 I/O lines of Port 6 - bitwise configurable I/O or as external programmable interrupts I/O line BP40 of Port 4 - configurable or timer/counter I/O T0OUT0 I/O line BP41 of Port 4 - configurable or timer/counter I/O T0OUT1 BPB0 - BPB3 BPC0 - BPC3 BP60 - BP61 BP40 (T0OUT0) BP41 (T0OUT1) BP42 (BUZ) TIM1 BP43 (NBUZ) SCLIN High current I/O line BP42 of Port 4 - configurable or buzzer output BUZ Dedicated I/O for Timer 1 High current I/O line BP43 of Port 4 - configurable or buzzer output NBUZ External trimming resistor or external clock input OSCIN TE 32-kHz quartz crystal or 4-MHz quartz crystal input pin OSCOUT NRST PM 32-kHz quartz crystal or 4-MHz quartz crystal output pin Testmode input, used to control the production test modes (internal pull-down) Reset input (/output), a logic low on this pin resets the device. An internal watchdog or coded reset can cause a low pulse on this pin. MTP program mode enable pin (internal pull-down) 2 (61) Rev. A2, 26-Feb-01
Name
Function
Preliminary Information
BP12
VDD
TE
20
T48C510
Table of Contents
1 MARC4 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Components of MARC4 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4 ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.5 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.6 I/O Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2 Software Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.1 Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.2 Oscillator Circuits and External Clock Input Stage . . . . . . . . . . . . . . . . . . . . . . . . RC-Oscillator 1 Fully Integrated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RC-Oscillator 2 with External Trimming Resistor . . . . . . . . . . . . . . . . . . . . . . . . . 4-MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-kHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quartz Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.3 Clock Management Register (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Configuration Register (SC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.4 Power-down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.5 Clock Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Peripheral Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Addressing Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Bidirectional Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Bidirectional Port 0 and Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Bidirectional Port 5, Port 7 and Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Bidirectional Port A and Port B with Port Monitor Function . . . . . . . . . . . . . . . . 2.2.4 Bidirectional Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.5 Bidirectional Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.6 TIM1 - Dedicated Timer 1 I/O Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Interval Timers / Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Interval Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Timer/Counter Module (TCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.1 General Timer/Counter Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 Timer/Counter in 16-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.3 Timer 0 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.4 Timer 1 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 5 5 6 6 9 9 9 9 11 11 12 13 13 14 14 14 14 15 15 15 16 16 17 17 18 18 21 22 23 23 25 27 28 28 29 30 30 32 35 35 44
2
Rev. A2, 26-Feb-01
3 (61)
Preliminary Information
T48C510
Table of Contents (continued)
2.6 2.7 2.8 Buzzer Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MTP Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Noise Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.1 Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8.2 Electromagnetic Emission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 DC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 49 50 50 51 51 51 51 53 57 57 58 59
3
4
5
4 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
1 MARC4 Architecture
Reset
Reset Clock
System clock
Sleep
1.1
General Description
The functionality, programming and pinning of the T48C510 is compatible with the M44C510E mask programmable microcontroller from Atmel Wireless & Microcontrollers. All on-chip modules are addressed and controlled with exactly the same programming code, so that a program targeted for the M44C510E can be read directly into the T48C510 and will operate in the same fashion. The MARC4 microcontroller consists of an advanced stack based 4-bit CPU core and on-chip peripherals. The CPU is based on the HARVARD architecture with physically separate program memory (EEPROM) and data memory (RAM). Three independent buses, the instruction bus, the memory bus and the I/O bus are used for parallel communication between EEPROM, RAM and peripherals. This enhances program execution speed by allowing both instruction prefetching, and a simultaneous communication to the on-chip peripheral circuitry. The
Rev. A2, 26-Feb-01
IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIII II IIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII
MARC4 CORE
PC X Y SP RP
Program memory
RAM
256 x 4-bit
Instruction bus
Instruction decoder Interrupt controller
Memory bus
TOS
CCR
ALU
I/O bus
On-chip peripheral modules
Figure 3. MARC4 core
94 8973
extremely powerful integrated interrupt controller with associated eight prioritized interrupt levels supports fast and efficient processing of hardware events. The MARC4 is designed for the high-level programming language qFORTH. The core includes an expression and a return stack. This architecture allows high-level language programming without any loss in efficiency or code density.
1.2
Components of MARC4 Core
The core contains EEPROM, RAM, ALU, a program counter, RAM address registers, an instruction decoder and an interrupt controller. The following sections describe each functional block in more detail:
1.2.1
EEPROM
The program memory (EEPROM) is programmed with the customer application program. The EEPROM is addressed by a 12-bit wide program counter, thus predefining a maximum program bank size of 4 Kbytes.
5 (61)
Preliminary Information
T48C510
FFFh 1F8 h 1F0h 1 E8h 1 E0h
SCALL addresses
EEPROM
1 E0 h 1 C0 h 18 0h
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
(4K x 8 bit)
Z ero p age
14 0h 1 00 h 0 C0 h 0 80 h
1FFh
Zero page
000h
0 20 h 01 8 h 01 0 h 00 8h 0 00 h
04 0h
00 8h 0 00 h
$RESET $AUTOSLEEP
Figure 4. EEPROM map of T48C510
The lowest user EEPROM address segment is taken up by a 512-byte zero page which contains predefined start addresses for interrupt service routines and special subroutines accessible with single-byte instructions (SCALL). The corresponding memory map is shown in figure 4. Look-up tables of constants can also be held in EEPROM and are accessed via the MARC4's built-in TABLE instruction.
Return Stack The 12-bit wide return stack is addressed by the return stack pointer (RP). It is used for storing return addresses of subroutines, interrupt routines and for keeping loop index counts. The return stack can also be used as a temporary storage area. The MARC4 instruction set supports the exchange of data between the top elements of the expression stack and the return stack. The two stacks within the RAM have a userdefinable location and maximum depth.
1.2.2
RAM
The MARC4 contains 256 x 4-bit wide static random access memory (RAM). It is used for the expression stack, the return stack and data memory for variables and arrays. The RAM is addressed by any of the four 8-bit wide RAM address registers SP, RP, X and Y. Expression Stack The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All arithmetic, I/O and memory reference operations take their operands from, and return their result to the expression stack. The MARC4 performs the operations with the top of stack items (TOS and TOS-1). The TOS register contains the top element of the expression stack and works in the same way as an accumulator. This stack is also used for passing parameters between subroutines and as a scratch pad area for temporary storage of data.
1.2.3
Registers
The MARC4 controller has seven programmable registers and one condition code register. They are shown in figure 6. Program Counter (PC) The program counter (PC) is a 12-bit register that contains the address of the next instruction to be fetched from the EEPROM. Instructions currently being executed are decoded in the instruction decoder to determine the internal micro operations. For linear code (no calls or branches) the program counter is incremented with every instruction cycle. If a branch, call, return instruction or an interrupt is executed, the program counter is loaded with a new address. The program counter is also used with the TABLE instruction to fetch 8-bit wide constants.
6 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
FCh FFh Global variables
RAM address register:
X Y SP RP
04h 00h
Return stack Global v 07h variables 03h
Figure 5. RAM map
RAM Address Registers The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y. These registers allow access to any of the 256 RAM nibbles. Expression Stack Pointer (SP) The stack pointer (SP) contains the address of the next-totop 4-bit item (TOS-1) of the expression stack. The pointer is automatically preincremented if a nibble is moved onto the stack, or postdecremented if a nibble is removed from the stack. Every postdecrement operation moves the item (TOS-1) to the TOS register before the SP is decremented. After a reset the stack pointer has to be initialized with " >SP S0 " to allocate the start address of the expression stack area. Return Stack Pointer (RP) The return stack pointer points to the top element of the 12-bit wide return stack. The pointer automatically preincrements if an element is moved onto the stack or it postdecrements if an element is removed from the stack. The return stack pointer increments and decrements in steps of 4. This means that every time a 12-bit element is stacked, a 4-bit RAM location is left unwritten. These locations are used by the qFORTH compiler to allocate 4-bit variables. After a reset, the return stack pointer has to be initialized with ">RP FCh ". RAM Address Register ( X and Y ) The X and Y registers are used to address any 4-bit item in the RAM. A fetch operation moves the addressed nibble onto the TOS. A store operation moves the TOS to the addressed RAM location. By using either the Rev. A2, 26-Feb-01
preincrement or postdecrement, addressing mode arrays in the RAM can be compared, filled or moved. Top Of Stack ( TOS ) The top of stack register is the accumulator of the MARC4. All arithmetic/logic, memory reference and I/O operations use this register. The TOS register receives data from the ALU, EEPROM, RAM or I/O bus. Condition Code Register ( CCR ) The 4-bit wide condition code register contains the branch, the carry and the interrupt-enable flag. These bits indicate the current state of the CPU. The CCR flags are set or reset by ALU operations. The instructions SET_BCF, TOG_BF, CCR! and DI allow direct manipulation of the condition code register. Carry/Borrow ( C ) The carry/borrow flag indicates that borrow or carry out of arithmetic logic unit ( ALU ) occurred during the last arithmetic operation. During shift and rotate operations, this bit is used as a fifth bit. Boolean operations have no affect on the C flag. Branch ( B ) The branch flag controls the conditional program branching. Should the branch flag have been set by a previous instruction, a conditional branch will cause a jump. This flag is affected by arithmetical, logical, shift, and rotate operations. Interrupt Enable ( I ) The interrupt-enable flag globally enables or disables the triggering of all interrupt routines with the exception of the non-maskable reset. After a reset, or on executing the 7 (61)
Preliminary Information
IIIII IIIII
TOS-1
Expression stack
Return stack
11 0 RP
III III
3 0 TOS TOS-1 TOS-2 4-bit 12-bit
(256 x 4-bit) Autosleep
RAM
Expression stack
SP
IIIII IIIII I IIIII I IIIIIII IIIIIII IIIII IIIIIII IIIIII IIII
IIIII IIIII
94 8975
T48C510
DI instruction, the interrupt-enable flag is reset, thus disabling all interrupts. The core will not accept any further interrupt requests until the interrupt-enable flag has been set again either by executing an EI, RTI or SLEEP instruction.
11
0
PC
7 0
Program counter
RP
7
0
0
0
Return stack pointer Expression stack pointer
SP
7 0
X
7 0
RAM address register (X) RAM address register (Y)
3 0
Y
TOS
3 0
Top of stack register C -- B I Condition code register
Interrupt enable Branch Reserved Carry / borrow
CCR
Figure 6. Programming model
8 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
1.2.4 ALU
The 4-bit ALU performs all the arithmetical, logical, shift and rotate operations with the top two elements of the expression stack (TOS and TOS-1) and returns the result to the TOS. The ALU operations affect the carry/borrow and branch flag in the condition code register (CCR).
1.2.5
Instruction Set
The MARC4 instruction set is optimized for the highlevel programming language qFORTH. Many MARC4 instructions are qFORTH words. This enables the compiler to generate a fast and compact program code. The CPU has an instruction pipeline which allows the controller to prefetch an instruction from EEPROM at the same time as the present instruction is being executed. The MARC4 is a zero-address machine. The instructions contain only the operation to be performed and no source or destination address fields. The operations are implicitly performed on the data placed on the stack. There are one and two byte instructions which are executed within 1 to 4 machine cycles. A MARC4 machine cycle is made up of two system clock (SYSCL) cycles. Most of the instructions are only one byte long and are executed in a single machine cycle.
1.2.6
I/O Bus
The I/O ports and the registers of the peripheral modules (Timer 0, Timer 1, Interval timer, Watchdog etc.) are I/O
Rev. A2, 26-Feb-01
IIIII IIII IIIII III II II IIIIIIII IIII IIIIIIIII IIII I IIII II I III I IIIIIIIIIIIIII I III II I I IIIII IIIIIIIIIIII IIII IIII IIIIIIIIIIIIIIIIII II IIIIIIII IIIII IIII IIIII IIII
RAM SP TOS-1 TOS-2 TOS-3 TOS-4 TOS ALU CCR
Figure 7. ALU zero-address operations
94 8977
mapped. All communication between the core and the onchip peripherals takes place via the I/O bus and the associated I/O control. With the MARC4 IN and OUT instructions, the I/O bus enables a direct read or write access to one of the 16 primary I/O addresses. More about the I/O access to the on-chip peripherals is described in the "Peripheral Modules". The I/O bus is internal and is not accessible by the customer on the final microcontroller device, but is used as the interface for the MARC4 emulation.
1.3
Interrupt Structure
The MARC4 can handle interrupts with eight different priority levels. They can be generated from the internal and external interrupt sources or by a software interrupt from the CPU itself. Each interrupt level has a hard-wired priority and an associated vector for the service routine in the EEPROM (see table 2, page 11). The programmer can postpone the processing of interrupts by resetting the interrupt enable flag (I) in the CCR. An interrupt occurrence will still be registered but the interrupt routine is only started after the I flag is set. All interrupts can be masked, and the priority individually software configured by programming the appropriate control register of the interrupting module (see section "Peripheral Modules").
9 (61)
Preliminary Information
T48C510
INT7
7 6 Priority level 5 4 3 2 1 0
INT3
INT5
INT3 active
Main / Autosleep
Time
Figure 8. Interrupt handling
Interrupt Processing For processing the eight interrupt levels, the MARC4 includes an interrupt controller with two 8-bit wide "interrupt pending" and "interrupt active" registers. The interrupt controller samples all interrupt requests during every non-I/O instruction cycle and latches these in the interrupt pending register. Whenever an interrupt request is detected, the CPU interrupts the program currently being executed, on condition that no higher priority interrupt is present in the interrupt active register. If the interrupt-enable bit is set, the processor enters an interrupt acknowledge cycle. During this cycle a short call (SCALL) instruction is executed to the service routine and the current PC is saved on the return stack. An interrupt service routine is finished with the RTI instruction. This instruction sets the interrupt-enable flag, resets the corresponding bits in the interrupt pending/active register and fetches the return address from the return stack to the program counter. When the interrupt-enable flag is reset
(triggering of interrupt routines is disabled), the execution of new interrupt service routines is inhibited, but not the logging of the interrupt requests in the interrupt pending register. The execution of the interrupt is then delayed until the interrupt-enable flag is set again. Note that interrupts are only lost if an interrupt request occurs while the corresponding bit in the pending register is still set (i.e., the interrupt service routine is not yet finished). After a master reset (power-on, external or watchdog reset), the interrupt-enable flag and the interrupt pending and interrupt active registers are all reset. Interrupt Latency The interrupt latency is the time from the occurrence of the interrupt to the interrupt service routine being activated. In the MARC4, this is extremely short and takes between 3 to 5 machine cycles depending on the state of the core.
10 (61)
Preliminary Information
AAAA AAAA AAAA I AAAIIIIII IIIIIII A
AAAI IA AAAAAAAAI IIIIII AIIII AAAAAI
AAA AAAA AAA AAAA AAAA AAAA
INT7 active RTI INT5 active INT2
RTI
AAA AAA
RTI
INT2 pending
INT2 active
RTI
SWI0
INT0 pending
INT0 active
RTI
AAAAA AAAAA
Main / Autosleep
94 8978
Rev. A2, 26-Feb-01
T48C510
Table 2 Interrupt priority table
Interrupt INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7
Priority lowest | | | | |
EEPROM Address 040h 080h 100h 140h 180h
Maskable Yes Yes Yes Yes Yes Yes Yes Yes
Interrupt Opcode C8h (SCALL 040h) D0h (SCALL 080h) E8h (SCALL 100h) E8h (SCALL 140h) F0h (SCALL 180h)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A A A AAAAAAA A A A AAA AAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAA A AA A A AAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAA A A AAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A AA A A AAAAAAA A A A AAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAA A AA A A AAAAAAA A A AAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAA A A A AAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAA A A A AAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAA A A A AAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAA A A A AAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAA A AAAAAAAA A AA A AA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAA A
AAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A
0C0h D8h (SCALL 0C0h) 1C0h 1E0h F8h (SCALL 1C0h) highest FCh (SCALL 1E0h)
1.3.1
Hardware Interrupts
Table 3 Hardware interrupts
Interrupt Source 0 NRST external Watchdog
Possible Interrupt Priorities 1 2 3 4 5 6 7
RST X # #
Interrupt Mask Register - - - Bit - - - 3 3
Function low level active level any inputs
1/2 - 2 sec. time out any edge, any input any edge, any input any edge any edge
Port A coded reset Port A monitor Port B monitor
* * * *
* * *
* * * *
* * *
PAIPR P6CR P6CR
PBIPR
Port 60 external Port 61 external
1,0 3,2 0 1 0 0
*
*
*
*
Interval timer INTA
ITIPR ITIPR T0CR T1CR
1 of 8 frequencies (1 - 128 Hz) 1 of 8 frequencies (8 - 8192 Hz)
Interval timer INTB Timer 0 Timer 1
*
*
*
*AA* *
*
overflow/compare/ end measurement compare
*
*
*
X = hardwired (neither optional or software configurable) # = configurable option (see "Hardware Options") * = software configurable (see "Peripheral Modules" section for further details) In the T48C510, there are eleven hardware interrupt sources which can be programmed to occupy a variety of priority levels. With the exception of the reset sources (RST), each source can be individually masked by mask bits in the corresponding control registers. An overview of the possible hardware configurations is shown in table 3.
The software triggered interrupt operates in exactly the same way as any hardware triggered interrupt. The SWI instruction takes the top two elements from the expression stack and writes the corresponding bits via the I/O bus to the interrupt pending register. Thus, by using the SWI instruction, interrupts can be re-prioritized or lower priority processes scheduled for later execution.
1.3.2
Software Interrupts
The program can generate interrupts using the software interrupt instruction (SWI) which is supported in qFORTH by predefined macros named SWI0...SWI7.
Rev. A2, 26-Feb-01
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Preliminary Information
T48C510
1.4 Hardware Reset
activate an external reset, the pin should be low for a minimum of 4 ms. Coded Reset (Port A) The coded reset circuit is connected directly to the Port A terminals. By using the appropriate configuration, the user can define a hardwired code combination (e.g., all pins low) which, if occurring on the Port A, will generate a reset in the same way as the NRST pin.
Table 4 Multiple key reset options
The master reset forces the CPU into a well-defined condition, is unmaskable and is activated independent of the current program state. It can be triggered by either initial supply power-up, a short collapse of the power supply, a watchdog time out, activation of the NRST input or the occurrence of a coded reset on Port A (see figure 9). A master reset activation will reset the interrupt enable flag, the interrupt pending registers, the interrupt active registers and initialize all on-chip peripherals. In this state all ports take on a high resistance input status with deactivated pullup and pulldown transistors (see figure 10). When the reset condition disappears, the hardware configuration previously programmed in the configuration EEPROM (see MTP Programming section) is loaded into the peripherals so that all port characteristics and pullup/ downs reflect the programmed configuration. This configuration period is immediately followed by a further reset delay time (approx. 80 ms), after which a short call instruction (opcode C1h) to the EEPROM address 008h is performed. This activates the initialization routine $RESET which in turn initializes all necessary RAM variables, stack pointers and internal peripheral configuration registers. Power-on Reset The fully integrated power-on reset circuit ensures that the core is held in a reset state until the minimum operating supply voltage has been reached. A reset condition is also generated should the supply voltage drop momentarily below the minimum operating supply. External Reset (NRST) An external reset can be triggered with the NRST pin. To
VDD Pull-up NRST
NO_RST RST2 RST3 RST4 RST5 RST6 RST7
Not used (default) BPA0 & BPA1 = low BPA0 & BPA1 & BPA2 = low BPA0 & BPA1 & BPA2 & BPA3 = low BPA0 & BPA1 = high BPA0 & BPA1 & BPA2 = high BPA0 & BPA1 & BPA2 & BPA3 = high
Note, that if this option is used, the reset is not maskable and will also trigger if the predefined code is written on to the Port A by the CPU itself. Care should also be taken not to generate an unwanted reset by inadvertently passing through the reset code on input transitions. This applies especially if the pins have a high capacitive load. Watchdog Reset The watchdog's function can be enabled via a configuration option and triggers a reset with every watchdog counter overflow. To suppress the watchdog reset, the counter must be regularly reset by reading the watchdog timer register address (CWD). The CPU reacts in exactly the same manner as a reset stimulus from any of the above sources.
* = Configuration
Reset delay timer Power-on reset
CPU reset
reset code
CODE *
VSS V DD
time out Port A I/O
Watchdog * rst
WD reset
Port A
CPU
Figure 9. Reset configuration/ start-up sequence
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Rev. A2, 26-Feb-01
Preliminary Information
T48C510
NRST
Device status
Reset
Configuration period 250 msec
Power-on reset delay 80 msec
Application program execution
Port status Pullup/ pulldown configuration
Program defined
Input mode
Input mode
Input mode
Program defined
Old config.
No pullup/ -down
No pullup/ pulldown
New configuration
New configuration
16539
Figure 10. Normal mode start-up
1.5
1.5.1
Clock Generation
Clock Module
The clock module generates two clocks. The system clock (SYSCL) supplies the CPU and the peripherals while the lower frequency periphery sub-clock (SUBCL) supplies only the peripherals. The modes for clock sources are programmable with the OS1-bit and OS0-bit in the SC-register and the CCS-bit in the CM-register. The clock module includes 4 different internal oscillator types: two RC-oscillators, one 4-MHz crystal oscillator and one 32-kHz crystal oscillator. The pins OSC1 and OSC2 provide the interface to connect a crystal either for the 4-MHz, or the 32-kHz crystal oscillator. SCLIN can be used as an input for an external clock or for connecting an external trimming resistor for the RC-oscillator 2. All necessary components with the exception of the crystal and the trimming resistor are integrated on-chip. Any one of these clock sources can be selected to generate the system clock (SYSCL). In applications that do not require exact timing, it is possible to use the fully integrated RC-oscillator 1 without any external components. The RC-oscillator 2 is more stable but the oscillator frequency must be trimmed with an external resistor attached between SCLIN and
VDD. In this configuration, for system clock frequencies below 2 MHz, the RC-oscillator 2 frequency can be maintained to within a tolerance of 10% over the full operating temperature and voltage range. The clock module is programmable via software using the clock management register (CM) and the system configuration register (SC). The required oscillator configuration is selected with the OS[1:0]-bits in the SC-register. A programmable 4-bit divider stage allows the adjustment of the system clock speed. A synchronization stage avoids any clock glitches which could be caused by clock source switching. The CPU always requires SYSCL clocks to execute instructions, process interrupts and enter or leave the SLEEP state. Internal oscillators are, depending on the condition of the NSTOP-bit automatically stopped and started where necessary. Special care must however be taken when using an external clock source which is gated by a one of the microcontroller port signals. This configuration can hang up if the external oscillator is switched off while the external clock source is still selected. It is therefore advisable in such a case to switch first to the internal RC-oscillator 1 source using CSS-bit. The external source can then be reselected later when the external oscillator has again been restarted.
Rev. A2, 26-Feb-01
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Preliminary Information
T48C510
SCLIN
Ext. clock
ExIn ExOut Stop RCOut2 Stop 4Out Stop
RC oscillator 1
IN1
SC: RC[1:0]
SYSCLmax SYSCL
RC oscillator2
OSCIN RTrim
RCOut1 Stop Control
/2 IN2
/2
/2 Divider chain
/2
to CPU and Timer/ counter
/8
4-MHz oscillator
Oscin Oscout
32-kHz oscillator
OSCOUT Oscin Oscout 32Out Stop SUBCL CM: NSTOP CCS CSS1 CSS0 32 kHz Sleep SYSCLmax/64
SC:
OS1
OS0
Figure 11. Clock module Table 5 Clock modes
Mode OS1 1 0 1 0 OS0 1 1 0 0 1 2 3 4
Clock Source for SYSCL CCS = 1 CCS = 0 RC-oscillator 1 (intern) External input clock
Clock Source for SUBCL CCS = 1 CCS = 0
SYSCL max/64 SYSCL max/64 SYSCL max/64 SCLIN / 128
A A A AAA AAA AAAA A AA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AA A A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAA A AAAAAA AAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA A AAA
RC-oscillator 1 (intern) RC-oscillator 1 (intern) RC-oscillator 1 (intern) RC-oscillator 2 with external trimming resistor 4-MHz oscillator 32-kHz oscillator
SYSCL max/64 fxtal / 128
32 kHz
1.5.2
Oscillator Circuits and External Clock Input Stage
External Input Clock
RC-Oscillator 1 Fully Integrated
For timing insensitive applications, it is possible to use the fully integrated RC oscillator 1. This operates without any external components and thus saves on component costs. The RC-oscillator 1 frequency tolerance is better than 50% over the full temperature and voltage range. A reduction in the application operating supply voltage and temperature ranges will result in an improved frequency tolerance. For more detailed information see figures 55 - 57. The basic center frequency of the RC-oscillator 1 is programmable with the RC1 and the RC0-bits in the SC register.
Control RC1 RC oscillator 1 RcOut1 RC0 Stop RcOut1 Osc-Stop
The SCLIN pin can be driven by an external clock source provided it meets the specified input levels, duty cycle, rise and fall times. The maximum system clock frequency fSYSCLmax that the core can operate is fSCLIN/2 (see figure 13).
Ext. input clock Ext. Clock SCLIN ExIn Stop ExOut ExOut Osc-Stop
Figure 13. External input clock
RC-Oscillator 2 with External Trimming Resistor
The RC-oscillator 2 is a high stability oscillator whereby the oscillator frequency can be trimmed with an external resistor connected between SCLIN and VDD. In this configuration, as long as the system clock frequency does not exceed 2 MHz, the RC-oscillator 2 frequency can be Rev. A2, 26-Feb-01
Figure 12. RC-oscillator 1
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Preliminary Information
T48C510
maintained stable to within a tolerance of 10% over the full operating temperature and voltage range. For example: A SYSCLmax frequency of 2 MHz, can be obtained by connecting a resistor Rext = 150 kW (see figures 14, 52, 53 and 54).
VDD Rext SCLIN RC oscillator 2 RcOut2 RTrim Stop RcOut2 Osc-Stop OSCIN 13377 Oscin XTAL 32 kHz OSCOUT 32Out 32-kHz oscillator Oscout 32Out
32-kHz Oscillator
Some applications require accurate long-term time keeping without putting excessive demands on the CPU or alternatively low resolution computing power. In this case, the on-chip ultra low power 32-kHz crystal oscillator can be used to generate both the SUBCL and/or the SYSCL. In this mode, power consumption can be significantly reduced. The 32-kHz crystal oscillator will remain operating (not stopped) during any CPU powerdown/SLEEP mode.
Figure 14. RC-oscillator 2
4-MHz Oscillator
The integrated system clock oscillator requires an external crystal or ceramic resonator connected between the OSCIN and OSCOUT pins to establish oscillation. All the necessary oscillator circuitry, with the exception of the actual crystal, resonator and the optional C3 and C4 are integrated on-chip.
C3 OSCIN Oscin XTAL Cer. Res 4Out 4-MHz oscillator Oscout C4 OSCOUT Stop 4Out
Figure 16. 32-kHz crystal oscillator
Quartz Oscillator Configuration
If the customer's application necessitates the use of a quartz crystal clock source and this requires capacitive trimming, the trimming capacitors are not integrated into the MTP unlike the M44C510E and should therefore be connected externally as descrete components between the respective Quartz Crystal terminals (OSCIN, OSCOUT) and VSS.
Osc-Stop
Figure 15. System clock oscillator
Rev. A2, 26-Feb-01
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Preliminary Information
A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA AAAAA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAA
If CCS = 0 in the CM-register, the RC-oscillator 1 is stopped.
AAAAA A A AA A A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA AAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A A A A A AA A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAA
System Configuration Register (SC)
The clock management register (CM) controls the system clock divider chain, as well as the peripheral clock in the power-down modes.
1.5.3
T48C510
16 (61) CCS CM:
OS1, OS0 Oscillator selection bits (in conjunction with the CCS-bit)
RC1, RC0 Internal RC oscillator 1 frequency select (SYSCLmax)
CSS[1:0]
NSTOP
SC: write
Clock Management Register (CM)
Core Speed Select
Not STOP peripheral clock NSTOP = 0, stops the peripheral clock (SUBCL) when the core is in SLEEP mode. The 32-kHz crystal oscillator SUBCL clock cannot be stopped. NSTOP = 1, enables the peripheral clock (SUBCL) when the core in SLEEP mode Core Clock Select CCS = 1, the internal RC-oscillator 1 generates SYSCL CCS = 0, the 4-MHz crystal oscillator, the 32-kHz crystal oscillator, an external clock source or the RC-oscillator 2 (with the external resistor) will generate SYSCL dependent on the setting of OS0 and OS1 in the system configuration register
CCS 0 0 0 0 1
CSS1 0 0 1 1
RC1 0 0 1 1
Bit 3 NSTOP
Bit 3
RC1
OS1 1 0 1 0 x
These two bits control the system clock divider chain
OS0 1 1 0 0 x
Bit 2 CCS
Bit 2
RC0
Preliminary Information
CSS0 0 1 0 1 RC0 0 1 0 1 32 kHz SYSCLmax/64 or 32 kHz Bit 1 CSS1 Bit 1 OS1 SYSCLmax/64
SYSCLmax @ 25C, VDD = 5 V
SUBCL
Divider 16 8 4 2
7.0 MHz (fiRC0) 3.0 MHz (fiRC1) 2.0 MHz (fiRC2) 0.8 MHz (fiRC3)
Bit 0 CSS0
Bit 0
OS0
Note SYSCLmax/8 SYSCLmax/4 SYSCLmax/2 Reset value = SYSCLmax
System Oscillator Selection External input clock at SCLIN RC-oscillator 2 with Rext 4-MHz crystal oscillator 32-kHz crystal oscillator RC-oscillator 1
Primary register address: 'E'hex
Auxiliary register address: 'E'hex
Auxiliary register address: 'E'hex
Reset value: 1111b
Reset value: 1111b
Reset value
Note
Rev. A2, 26-Feb-01
T48C510
1.5.4 Power-down Modes
The T48C510 encorporates several modes which enable the power consumption to be tailored to a minimum without sacrificing computational power. When the controller exits the lowest priority interrupt task, it reverts to a SLEEP state. This is a CPU shutdown condition which is used to reduce average system power consumption where the CPU itself is only partially utilized. In SLEEP, the CPU clocking system is deactivated whereby the peripherals and associated clock sources may remain active (Standby Mode) or they can also be halted (Halt Mode). In Standby Mode, the peripherals are able to continue operation and if required also generate interrupts which can, along with a reset reactivate the CPU to bring it out of the sleep state. SLEEP can only be maintained when none of the interrupt pending or active register bits are set. The application of the $AUTOSLEEP routine ensures the correct function of the sleep mode. In both Standby and Active modes the current consumption is largely dependent on the frequency of the CPU system clock (SYSCL) and the supply voltage (VDD). (see figures 50 and 51) while the Halt Mode current is merely controller static leakage current. Selection of Standby or Halt mode is performed by the NSTOP bit in the clock managent register (CM). It should be noted that the low power 32-kHz crystal oscillator, if enabled will always remain active in both Standby and Halt modes.
Table 6 Power-down modes
Mode
CPU Core State RUN
NSTOP
RC-Oscillator 1 RC-Oscillator 2 4-MHz Oscillator RUN RUN
32-kHz Oscillator
External Input Clock at SCLIN Enabled Enabled
AAAAAAA A A AA A AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAA A A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AA A
Active Halt 1 1 0 RUN RUN RUN Standby SLEEP SLEEP STOP Disabled
1.5.5
Clock Monitor Mode
NRST TE SYSCL clocks BP11 SUBCL clocks
BP10
Oscillator supervisory mode
13387
Normal operation
Figure 17. Clock monitoring
For trimming purposes, the T48C510 can be put into a clock monitor mode. By forcing the test input (TE) high, the SYSCL clock will appear on BP11 (Port 1, bit 1) and
SUBCL clock on Port BP10 (Port 1, bit 0). On releasing the TE pin, the BP10 and BP11 will resume their normal function (see figure 17).
Rev. A2, 26-Feb-01
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Preliminary Information
T48C510
2
2.1
Peripheral Modules
Addressing Peripherals
performed with the same instruction preceded by writing the module address into the auxiliary switching module. Byte-wide registers are accessed by multiple IN (or OUT) instructions. Extended addressing is used for more complex peripheral modules, with a larger number of registers. In this case, a bank of up to 16 subport registers are indirectly addressed with the subport address being initially written into the auxiliary register. Please refer to the 'HARDC510.SCR' hardware interface file as a programming guideline.
Accessing the peripheral modules takes place via the I/O bus (see figure 18). The IN or OUT instructions allow direct addressing of up to 16 I/O modules. A dual register addressing scheme has been adopted which addresses the "primary register" directly. To address the "auxiliary register", the access must be switched with an "auxiliary switching module". Thus, a single IN (or OUT) to the module address will read (or write) into the module primary register. Accessing the auxiliary register is
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Rev. A2, 26-Feb-01
Preliminary Information
T48C510
Module ASW Module M1
(Address Pointer) Aux. Reg. Bank of Primary Regs. Subport Fh Subport Eh Aux. Reg. 6
Module M2
Module M3
2 Auxiliary Switch Module
Subport 1 Primary Reg. Subport 0 3 1 5 Primary Reg. 4
7
Primary Reg.
I/O bus
to other modules
Indirect Subport Access (Subport Register Write)
1 2
Dual Register Access (Primary Register Write)
4
Single Register Access (Prima ry Register Write)
7
Addr.(M1) SPort_Data
Addr.(ASW) OUT OUT OUT Addr.(M1)
Prim._Data
Address(M2) OU T
Prim._Data Address(M3) O UT
Addr.(SPort) Addr.(M1)
3
( Auxiliary Register Write ) 5 6 Address(M2) Address(ASW) OUT Aux._Data Address(M2) OUT 7 (Prima ry Register Read) Address(M3) IN
(Subport Register Read) 1 2 3 Addr.(M1) Addr.(ASW) OUT OUT IN
Addr.(SPort) Addr.(M1) Addr.(M 1)
(Primary Register Rea d) 4 Address(M 2) (Auxiliary Register Rea d) IN
Example of qFORTH Program Code
(Subport Register Write Byte) 1
2 3
Addr.(M1)
Addr.(ASW) OUT OUT
5
Addr.(SPort) Addr.(M1)
SPort_Data(lo) Addr.(M1) OUT SPort_Data(hi) Addr.(M1) OUT (Subport Register Rea d Byte)
6
Address(M2) Address(ASW) OUT Address(M 2) IN (Auxiliary Register Write Byte)
3
5 6 6
Address(M2) Address(ASW) OUT Aux._Data(lo) Address(M2) OUT Aux._Data(hi) Address(M2) OUT Addr.(ASW) = Auxiliary Switch Module Address Addr.(Mx) = Module Mx Addr ess Addr.(SPort) = Subport Address Prim._D ata = da ta to be written into Primary Register. Aux._D ata = data to be written into Auxilia ry Register Aux._Data (lo)= data to be written into Auxilia ry Register (low nibble) Aux._Data (hi) = da ta to be written into Auxiliary Register(high nibble) SPort_Data(lo) = data to be written into SubP ort (low nibble) SPort_Data(hi) = data to be written into Subport (high nibble)
96 11522
1 2 3
3
Addr.(M1)
Addr.(ASW) OUT OUT IN IN Addr.(M 1) Addr.(M 1)
Addr.(SPort) Addr.(M1)
(Auxiliary Register Rea d)
1 2
Address(M1) Address(ASW) OUT Address(M1) IN
Figure 18. Example of I/O addressing
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19 (61)
Preliminary Information
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAA A A AA AA AA AAAA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA A A A AA A A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA A AA A A A AA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA A A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AA A AAAA A AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA A A A AA A A A A AA A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA A A AA A AAAA A AA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AA A AA A AAAA A AA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AA A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AA A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA A A A AA A A A A AA A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AA A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA A A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA A A A AA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAA A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAA A AA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AA A A
Table 7 T48C510 Peripheral addresses
T48C510
20 (61) D E A C B F 8 9 7 6 5 4 3 0 1 2
Port Address
Write /Read P0DAT W/R P1DAT W/R PAIPR W Aux. PAICR W CWD R PBIPR W Aux. PBICR W P4DAT W/R Aux. P4DDR W P5DAT W/R Aux. P5DDR W P6DAT W/R Aux P6CR W P7DAT W/R Aux. P7DDR W ASW W TCM W/R Aux. T0SR R TCSUB W Subport address 0 T0MO W 1 T0CR W 2 T1MO W 3 T1CR W 4 TCMO W 5 TCIOR W 6 TCCR W 7 TCIP W 8 T1CP W T1CA R 9 T0CP W T0CA R A BZCR W B-F PADAT W/R Aux. PADDR W PBDAT W/R Aux. PBDDR W PCDAT W/R Aux. PCDDR W --- --- SC W Aux. CM W/R ITFSR W Aux. ITIPR W
Name
Preliminary Information
1111b 1111b 1111b 1111b 1111b 1111b 1111b 1111b xxxx xxxxb xxxx xxxxb xxxx xxxxb xxxx xxxxb 1111b ---- 1111b 1111b 1111b 1111b 1111b 1111b ---- 1111b 1111b 1111b 1111b Reset Value 1111b 1111b 1111b 1111b ---- 1111b 1111b 1111b 1111b 1111b 1111b 0011b 1111 1111b 1111b 1111b 1111b 1111b 0000b 1111b Timer 0 mode register Timer 0 control register Timer 1 mode register Timer 1 control register Timer/counter mode register Timer/counter I/O control register Timer/counter control register Timer/counter interrupt priority Timer 1 compare register (byte) Timer 1 capture register (byte) Timer 0 compare register (byte) Timer 0 capture register (byte) Buzzer control register Reserved Port A - data register/pin data Port A - data direction register Port B - data register/pin data Port B - data direction register Port C - data register/pin data Port C - data direction register Reserved System configuration register Clock management register Interval timer frequency select register Interval timer interrupt priority register Timer 0 interrupt status register Timer/counter subport address pointer Port 0 - data register/input data Port 1 - data register/input data Port A - interrupt priority register Port A - interrupt control register Watchdog timer reset Port B - interrupt priority register Port B - interrupt control register Port 4 - data register/pin data Port 4 - data direction register Port 5 - data register/pin data Port 5 - data direction register Port 6 - data register/pin data Port 6 - control register (byte) Port 7 - data register/pin data Port 7 - data direction register Auxiliary switch register Register Function
Data to/from subport addressed by TCSUB
Rev. A2, 26-Feb-01 Module Type M3 M3 M2 ASW M1 M1 M1 M2 M2 M2 M2 M2 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M1 M2 M2 M2 M2 M3 M2 35 36 43 43/44 33 32 31 32 44 See Page 21 21 22 22 29 22 22 20 21 20 21 25 25 20 21 18 18 35 30/31 16 15 28 20 21 20 21 20 21 47 37
T48C510
2.2 Bidirectional Ports
Port Address Number of bits Bitwise programmable direction Output drivers configurable 1) Dynamic pullup/ down typ. (Ohm) 3) Static pullup/ down typ. (Ohm) 4) Schmitt trigger inputs Additional functions 0 4 no no 2) 500k none yes 1 4 no yes 500k none yes 4 4 yes yes 500k 30k yes
Timer 0 Table 8 Overview of Port Features
5 4 yes yes 500k 30k no
6 2 yes yes 500k 4k yes
External interrupt
7 4 yes yes 500k 30k no
A 4 yes yes 500k 30k yes
Port monitor/ coded reset
B 4 yes yes 500k 30k yes
Port monitor
C 4 yes yes 500k 30k no
1) 2) 3)
4)
Either "open drain down", "open drain up" or CMOS output configuration. This output must always be CMOS. The Dynamic pullup/down transistors are configurable and if selected, are only activated when the associated complementry driver transistor is off. ie. A dynamic pull up transistor is only active when the port is either in input mode (both drivers off) or when a logical 1 is written to the port pad (low driver off) in output mode. (figure 20) The Static Pullup/down transitors are configurable and if selected, are always active independant of the port direction or driven state. (figure 20)
For further data see section 3.2 . All Ports (0, 1, 4, 5, 7, A, B and C with the exception of Port 6) are 4 bits wide. Port 6 has a data width of 2 bits (bit 0 and bit 1) only. The ports may be used for data input or output. All ports that can either directly or indirectly generate an interrupt are equipped with Schmitt-trigger inputs. A variety configurable options are available such as open drain, open source and full complementary outputs as well as different types of pull-up and pull-down transistors. All Port Data Registers (PxDAT) are I/O mapped to the primary address register of the respective port address, and the Port Data Direction Register (PxDDR) to the corresponding auxiliary register. All bidirectional ports except Port 0 and Port 1, include a bitwise- programmable Data Direction Register (PxDDR) which allows the individual programming of each port bit as input or output. It is also possible to read the pin condition when in output mode. This is a useful feature for self testing and for collision detection on Port Data Register (PxDAT)
wired-OR bus systems. There are five different types of bidirectional ports: D Ports 0 and 1 - 4-bit wide, bidirectional ports with automatic full bus width direction switching. D Port 4 - 4-bit wide, bitwise programmable bidirectional port also provides the I/O interface to Timer 0 and the Buzzer. D Ports 5, 7 and C - 4-bit wide, bitwise programmable high drive I/O port. D Port 6 - 2-bit wide, bitwise programmable bidirectional ports with optional static (4 kW) pull-up/-down and programmable interrupt logic. D Ports A and B - 4-bit wide, bitwise programmable bidirectional ports with optional port monitor function.
AAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A
Bit 3 Bit 2 Bit 1 Bit 0 PxDAT PxDAT3 PxDAT2 PxDAT1 PxDAT0 Reset value: 1111b Bit 3 MSB, bit 0 LSB, x Port address Rev. A2, 26-Feb-01 21 (61)
Primary register address: 'Port address'hex
Preliminary Information
T48C510
Port Data Direction Register (PxDDR)
AAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAA A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A
Bit 3 Bit 2 Bit 1 Bit 0 PxDDR PxDDR3 PxDDR2 PxDDR1 PxDDR0 Reset value: 1111b
Table 9 Port Data Direction Register (PxDDR)
Auxiliary register address: 'Port address'hex
Code: 3 2 1 0 xxx1 xxx0 xx1x xx0x x1xx x0xx 1xxx 0xxx
Function
BPx0 in input mode BPx1 in input mode BPx2 in input mode BPx3 in input mode
BPx0 in output mode BPx1 in output mode BPx2 in output mode BPx3 in output mode
2.2.1
Bidirectional Port 0 and Port 1
In this port type, the data direction register is not independently software programmable because the direction of the complete port is switched automatically when an I/O instruction occurs (see figure 19). The port can be switched to output mode with an OUT instruction and to input with an IN instruction. The data written to a port will be stored in the output data latches and appears immediately at the port pin following the OUT instruction. After RESET, all output latches are set to '1' and the ports are switched to input mode. An IN instruction reads the condition of the associated pins. Note: Care must be taken when switching these bidirectional ports from output to input. The capacitive pin
I/O Bus
loading at this port, in conjunction with the high resistance pull-ups, may cause the CPU to read the contents of the output data register rather than the external input state. This can be avoided by using either of the following programming techniques: D Use two IN instructions and DROP the first data nibble. The first IN switches the port from output to input and the DROP removes the first invalid nibble. The second IN reads the valid pin state.
D Use an OUT instruction followed by an IN instruction. With the OUT instruction, the capacitive load is charged or discharged depending on the optional pull-up /pull-down configuration. Write a "1" for pins with pull-up resistors, and a "0" for pins with pulldown resistors.
VDD
*
VDD (Data out) D Q
*
Pull-up
PxDATy R Reset (Direction) OUT IN Master reset S R Q NQ
BPxy * *
*) Configurable option Port 1 only Pull-down
Figure 19. Bidirectional Ports 0 and 1
22 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
2.2.2 Bidirectional Port 5, Port 7 and Port C
Port B are equipped with the same standard I/O logic. However, Port 5, Port 7 and Port C include standard CMOS input stages, whereas Port A, Port B and all other digital signal pins have Schmitt-trigger inputs. Port 5 and Port 7 have high current output drive capability for up to 20 mA @ 5 V. Whereby the instantaneous sum of the output currents should not exceed 100 mA.
V Pull-up
All bidirectional ports except Port 0 and Port 1, include a bitwise-programmable Data Direction Register (PxDDR) which allows the individual programming of each port bit as input or output. It also enables the reading of the pin condition in output mode. The bidirectional Ports 5, 7 and C as well as Port A and
Port A and Port B with Schmitt-trigger I/O Bus
*
(Data out) I/O Bus D Q PxDATy S Master reset I/O Bus DSQ PxDDRy (Direction)
DD Static Pull-up * 30 kW @ 5 V
* BPxy *
V DD
*
Pull-down
* Pull-down
Static
* Configurable option
Figure 20. Bidirectional Ports 5, 7, A, B and C
2.2.3
Bidirectional Port A and Port B with Port Monitor Function
PRx1 PRx2
Connected to Ports A and B (x = A or B) PxICR ENx3
BPx3 BPx2 BPx1 BPx0
ENx2
ENx1
ENx0
IMAx
ITRx
PRx1
PRx2
PxIPR Decoder 2:4
0 0 1 1
0 1 0 1
INT7 INT5 INT3 INT1
INT7 INT5 INT3 INT1
16507
Figure 21. Port monitor module of Port A and Port B
In addition to the standard I/O functions described in section 2.2.2, both Port A (BPA3 - BPA0) and Port B (BPB3 - BPB0) are equipped with Schmitt-trigger inputs and a port monitor module. This module is connected across all four port pins (see figure 21) and is intended for monitoring those pins selected by control bits Enx3 - Enx0 and generating an interrupt when the first pin leaves a preselected logical default idle state. This state is defined by control bit ITRx . Transitions on other pins will only cause
an interrupt if the other pins have first returned to the idle state. This, for example is useful for interrupt initiated port scanning without the power consuming task of continuously polling for port activity. Using the Port Interrupt Control Register (PxICR), pins can be individually selected. A non-selected pin cannot generate an interrupt. The Port Interrupt Priority Register (PxIPR) allows masking of each interrupt, definition of
Rev. A2, 26-Feb-01
23 (61)
Preliminary Information
T48C510
the interrupt edge and programming of the interrupt priority levels. When programming or reprogramming either of the port monitor control registers, any previously generated interrupt on that port which has not yet been acknowledged by the CPU or an interrupt generated by the reprogramming itself is automatically cleared. Port A can also be used for a configurable coded reset. For more information see section 1.4 'Hardware Reset'. Port Monitor Interrupt Priority Register (PxIPR) x = 'A' (Port A) or 'B' (Port B) Bit 3 IMx Bit 2 Bit 1 Bit 0 The Port Interrupt Priority Registers PAIPR and PBIPR are I/O mapped to the the primary address registers of the Port Monitor Module addresses '2'h and '3'h respectively. The Port Interrupt Control Registers PAICR and PBICR are mapped to the corresponding auxiliary registers.
(Port A) Primary register address: '2'hex (Port B) Primary register address: '3'hex ITRx PRx2 PRx1 Reset value: 1111b
AAAAAAAAAAAA AAAAAAAAAAAA AA AA A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA
xxx0 xxx1 xx0x xx1x x0xx x1xx 0xxx 1xxx 24 (61)
AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAA AA A A A A A AAAAAAAAAAAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAA A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A
PxIPR IMx ITRx PRx2..1 - Interrupt Mask - Interrupt Transition - Interrupt Priority code
Table 10 Port Monitor Interrupt Priority Register (PxIPR)
Code 3210 xx00 xx01 xx10 xx11 x0xx x1xx 0xxx 1xxx Port monitor interrupt priority 7 Port monitor interrupt priority 5 Port monitor interrupt priority 3 Port monitor interrupt priority 1
Function
Port monitor interrupt on falling edge Port monitor interrupt on rising edge Port monitor interrupt enabled Port monitor interrupt disabled
Port Monitor Interrupt Control Register (PxICR) x = 'A' (Port A) or 'B' (Port B) Bit 3 ENx3
(Port A) Auxiliary register address: '2'hex (Port B) Auxiliary register address: '3'hex Reset value: 1111b
PxICR
Bit 2 ENx2
Bit 1 ENx1
Bit 0 ENx0
ENx3 ... 0 port monitor input ENable code Code 3210
Table 11 Port Monitor Interrupt Control Register (PxICR)
Function Bit 0 can generate an interrupt Bit 1 can generate an interrupt Bit 2 can generate an interrupt Bit 3 can generate an interrupt
Bit 0 cannot generate an interrupt Bit 1 cannot generate an interrupt Bit 2 cannot generate an interrupt Bit 3 cannot generate an interrupt
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
2.2.4 Bidirectional Port 6
V I/O Bus DD Pull-up V DD Strong Static Pull-up * 4k @ 5 V
*
VDD (Data out) I/O Bus D Q P6DATy S Master reset IN enable
* BP6y *
V y = 0 or 1 DD
*
Pull-down
*
Strong Static Pull-down 4k @ 5 V
* Configurable Figure 22. Bidirectional Port 6
This 2-bit bidirectional port can be used as bitwise-programmable I/O. The data is LSB aligned so that the two MSB's will not appear on the port pins when written. The port pins can also be used as external interrupt inputs (see figures 22 and 23). Both interrupts can be masked or independently configured to trigger on either edge. The interrupt priority levels are also configurable. The interrupt configuration and port direction is controlled by the Port 6 Control Register (P6CR). An additional low resistance pull-up transistor (configurable option) provides an internal bus pull-up for serial bus applications. In output mode (PxDDR bit = 0), the respective Port Data Register (PxDAT) bit appears on the port pin, driven by an output port driver stage which can be configurable as open drain, or full complementary CMOS. With an IN instruction the actual pin state can be read back into the controller at any time without changing the port directional mode. If the output port is configured as an open
drain driver, the controller is able to receive the external data on this pin without switching into input mode as long as the output transistor is switched off. In input mode (PxDDR bit = 1), the output driver stage is deactivated, so that an IN instruction will directly read the pin state which can be driven from an external source. In this case, the state of the Port Data Register (PxDAT), although not appearing at the pin itself, remains unchanged. High resistance configurable pull-up or pulldown transistors are automatically switched onto the port pin in input mode. The Port Data Register is written to the respective port address with an OUT instruction. The Port 6 Data Register (P6DAT) is I/O mapped to the primary address register of address '6'hex and the Port 6 Control Register (P6CR) to the corresponding auxiliary register. The P6CR is a byte wide register and is written by writing the low nibble first and then the high nibble (see section 2.1 "Addressing peripherals").
Rev. A2, 26-Feb-01
25 (61)
Preliminary Information
T48C510
Port 6 Data Register (P6DAT) Primary register address: '6'hex
AAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAA A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A
Bit 3 Bit 2 Bit 1 Bit 0 P6DAT not used not used P6DAT1 P6DAT0 Reset value: xx11b The unused bits 2 and 3 are '0', if read. Port 6 Control Register (P6CR) Auxiliary register address: '6'hex
AAAAAAAAAAAAA A A A A A AAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA AAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A
Bit 3 Bit 7 Bit 2 Bit 6 Bit 1 Bit 5 Bit 0 Bit 4 P6CR First write cycle P61IM2AAAA P60IM2 P61IM1 P60IM1 Reset value: 1111b Reset value: 1111b Second write cycle P61PR2AAAA P60PR2 P61PR1 P60PR1 P6xIM2, P6xIM1 - Port 6x Interrupt mode/direction code P6xPR2, P6xPR1 - BP6x Interrupt priority code
Table 12 Port 6 control register (P6CR)
Auxiliary Address: '6'hex Code 3210 xx11 xx01 xx10 xx00 11xx 01xx 10xx 00xx Function
First Write Cycle Code 3210
Second Write Cycle Function
AAAAAAAAAA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAA
BP60 in input mode - interrupt disabled xx11 xx10 xx01 xx00 11xx 10xx 01xx 00xx BP60 set to priority 1 BP60 set to priority 3 BP60 set to priority 5 BP60 set to priority 7 BP61 set to priority 0 BP61 set to priority 2 BP61 set to priority 4 BP61 set to priority 6 BP60 in input mode - rising edge interrupt BP60 in output mode - interrupt disabled BP61 in input mode - interrupt disabled BP60 in input mode - falling edge interrupt BP61 in input mode - rising edge interrupt BP61 in output mode - interrupt disabled BP61 in input mode - falling edge interrupt 26 (61) Rev. A2, 26-Feb-01
Preliminary Information
T48C510
INT6 INT4 INT2 INT0 INT7 INT5 INT3 INT1
Mask
Edge Data in Dir. BP61
Bidir. Port
IN_Enable
Mask
Edge Data in Dir. BP60
Bidir. Port
IN_Enable
decode P6CR:
CR7 CR6
decode
CR5 CR4
decode
CR3
decode I/O bus
CR2 CR1 CR0
CR1 CR7 CR6 CR5 INT6 INT4 INT2 INT0 CR4 CR3 INT7 INT5 INT3 INT1
CR0 CR2
Dir.
INT edge
INT disabled
0 0 1 1
0 1 0 1
0 0 1 1
0 1 0 1
0 0 1 1
0 1 0 1
out in in in
- -
yes no no yes
96 11526
Figure 23. Port 6 external interrupts
2.2.5
Bidirectional Port 4
The bidirectional Port 4 is both a bitwise configurable I/O port and provides the external pins for both the Timer 0 and the internal buzzer generator. As an I/O port, it performs in exactly the same way as bidirectional Port 5, 7,
A, B and C (see figure 20). Two additional multiplexers allow data and port direction control to be passed over to other internal modules (Timer 0 or Buzzer). Each of the four Port 4 pins can be individually switched by the Timer/Counter I/O Register (TCIO). Figure 24 shows the internal interfaces to Port 4.
V V DD
DD Pull-up
I/O Bus T0In T0Out I/O Bus D S Master reset I/O Bus D (Direction) S Q Q P4DATy (Data out) TCIOy VDD
*
*
Static Pull-up 30 kW @ 5 V
* BP4y *
V DD
*
Pull-down
*
Static Pull-down
P4DDRy TDir
* Configurable option Figure 24. Bidirectional Port 4
Rev. A2, 26-Feb-01
27 (61)
Preliminary Information
T48C510
2.2.6 TIM1 - Dedicated Timer 1 I/O Pin
V T1IN (Timer 1 input) DD Pull-up
*
VDD
* TIM1 *
T1Dir (direction control)
T1OUT (Timer 1 output)
* * Configurable options Figure 25. Bidirectional pin TIM1
Pull-down
TIM1 is a dedicated bidirectional I/O stage for signal communication to and from the Timer 1 in the timer/ counter module (see figure 25). It has no I/O bus interface and is not directly accessible from the CPU. The direction control is performed from the timer/counter configuration registers.
2.3
Interval Timers / Prescaler
ure 11 ) and consists of a 15-stage binary divider and two programmable multiplexers for selecting the appropriate interrupt frequencies for each interrupt source (see figure 26). Each multiplexer is completely independent and is controlled by the common Interval Timer Frequency Select Register (ITFSR). Buffer registers store the respective frequency select codes and ensure complete programming independence of each interrupt channel. Interrupt masking and programming of the interrupt priority levels is performed with the aid of the Interval Timer Interrupt Priority Register (ITIPR).
FS3 FS2 FS1 FS0
The interval timers are based on a frequency divider for generating two independent time base interrupts. It is driven by SUBCL generated by the clock module (see figITIPR INT5 INT1
Buffer PRB PRA MIB MIA
ITFSR
Buffer
INT6 INT2
Fh Eh Dh INTB Ch 8:1 Bh Mux Ah 9h 8h
8092Hz 2048Hz 4096Hz
8192Hz 4096Hz 2048Hz 1024Hz 256Hz 64Hz 16Hz 8Hz 128Hz
7h 6h 5h INTA 4h 8:1 3h Mux 2h 1h 0h
32Hz 8Hz 16Hz 4Hz
128Hz 64Hz 32Hz 16Hz 8Hz 4Hz 2Hz 1Hz 2Hz 1Hz
1024Hz 256Hz
64Hz
R SUBCL
CK
2 2 2 3 2 4 2 5 2 6 27 2 8 2
9
210 2 11 212 213 214 215
96 11530
(e.g. SUBCL = 32 kHz)
15-stage binary counter Figure 26. Interval timers / prescaler
28 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
2.3.1 Interval Timer Registers
The Interval Timer Frequency Select Register (ITFSR) is I/O mapped to the primary address register of the prescaler/ interval timer address ('F'hex) and the Interval Timer Interrupt Priority Register (ITIPR) to the correInterval Timer Interrupt Priority Register (ITIPR) Bit 3 PRB Bit 2 Bit 1 MIB sponding auxiliary register. The interrupt masks MIA and MIB enable interrupt masking of INTA and INTB respectively. Each interrupt source can be programmed with PRA and PRB to one of two interrupt priority levels. Disabling both interrupts resets the interval timer.
AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA
AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AA A
ITIPR PRA MIA Reset value: 1111b PRB - Priority select Interval Timer Interrupt INTB PRA - Priority select Interval Timer Interrupt INTA MIB - Mask Interval Timer Interrupt INTB MIA - Mask Interval Timer Interrupt INTA
Table 13 Interval Timer Interrupt Priority Register (ITIPR)
Auxiliary register address (write only): 'F'hex Bit 0
Code 3210 xx11 xxx1 xxx0 xx1x xx0x x1xx x0xx 1xxx 0xxx Reset prescaler and halt Interrupt A disabled Interrupt A enabled Interrupt B enabled Interrupt B disabled
Function
Interrupt A => priority 1 Interrupt A => priority 5 Interrupt B => priority 2 Interrupt B => priority 6
Interval Timer Frequency Select Register (ITFSR) Bit 3 FS3 Bit 2 FS2
AAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A
Bit 1 FS1 Bit 0 FS0 ITFSR Reset value: 1111b FS3 ... 0 - Frequency select code Code 3210 0000 0001 0010 0011 0100 0101 0110 0111 Function INTA
SUBCL divide by
Table 14 Interval Timer Frequency Select Register (ITFSR)
Primary register address (write only): 'F'hex
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAA AAAAAAA A A A AAAAAAA A A A A A A A A A AAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAA A A AAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAA A A A AAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAA A A AA A A AAA AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AA A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAA
215 214 213 212 211 29 28 210 1000 1001 1010 1011 1100 1101 1110 1111 INTB 212 211 29 27 25 24 23 22 Select 8 Hz Select 2 Hz Select 4 Hz Select 8 Hz Select 16 Hz Select 64 Hz Select 256 Hz Select 16 Hz Select 32 Hz Select 64 Hz Select 1024 Hz Select 2048 Hz Select 4096 Hz Select 8192 Hz Select 128 Hz The control bit FS3 determines whether the INTA or the INTB buffer register is loaded with the select code (FS2-FS0). This allows independent programming of interval times for INTA and INTB. Rev. A2, 26-Feb-01 29 (61)
SUBCL = 32 kHz Select 1 Hz
Code 3210
Function
SUBCL divide by
SUBCL = 32 kHz
Preliminary Information
T48C510
2.4 Watchdog Timer
NRST

2
14

2
15
216 *
R R
*
SUBCL Read WDRES Master Reset
CK R R R R
*
R R R
17-stage binary counter
R R R R R R R R
*
Watchdog enable
VDD Figure 27. Watchdog timer
* Configurable option
The watchdog timer is a 17-stage binary divider clocked by SUBCL generated within the clock module (see figures 11 and 27). It can only be enabled as a configurable option whereby it must be periodically reset from the application program. The program cannot disable the watchdog. If the CPU find itself for an extended length of time in SLEEP mode or in a section of program that includes no watchdog reset, then the watchdog will overflow, thus forcing the NRST pin low. This initiates a master reset. The timeout period can be set to 0.5, 1 or 2 seconds (if SUBCL = 32 kHz) by using a configurable option. To reset the watchdog, the program must perform an INinstruction on the address CWD ('3'hex). No relevant data is received. The operation is therefore normally followed by a DROP to flush the data from the stack.
Timer 1 Control Register (T1CR). Capture and compare registers (T0CA,T1CA,T0CP and T1CP) not only allow event counting, but also the generation of various timed output waveforms including programmable frequencies, modulated melody tones, Pulse Width Modulated (PWM) and Pulse Density Modulated (PDM) output signals. When in one of these signal generation modes, the capture register acts as timer shadow register, the current timer state is freezed whenever read by the CPU. The Timer 0 is further equipped for performing a variety of time measurement operations. In this mode the capture register is used together with the gating logic for performing asynchronous, externally triggered snapshot measurements. These measurements include single input pulse width and period measurements and also dual input phase and positional measurement. The mode configuration is set in the Timer 0 and Timer 1 Mode Registers (T0MO and T1MO). Each timer represents a single maskable interrupt source (T0INT and T1INT), the priority of which can be configured under program control. A Timer 0 interrupt can be caused by any of three conditions (overflow, compare or end-of-measurement). The associated status register (T0SR) differentiates between these. A status register is not necessary in the Timer 1 as an interrupt is caused only on a compare condition.
2.5
Timer/Counter Module (TCM)
The TCM consists of two timer/counter blocks (Timer 0 and Timer 1) which can be used separately, or together as a single 16-bit counter/timer (see figures 28 and 30). Each timer can be supplied by various internal or external clock sources. These can be selected and divided under program control using the Timer/Counter Control Register (TCCR), the Timer 0 Control Register (T0CR) and the
30 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
T0IN1 T0IN0 SYSCL MUX 4:1 SUBCL ck Prescaler rst Gating control up/down Capture register T0CA
Timer 0
Status register T0SR
MUX 8:1
Clock control reset
up/down counter
overflow
end-of- measu- rement
Reload control
Compare
T0CP T0CR T0MO Compare register Int. enable T1OUT TCCR TCMO T0OUT0
Output control Int
T0OUT1 T0OUT0 T0INT
16-bit mode T1CR T1MO
Int. enable Compare register T1CP carry T1INT Int Output control T1OUT
Reload control reset
Compare
MUX 8:1
MUX 2:1
Clock control
up/down counter
overflow
SUBCL MUX 4:1 SYSCL T1IN
rst Prescaler ck
T1CA Capture register
Timer 1
13909
< = CPU Read/write registers
Figure 28. Timer/counter module
Rev. A2, 26-Feb-01
31 (61)
Preliminary Information
T48C510
2.5.1 General Timer/Counter Control Registers
accessed. Care has to be taken to ensure that this subport access sequence is not interrupted. Please refer to the 'HARDC510.SCR' hardware interface file as a programming guideline. With the exception of the Timer 0 Interrupt Status Register (T0SR), all the timer/counter registers are indirectly addressed using extended addressing as described in the section "Addressing peripherals". An overview of all register and subport addresses is shown in table 7. The Timer/Counter auxiliary register (TCSUB) holds the subport address of the particular register about to be Timer/Counter Clock Control Register (TCCR) Subport address (indirect write access): '6`hex of Port address '9`hex
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAA AAAAAAAAAAAA AA AA A A AA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AA
Bit 3 Bit 2 Bit 1 Bit 0 TCCR T1CL2 T1CL1 T0CL2 T0CL1 Reset value: 1111b T0CL2, T0CL1 - Timer 0 Clock source select T1CL2, T1CL1 - Timer 1 Clock source select
Table 15 Timer/Counter Clock Control Register (TCCR)
AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA
xx00 xx01 xx10 xx11 00xx 01xx 10xx 11xx Timer 0 clock = SUBCL Timer 0 clock = SYSCL out out out in x x x x x x x x Timer 0 clock = Timer1 output (T1OUT connected internally) Timer 0 clock = T0IN0 ( BP40*) Timer 1 clock = SUBCL Timer 1 clock = SYSCL Timer 1 clock = TIM1 out out out in Timer 1 clock = Timer 0 output (T0OUT0 connected internally) * if TCIO0 = low (connects Timer 0 to Port 4) The Timer/Counter Clock Control Register (TCCR) controls the clock source to both Timer 0 and Timer 1 prescalers. If an external clock source (on BP40 or TIM1) is selected, then the corresponding port direction is automatically switched to input mode (see figure 27). Note: The TCIO0 bit must be set low for the BP40 external timer/counter access. 32 (61) Rev. A2, 26-Feb-01
Code 3210
Function
Direction (TDir) BP40* TIM1
Preliminary Information
T48C510
Timer/Counter Interrupt Priority Register (TCIP) The Timer/Counter Interrupt Priority register (TCIP) is used to configure the Timer 0 and Timer 1 interrupt priority levels.
AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA
xx11 xx10 xx01 xx00 11xx 10xx 01xx 00xx Timer 0 interrupt priority 1 Timer 0 interrupt priority 3 Timer 0 interrupt priority 5 Timer 0 interrupt priority 7 Timer 1 interrupt priority 0 Timer 1 interrupt priority 2 Timer 1 interrupt priority 4 Timer 1 interrupt priority 6 Timer/Counter I/O Control Register (TCIOR) Subport address (indirect write access): '5'hex of Port adddress '9`hex xxx1 xxx0 xx1x xx0x x1xx x0xx 1xxx 0xxx BP43 - Buzzer output (NBUZ) By using the Timer/Counter I/O Control Register (TCIOR) the program can configure the respective Port 4 pins as either standard data I/O ports or as external signal ports for the Timer 0 and Buzzer. The Timer 1 uses a dedicated I/O pin TIM1, whose direction is controlled solely by the TCCR (see figure 29). It should be noted that if a Rev. A2, 26-Feb-01
AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAA AAAAAAAAAAAA A A A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AA A
TCIP Bit 3 T1IP2 Bit 2 T1IP11 T0IP2, T0IP1 - Timer 0 Interrupt Priority code T1IP2, T1IP1 - Timer 1 Interrupt Priority code
Table 16 Timer/Counter Interrupt Priority Register (TCIP)
Subport address (indirect write access): '7'hex of Port address '9`hex Bit 1 Bit 0 T0IP2 T0IP1 Reset value: 1111b
Code 3210
Function
AAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A A A A A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A A
TCIOR Bit 3 TCIO3 Bit 2 TCIO2 Bit 1 TCIO1 Bit 0 TCIO0 Reset value: 1111b TCIO3...0 - Timer / Counter I/0 mode select
Table 17 Timer/Counter I/O Control Register (TCIOR)
Code 3210
Function
BP40 - standard port mode BP41 - standard port mode BP42 - standard port mode BP43 - standard port mode
BP40 - Timer 0 clock input (T0IN0) or Timer 0 output (T0OUT0) BP41 - Timer 0 gate input (T0IN1) or Timer 0 output (T0OUT1) BP42 - Buzzer output (BUZ)
TCIOR bit is set low, then the corresponding port data direction register (P4DDR) bit no longer influences the port direction. In the case of BP40 and BP41, the port direction is then controlled entirely by the timer/counter configuration registers (TCCR,T0MO), while pins BP42 and BP43 become unidirectional buzzer outputs.
33 (61)
Preliminary Information
T48C510
TIMER 0
T0IN0
P4DAT0
T0OUT0
BP40 to CPU
TCIO0 TCCR
Select Ext. Clock
T0IN1
P4DDR0
P4DAT1
T0OUT1
BP41 to CPU BP42 to CPU
T0MO PWM,PDM
Melody,Counter
TCIO1 P4DDR1 P4DAT2
BUZZER
BUZ
TCIO2 P4DDR2
'0'
P4DAT3
NBUZ
BP43 to CPU
TCIO3 P4DDR3
TIMER 1
T1IN T1OUT
'0'
TIM1
TCCR
Select Ext. Clock
96 11533
Figure 29. Timer/counter and buzzer external interface
Timer/Counter Mode Register (TCMO)
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA
AAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAA A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A
TCMO Bit 3 T0NINV Bit 2 TC8 Bit 1 T1RST Bit 0 T0RST Reset value: 1111b T0NINV TC8 - Timer 0 output (BP41) appears non-inverted at BP40 - Timer/Counter in 8-/16-bit mode - Timer 1 Stop/Run - Timer 0 Stop/Run T1STP T0STP
Table 18 Timer/Counter Mode Register (TCMO)
Subport address (indirect write access): '4'hex of Port address '9`hex
Code 3210 xxx0 xxx1 xx0x xx1x x0xx x1xx 0xxx 1xxx Timer 0 running Timer 0 halted Timer 1 halted Timer 1 running
Function
Timer/counter in 16-bit mode Timer/counter in 8-bit mode
Inverted output BP41 appears on BP40 (BP40 = NOT BP41) Non-inverted output BP41 appears on BP40 (BP40 = BP41)
34 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
2.5.2 Timer/Counter in 16-bit Mode
Timer 0
Compare Register
Timer 1
Compare Register
Comparator
Carry 8bit/16bit
Comparator
Compare Interrupt
Prescaler
Counter
Prescaler
MUX
Counter
to TIM1
Overflow/compare Figure 30. 16-bit mode
96 11549
In 16-bit mode, Timer 0 and Timer 1 are cascaded thus forming a 16-bit counter (see figure 30) whereby, irrespective of the state of Timer 0 interrupt mask bit (T0IM), the Timer 1 counts both Timer 0 overflow and compares interrupt events. These are generated according to the state of the Timer 0 Mode Register as described in the T0MO table. The comparators are also cascaded so that when both Timer 0 and Timer 1 match their respective compare registers, the Timer 1 generates both an output signal and a compare interrupt (if unmasked). In measurement modes, only Timer 0 capture register is loaded with Timer 0's contents on an end-of-measurement event. Timer 1 capture register operates solely as a shadow register. There is no 16-bit capture operation, so the user program must check if Timer 1 has incremented between reading the lower and higher byte. Likewise, there is no automatic suppression of spurious interrupts which could conceivably be generated between writing Timer 0 and Timer 1 compare registers.
2.5.3
Timer 0 Modes
The Timer 0 mode configuration is defined in the Timer 0 Mode Register (T0MO). The available modes and the effect on the Timer 0 interrupt and interrupt flags is shown below. In all modes except the position measurement mode, Timer 0 acts as an up-counter, the related clock frequency being defined by the selected clock source and the prescaler division factor. The counter can be reset and halted at any time by the T0RST bit of the TCMO register which also resets all the interrupt status flags and capture registers. Whenever Port 4 BP40 and BP41 pins are required for Timer 0 I/O, then the appropriate TCIOR enable bit must be set low. In this case, the port direction switching is handled automatically by the hardware. In modes where the BP40 is not used as a timer clock input or as a melody envelope output, the BP40 outputs the same signal as that appearing on BP41. With the help of the T0NINV bit of the Timer/Counter Mode Register (TCMO), the BP41 output can be inverted so that BP40 and BP41 form a differential output stage which can be used for directly driving piezo buzzers or small stepper motors.
Rev. A2, 26-Feb-01
35 (61)
Preliminary Information
T48C510
Timer 0 Mode Register (T0MO)
AAAAAAAAAAAA AA A A A A A AAAAAAAAAAAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAA A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A
T0MO Bit 3 T0MO3 Bit 2 T0MO2 Bit 1 T0MO1 Bit 0 T0MO0 Reset value: 1111b T0MO3 ... 0 - Timer 0 Mode Code
Table 19 Timer 0 Mode Register (T0MO)
Subport address (indirect write access): '0'hex of Port adress '9'hex
AAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAA AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A
AAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A AAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAA A A A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AAA A A A AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A AAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAA A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA A A AAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AA A
BP40 (*3) BP41 cmp - - ofl - - eom - - 0000 0001 0010 0011 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 reserved reserved Modulated melody mode Melody mode Envelope (out) Tone (out) Tone (out) Tone (out) y/y y/y y/y n/y n/y n/y n/n n/y n/y y/y n/y n/y n/y y/y y/y y/y y/y y/y y/y y/y y/y y/y y/y y/y y/y y/y n/n n/n n/n n/n n/n n/n y/y n/n y/y y/y n/y n/y y/y y/y 0100 Counter-auto reload (50% duty cycle) Pulse density modulation Pulse width modulation Phase measurement Position measurement
Toggle (out) /Clock (in) Toggle (out) /Clock (in) PWM (out) /Clock (in)
Code 3210
Function
Assuming TCIOR1=TCIOR0=low
Interrupt set / T0SR affected
Toggle (out) Toggle (out) PWM (out)
Counter-free running (50% duty cycle)
PDM (out) /Clock (in) PDM (out) Signal 1 (in) Signal 1 (in) Clock (in) Clock (in)
Signal 2 (in) Signal 2 (in) Signal (in) Signal (in)
(*1)
(*2)
Low pulse width measurement Counter- auto reload (strobe)
High pulse width measurement Counter-free running (strobe)
Strobe (out) /Clock (in) Strobe (out) /Clock (in)
Strobe (out) Strobe (out) Signal (in) Signal (in)
Period measurement (rising edge)
Clock (in) Clock (in)
Period measurement (falling edge)
*1 Note: *2 Note: *3 Note:
The compare interrupt/status flag can only be set when counting up.
The overflow interrupt/status flag is set on both an overflow or an underflow. The BP40 signals can be inverted if T0NINV=0 (TCMO register)
Timer 0 Interrupt Status Register (T0SR) Auxiliary register address (read access): '9'hex Bit 3 Bit 2 Bit 1 Bit 0
T0SR
not used
T0EOM
T0OFL
T0CMP
Reset value: x000b
Note:
The status register is reset automatically when read and also when Timer 0 is reset.
T0EOM- Timer 0 End Of Measurement status flag T0OFL - Timer 0 OverFLow status flag T0CMP - Timer 0 CoMPare status flag 36 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
Table 20 Timer 0 Interrupt Status Register (T0SR)
Code 3210 xxx1 xx1x x1xx
Function Timer 0 compare has occurred (Timer 0 = T0CP) Timer 0 overflow or underflow has occurred Timer 0 measurement completed
AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA
The interrupt flags will be set whenever the associated condition occurs irrespective of whether the corresponding interrupt is triggered. Therefore, the status flags are still set if the interrupt condition occurs when the interrupt is masked. To see exactly when the flags are set, see T0MO control code table 18. Reading from the timer/counter auxiliary register will access the Timer 0 Interrupt Status Register (T0SR). Timer 0 Control Register (T0CR) The T0CR is responsible for the predivision of the selected Timer 0 input clock (see TCCR). It can be divided or used directly as clock for the up/down counter. Bit 0 is the mask bit for the Timer 0 interrupt.
AAAAAAAAAAAA A A AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AA A
T0CR Bit 3 T0FS3 Bit 2 T0FS2 Bit 1 T0FS1 Bit 0 T0IM Reset value: 1111b T0FS3 ... 1 - Timer 0 prescaler division factor code T0IM - Timer 0 Interrupt Mask
Table 21 Timer 0 Control Register (T0CR)
Subport address (indirect write access): '1'hex of Port address '9`hex
Code 3210 xxx1 xxx0 000x 001x 010x 011x 100x 101x 110x 111x Timer 0 interrupt disabled Timer 0 interrupt enabled
Function
Timer 0 prescaler divide by 256 Timer 0 prescaler divide by 128 Timer 0 prescaler divide by 64 Timer 0 prescaler divide by 32 Timer 0 prescaler divide by 16 Timer 0 prescaler divide by 8 Timer 0 prescaler divide by 4 Timer 0 prescaler bypassed
Rev. A2, 26-Feb-01
37 (61)
Preliminary Information
T48C510
Timer 0 Compare Register (T0CP) - Byte Write
AAAAAAAAAAAAA A AA A A AAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA A AAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A
Bit 3 Bit 7 Bit 2 Bit 6 Bit 1 Bit 5 Bit 0 Bit 4 T0CP First write cycle T0CP3 T0CP7 T0CP2 T0CP6 T0CP1 T0CP5 T0CP0 T0CP4 Reset value: xxxxb Reset value: xxxxb Second write cycle T0CP3 ... T0CP0 - Timer 0 Compare Register Data (low nibble) - first write cycle T0CP7 ... T0CP4 - Timer 0 Compare Register Data (high nibble) - second write cycle The compare register T0CP is 8-bit wide and must be accessed as byte wide subport (see section "Addressing Peripherals). First of all, the data is written low nibble and is then followed by the high nibble. Any timer interrupts are automatically suppressed until the complete compare value has been transferred. Timer 0 Capture Register (T0CA) - Byte Read Subport address (indirect read access): '9'hex of Port address '9`hex
Subport address (indirect write access): '9'hex of Port address '9`hex
AAAAAAAAAAAA A AA A A AAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAA A
Bit 7 Bit 3 Bit 6 Bit 2 Bit 5 Bit 1 Bit 4 Bit 0 T0CA First read cycle T0CA7 T0CA3 T0CA6 T0CA2 T0CA5 T0CA1 T0CA4 T0CA0 Reset value: xxxxb Reset value: xxxxb Second read cycle T0CA7. .. T0CA4 - Timer 0 Capture Register Data (high nibble) - first read cycle T0CA3 ... T0CA0 - Timer 0 Capture Register Data (low nibble) - second read cycle Note: If the timer is read (in PDM mode only) the bit order will appear reversed, so that T0CA0 =MSB, T0CA1=MSB-1 .... T0CA6=LSB+1, T0CA7 = LSB. The 8-bit capture register T0CA is read as byte wide subport. Note, however, unlike the writing to the compare register, the high nibble is read first followed by the low nibble. The 8-bit timer state is captured on reading the first nibble and held until the complete byte has been read. During this transfer, the timer is free to continue counting. 38 (61) Rev. A2, 26-Feb-01
Preliminary Information
T48C510
Timer 0 Free Running Counter Modes (Strobe and 50% Duty Cycle) In the free running counter mode, Timer 0 can be used as an event counter for summing external event pulses on BP40, or as a timer with an internal time-based clock. When enabled, the counter will count up generating an output signal on BP41 whenever the counter contents match the compare register (see figure 31). This signal can appear either as a strobe pulse or as a simple toggling of the output state (50% duty cycle) depending on the timer mode. Interrupts (if not masked) are generated every 256 clocks on the overflow condition. The current counter state can be read at any time by reading the capture register,. The compare register has no effect on the counter cycle time and will not influence interrupts.
Overflow Interrupt
strobe
T0OUT1 (BP41)
50% duty cycle
Timer Clock Timer resets on overflow Timer = compare register (= 4) Figure 31. Timer 0 free running counter mode
Timer 0 Counter Reload Modes (Strobe and 50% Duty Cycle) As in the free running mode, the counter can also be clocked from either an external signal on BP40 or from an internal clock source. In this mode, the counter repetition period is completely defined by the contents of the compare register (T0CP) (see figure 32). The counter counts up with the selected clock frequency. When it reaches the value held in the compare register, the counter then returns to the zero state. At the same time, depending on the selected timer mode, the BP41 either toggles or generates a strobe pulse. If the Timer 0 interrupt is unmasked, a compare interrupt is also generated. The resultant output frequency fOUT = fIN/2*(n+1) where n = compare value (n = 1 - 255).
0 123 45670 123 4567 0 123 4567 0
Compare Interrupt
strobe
T0OUT1 (BP41)
50% duty cycle
Timer Clock
Timer = compare register (= 7) Resets timer Figure 32. Timer 0 counter reload mode
Rev. A2, 26-Feb-01
Preliminary Information
I I
II II II II
Timer State
I
I
II
Timer State
255
0
1
2
3
4
56
255
0
1
2
3
4
56
255
0
1
2
3
4
56
96 11534
96 11535
39 (61)
T48C510
Melody Mode (with/without Modulation) The non-modulated melody mode is identical to the auto- reload counter (50% duty cycle) mode. The melody tone frequency appearing on BP41 and/or BP40 is determined in exactly the same way as the value written into the comparator register. In the modulated melody mode, the T48C510 generates two output signals, a melody tone and an envelope pulse (see figure 33). The tone frequency output on BP41 is generated in exactly the same way as in the simple melody mode. While the envelope pulse on BP40 is a single pulse, of a clock period in duration which appears shortly after loading the compare value into the compare register. In this mode, an analog switch is activated between the BP40 and BP41 outputs (see figure 34). With the external capacitor connected, the resultant signal on BP41 exhibits a melody chime effect with an exponential decay.
Timer State Compare Interrupt T0OUT1 (BP41) T0OUT0 (BP40) Timer Clock 01 2 3 4 5 6 024602460246 0246 71357135713571357
New value (=7) loaded into compare register
Timer = compare register resets timer Figure 33. Modulated melody mode
96 11538
V DD T0OUT0 (melody output) Modulated melody mode T0OUT1 (envelope) V SS T0OUT1 T0OUT0 BP41 BP40
Figure 34. Modulated melody output circuit
V DD BP40 R
(optional)
Analog switch
10...47uF
Piezo buzzer VSS
BP41
96 11539
40 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
Timer 0 Pulse Width Modulation Mode A pulse width modulated (PWM) signal exhibits a fixed repetition frequency and a variable mark space ratio. It is often used as a simple method for D/A conversion, where the high period is proportional to the digital value to be converted. Therefore by connecting a simple low-pass RC network to the PWM signal, the analog value can be retrieved. Timer 0 generates the PWM signal by comparing the state of the free running up counter with the contents of the compare register (see figure 35). If the result is less than the compare register value, then the BP41 output is high. If the result is greater or equal to the compare register value, then the BP41 output is set low. Thus, the high phase of the PWM signal is directly proportional to the compare register contents. A total of 256 possible discrete mark space ratios can be generated ranging from a continuous low signal over a variable pulse width signal to a continuous high signal. The PWM signal has a repetition period of 256 clocks, an interrupt (if unmasked) being generated on every overflow event. Care should be taken if the SYSCL clock is used as the PWM clock source because it may stop if the CPU goes into SLEEP mode (see Section 1.5.4 Power-Down Modes).
Overflow Interrupt t_hi T0OUT1 (BP41) Timer Clock
t_low
Timer = compare register (= 4) t_hi = (comparator value)*clock period t_low = (255-comparator value)*clock period Figure 35. Timer 0 pulse width modulation
96 11540
Pulse Density Modulation Mode Pulse density modulation (PDM) is also used for simple D/A conversion. Unlike the PWM signal,where the high and low signal phases are always continuous during a single repetition cycle, the PDM distributes these evenly as a series of pulses (see figure 36). This has the advantage that, if used together with an RC smoothing filter for D/A conversion, either the ripple is less than the PWM, or, for a corresponding ripple error, the filter components can be smaller or the clock frequency lower. To generate the PDM output on BP41, the pulse density is controlled by the contents of the compare register in the same way as the PWM generation. Each of the pulses has a width equal to the counter clock period.
Repetition period PWM=0.25
PWM=0.75 PDM=0.25
PDM=0.75
96 11541
Figure 36. An example 4-bit PWM/PDM comparison
Rev. A2, 26-Feb-01
Preliminary Information
I
41 (61)
II
II
Timer State
255
0
1
2
3
4
255
0
1
3
4
255
0
1
3
4
T48C510
Period Measurement Modes (Rising and Falling Edge) During the period measurement mode, the counter counts the number of either internal or external clocks in one period of the BP41 input signal (see figure 37). Dependent on the mode chosen, this will be from rising edge to the next rising edge or conversely, falling edge to the following falling edge. On the trigger edge, the counter state is loaded into the capture register and subsequently reset. The measured value remains in the capture register until overwritten by the following measured value. Interrupts can be generated by either an overflow condition or an end-of-measurement (eom) event. An 'eom' event signals the CPU that a new measured value is present in the capture register and can be read, if required.
Captures and resets timer
"eom" Interrupt
t_period t_period
T0IN1 (BP41)
Falling edge triggered Figure 37. Period measurement Rising edge triggered
96 11542
Pulse Width Measurement Modes (High and Low) In this mode, the selected clock source is gated to the counter for the duration of each input pulse received on BP41 (see figure 38). Whether the measurement takes place during the high or low phase depends on the selected mode. At the end of each pulse, the counter state is loaded into the capture register and subsequently reset. Interrupts can be generated by either an overflow condition or an end-of-measurement (eom) event. An 'eom' event signals the CPU that a new measured value is present in the capture register can be read, if required.
Captures and resets timer "eom" Interrupt t_low T0IN1 (BP41)
96 11543
t_high
Figure 38. Pulse width measurement
42 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
Phase Measurement Mode This mode allows the Timer 0 to measure the phase misalignment between two 1:1 mark space ratio input signals connected to the BP40 and BP41 pins (see figure 39). The counter clock is gated with the phase misalignment period (tp), during which time the counter increments with the selected clock frequency. This misalignment period is defined as the period during which BP40 is high and BP41 is low. Capturing and resetting of the counter always takes place on the rising edge of BP41. The measured value remains in the capture register until overwritten by the next measurement. Interrupts can be generated by either an overflow condition or an end-of-measurement ('eom') event. An 'eom' event signals the CPU that a new measured value is present in the capture register and can be read, if required.
Captures & resets timer
"eom" Interrupt
tp tp tp
T0IN0 (BP40) T0IN1 (BP41)
Figure 39. Phase measurement
96 11544
Position Measurement Mode This mode is intended for the evaluation of positional sensors with biphase output signals. Figure 40 illustrates a typical positional sensor system which delivers both incremental positional stepping signals and also directional information. The direction can be deduced from the relative phase of the two signals. Therefore if BP40 is high on the rising edge of BP41, the moving mask travels to the left and if it is low then it travels to the right. The direction (left/right) information is used to set the direction of the up/down counter which enables the BP40 pulses to be counted. Assuming that the system has been reset on a reference position, the counter will always hold the absolute current position of the moving mask. This can be read by the CPU if necessary. This mode is the only one in which the counter is allowed to decrement. Therefore, in this case it is possible for both an underflow or an overflow to occur. The overflow interrupt (if unmasked) will trigger on either of these conditions while the compare interrupt on the other hand will only trigger if the counter is counting upwards. To differentiate between an overflow or underflow, the compare value can be set to '0' hex, for example. An overflow would then set both the overflow and compare status flags while an underflow sets the overflow status flag only.
T0IN0
T0IN1
Timer T0IN0 (BP40) T0IN1 (BP41)
N
Rev. A2, 26-Feb-01
AAAAAAAA AAAA AAAAAA
light light left movement N+1 N+2 N+3 N right movement N-1 N-2
Typical sensor
Moving mask Static mask
N-3
96 11545
Figure 40. Position measurement mode
43 (61)
Preliminary Information
T48C510
2.5.4 Timer 1 Modes
The Timer 1 is aimed at performing event counting and timing functions (see figure 28). It has, unlike the Timer 0, no gated clock or externally triggered capture modes. The counter counts up with an internal or external clock, depending on the state of the Timer 1 Control Register (T1CR) and the Timer/Counter Clock Control Register (TCCR) and generates a compare interrupt whenever the counter matches the Timer 1 compare register. This is the only Timer 1 interrupt source. Masking can be performed using the mask bit in the Timer 1 Control Register (T1CR) and priority can be defined in the Timer/ Counter Interrupt Priority Register (TCIP). The TIM1 pin Timer 1 Mode Register (T1MO) is used by the Timer 1 either as clock/event input or timer output. I/O control of the Timer 1 pin TIM1 is controlled entirely by the hardware, therefore if the TIM1 is selected as an external clock or event source (in the TCCR), there can be no Timer 1 signal output. In this case, the timer would be used solely to generate interrupts. In autostop operation, the Timer 1 will halt both itself and Timer 0 whenever the Timer 1 compare value is reached. This feature can be used for example to generate an exact burst of pulses. Both timers will remain stopped until restarted. Restarting is performed in the normal way by setting the appropriate control bits in the Timer/Counter Mode Register (TCM0).
AAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A
T1MO Bit 3 T1MO3 Bit 2 T1MO2 Bit 1 T1MO1 Bit 0 T1MO0 Reset value: 1111b T1MO3 ... 0 - Timer 1 Mode Control
Table 22 Timer 1 Mode Register (T1MO)
Subport address (indirect write address): '2'hex of Port address '9`hex
Code 3210 xx00 xx01 xx10 xx11 x0xx x1xx 1xxx 0xxx
Function Counter free running (50% duty cycle) Counter auto reload (50% duty cycle) Pulse width modulation Counter auto-reload (strobe output) Increment on falling edge of clock Increment on rising edge of clock Normal operation (no autostop)
Compare Interrupt yes yes yes yes - -
AAAAAAAAAAAA AA A A A A A AAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAA A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A
AAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA
yes yes Autostop operation (Timer 1 stops Timer 2) Timer 1 Control Register (T1CR) The T1CR is responsible for the predivision of the selected Timer 1 input clock (see TCCR). It can be divided or used directly as clock for the up counter. Bit 0 is the mask bit for the Timer 1 interrupt. Subport address (indirect write access): '3'hex of Port adress '9`hex T1CR Bit 3 T1FS3 Bit 2 T1FS2 Bit 1 T1FS1 Bit 0 T1IM Reset value: 1111b T1FS3 ... 1 T1IM - Timer 1 Prescaler Division Factor Code - Timer 1 Interrupt Mask 44 (61) Rev. A2, 26-Feb-01
Preliminary Information
T48C510
Table 23 Timer 1 Control Register (T1CR)
Code 3210 xxx1 xxx0 000x 001x 010x 011x 100x 101x 110x 111x Timer 1 interrupt disabled Timer 1 interrupt enabled
Function
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA
Timer 1 prescaler divide by 256 Timer 1 prescaler divide by 128 Timer 1 prescaler divide by 64 Timer 1 prescaler divide by 32 Timer 1 prescaler divide by 16 Timer 1 prescaler divide by 8 Timer 1 prescaler divide by 4 Timer 1 prescaler bypassed Timer 1 Compare Register (T1CP) - Byte Write Subport address (indirect write access): '8'hex of Port address '9`hex
AAAAAAAAAAA A AA A A AAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A AAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAA
Bit 3 Bit 7 Bit 2 Bit 6 Bit 1 Bit 5 Bit 0 Bit 4 T1CP First write cycle T1CP3 T1CP7 T1CP2 T1CP6 T1CP1 T1CP5 T1CP0 T1CP4 Reset value: xxxxb Reset value: xxxxb Second write cycle T1CP3 ... T1CP0 - Timer 1 Compare Register Data (low nibble) - first write cycle T1CP7. .. T1CP4 - Timer 1 Compare Register Data (high nibble) - second write cycle The compare register T1CP is 8 bits wide and must be accessed as byte wide subport (see section "Addressing Peripherals"). The data is written low nibble first, followed by high nibble. Any timer interrupts are automatically suppressed until the complete compare value has been transferred. Timer 1 Capture Register (T1CA) - Byte Read Subport address (indirect read access): '8'hex of Port address '9`hex
AAAAAAAAA A AAAA A A AAAAAAAAA A AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAA
Bit 7 Bit 3 Bit 6 Bit 2 Bit 5 Bit 1 Bit 4 Bit 0 T1CA First read cycle T1CA7 T1CA3 T1CA6 T1CA2 T1CA5 T1CA1 T1CA4 T1CA0 Reset value: xxxxb Reset value: xxxxb Second read cycle T1CA7 ... T1CA4 - Timer 1 Capture Register Data (high nibble) - first read cycle T1CA3 ... T1CA0 - Timer 1 Capture Register Data (low nibble) - second read cycle The 8-bit capture register T1CA is read as byte-wide subport. Note, however, unlike the writing to the compare register, the high nibble is read first followed by low nibble. The 8-bit timer state is captured on reading the first nibble and held until the complete byte has been read. During this transfer, the timer is free to continue counting. The previous capture value will be held until the timer is restarted again. Rev. A2, 26-Feb-01 45 (61)
Preliminary Information
T48C510
Timer 1 Counter Free Running (50% Duty Cycle) In the free running counter mode, the counter counts up with either an internal or external clock and cycles through all 256 timer states. On the clock following a match between the compare register (T1CR) and the counter, a compare interrupt (if unmasked) is generated and the TIM1 pin is toggled (see figure 40).
0 2 4 0 2 4 0 2 4
Compare Interrupt T1OUT (TIM1) Timer Clock
50% duty cycle
(clock set to rising edge)
Timer = compare register (= 4) Figure 41. Timer 1 counter free running (50% duty cycle)
Timer 1 Counter Auto Reload (Strobe and 50% Duty Cycle) In the auto-reload mode, the counter counts up with either an internal or external clock. On the clock cycle following a match between the compare register (T1CR) and the counter, a compare interrupt (if unmasked) is generated. The TIM1 output is either strobed or toggled and the counter reset (see figure 42). Therefore, the counter cycle period is defined by the contents of the compare register. In 50% duty cycle mode the frequency of TIM1 is: fTIM1 = fin/2(n+1)
Timer State Compare Interrupt strobe T1OUT (TIM1) 50% duty cycle Timer Clock
where the compare value (n) =1 ... 255.
0 123 4567 0 1234567 0 123 45670
(clock set to neg. edge) Timer = compare register (= 7) Resets timer Figure 42. Timer 1 counter auto reload
46 (61)
Rev. A2, 26-Feb-01
Preliminary Information
II
I
II
II
I
I
Timer State
255
1
3
56
255
1
3
56
255
1
3
56
96 11546
96 11547
T48C510
Timer 1 Pulse Width Modulation The Timer 1 generates the PWM signal by comparing the state of the free running up counter with the contents of the compare register (see figure 43). If the result is less or equal to the compare register value, then the TIM1 output is high. If the result is greater than the compare register value, then the TIM1 output is set low. Thus, the high phase of the PWM signal is directly proportional to the compare register contents. A total of 256 possible discrete mark space ratios can be generated ranging from a continuous low signal over a variable pulse width signal. The PWM signal has a repetition period of 256 clock periods, an interrupt (if unmasked) being generated on every compare event. Care should be taken if SYSCL is used as the PWM clock source. The PWM output may stop if the CPU goes into SLEEP depending on the programming of the NSTOP bit in the CM-register. Using this mode of operation recommends to set the bit NSTOP =1.
Compare Interrupt t_hi T1OUT (TIM1) Timer Clock t_hi = (comparator value)*clock period t_low = (256-comparator value)* clock period
t_low
Timer = compare register (=4)
96 11548
Figure 43. Timer 1 pulse width modulation
2.6
Buzzer Module
The buzzer is a 4 stage frequency divider which divides the SUBCL and depending on the state of the Buzzer Control Register (BZCR) can output one of four frequencies. An external piezo or buzzer can be driven by the complementary buzzer outputs (BUZ and NBUZ) which are directed to Port 4 (BP42 and BP43) under control of the Timer/Counter I/O Register (TCIOR) as shown in figure 28. When the buzzer is switched off, both of the buzzer outputs take up the same logical state. This is controlled by the BZOP bit of the BZCR.
BZCR
BZFS2 BZFS1 BZOP BZOF
NBUZ
SUBCL (32 kHz) SUBCL / 4 (8 kHz) SUBCL / 8 (4 kHz) SUBCL / 16 (2 kHz) BUZ 4 :1 MUX
SUBCL
CK
4 stage divider R R R
96 11550
R
Figure 44. Buzzer module
Rev. A2, 26-Feb-01
Preliminary Information
II
47 (61)
II
I
Timer State
255
0
1
2
3
4
255
0
1
2
3
4
255
0
1
2
3
4
AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA
Table 24 Buzzer Control Register (BZCR)
AAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A AAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAA A AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA A
Buzzer Control Register (BZCR) BZFS2, BZFS2
NBUZ
BUZ
BZOF
BZOP
T48C510
48 (61) BZCR
NBUZ BUZ
11xx
10xx
01xx
00xx
xx1x
xx0x
xxx1
xxx0
Code 3210
Buzzer frequency: 2 kHz (= SUBCL / 16)
Buzzer frequency: 4 kHz (= SUBCL / 8)
Buzzer frequency: 8 kHz (= SUBCL / 4)
Buzzer frequency: 32 kHz (= SUBCL)
Buzzer output stop state: BP42 = BP43 = high
Buzzer output stop state: BP42 = BP43 = low
Buzzer off
Buzzer on
Bit 3 BZFS2
- Buzzer off/on
- Buzzer Output Stop State
- Buzzer Frequency Select code
Bit 2 BZFS1
Preliminary Information
Figure 45. Buzzer waveform
Subport address (indirect write access): 'A`hex of Port adress '9`hex
Bit 1 BZOP
Function
Bit 0 BZOF
BUZZER Off
BZOP=0
BZOP=1
Reset value: 1111b
Rev. A2, 26-Feb-01
96 11551
T48C510
2.7 MTP Programming
The state of the T48C510 PM pin defines the MTP operational mode ie. PM = high (Program Mode), PM = low (Normal operation Mode) while the 3 TPI data lines are used to serially load or read the customer's data into or out of the T48C510.
Application Program
The Programmer software requires only the customer's binary *.hex file which is generated by the MARC4 program compiler and also provides the primary data base for emulation. This is displayed on the screen as an editable hexadecimal memory map. Contents of an already programmed device can be read back and displayed an the same hex. form provided that the device's "Read Lock" has not been set. A "Read Lock" Protected device, if read will appear to be full of F hex .
In Circuit Programmer (ICP) Target Programmer Interface (TPI)
16541
Figure 46. Programmer System
Hardware Configuration
All hardware configurations are set up within the software's intuitive user interface by selecting the required options from the masks provided. The available configurable hardware options are similar to those of the M44C510E (see "Hardware Options" section). These effect primarily port configurations, watchdog and coded reset settings. The port driver strengths, although mask programmable in the M44C510E are not configurable in the MTP - all output drivers being internally "hardwired" to the default "standard drive" strength.
To accomodate the application program and the associated hardware option configuration, the T48C510 is equipped with 2 on-chip EEPROM memory blocks. These are written via a 6-signal Target Programmer Interface (TPI), comprising of 2 power lines (VDD and VSS), a Programm Mode signal (PM) and 3 data lines which are multiplexed onto 3 of the T48C510 functional pins - BP00, BP01 and BP02 (see figure 47). For setting up the required hardware options and downloading these along with the application program into the T48C510, the customer can be supplied with a dedicated PC based programmer software operating under Windows95/98 or NT and an In Circuit Programmer unit (ICP). The ICP is connected to the PC via a standard PC serial interface port and to the target device or application board (for in system programming) via the TPI flat band cable.
Table 25 Target programmer interface signals
Read Lock Protection
The programmer software encorporates a so called "Read Lock" which can be set by the user. This is provided for customer security purposes and inhibits the reading of the customer 's Application Program by unauthorized persons. If set, the "Read Lock" sets a hardware key in the MTP EEPROM which disables reading of the Program/ Configuration data. It should be noted that this is a "Read Lock" and not a "Write Lock", so even if the lock is set, it is still possible to overwrite the customer data with new program code.
TPI Connector Pin 1 2 3 4 5 6 7 8 9 10
Pin Name PM VDD BP02 BP01 BP00 VSS n/c n/c n/c n/c
T48C510 Function Programming Mode Input +5 volt Supply Port02 (Clock) Input Port01 (Data ) Input Port00 (Data ) Output Ground Supply not connected not connected not connected not connected
In-System Programming
For "in-system programming", the application circuit board must be fitted with a 10-pin male connector to accomodate the TPI connector. To ensure conflict-free access to the target T48C510 TPI related Pins (BP00, BP01, BP02 and PM) it is recommended that these are equipped with jumpers (J5, J4, J3 and J1) to avoid signal contention with other on board drivers sources. ( see figure 47). However, if these can be overdriven, or if the Port 0 is not used in the application, then the jumpers can be omitted or replaced by isolating resistors. Prior to connecting the TPI, all other application power supply sources should be disconnected from the application circuit board. Should 49 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
other on board components either present an excessive power supply load or be unable to withstand the ICP 5-Volt supply voltage, then the VDD power line should also be jumpered (J2). During the programming operation all ports are set into
1 2 3 4 5 6 7 8 9 10 VSS n.c. n.c. n.c. n.c.
input mode, with the previously programmed pullup/pulldowns transitors deactivated. In normal operational mode, the PM pin is strapped to ground and the Port 0 reverts to a port function as described in section 2.2.1.
1 2 3
VSS BP53 BP52 BP51 BP50 VDD BP43 BP42 BP41 BP40 BP03 BP02 BP01 BP00 TIM1 BPC1 TE BPC0 BP13 BP12 BP11 BP10
BP70 BP71 BP72 BP73 PM SCLIN BP61 BP60 BPB3
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 J1
Programmer interface
J2
4
*
5 6 7 8 9
*
VSS
T48C510
Application: BP00
BP01
BP02 VDD
J3 J4
10 11 12 13 14 15 16 17 18 19 20
BPB2 BPB1 BPB0 BPC3 BPC2 AVDD OSCIN OSCOUT NRST BPA0 BPA1 BPA2 BPA3
J5
*
*
*
*Optional jumpers
21 22
Figure 47. In-system programming
2.8
Noise Considerations
2.8.1
Noise Immunity
When designing the microcontroller based application, several factors should be taken into consideration to increase noise immunity and reduce electromagnetic emission (EME). Many such potential problems can be avoided by careful layout of the printed circuit board (PCB). The PCB contains many parasitic components which at first sight are not apparent. PCB tracks can act as antennas or as coupling capacitors. Long stretches of parallel tracks and long high frequency signal lines should thus be avoided wherever possible to minimise the chance of picking up or transmitting unwanted signals.
The following guidelines will increase system noise immunity: D Unconnected inputs should not be left open. If port pins are not required then it is recommended to set pullup or pulldown option on these pins. D Special care should be taken when laying out the PCB that interrupt, reset and clock signal lines are kept short and are carefully shielded or have sufficient spacing from other on board noise generating sources. D A quartz crystal should always be directly located immediately next to the microcontroller crystal oscillator terminals (OSCIN and OSCOUT), the connections being always very short. This avoids not only signal coupling onto the clock source but can also reduces EME.
50 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
D PCB's should where economically possible be equipped with adequate ground planes. D The microcontroller power supply should be decoupled with an electrolytic capacitance (approx. 10 mF) in parallel with a ceramic capacitance (approx.100 nF) situated as close to the microcontroller device as possible. D Keep the length of PCB current switching signal tracks to a minimum.. D Adopt a PCB star power routing system connected at one point. D Many of the microcontroller port outputs can be configured with several drive strengths. This means that a high drive output will switch a signal faster than for example standard drive output. The resulting change in current in the signal and power lines will also increase, causing an increase in EME. So wherever speed and drive current is not necessary the ports should be configured with the lowest drive possible. D If possible, write the application program to avoid multiple outputs switching at any instant. D Cables can be equipped with ferrite rings to slow current spikes or the system can be encased in a grounded conducting casing.
2.8.2
Electromagnetic Emission
Electromagnetic emmision is caused by rapidly changing electrical current (dI/dt) in long antenna like connection lines and cables. This can result in electrical interference on other telecommunication devices. These current spikes are more often than not present in the system power supply lines and driver signal lines. The following guide will help to reduce EME:
3
3.1
Electrical Characteristics
Absolute Maximum Ratings
Parameters Symbol VDD VIN Value Unit V V s
Voltages are given relative to VSS .
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAA A A A A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
Supply voltage -0.3 to + 7.0 indefinite Input voltage (on any pin)
VSS -0.3 VIN VDD +0.3
Output short circuit duration Storage temperature range
tshort Tstg Tsld
Operating temperature range Thermal resistance (SSO44)
Tamb
-40 to +85 110
C C C
-65 to +150 260
RthJA
K/W
Soldering temperature (t 10 s)
Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any condition above those indicated in the operational section of these specification is not implied. Exposure to absolute maximum rating condition for an extended period may affect device
reliability. All inputs and outputs are protected against high electrostatic voltages (4kV, HBM) or electric fields. However, precautions to minimize the build-up of electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g. VDD).
3.2
DC Operating Characteristics
Supply voltage VDD = 5 V, VSS = 0 V, Tamb = -40 to 85C unless otherwise specified. Typical values relate to VDD = 5 V, Tamb = 25C and are for reference only. Parameters Test Conditions / Pins Symbol VDD IDD Min. 2.2 Typ. Max. 6.2 Unit V Power supply Active current
Supply voltage
CPU running TestROM @SYSCL_iRC3
200
500
mA
Rev. A2, 26-Feb-01
51 (61)
Preliminary Information
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAA AAAA A A A A A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AA A A AAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAA AAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AAA A AAAAAAA A A A A AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAA A AAAAAA AAAAAAAAAAAAA A AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAA AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAA A A A AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAA AAAAAAA AA A A AAA A A A A AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A
Note: The total sum of all port static output currents must not exceed 100 mA. The sum of all port currents switched at any instant (dI/ dt) must not exceed 30 mA.
T48C510
52 (61) Input HIGH current static pull-down (4 kW) Input LOW current static pull-up (4 kW) Bidirectional Port BP60 and BR61 Input HIGH current static pull-down (30 kW) Input LOW current Static pull-up (30 kW) Bidirectional Port BP4, BP5, BP7, BPA, BPB and BPC Output HIGH current Output LOW current Dynamic input HIGH current (pull-down) Dynamic input LOW current (pull-up) Input voltage HIGH Input voltage LOW All Bidirectional Ports and TIM1 Input HIGH current Input TE with pull-down resistor Input LOW current Input NRST with pull-up resistor Input voltage HIGH Input voltage LOW Input Pins: NRST and TE Hysteresis (VT+ - VT-) Positive-going threshold voltage Negative-going threshold voltage Schmitt-trigger input voltage: (all inputs except Port 5, 7 and C) POR threshold voltage Power-on reset threshold voltage Halt current Quotient IDD/SYSCL_iR3 Parameters VDD = 2.4 V, VIL = VSS VDD = 5.0 V VDD = 2.4 V VDD = 5.0 V VDD = 2.4 V VDD = 5.0 V VDD = 2.4 V VDD = 5.0 V VDD = 2.4 V VOH = 0.8*VDD VDD = 5.0 V VDD = 2.4 V VOL = 0.2*VDD VDD = 5.0 V VDD = 2.4 V, VIH = VDD VDD = 5.0 V VDD = 2.4 V, VIL= VSS VDD = 5.0 V VDD = 2.4 to 6.2 V VDD = 2.4 to 6.2 V VDD = 5.0 V VDD = 2.4 V, VIL= VSS VDD = 5.0 V VDD = 2.4 to 6.2 V VDD = 2.4 to 6.2 V VDD = 2.4 to 6.2 V VDD = 2.4 to 6.2 V VDD = 2.4 to 6.2 V CPU in sleep mode, NSTOP = 0 CPU running TestROM @SYSCL_iRC3 Test Conditions / Pins Symbol VPOR IDDQ IHalt VT+ VT- VIH VIH IOH VIL VIL IOL VH IIH IIH IIH IIH IIH IIH IIL IIL IIL IIL IIL IIL
0.8 VDD 0.55x VDD
Preliminary Information
0.8 VDDAAAA VDD
-15 -100
Min.
0.15 1
-0.2 -1
-1.0 -5
-1.0 -5
VSS
VSS
VSS
15 100
1.0 5
0.8
-6
-1
6
1
1
0.1xVDD
-0.3 -1.35
-25 -150
Typ.
0.25 1.4
-1.5 -10
-1.5 -10
0.25
25 150
1.5 10
1.4
1.0
0.1
-8
-2
9
2
0.2 VDD
0.2 VDD
0.4xVDD
Rev. A2, 26-Feb-01 Max. -45 -220 VDD VDD -0.5 -2 -3.0 -18 -3.0 -18 45 220 -13 2.5 18 1.5 0.5 0.5 -4 13 4 2 0.5 2 A/kHz Unit mA mA mA mA mA mA mA mA mA A A A A A A A A A A mA V V V V V V V
AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAA AAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAA A A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAA A AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAA A AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
Supply voltage VDD = 2.4 to 6.2 V, VSS = 0 V, Tamb = -40 to 85C unless otherwise specified. Typical values relate to VDD = 5 V, Tamb = 25C and are for reference only.
Rev. A2, 26-Feb-01
3.3
Stability
Frequency
Standby current
RC oscillator - external resistor (for additional characteristics see figures 52 to 54)
Stability
Start-up time
Standby current
System clock crystal/ceramic oscillator (for additional characteristics see figures 49)
Stability
SYSCL_iRC3
Standby current of iRC3
SYSCL_iRC2
Standby current of iRC2
SYSCL_iRC1
Standby current of iRC1
SYSCL_iRC0
Standby current of iRC0
Internal RC oscillator (for additional characteristics see figures 55 to 57)
Int. request HIGH time
Int. request LOW time
Interrupt request input timing
NRST input LOW time
Power-on reset delay
Reset timing
AC Characteristics
Parameters
VDD = 2.4 V to 5.5 V
CPU active, Rext = 150 kW
CPU in SLEEP mode, Rext = 150 kW ("1 %)
DVDD = 3 V to 5.5 V
VDD = 2.4 V
CPU in SLEEP mode, 4-MHz crystal active
DVDD = 5 V " 20 %
CPU active, SC = 1111b, CM = 1111b
CPU in SLEEP mode, SC = 1111b, CM = 1111b
CPU active, SC = 1011b, CM = 1110b
CPU in SLEEP mode, SC = 1011b, CM = 1110b
CPU active, SC = 0111b, CM = 1101b
CPU in SLEEP mode, SC = 0111b, CM = 1101b
CPU active, SC = 0011b, CM = 1100b
CPU in SLEEP mode, SC = 0011b, CM = 1100b
VDD u VPOR
Test Conditions / Pins
Preliminary Information
Symbol fSYSCL fSYSCL fSYSCL fSYSCL fSYSCL tstartup tNRST IiRC3 IiRC2 IiRC1 IiRC0 df/f0 df/f0 df/f0 tPOR IxRC tIRH Ixtal tIRL Min. 0.60 1.8 1.4 1.9 3.5 50 50 4 Typ. 0.80 100 150 300 2.0 0.3 2.0 3.0 7.0 40 80 8
T48C510
Max.
10.5
125
125
150
250
500
"10
2.2
0.5
1.3
3.0
4.5
10
70
"5
53 (61) MHz MHz MHz MHz MHz ppm Unit mA mA mA mA mA mA ms ms s ns ns % %
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAA AAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
Crystal Characteristics Dynamic capacitance Static capacitance Series resistance Crystal frequency System clock crystal Load capacitance Dynamic capacitance Static capacitance Series resistance Crystal frequency 32-kHz crystal Parameters Test Conditions / Pins
100.0000
A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA AAAA AAAAAAA AAAA AAAAAAAAAAAAAAAAA AAAA A A A AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A AAAAA AAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
AC Characteristics (continued)
T48C510
54 (61) Parameters Test Conditions / Pins 32-kHz crystal oscillator Active current CPU active/running HALT current CPU in SLEEP mode Start-up time VDD = 2.4 V Stability DAVDD = 100 mV External clock input at SCLIN, TIM1 and T0IN SCLIN input clock CPU active, VDD > 2.4 V fSCLIN = 2 fSYSCL rise/fall time < 50 ns, see figure 47 TIM1, T0IN input frequ. rise/fall time < 30 ns EEPROM program/ configuration memory Number of programming cycles
Equivalent circuit
Figure 48. Crystal equivalent circuit
OSCIN
OSCOUT
fSYSCL ( MHz )
L
C1
C0
RS
Preliminary Information
Figure 49. Worst case minimum/ maximum system frequency (using external RC or crystal oscillator)
Symbol
Symbol
10.0000
fSYSCL
IDD32k IHALTx tstartup df/f0
0.0010
0.0100
0.1000
1.0000
RS
RS
C1
C0
CL
C1
C0
fIN
fX
fX
n
0
1
1000
Min.
Min.
1.5
8
2
32.768
fSYSCLmax
VDD ( V )
3
Typ.
Typ.
1.5
0.1
1.0
30
10
30
3
2
4
3
4
fSYSCLmin
4
Rev. A2, 26-Feb-01 Max. Max.
5
12.5
4.5
10 1.5 1.5 0.3
15
50
50
10
8
8
6
Cycles
MHz
MHz
MHz
Unit
mA mA s ppm
Unit
kHz
kW
pF pF pF fF W
fF
T48C510
10000.00 1000.00 100.00 I DD ( mA ) 10.00 1.00 0.10 0.01 10
Halt
10000
Standby
fSYSCL ( kHz )
VDD = 3 V Tamb = 25C
100% active
VDD = 5 V Tamb = 25C
1000
100 1000 fSYSCL ( kHz )
10000
100 10
100 Rext ( kW )
1000
Figure 50. IDD = f (fSYSCL)
10000.0 1000.0 I DD ( mA ) 100.0 10.0 1.0
Halt
Figure 53. fSYSCL = f (Rext)
6000
VDD = 5 V Tamb = 25C
100% active
5000 fSYSCL ( kHz ) 4000 3000
Rext = 47 k
Tamb = 25C
Rext = 150 k
Standby
2000 1000 Rext = 477 k 0
0.1 10
100 1000 fSYSCL ( kHz )
10000
1.5
2.5
3.5 4.5 VDD ( V )
5.5
6.5
Figure 51. IDD = f (fSYSCL)
2200 Rext = 150 k 2150 VDD = 5 V fSYSCL ( kHz ) fSYSCL ( kHz ) 2100 2050 2000 1950 1900 -40
16512
Figure 54. fSYSCL = f (VDD, Rext)
7000
fiRC0
6000 5000 4000 3000 2000 1000 0 -20 0 20 40 60 Tamb ( _C ) 80 100 1.5 2.5 3.5 4.5 VDD ( V ) 5.5 6.5
fiRC3 fiRC1 fiRC2
Tamb = 25C
VDD = 3 V
Figure 52. fSYSCL = f (Tamb); external RC
Figure 55. fSYSCL = f (VDD); internal RC
Rev. A2, 26-Feb-01
55 (61)
Preliminary Information
T48C510
9000 8000 7000 fSYSCL ( kHz ) IOL ( mA) 6000 5000 4000 3000 2000 1000 0 -40
16514
VDD = 3 V
14 12
fiRC3
VDD = 3 V
10 8 6 4 2 0
fiRC2 fiRC1 fiRC0
-20
0
20 40 60 Tamb ( C )
80
100
16516
0.0
0.5
1.0
1.5 2.0 VOL ( V )
2.5
3.0
Figure 56. fSYSCL = f (Tamb)
10000 9000 8000 fSYSCL ( kHz ) 7000 6000 5000 4000 3000 2000 1000 0 -40
16515
Figure 59. Typical low output driver
35 30 25 IOL ( mA) VDD = 5 V
VDD = 5 V
fiRC3
20 15 10 5 0
fiRC2 fiRC1 fiRC0
-20
0
20 40 60 Tamb ( C )
80
100
16517
0
1
2
3 VOL ( V )
4
5
Figure 57. fSYSCL = f (Tamb)
0 VDD = 3 V -2 -4 -6 -8 -10 -12 0.0
16518
Figure 60. Typical low output driver
0 -5 -10 IOH ( mA ) -15 -20 -25 -30 -35
VDD = 5 V
IOH ( mA )
0.5
1.0 1.5 2.0 VDD-VOH ( V )
2.5
3.0
16519
0
1
2 3 VDD-VOH ( V )
4
5
Figure 58. Typical high output driver
Figure 61. Typical high output driver
56 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
4
4.1
Device Information
Pad Layout
NRST BPA1 BPA3 OSCOUT BPA0 BPA2
12 13 14 15 16 17 11 10 9 25 8 7 6 5 4 31 3 2 1 44 43 42 41 40 39 38 37 36 35 33 Mask/chip ID 32 26 24
BP13 TE BP1 BP10 1 BP12 BPC0
18 19 20 21 22 23
Die size: 2.99 x 4.30 mm Standard pad size: 96 x 96 mm Pad size (VSS): 246 x 96 mm Thickness: 480 25 mm ( 19 1 mil )
OSCIN AVDD BPC2 BPC3 BPB0 BPB1 BPB2 BPB3 BP60 BP61 SCLIN
BPC1 TIM1
T48C510
27 28 29 30
BP00 BP01 BP02 BP03 BP40 BP41 BP42 BP43 VDD
34
PM BP73
BP72 BP71
BP70 VSS
BP51 BP53 BP50 BP52
Figure 62. Pad layout Table 26 Pad coordinates Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Name SCLIN BP61 BP60 BPB3 BPB2 BPB1 BPB0 BPC3 BPC2 AVDD OSCIN OSCOUT NRST BPA0 BPA1 BPA2 BPA3 BP10 BP11 BP12 BP13 BPC0 X-Coord. 113.80 113.80 113.80 113.80 113.80 113.80 113.80 113.80 113.80 113.80 113.80 421.80 571.80 721.80 962.25 1202.70 1443.15 2659.55 2900.00 3140.45 3380.90 3621.35 Y-Coord 353.95 503.95 744.40 984.85 1225.30 1465.75 1706.20 1946.65 2187.10 2426.65 2576.65 2678.70 2678.70 2678.70 2678.70 2678.70 2678.70 2678.70 2678.70 2678.70 2678.70 2678.70 Pad No. 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name TE BPC1 TIM1 BP00 BP01 BP02 BP03 BP40 BP41 BP42 BP43 VDD BP50 BP51 BP52 BP53 VSS BP70 BP71 BP72 BP73 VSS X-Coord. 3861.80 3939.70 3939.70 3939.70 3939.70 3939.70 3939.70 3939.70 3939.70 3939.70 3939.70 3939.70 3590.95 3350.50 3110.05 2869.60 2474.15 1431.05 1190.60 950.15 709.70 469.25 Y-Coord. 2678.70 2374.60 2134.15 1744.20 1594.20 1444.20 1294.20 1144.20 903.75 663.30 422.85 147.90 146.45 146.45 146.45 146.45 146.45 146.45 146.45 146.45 146.45 146.45
Rev. A2, 26-Feb-01
57 (61)
Preliminary Information
4.2
T48C510
58 (61)
Dimensions in mm
Package SSO44
0.3
44
1
0.8 16.8
Packaging
VSS BP53 BP52 BP51 BP50 VDD BP43 BP42 BP41 BP40 BP03 BP02 BP01 BP00 Figure 63. Pin connections SSO44-package
1 2 3 4 5 6 7 8 9 10 11 12 13 14
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
BP70 BP71 BP72 BP73 VSS SCLIN BP61 [INTy] BP60 [INTx] BPB3 BPB2 BPB1 BPB0 BPC3 BPC2 AVDD OscIn OscOut NRST BPA0 BPA1 BPA2 BPA3
18.05 17.80
Preliminary Information
Rev. A2, 26-Feb-01
T48C510
22
technical drawings according to DIN specifications 13040
23
0.25 0.10 10.50 10.20 0.25
TIM1 15 BPC1 16 17 TE BPC 0 BP13 BP12 BP11 18 19 20 21 22
2.35 7.50 7.30 9.15 8.65
BP10
T48C510
5 Hardware Options
The following list shows all the T48C510 hardware options that can be programmed into the configuration EEPROM. SPD -> strong static pull-down, SPU -> strong static pull-up
Port 0 Output Standard drive BP00 CMOS Pull-up BP01 CMOS BP02 CMOS BP03 CMOS Pull-up Pull-up Pull-up
Port 5 Output BP50 BP51 BP52 BP53 -
Standard drive CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] Standard drive CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] Standard drive CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] -
Pull-up Pull-down SPU (30 kW) SPD (30 kW) Pull-up Pull-down SPU (30 kW) SPD (30 kW) Pull-up Pull-down SPU (30 kW) SPD (30 kW) Pull-up Pull-down SPU (30 kW) SPD (30 kW)
Port 1 Output BP10 BP11 BP12 BP13 Port 4 Output BP40 BP41 BP42 BP43 -
Standard drive CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] Standard drive CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] -
Pull-up Pull-down Pull-up Pull-down Pull-up Pull-down Pull-up Pull-down
Port 7 Output BP70 BP71 BP72 BP73 -
Pull-up Pull-down SPU (30 kW) SPD (30 kW) Pull-up Pull-down SPU (30 kW) SPD (30 kW) Pull-up Pull-down SPU (30 kW) SPD (30 kW) Pull-up Pull-down SPU (30 kW) SPD (30 kW)
Pull-up Pull-down SPU (30 kW) SPD (30 kW) Pull-up Pull-down SPU (30 kW) SPD (30 kW) Pull-up Pull-down SPU (30 kW) SPD (30 kW) Pull-up Pull-down SPU (30 kW) SPD (30 kW)
Port 6 Output BP60 BP61 -
Pull-up Pull-down SPU (4 kW) SPD (4 kW) Pull-up Pull-down SPU (4 kW) SPD (4 kW)
Rev. A2, 26-Feb-01
59 (61)
Preliminary Information
T48C510
Port A Output Standard BPA0 - CMOS - Open drain [N] - Open drain [P] BPA1 BPA2 BPA3 Drive - Pull-up - Pull-down - SPU (30 kW) - SPD (30 kW) Pull-up Pull-down SPU (30 kW) SPD (30 kW) Pull-up Pull-down SPU (30 kW) SPD (30 kW) Pull-up Pull-down SPU (30 kW) SPD (30 kW) Port C Output Standard BPC0 - CMOS - Open drain [N] - Open drain [P] BPC1 BPC2 BPC3 Drive - Pull-up - Pull-down - SPU (30 kW) - SPD (30 kW) Pull-up Pull-down SPU (30 kW) SPD (30 kW) Pull-up Pull-down SPU (30 kW) SPD (30 kW) Pull-up Pull-down SPU (30 kW) SPD (30 kW)
CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] -
CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] -
Port B Output Standard BPB0 - CMOS - Open drain [N] - Open drain [P] BPB1 BPB2 BPB3 -
Drive - Pull-up - Pull-down - SPU (30 kW) - SPD (30 kW) Pull-up Pull-down SPU (30 kW) SPD (30 kW) Pull-up Pull-down SPU (30 kW) SPD (30 kW) Pull-up Pull-down SPU (30 kW) SPD (30 kW)
BPA-Reset
-
CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] CMOS Open drain [N] Open drain [P] -
No - BPA0 & BPA1 = low - BPA0 & BPA1 & BPA2 = low - BPA0 & BPA1 & BPA2 & BPA3 = low - BPA0 & BPA1 = high - BPA0 & BPA1 & BPA2 = high - BPA0 & BPA1 & BPA2 & BPA3 = high
1/ 2
Watchdog
-
s
-
Disabled
1s 2s
OSCIN OSCOUT
No integrated capacitance No intergrated capacitance
TIM1 Output - Standard - Drive - CMOS - Open drain [N] -Pull-up - Open drain [P] -Pull-down
60 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
Ozone Depleting Substances Policy Statement
It is the policy of Atmel Germany GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
10.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Atmel Wireless & Microcontrollers products for any unintended or unauthorized application, the buyer shall indemnify Atmel Wireless & Microcontrollers against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.atmel-wm.com
Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
Rev. A2, 26-Feb-01
61 (61)
Preliminary Information

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