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HANBit
HMD2M32M4EAG
8Mbyte(2Mx32) EDO Mode, 1K Refresh 72Pin SIMM, 5V Design Part No. HMD2M32M4EAG
GENERAL DESCRIPTION
The HMD2M32M4EAG is a 2M x 32bit dynamic RAM high-density memory module. The module consists of four CMOS 1M x 16bit DRAMs in 42-pin SOJ packages mounted on a 72-pin, double-sided, FR-4-printed circuit board. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single In-line Memory Module with edge connections and is intended for mounting in to 72-pin edge connector sockets. All module components may be powered from a single 5V DC power supply and all inputs and outputs are TTL-compatible.
FEATURES
w Part Identification HMD2M32M4EAG : 1024 Cycles/32ms Ref . Gold w Access times : 50, 60ns w High-density 8MByte design w Single + 5V 0.5V power supply w JEDEC standard pinout w EDO mode operation w TTL compatible inputs and outputs w FR4-PCB design PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 M 15 16 17
PIN ASSIGNMENT
SYMBOL Vss DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 Vcc NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ20 DQ5 DQ21 DQ6 PIN 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SYMBOL DQ22 DQ7 DQ23 A7 A11 Vcc A8 A9 /RAS3 /RAS2 NC NC NC NC Vss /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 /RAS1 NC /WE NC PIN 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 SYMBOL DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 Vcc DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC Vss
OPTIONS
w Timing 50ns access 60ns access 70ns access w Packages 72-pin SIMM
MARKING
-50 -60 -70
PERFORMANCE RANGE
Speed 5 6 7 tRAC 50ns 60ns 70ns tCAC 15ns 15ns 15ns tRC 90ns 110ns 130ns
18 19 20 21 22 23 24
PRESENCE DETECT PINS
Pin PD1 PD2 PD3 PD4
URL:www.hbe.co.kr REV. 1.0 (August.2002)
50ns NC NC Vss Vss
60ns NC NC NC NC
70ns NC NC Vss NC
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FUNCTIONAL BLOCK DIAGRAM
DQ0-15
HMD2M32M4EAG
U2
/RAS0
/RAS
/CAS0
/LCAS 47
/CAS1
/UCAS 47 /OE
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A0-A11
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
U4
/RAS1 /RAS /CAS0 47 /CAS1 47 /OE
LCAS
/UCAS
/W
/W
A0-A11
DQ16-31
U1
/RAS2
/RAS
/CAS2
/LCAS 47
/CAS3
/UCAS 47
/OE
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 /W
U3
/RAS /RAS3 /CAS2 /LCAS 47 /CAS3 /UCAS 47 /OE
/W
A0-A11 A0-A11
/WE A0-A11
Vcc Vss
0.1 or0.22 Capacitor foreachDRAM To all DRAMs
URL:www.hbe.co.kr REV. 1.0 (August.2002)
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN ,OUT Vcc PD TSTG
HMD2M32M4EAG
RATING -1V to 7.0V -1V to 7.0V 4W -55oC to 150oC
Short Circuit Output Current IOS 50mA w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(Voltage reference to VSS, TA=0 to 70 o C ) PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage SYMBOL Vcc Vss VIH VIL MIN 4.5 0 2.4 -1.0 TYP 5.0 0 MAX 5.5 0 Vcc+1 0.8 UNIT V V V V
DC AND OPERATING CHARACTERISTICS
SYMBOL ICC1 ICC2 ICC3 -5 -6 -5 -6 SPEED -5 -6 MIN -5 -6 -20 -10 MAX 305 284 8 304 284 244 224 4 304 284 20 10 UNITS mA mA mA mA mA mA mA mA mA mA A A V V
ICC4 ICC5 ICC6 Il(L) IO(L)
VOH 2.4 VOL 0.4 ICC1 : Operating Current * (/RAS , /CAS , Address cycling @t RC=min.) ICC2 : Standby Current ( /RAS=/CAS=VIH ) ICC3 : /RAS Only Refresh Current * ( /CAS=V IH, /RAS, Address cycling @tRC=min ) ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min ) ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V ) ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min ) IIL : Input Leakage Current (Any input 0V VIN 6.5V, all other pins not under test = 0V) IOL : Output Leakage Current (Data out is disabled, 0V VOUT 5.5V VOH : Output High Voltage Level (IOH= -5mA ) VOL : Output Low Voltage Level (IOL = 4.2mA )
URL:www.hbe.co.kr REV. 1.0 (August.2002)
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HMD2M32M4EAG
* NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle.
o
CAPACITANCE ( TA=25 C, Vcc = 5V, f = 1Mz )
DESCRIPTION Input Capacitance (A0-A10) Input Capacitance (/W) Input Capacitance (/RAS0) Input Capacitance (/CAS0-/CAS3) Input/Output Capacitance (DQ0-31)
o
SYMBOL CIN1 C IN2 CIN3 CIN4 CDQ1
MIN -
MAX 44 48 40 29 29
UNITS pF pF pF pF pF
AC CHARACTERISTICS ( 0 C TA 70oC , Vcc = 5V10%, See notes 1,2.)
-5 STANDARD OPERATION Random read or write cycle time Access time from /RAS Access time from /CAS Access time from column address /CAS to output in Low-Z Output buffer turn-off delay Transition time (rise and fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS to /CAS delay time /RAS to column address delay time /CAS to /RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column Address to /RAS lead time Read command set-up time Read command hold referenced to /CAS
URL:www.hbe.co.kr REV. 1.0 (August.2002)
-6 UNIT MIN 110 50 15 25 60 17 30 3 13 50 3 2 40 10K 60 17 50 10K 37 25 10 20 15 5 0 10 0 10 30 0 0 10K 45 30 10K 15 50 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SYMBOL MIN tRC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH 3 3 2 30 50 13 40 8 20 15 5 0 10 0 8 25 0 0 90 MAX
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Read command hold referenced to /RAS Write command hold time Write command pulse width Write command to /RAS lead time Write command to /CAS lead time Data-in set-up time Data-in hold time Refresh period 2K Ref. tRRH tWCH tWP tRWL tCWL tDS tDH tREF tWCS tCSR tCHR tRPC tCPA tCP tRASP tWRP tWRH 8 50 10 10 0 5 10 5 0 10 10 13 13 0 8
HMD2M32M4EAG
0 10 10 15 15 0 10 16 0 5 10 5 30 10 200K 60 10 10 200K 35 16 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Write command set-up time /CAS setup time (C-B-R refresh) /CAS hold time (C-B-R refresh) /RAS precharge to /CAS hold time Access time from /CAS precharge /CAS precharge time (Fast page) /RAS pulse width (Fast page ) /W to /RAS precharge time (C-B-R refresh) /W to /RAS hold time (C-B-R refresh) NOTES
1.An initial pause of 200s is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 2TTL loads and 100pF 4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD
is greater than the specified tRCD(max) limit, then access time is controlled exclusively by t CAC.
5.Assumes that tRCD tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max) 7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristic only. If t WCS tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in readwrite cycles. 11. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit. then access time is controlled by tAA.
URL:www.hbe.co.kr REV. 1.0 (August.2002)
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TIMING DIAGRAMS TIMING
WAVEFORM OF READ CYCLE /RAS VIHVIL-
HMD2M32M4EAG
tRC tRAS tCRP tRCD tRAD tASR tRAH tASC tCAH
COLUMN ADDRESS
tRP
tCSH
tRSH tCAS tRAL
tCRP
VIH/CAS VIL-
VIHA
VILVIHVILVIH-
ROW ADDRESS
tRCS
/W
tRRH tAA tOEA tCAC tCLZ
tRCH
tOFF tOEZ
/OE VIL-
VOHDQ
tRAC
OPEN
VOL-
DATA-OUT
TIMING WAVEFORM OF WRITE CYCLE (EARLY WRITE)
tRC /RAS VIHVILtCSH tCRP /CAS VIHVILtASR A VIHVILtRAH tRAD tASC tCAH
COLUMN ADDRESS
tRP tRAS tCRP
tRCD
tRSH tCAS tRAL
ROW ADDRESS
tCWL tRWL tWCS tWCH tWP
VIH/W VILVIH/OE VILtDS DQ0 VOHVOLDATA-IN
tDH
NOTE : Dout = Open
URL:www.hbe.co.kr REV. 1.0 (August.2002)
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PACKAGING INFORMATION
72pin -SIMM Design
HMD2M32M4EAG
(Front view)
107.95 mm 3.38 mm R 1.57 mm 101.19 mm 3.18 mm DIA 0.51 mm
19.05 mm 10.16 mm 6.35 mm
1
2.03 mm 1.02 mm 6.35 mm 95.25 mm 6.35 mm 1.27 mm 3.17 mm
0.25 mm MAX
2.54 mm MIN
Gold : 1.040.10 mm 1.27mm Solder:0.9140.10mm
1.290.08 mm
ORDERING INFORMATION
Part Number
Density
Org.
Package
Vcc
SPEED
HMD2M32M4EAG-5 HMD2M32M4EAG-6 HMD2M32M4EAG-7
8MByte 8MByte 8MByte
2MX 32bit 2MX 32bit 2MX 32bit
72 Pin-SIMM 72 Pin-SIMM 72 Pin-SIMM
5.0V 5.0V 5.0V
50ns 60ns 70ns
URL:www.hbe.co.kr REV. 1.0 (August.2002)
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