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DECEMBER 2004
XRT73R06
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.0
GENERAL DESCRIPTION
The XRT73R06 is a six channel fully integrated Line Interface Unit (LIU) featuring EXAR's R3 Technology (Reconfigurable, Relayless, Redundancy) for E3/ DS3/STS-1 applications. The LIU incorporates 6 independent Receivers, Transmitters and Jitter Attenuators in a single 217 Lead BGA package. Each channel of the XRT73R06 can be independently configured to operate in E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1 (51.84 MHz). Each transmitter can be turned off and tri-stated for redundancy support or for conserving power. The XRT73R06's differential receiver provides high noise interference margin and is able to receive data over 1000 feet of cable or with up to 12 dB of cable attenuation.
The XRT73R06 provides a Parallel Microprocessor Interface for programming and control. The XRT73R06 supports analog, remote and digital loop-backs. The device also has a built-in Pseudo Random Binary Sequence (PRBS) generator and detector with the ability to insert and detect single bit error for diagnostic purposes.
APPLICATIONS * E3/DS3 Access Equipment * DSLAMs * Digital Cross Connect Systems * CSU/DSU Equipment * Routers * Fiber Optic Terminals
FIGURE 1. BLOCK DIAGRAM OF THE XRT 73R06
CS RD WR Addr[7:0] D[7:0] PCLK RDY INT Pmode RESET
XRT73R06 XRT73R06
Processor Interface
CLKOUT_n SFM_en RLOL_n E3Clk DS3Clk STS-Clk/12M RxClk_n RxPOS_n RxNEG/LCV_n
Peak Detector AGC/ Equalizer Slicer Clock & Data Recovery LOS Detector
Clock Synthesizer HDB3/ B3ZS Decoder
RTIP_n RRing_n
MUX
Local LoopBack
Remote LoopBack RLOS_n TxClk_n TxPOS_n TxNEG_n
TTIP_n TRing_n MTIP_n MRing_n DMO_n ICT
Line Driver
Tx Pulse Shaping Tx Control
Timing Control
MUX
HDB3/ B3ZS Encoder
Device Monitor
TxON Channel 0 Channel n... Channel 5
ORDERING INFORMATION
PART NUMBER XRT73R06IB PACKAGE 217 Lead BGA OPERATING TEMPERATURE RANGE -40C to +85C
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRT73R06
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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FEATURES
RECEIVER
* - 40C to 85C Industrial Temperature Range
TRANSMIT INTERFACE CHARACTERISTICS (Reconfigurable, Relayless,
* R3
Technology Redundancy) input jitter tolerance
* Accepts either Single-Rail or Dual-Rail data from
Terminal Equipment and generates a bipolar signal to the line
* On chip Clock and Data Recovery circuit for high * Meets E3/DS3/STS-1 Jitter Tolerance Requirement * Detects and Clears LOS as per G.775 * Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation
* Integrated Pulse Shaping Circuit * Built-in B3ZS/HDB3 Encoder (which can be
disabled)
* Accepts Transmit Clock with duty cycle of 30%70%
* On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled
* Generates pulses that comply with the ITU-T G.703
pulse template for E3 applications
* On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock
* Generates pulses that comply with the DSX-3 pulse
template, as specified in Bellcore GR-499-CORE and ANSI T1.102_1993
* Provides low jitter output clock
TRANSMITTER
* Generates pulses that comply with the STSX-1
Relayless, pulse template, as specified in Bellcore GR-253CORE
*R
Technology Redundancy)
3
(Reconfigurable,
* Transmitter can be turned off in order to support
redundancy designs RECEIVE INTERFACE CHARACTERISTICS
* Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
* Tri-state Transmit output capability for redundancy
applications
* Integrated Adaptive Receive Equalization (optional)
for optimal Clock and Data Recovery
* Each Transmitter can be independently turned on
or off
* Declares and Clears the LOS defect per ITU-T
G.775 requirements for E3 and DS3 applications
* Transmitters provide Voltage Output Drive
CONTROL AND DIAGNOSTICS
* Meets Jitter Tolerance Requirements, as specified
in ITU-T G.823_1993 for E3 Applications
* Parallel Microprocessor Interface for control and
configuration
* Meets Jitter Tolerance Requirements, as specified
in Bellcore GR-499-CORE for DS3 Applications
* Supports
monitoring
optional
internal
Transmit
driver
* Each channel supports Analog, Remote and Digital
Loop-backs
* Declares Loss of Lock (LOL) Alarm * Built-in B3ZS/HDB3 Decoder (which can be
disabled)
* Single 3.3 V 5% power supply * 5 V Tolerant digital inputs * Available in 217 pin BGA Package
* Recovered Data can be muted while the LOS
Condition is declared
* Outputs either Single-Rail or Dual-Rail data to the
Terminal Equipment
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT FIGURE 2. XRT73R06 IN BGA PACKAGE (BOTTOM VIEW)
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XRT73R06
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(See pin list for pin names and function)
A B C D E F G H J K L
XRT73R06
M N P R T U
17
16
15
14
12
12
11
10
9
8
7
6
5
4
3
2
1
3
XRT73R06
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
APPLICATIONS .............................................................................................................................................. Figure 1. Block Diagram of the XRT 73R06 ...................................................................................................... ORDERING INFORMATION ................................................................................................................... 1 FEATURES .................................................................................................................................................... TRANSMIT INTERFACE CHARACTERISTICS ...................................................................................................... RECEIVE INTERFACE CHARACTERISTICS ........................................................................................................ Figure 2. XRT73R06 in BGA package (Bottom View) ....................................................................................... TABLE OF CONTENTS ................................................................................................................................... 1 1 2 2 2 3 1
PIN DESCRIPTIONS (BY FUNCTION) ............................................................................. 4
TRANSMIT INTERFACE ................................................................................................................................... 4 RECEIVE INTERFACE ..................................................................................................................................... 6 CLOCK INTERFACE ........................................................................................................................................ 8 CONTROL AND ALARM INTERFACE ....................................................................................................... 9 ANALOG POWER AND GROUND ................................................................................................................... 12 DIGITAL POWER AND GROUND ..................................................................................................................... 14
FUNCTIONAL DESCRIPTION ......................................................................................... 16
1.0 R3 Technology (reconfigurable, relayless redundancy) ............................................................... 16
1.1 NETWORK ARCHITECTURE ................................................................................................................................ 16
Figure 3. Network Redundancy Architecture ................................................................................................. 16 2.0 clock Synthesizer ............................................................................................................................. 17
2.1 CLOCK DISTRIBUTION ....................................................................................................................................... 17
Figure 5. Clock Distribution Congifured in E3 Mode Without Using SFM ....................................................... Figure 4. Simplified Block Diagram of the Input Clock Circuitry Driving the Microprocessor .......................... 3.0 The Transmitter Section .................................................................................................................. Figure 6. Transmit Path Block Diagram ..........................................................................................................
17 17 19 19
3.1 TRANSMIT DIGITAL INPUT INTERFACE ................................................................................................................ 19
Figure 7. Typical interface between terminal equipment and the XRT73R06 (dual-rail data) ......................... 19 Figure 8. Transmitter Terminal Input Timing ................................................................................................... 20 Figure 9. Single-Rail or NRZ Data Format (Encoder and Decoder are Enabled) ........................................... 20
3.2 TRANSMIT CLOCK ............................................................................................................................................ 3.3 B3ZS/HDB3 ENCODER .................................................................................................................................... 3.3.1 B3ZS Encoding ................................................................................................................................... 3.3.2 HDB3 Encoding .................................................................................................................................. 21 21 21 21
Figure 10. Dual-Rail Data Format (encoder and decoder are disabled) ......................................................... 21 Figure 11. B3ZS Encoding Format ................................................................................................................. 21
3.4 TRANSMIT PULSE SHAPER ................................................................................................................................ 22
Figure 13. Transmit Pulse Shape Test Circuit ................................................................................................ 22
3.4.1 Guidelines for using Transmit Build Out Circuit ............................................................................. 22
Figure 12. HDB3 Encoding Format ................................................................................................................. 22
3.5 E3 LINE SIDE PARAMETERS ............................................................................................................................... 23
Figure 14. Pulse Mask for E3 (34.368 mbits/s) interface as per itu-t G.703 ................................................... TABLE 1: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS ........................... Figure 15. Bellcore GR-253 CORE Transmit Output Pulse Template for SONET STS-1 Applications .......... TABLE 2: STS-1 PULSE MASK EQUATIONS ........................................................................................................ TABLE 3: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253) . Figure 16. Transmit Ouput Pulse Template for DS3 as per Bellcore GR-499 ................................................ TABLE 5: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) ..... TABLE 4: DS3 PULSE MASK EQUATIONS ...........................................................................................................
23 24 25 25 26 26 27 27
3.6 TRANSMIT DRIVE MONITOR ............................................................................................................................... 28 3.7 TRANSMITTER SECTION ON/OFF ....................................................................................................................... 28
Figure 17. Transmit Driver Monitor set-up. ..................................................................................................... 28 4.0 The Receiver Section ....................................................................................................................... 30
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Figure 18. Receive Path Block Diagram ......................................................................................................... 30
4.1 RECEIVE LINE INTERFACE ................................................................................................................................ 30
Figure 19. Receive Line InterfaceConnection ................................................................................................ 30
4.2 ADAPTIVE GAIN CONTROL (AGC) .................................................................................................................... 31 4.3 RECEIVE EQUALIZER ........................................................................................................................................ 31
Figure 20. ACG/Equalizer Block Diagram ...................................................................................................... 31
4.3.1 Recommendations for Equalizer Settings ....................................................................................... 4.4 CLOCK AND DATA RECOVERY .......................................................................................................................... 4.4.1 Data/Clock Recovery Mode ............................................................................................................... 4.4.2 Training Mode .................................................................................................................................... 4.5 LOS (LOSS OF SIGNAL) DETECTOR .................................................................................................................. 4.5.1 DS3/STS-1 LOS Condition ................................................................................................................. 4.5.2 Disabling ALOS/DLOS Detection ...................................................................................................... 31 31 31 31 32 32 32
TABLE 6: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS) ................................................................... 32
4.5.3 E3 LOS Condition: ............................................................................................................................. 33
Figure 21. Loss Of Signal Definition for E3 as per ITU-T G.775 .................................................................... 33 Figure 22. Loss of Signal Definition for E3 as per ITU-T G.775. .................................................................... 33
4.5.4 Interference Tolerance ...................................................................................................................... 34
Figure 23. Interference Margin Test Set up for DS3/STS-1 ........................................................................... 34 Figure 24. Interference Margin Test Set up for E3. ........................................................................................ 34 TABLE 7: INTERFERENCE MARGIN TEST RESULTS .............................................................................................. 35
4.5.5 Muting the Recovered Data with LOS condition: ............................................................................ 36 4.6 B3ZS/HDB3 DECODER ................................................................................................................................... 36
Figure 25. Receiver Data output and code violation timing ............................................................................ 36 5.0 Jitter .................................................................................................................................................. 37
5.1 JITTER TOLERANCE .......................................................................................................................................... 37 5.1.1 DS3/STS-1 Jitter Tolerance Requirements ...................................................................................... 37
Figure 26. Jitter Tolerance Measurements ..................................................................................................... 37
5.1.2 E3 Jitter Tolerance Requirements .................................................................................................... 38
Figure 27. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 38 Figure 28. Input Jitter Tolerance for E3 ......................................................................................................... 38
5.2 JITTER TRANSFER ............................................................................................................................................ 39
TABLE 8: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) ....................................... 39 TABLE 9: JITTER TRANSFER SPECIFICATION/REFERENCES ................................................................................. 39 TABLE 10: JITTER TRANSFER PASS MASKS ....................................................................................................... 39
5.2.1 Jitter Generation ................................................................................................................................ 40
Figure 29. Jitter Transfer Requirements and Jitter Attenuator Performance .................................................. 40 6.0 Diagnostic Features ......................................................................................................................... 41
6.1 PRBS GENERATOR AND DETECTOR ................................................................................................................. 41
Figure 30. PRBS MODE ................................................................................................................................. 41
6.2 LOOPBACKS ................................................................................................................................................ 42 6.2.1 ANALOG LOOPBACK ........................................................................................................................ 42
Figure 31. Analog Loopback ........................................................................................................................... 42
6.2.2 DIGITAL LOOPBACK ......................................................................................................................... 43 6.2.3 REMOTE LOOPBACK ........................................................................................................................ 43
Figure 32. Digital Loopback ............................................................................................................................ 43 Figure 33. Remote Loopback ......................................................................................................................... 43
6.3 TRANSMIT ALL ONES (TAOS) .................................................................................................................... 44
Figure 34. Transmit All Ones (TAOS) ............................................................................................................. 7.0 Microprocessor interface Block ..................................................................................................... TABLE 11: SELECTING THE MICROPROCESSOR INTERFACE MODE ...................................................................... Figure 35. Simplified Block Diagram of the Microprocessor Interface Block ..................................................
44 46 46 46
7.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ........................................................................................ 47
TABLE 12: XRT73R06 MICROPROCESSOR INTERFACE SIGNALS ........................................................................ 47
7.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION ......................................................................................... 48
TABLE 13: ASYNCHRONOUS TIMING SPECIFICATIONS ......................................................................................... 49
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49 50 50 51 52 53 53 55 60 60 60
Figure 36. Asynchronous P Interface Signals During Programmed I/O Read and Write Operations ........... Figure 37. Synchronous P Interface Signals During Programmed I/O Read and Write Operations ............. TABLE 14: SYNCHRONOUS TIMING SPECIFICATIONS ........................................................................................... Figure 38. Interrupt process ............................................................................................................................ TABLE 15: REGISTER MAP AND BIT NAMES ........................................................................................................ TABLE 16: REGISTER MAP DESCRIPTION - GLOBAL ............................................................................................ TABLE 17: REGISTER MAP AND BIT NAMES - CHANNEL N REGISTERS (N = 0,1,2,3,4,5) ...................................... TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N ....................................................................................... 8.0 ELECTRICAL CHARACTERISTICS ................................................................................................. TABLE 19: ABSOLUTE MAXIMUM RATINGS .......................................................................................................... TABLE 20: DC ELECTRICAL CHARACTERISTICS: .................................................................................................
7.2.1 Hardware Reset: ................................................................................................................................. 52
APPENDIX A .................................................................................................................... 62
TABLE 21: TRANSFORMER RECOMMENDATIONS ..................................................................................... 62 TABLE 22: TRANSFORMER DETAILS ................................................................................................................... 62 ORDERING INFORMATION ................................................................................................................. 64 PACKAGE DIMENSIONS - 23 X 23 MM 217 LEAD BGA PACKAGE .................................................................. 64
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PIN DESCRIPTIONS (BY FUNCTION)
TRANSMIT INTERFACE
LEAD # T15 R16 R15 N14 P14 P13 SIGNAL NAME TxON_0 TxON_1 TxON_2 TxON_3 TxON_4 TxON_5 TYPE I DESCRIPTION
Transmitter ON Input - Channel 0: Transmitter ON Input - Channel 1: Transmitter ON Input - Channel 2: Transmitter ON Input - Channel 3: Transmitter ON Input - Channel 4: Transmitter ON Input - Channel 5:
These pins are active only when the corresponding TxON bits are set. Table below shows the status of the transmitter based on theTxON bit and TxON pin settings. Bit 0 0 1 1 Pin 0 1 0 1 Transmitter Status OFF OFF OFF ON
NOTES: 1. These pins will be active and can control the TTIP and TRING outputs only when the TxON_n bits in the channel register are set . 2. When Transmitters are turned off the TTIP and TRING outputs are Tristated. 3. These pins are internally pulled up.
E3 M3 F15 P16 G3 H15 TxCLK_0 TxCLK_1 TxCLK_2 TxCLK_3 TxCLK_4 TxCLK_5 I
Transmit Clock Input for TPOS and TNEG - Channel 0: Transmit Clock Input for TPOS and TNEG - Channel 1: Transmit Clock Input for TPOS and TNEG - Channel 2: Transmit Clock Input for TPOS and TNEG - Channel 3: Transmit Clock Input for TPOS and TNEG - Channel 4: Transmit Clock Input for TPOS and TNEG - Channel 5:
The frequency accuracy of this input clock must be of nominal bit rate 20 ppm. The duty cycle can be 30%-70%. By default, input data is sampled on the falling edge of TxCLK.
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TRANSMIT INTERFACE
LEAD # F2 P2 G15 R17 H3 K15 SIGNAL NAME TNEG_0 TNEG_1 TNEG_2 TNEG_3 TNEG_4 TNEG_5 TYPE I DESCRIPTION
Transmit Negative Data Input - Channel 0: Transmit Negative Data Input - Channel 1: Transmit Negative Data Input - Channel 2: Transmit Negative Data Input - Channel 3: Transmit Negative Data Input - Channel 4: Transmit Negative Data Input - Channel 5:
In Dual-rail mode, these pins are sampled on the falling or rising edge of TxCLK_n . NOTES:
1. These input pins are ignored and must be grounded if the Transmitter Section is configured to accept Single-Rail data from the Terminal Equipment.
F3 N3 F16 P15 G2 J15 TPOS_0 TPOS_1 TPOS_2 TPOS_3 TPOS_4 TPOS_5 I
Transmit Positive Data Input - Channel 0: Transmit Positive Data Input - Channel 1: Transmit Positive Data Input - Channel 2: Transmit Positive Data Input - Channel 3: Transmit Positive Data Input - Channel 4: Transmit Positive Data Input - Channel 5:
By default sampled on the falling edge of TxCLK.
D1 N1 D17 N17 H1 H17
TTIP_0 TTIP_1 TTIP_2 TTIP_3 TTIP_4 TTIP_5
O
Transmit TTIP Output - Channel 0: Transmit TTIP Output - Channel 1: Transmit TTIP Output - Channel 2: Transmit TTIP Output - Channel 3: Transmit TTIP Output - Channel 4: Transmit TTIP Output - Channel 5:
These pins along with TRING transmit bipolar signals to the line using a 1:1 transformer.
E1 M1 E17 M17 J1 J17
TRING_0 TRING_1 TRING_2 TRING_3 TRING_4 TRING_5
O
Transmit Ring Output - Channel 0: Transmit Ring Output - Channel 1: Transmit Ring Output - Channel 2: Transmit Ring Output - Channel 3: Transmit Ring Output - Channel 4: Transmit Ring Output - Channel 5:
These pins along with TTIP transmit bipolar signals to the line using a 1:1 transformer.
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT RECEIVE INTERFACE
LEAD # A2 U2 A17 U17 D8 P8 SIGNAL NAME RxCLK_0 RXCLK_1 RxCLK_2 RxCLK_3 RxCLK_4 RxCLK_5 TYPE O DESCRIPTION
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Receive Clock Output - Channel 0: Receive Clock Output - Channel 1: Receive Clock Output - Channel 2: Receive Clock Output - Channel 3: Receive Clock Output - Channel 4: Receive Clock Output - Channel 5: By default, RPOS and RNEG data sampled on the rising edge RxCLK.. Set the RxCLKINV bit to sample RPOS/RNEG data on the falling edge of RxCLK
A1 U1 A16 U16 D9 P9
RPOS_0 RPOS_1 RPOS_2 RPOS_3 RPOS_4 RPOS_5
O
Receive Positive Data Output - Channel 0: Receive Positive Data Output - Channel 1: Receive Positive Data Output - Channel 2: Receive Positive Data Output - Channel 3: Receive Positive Data Output - Channel 4: Receive Positive Data Output - Channel 5:
NOTE: If the B3ZS/HDB3 Decoder is enabled in Single-rail mode, then the zero suppression patterns in the incoming line signal (such as: "00V", "000V", "B0V", "B00V") are removed and replaced with `0'.
B2 T2 B16 T16 D10 P10
RNEG_0/ LCV_0 RNEG_1/ LCV_1 RNEG_2/ LCV_2 RNEG_3/ LCV_3 RNEG_4/ LCV_4 RNEG_5/ LCV_5
O
Receive Negative Data Output/Line Code Violation Indicator - Channel 0: Receive Negative Data Output/Line Code Violation Indicator - Channel 1: Receive Negative Data Output/Line Code Violation Indicator - Channel 2: Receive Negative Data Output/Line Code Violation Indicator - Channel 3: Receive Negative Data Output/Line Code Violation Indicator - Channel 4: Receive Negative Data Output/Line Code Violation Indicator - Channel 5:
In Dual Rail mode, a negative pulse is output through RNEG.
Line Code Violation Indicator - Channel n:
If configured in Single Rail mode then Line Code Violation will be output.
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RECEIVE INTERFACE
LEAD # A5 U5 A14 U14 A9 U9 SIGNAL NAME RRING_0 RRING_1 RRING_2 RRING_3 RRING_4 RRING_5 TYPE I DESCRIPTION
Receive Input - Channel 0: Receive Input - Channel 1: Receive Input - Channel 2: Receive Input - Channel 3: Receive Input - Channel 4: Receive Input - Channel 5:
These pins along with RTIP receive the bipolar line signal from the remote DS3/ E3/STS-1 Terminal.
A6 U6 A13 U13 A10 U10
RTIP_0 RTIP_1 RTIP_2 RTIP_3 RTIP_4 RTIP_5
I
Receive Input - Channel 0: Receive Input - Channel 1: Receive Input - Channel 2: Receive Input - Channel 3: Receive Input - Channel 4: Receive Input - Channel 5:
These pins along with RRING receive the bipolar line signal from the Remote DS3/E3/STS-1 Terminal.
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT CLOCK INTERFACE
LEAD # E15 SIGNAL NAME E3CLK TYPE I DESCRIPTION E3 Clock Input (34.368 MHz 20 ppm):
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If any of the channels is configured in E3 mode, a reference clock 34.368 MHz is applied on this pin.
NOTE: In single frequency mode, this reference clock is not required.
G16 DS3CLK I DS3 Clock Input (44.736 MHz 20 ppm): If any of the channels is configured in DS3 mode, a reference clock 44.736 MHz. is applied on this pin.
NOTE: In single frequency mode, this reference clock is not required.
C16 STS-1CLK/ 12M I STS-1 Clock Input (51.84 MHz 20 ppm): If any of the channels is configured in STS-1 mode, a reference clock 51.84 MHz is applied on this pin.. In Single Frequency Mode, a reference clock of 12.288 MHz 20 ppm is connected to this pin and the internal clock synthesizer generates the appropriate clock frequencies based on the configuration of the channels in E3, DS3 or STS-1 modes. L15 SFM_EN I Single Frequency Mode Enable: Tie this pin "High" to enable the Single Frequency Mode. A reference clock of 12.288 MHz 20 ppm is applied. In the Single Frequency Mode (SFM) a low jitter output clock is provided for each channel if the CLK_EN bit is set thus eliminating the need for a separate clock source for the framer. Tie this pin "Low" if single frequency mode is not selected. In this case, the appropriate reference clocks must be provided.
NOTE:
B1 T1 B17 T17 D11 P11 CLKOUT_0 CLKOUT_1 CLKOUT_2 CLKOUT_3 CLKOUT_4 CLKOUT_5 O
This pin is internally pulled down
Clock output for channel 0 Clock output for channel 1 Clock output for channel 2 Clock output for channel 3 Clock output for channel 4 Clock output for channel 5 Low jitter clock output for each channel based on the mode selection (E3,DS3 or STS-1) if the CLKOUTEN_n bit is set in the control register. This eliminates the need for a separate clock source for the framer.
NOTES: 1. The maximum drive capability for the clockouts is 16 mA. 2. This clock out is available both in SFM and non-SFM modes.
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CONTROL AND ALARM INTERFACE
LEAD # B7 R6 C14 R14 C6 D14 SIGNAL NAME TYPE MRING_0 MRING_1 MRING_2 MRING_3 MRING_4 MRING_5 I DESCRIPTION
Monitor Ring Input - Channel 0: Monitor Ring Input - Channel 1: Monitor Ring Input - Channel 2: Monitor Ring Input - Channel 3: Monitor Ring Input - Channel 4: Monitor Ring Input - Channel 5:
The bipolar line output signal from TRING_n is connected to this pin via a 270 resistor to check for line driver failure.
NOTE: This pin is internally pulled up.
B8 R7 C13 R13 C7 D13 MTIP_0 MTIP_1 MTIP_2 MTIP_3 MTIP_4 MTIP_5 I
Monitor Tip Input - Channel 0: Monitor Tip Input - Channel 1: Monitor Tip Input - Channel 2: Monitor Tip Input - Channel 3: Monitor Tip Input - Channel 4: Monitor Tip Input - Channel 5:
The bipolar line output signal from TTIP_n is connected to this pin via a 270ohm resistor to check for line driver failure.
NOTE: This pin is internally pulled up.
C5 T4 B12 T12 D5 B15 DMO_0 DMO_1 DMO_2 DMO_3 DMO_4 DMO_5 O
Drive Monitor Output - Channel 0: Drive Monitor Output - Channel 1: Drive Monitor Output - Channel 2: Drive Monitor Output - Channel 3: Drive Monitor Output - Channel 4: Drive Monitor Output - Channel 5:
If MTIP_n and MRING_n has no transition pulse for 128 32 TxCLK_n cycles, DMO_n goes "High" to indicate the driver failure. DMO_n output stays "High" until the next AMI signal is detected.
C8 T7 C12 T11 B11 R8
RLOS_0 RLOS_1 RLOS_2 RLOS_3 RLOS_4 RLOS_5
O
Receive Loss of Signal - Channel 0: Receive Loss of Signal - Channel 1: Receive Loss of Signal - Channel 2: Receive Loss of Signal - Channel 3: Receive Loss of Signal - Channel 4: Receive Loss of Signal - Channel 5:
This output pin toggles "High" if the receiver has detected a Loss of Signal Condition.
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT CONTROL AND ALARM INTERFACE
C9 T8 D12 R11 C11 R9 RLOL_0 RLOL_1 RLOL_2 RLOL_3 RLOL_4 RLOL_5 O
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Receive Loss of Lock - Channel 0: Receive Loss of Lock - Channel 1: Receive Loss of Lock - Channel 2: Receive Loss of Lock - Channel 3: Receive Loss of Lock - Channel 4: Receive Loss of Lock - Channel 5:
This output pin toggles "High" if a Loss of Lock Condition is detected. LOL (Loss of Lock) condition occurs if the recovered clock frequency deviates from the Reference Clock frequency (available at either E3CLK or DS3CLK or STS1CLK input pins) by more than 0.5%.
L16
RXA
****
External Resistor of 3.01K 1%. Should be connected between RxA and RxB for internal bias. External Resistor of 3.01K 1%. Should be connected between RxA and RxB for internal bias.
K16
RXB
****
P12
ICT
I
In-Circuit Test Input:
Setting this pin "Low" causes all digital and analog outputs to go into a highimpedance state to allow for in-circuit testing. For normal operation, tie this pin "High".
NOTE: This pin is internally pulled up.
R12 TEST **** Factory Test Pin
NOTE: This pin must be connected to GND for normal operation.
MICROPROCESSOR INTERFACE
LEAD # K3 SIGNAL NAME CS TYPE I DESCRIPTION Chip Select Tie this "Low" to enable the communication with the Microprocessor Interface. Processor Clock Input To operate the Microprocessor Interface, appropriate clock frequency is provided through this pin. Maximum frequency is 66 Mhz. Write Data : To write data into the registers, this active low signal is asserted. Read Data: To read data from the registers, this active low pin is asserted.
R1
PCLK
I
K2
WR
I
L2
RD
I
J3
RESET
I
Register Reset:
Setting this input pin "Low" resets the contents of the Command Registers to their default settings and default operating configuration
NOTE: This pin is internally pulled up.
L3 PMODE I Processor Mode Select: When this pin is tied "High", the microprocessor is operating in synchronous mode which means that clock must be applied to the PCLK (pin 55). Tie this pin "Low" to select the Asynchronous mode. An internal clock is provided for the microprocessor interface.
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MICROPROCESSOR INTERFACE
LEAD # T3 SIGNAL NAME RDY TYPE O Ready Acknowledge: DESCRIPTION
NOTE: This pin must be connected to VDD via 3 k 1% resistor.
U3 INT O INTERRUPT Output: A transition to "Low" indicates that an interrupt has been generated. The interrupt function can be disabled by clearing the interrupt enable bit in the Channel Control Register.
NOTES: 1. This pin will remain asserted "Low" until the interrupt is serviced. 2. This pin must be conneced to VDD via 3 k 1% resistor.
B4 A3 B3 C4 C3 C2 D3 D4 N4 P3 P4 P5 R5 R4 R3 R2 ADDR[0] ADDR[1] ADDR[2] ADDR[3] ADDR[4] ADDR[5] ADDR[6] ADDR[7] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] I ADDRESS BUS: 8 bit address bus for the microprocessor interface
I/O
DATA BUS: 8 bit Data Bus for the microprocessor interface
11
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT ANALOG POWER AND GROUND
LEAD # E2 N2 E16 N16 J2 J16 D2 M2 D16 M16 H2 H16 A4 U4 A15 U15 A8 U8 A7 U7 A12 U12 A11 U11 E4 K4 E14 K14 G4 G14 F4 SIGNAL NAME TxAVDD_0 TxAVDD_1 TxAVDD_2 TxAVDD_3 TxAVDD_4 TxAVDD_5 TxAGND_0 TxAGND_1 TxAGND_2 TxAGND_3 TxAGND_4 TxAGND_5 RxAVDD_0 RxAVDD_1 RxAVDD_2 RxAVDD_3 RxAVDD_4 RxAVDD_5 RxAGND_0 RxAGND_1 RxAGND_2 RxAGND_3 RxAGND_4 RxAGND_5 JaAVDD_0 JaAVDD_1 JaAVDD_2 JaAVDD_3 JaAVDD_4 JaAVDD_5 JaAGND_0 TYPE **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** DESCRIPTION
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XRT73R06
REV. 1.0.0
Transmitter Analog 3.3 V 5% VDD - Channel 0 Transmitter Analog 3.3 V 5% VDD - Channel 1 Transmitter Analog 3.3 V 5% VDD - Channel 2 Transmitter Analog 3.3 V 5% VDD - Channel 3 Transmitter Analog 3.3 V 5% VDD - Channel 4 Transmitter Analog 3.3 V 5% VDD - Channel 5 Transmitter Analog GND - Channel 0 Transmitter Analog GND - Channel 1 Transmitter Analog GND - Channel 2 Transmitter Analog GND - Channel 3 Transmitter Analog GND - Channel 4 Transmitter Analog GND - Channel 5 Receiver Analog 3.3 V 5% VDD - Channel 0 Receiver Analog 3.3 V 5% VDD - Channel 1 Receiver Analog 3.3 V 5% VDD - Channel 2 Receiver Analog 3.3 V 5% VDD - Channel 3 Receiver Analog 3.3 V 5% VDD - Channel 4 Receiver Analog 3.3 V 5% VDD - Channel 5 Receiver Analog GND - Channel_0 Receive Analog GND - Channel 1 Receive Analog GND - Channel 2 Receive Analog GND - Channel 3 Receive Analog GND - Channel 4 Receive Analog GND - Channel 5 Analog 3.3 V 5% VDD - Jitter Attenuator Channel 0 Analog 3.3 V 5% VDD - Jitter Attenuator Channel 1 Analog 3.3 V 5% VDD - Jitter Attenuator Channel 2 Analog 3.3 V 5% VDD - Jitter Attenuator Channel 3 Analog 3.3 V 5% VDD - Jitter Attenuator Channel 4 Analog 3.3 V 5% VDD - Jitter attenuator Channel 5
Analog GND - Jitter Attenuator Channel 0
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XRT73R06
REV. 1.0.0
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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ANALOG POWER AND GROUND
LEAD # J4 F14 J14 H4 H14 C10 R10 H9 J9 K9 N15 M15 SIGNAL NAME JaAGND_1 JaAGND_2 JaAGND_3 JaAGND_4 JaAGND_5 AGND AGND AGND AGND AGND REFAVDD REFGND TYPE **** **** **** **** **** **** **** **** **** **** **** **** DESCRIPTION Analog GND - Jitter Attenuator Channel 1 Analog GND - Jitter Attenuator Channel 2 Analog GND - Jitter Attenuator Channel 3 Analog GND - Jitter Attenuator Channel 4 Analog GND - Jitter Attenuator Channel 5 Analog GND Analog GND Analog GND Analog GND Analog GND Analog 3.3 V 5% VDD - Reference Reference GND
13
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT DIGITAL POWER AND GROUND
LEAD # F1 L1 F17 L17 K1 K17 C1 P1 C17 P17 G1 G17 B5 T5 B14 T14 B9 T9 B6 T6 B13 T13 B10 T10 P6 C15 L4 D6 L14 D15 D7 SIGNAL NAME TxVDD_0 TxVDD_1 TxVDD_2 TxVDD_3 TxVDD_4 TxVDD_5 TxGND_0 TxGND_1 TxGND_2 TxGND_3 TxGND_4 TxGND_5 RxDVDD_0 RxDVDD_1 RxDVDD_2 RxDVDD_3 RxDVDD_4 RxDVDD_5 RxDGND_0 RxDGND_1 RxDGND_2 RxDGND_3 RxDGND_4 RxDGND_5 DVDD_1 DVDD_2 JaDVDD_1 DVDD(uP) JaDVDD_2 DGND_1 DGND(uP) TYPE **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** **** DESCRIPTION
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XRT73R06
REV. 1.0.0
Transmitter 3.3 V 5% VDD Channel 0 Transmitter 3.3 V 5% VDD Channel 1 Transmitter 3.3 V 5% VDD Channel 2 Transmitter 3.3 V 5% VDD Channel 3 Transmitter 3.3 V 5% VDD Channel 4 Transmitter 3.3 V 5% VDD Channel 5 Transmitter GND - Channel 0 Transmitter GND - Channel 1 Transmitter GND - Channel 2 Transmitter GND - Channel 3 Transmitter GND - Channel 4 Transmitter GND - Channel 5
Receiver 3.3 V 5% VDD - Channel 0 Receiver 3.3 V 5% VDD - Channel 1 Receiver 3.3 V 5% VDD - Channel 2 Receiver 3.3 V 5% VDD - Channel 3 Receiver 3.3 V 5% VDD - Channel 4 Receiver 3.3 V 5% VDD - Channel 5
Receiver Digital GND - Channel 0 Receiver Digital GND - Channel 1 Receiver Digital GND - Channel 2 Receiver Digital GND - Channel 3 Receiver Digital GND - Channel 4 Receiver Digital GND - Channel 5 VDD 3.3 V 5% VDD 3.3 V 5% VDD 3.3 V 5%
VDD 3.3 V 5% VDD 3.3 V 5% Digital GND Digital GND
14
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REV. 1.0.0
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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DIGITAL POWER AND GROUND
LEAD # M14 M4 P7 H8 J8 K8 H10 J10 K10 SIGNAL NAME JaDGND_2 JaDGND_1 DGND DGND DGND DGND DGND DGND DGND TYPE **** **** **** **** **** **** **** **** **** Digital GND Digital GND Digital GND Digital GND Digital GND Digital GND Digital GND Digital GND Digital GND DESCRIPTION
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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XRT73R06
REV. 1.0.0
FUNCTIONAL DESCRIPTION
The XRT73R06 is a six channel fully integrated Line Interface Unit featuring EXAR's R3 Technology (Reconfigurable, Relayless Redundancy) for E3/DS3/STS-1 applications. The LIU incorporates 6 independent Receivers, Transmitters and Jitter Attenuators in a single 217 Lead BGA package. Each channel can be independently programmed to support E3, DS-3 or STS-1 line rates using one input clock reference of 12.288MHz in Single Frequency Mode (SFM). The LIU is responsible for providing the physical connection between a line interface and an aggregate mapper or framing device. Along with the analog-to-digital processing, the LIU offers monitoring and diagnostic features to help optimize network design implementation. A key characteristic within the network topology is Automatic Protection Switching (APS). EXAR's proven expertise in providing redundany solutions has paved the way for R3 Technology. 1.0 R3 TECHNOLOGY (RECONFIGURABLE, RELAYLESS REDUNDANCY) Redundancy is used to introduce reliability and protection into network card design. The redundant card in many cases is an exact replicate of the primary card, such that when a failure occurs the network processor can automatically switch to the backup card. EXAR's R3 technology has re-defined E3/DS-3/STS-1 LIU design for 1:1 and 1+1 redundancy applications. Without relays and one Bill of Materials, EXAR offers multi-port, integrated LIU solutions to assist high density aggregate applications and framing requirements with reliability. The following section can be used as a reference for implementing R3 Technology with EXAR's world leading line interface units. 1.1 Network Architecture A common network design that supports 1:1 or 1+1 redundancy consists of N primary cards along with N backup cards that connect into a mid-plane or back-plane architecture without transformers installed on the network cards. In addition to the network cards, the design has a line interface card with one source of transformers, connectors, and protection components that are common to both network cards. With this design, the bill of materials is reduced to the fewest amount of components. See Figure 3. for a simplified block diagram of a typical redundancy design. FIGURE 3. NETWORK REDUNDANCY ARCHITECTURE
GND 37.5 0.01F Rx 0.01F 31.6 31.6 37.5
1:1
Framer/ Mapper
LIU
Tx
1:1
Primary Line Card
Line Interface Card
0.01F Rx 0.01F 31.6 31.6
Framer/ Mapper
LIU
Tx
Redundant Line Card Back Plane or Mid Plane
16
XRT73R06
REV. 1.0.0
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ac
2.0 CLOCK SYNTHESIZER The LIU uses a flexible user interface for accepting clock references to generate the internal master clocks used to drive the LIU. The reference clock used to supply the microprocessor timing is generated from the DS3 or SFM clock input. Therefore, if the chip is configured for STS-1 only or E3 only, then the DS-3 input pin must be connected to the STS-1 pin or E3 pin respectively. In DS-3 mode or when SFM is used, the STS-1 and E3 input pins can be left unconnected. If SFM is enabled by pulling the SFM_EN pin "High", 12.288MHz is the only clock reference necessary to generate DS-3, E3, or STS-1 line rates and the microprocessor timing. A simplified block diagram of the clock synthesizer is shown in Figure 4 FIGURE 4. SIMPLIFIED BLOCK DIAGRAM OF THE INPUT CLOCK CIRCUITRY DRIVING THE MICROPROCESSOR
SFM_EN STS-1Clk/12M DS3Clk E3Clk
Clock Synthesizer
CLKOUT_n LOL_n
0 1
Processor
2.1
Clock Distribution
Network cards that are designed to support multiple line rates which are not configured for single frequency mode should ensure that a clock is applied to the DS3Clk input pin. For example: If the network card being supplied to an ISP requires E3 only, the DS-3 input clock reference is still necessary to provide read and write access to the internal microprocessor. Therefore, the E3 mode requires two input clock references. If however, multiple line rates will not be supported, i.e. E3 only, then the DS3Clk input pin may be hard wire connected to the E3Clk input pin. FIGURE 5. CLOCK DISTRIBUTION CONGIFURED IN E3 MODE WITHOUT USING SFM
DS3Clk
E3Clk
Clock Synthesizer
CLKOUT_n LOL_n
Processor
NOTE: For one input clock reference, the single frequency mode should be used.
17
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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XRT73R06
REV. 1.0.0
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XRT73R06
REV. 1.0.0
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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3.0 THE TRANSMITTER SECTION The transmitter is designed so that the LIU can accept serial data from a local device, encode the data properly, and then output an analog pulse according to the pulse shape chosen in the appropriate registers. This section describes the detailed operation of various blocks within the transmit path. A simplified block diagram of the transmit path is shown in Figure 6. FIGURE 6. TRANSMIT PATH BLOCK DIAGRAM
TTIP_n TRing_n MTIP_n MRing_n DMO_n
Line Driver
Tx Pulse Shaping
Timing Control
Jitter Attenuator
MUX
HDB3/ B3ZS Encoder
TxClk_n TxPOS_n TxNEG_n
Device Monitor
Tx Control Channel n
TxON
3.1
Transmit Digital Input Interface
The method for applying data to the transmit inputs of the LIU is a serial interface consisting of TxClk, TxPOS, and TxNEG. For single rail mode, only TxClk and TxPOS are necessary for providing the local data from a Framer device or ASIC. Data can be sampled on either edge of the input clock signal by programming the appropriate register. A typical interface is shown in Figure 7. FIGURE 7. TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT73R06 (DUAL-RAIL DATA)
TxPOS Terminal Equipment (E3/DS3 or STS-1 Framer) TxNEG TxLineClk
TPData TNData TxClk
Transmit Logic Block
Exar E3/DS3/STS-1 LIU
19
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT FIGURE 8. TRANSMITTER TERMINAL INPUT TIMING
tRTX TxClk tTSU TPData or TNData TTIP or TRing tTHO tFTX
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XRT73R06
REV. 1.0.0
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
TxClk
Duty Cycle TxClk Frequency E3 DS-3 STS-1
30
50
70
%
34.368 44.736 51.84 4 4 3 3
MHz MHz MHz ns ns ns ns
tRTX tFTX tTSU tTHO
TxClk Rise Time (10% to 90%) TxClk Fall Time (10% to 90%) TPData/TNData to TxClk falling set up time TPData/TNData to TxClk falling hold time
FIGURE 9. SINGLE-RAIL OR NRZ DATA FORMAT (ENCODER AND DECODER ARE ENABLED)
Data
1
1
0
TPData TxClk
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ac
FIGURE 10. DUAL-RAIL DATA FORMAT (ENCODER AND DECODER ARE DISABLED)
Data
1
1
0
TPData TNData TxClk
3.2
Transmit Clock
The Transmit Clock applied via TxClk_n pins, for the selected data rate (for E3 = 34.368 MHz, DS3 = 44.736 MHz or STS-1 = 51.84 MHz), is duty cycle corrected by the internal PLL circuit to provide a 50% duty cycle clock to the pulse shaping circuit. This allows a 30% to 70% duty cycle Transmit Clock to be supplied. 3.3 B3ZS/HDB3 ENCODER When the Single-Rail (NRZ) data format is selected, the Encoder Block encodes the data into either B3ZS format (for either DS3 or STS-1) or HDB3 format (for E3). 3.3.1 B3ZS Encoding An example of B3ZS encoding is shown in Figure 11. If the encoder detects an occurrence of three consecutive zeros in the data stream, it is replaced with either B0V or 00V, where `B' refers to Bipolar pulse that is compliant with the Alternating polarity requirement of the AMI (Alternate Mark Inversion) line code and `V' refers to a Bipolar Violation (e.g., a bipolar pulse that violates the AMI line code). The substitution of B0V or 00V is made so that an odd number of bipolar pulses exist between any two consecutive violation (V) pulses. This avoids the introduction of a DC component into the line signal. FIGURE 11. B3ZS ENCODING FORMAT
TClk TPDATA Line Signal
1 1 0 0 1 11 1 0 0 1 0 0 V 0 0 B 0 0 0 V B V 0 0 0
0 0
0 0
0 V
0 0
1
3.3.2
HDB3 Encoding
An example of the HDB3 encoding is shown in Figure 12. If the HDB3 encoder detects an occurrence of four consecutive zeros in the data stream, then the four zeros are substituted with either 000V or B00V pattern. The substitution code is made in such a way that an odd number of pulses exist between any consecutive V pulses. This avoids the introduction of DC component into the analog signal.
21
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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REV. 1.0.0
FIGURE 12. HDB3 ENCODING FORMAT
TClk TPDATA Line Signal
1 1 0 0 1 11 1 0 0 0 0 0 0 0 V 1 1 0 0 0 0 0 0 V 0 0 B 0 0 0 0 0 V
3.4
TRANSMIT PULSE SHAPER
The Transmit Pulse Shaper converts the B3ZS encoded digital pulses into a single analog Alternate Mark Inversion (AMI) pulse that meets the industry standard mask template requirements for STS-1 and DS3. For E3 mode, the pulse shaper converts the HDB3 encoded pulses into a single full amplitude square shaped pulse with very little slope. The Pulse Shaper Block also includes a Transmit Build Out Circuit, which can either be disabled or enabled by setting the TxLEV_n bit to "1" or "0" in the control register. For DS3/STS-1 rates, the Transmit Build Out Circuit is used to shape the transmit waveform that ensures that transmit pulse template requirements are met at the Cross-Connect system. The distance between the transmitter output and the Cross-Connect system can be between 0 to 450 feet. For E3 rate, since the output pulse template is measured at the secondary of the transformer and since there is no Cross-Connect system pulse template requirements, the Transmit Build Out Circuit is always disabled. The differential line driver increases the transmit waveform to appropriate level and drives into the 75 load as shown in Figure 13. FIGURE 13. TRANSMIT PULSE SHAPE TEST CIRCUIT
R1
TxPOS(n) TxNEG(n) TxLineClk(n)
TPData(n) TNData(n) TxClk(n) TRing(n)
TTIP(n)
31.6 +1%
R2
31.6 + 1%
R3 75 1:1
3.4.1
Guidelines for using Transmit Build Out Circuit
If the distance between the transmitter and the DSX3 or STSX-1, Cross-Connect system, is less than 225 feet, enable the Transmit Build Out Circuit by setting the TxLEV_n control bit to "0". If the distance between the transmitter and the DSX3 or STSX-1 is greater than 225 feet, disable the Transmit Build Out Circuit.
22
XRT73R06
REV. 1.0.0
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
ac
3.5
E3 line side parameters
The XRT73R06 line output at the transformer output meets the pulse shape specified in ITU-T G.703 for 34.368 Mbits/s operation. The pulse mask as specified in ITU-T G.703 for 34.368 Mbits/s is shown in Figure 22. FIGURE 14. PULSE MASK FOR E3 (34.368 MBITS/S) INTERFACE AS PER ITU-T G.703
17 ns (14.55 + 2.45)
V = 100%
8.65 ns
Nominal Pulse
50%
14.55ns 12.1ns (14.55 - 2.45) 10% 20%
10% 0%
23
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT TABLE 1: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS
PARAMETER MIN TYP MAX
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XRT73R06
REV. 1.0.0
UNITS
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS Transmit Output Pulse Amplitude (Measured at secondary of the transformer) Transmit Output Pulse Amplitude Ratio Transmit Output Pulse Width Transmit Intrinsic Jitter RECEIVER LINE SIDE INPUT CHARACTERISTICS Receiver Sensitivity (length of cable) Interference Margin Jitter Tolerance @ Jitter Frequency 800KHz Signal level to Declare Loss of Signal Signal Level to Clear Loss of Signal Occurence of LOS to LOS Declaration Time Termination of LOS to LOS Clearance Time -15 10 10 255 255 900 -20 0.15 1200 -14 0.28 -35 feet dB UI PP dB dB UI UI 0.95 12.5 1.00 14.55 0.02 1.05 16.5 0.05 ns UIPP 0.90 1.00 1.10 Vpk
NOTE: The above values are at TA = 250C and VDD = 3.3 V 5%.
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REV. 1.0.0
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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FIGURE 15. BELLCORE GR-253 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS
S T S -1 P u ls e T em p la te
1.2
1
0.8
Norm a lize d Am plitude
0.6 Lower Curve Upper Curve 0.4
0.2
0
-0.2
0 -1 1 2 3 4 5 6 7 8 9 1 1 2 3 1. 9 8 7 6 5 4 3 2 1 0. 0. 0. 0. 0. 0. 0. 0. 0. 1. 1. -0 . -0 . -0 . -0 . -0 . -0 . -0 . -0 . -0 . 1. 4
Tim e , in UI
TABLE 2: STS-1 PULSE MASK EQUATIONS
TIME IN UNIT INTERVALS LOWER CURVE -0.85 < T < -0.38 -0.38 - 0.03 NORMALIZED AMPLITUDE
< T < 0.36
* T- 0.5 1 + sin -- 1 + ---------- - 0.03 0.18 2
- 0.03 UPPER CURVE
0.36 < T < 1.4
-0.85 < T < -0.68 -0.68 < T < 0.26
0.03
* T- 0.5 1 + sin -- 1 + ---------- + 0.03 0.34 2 0.1 + 0.61 x e-2.4[T-0.26]
0.26 < T < 1.4
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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REV. 1.0.0
TABLE 3: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253)
PARAMETER MIN TYP MAX UNITS
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS Transmit Output Pulse Amplitude (measured with TxLEV = 0) Transmit Output Pulse Amplitude (measured with TxLEV = 1) Transmit Output Pulse Width Transmit Output Pulse Amplitude Ratio Transmit Intrinsic Jitter RECEIVER LINE SIDE INPUT CHARACTERISTICS Receiver Sensitivity (length of cable) Jitter Tolerance @ Jitter Frequency 400 KHz Signal Level to Declare Loss of Signal Signal Level to Clear Loss of Signal 900 0.15 Refer to Table 10 Refer to Table 10 1100 feet UIpp 8.6 0.90 9.65 1.00 0.02 10.6 1.10 0.05 UIpp ns 0.90 1.00 1.10 Vpk 0.65 0.75 0.90 Vpk
NOTE: The above values are at TA = 250C and VDD = 3.3 V 5%.
FIGURE 16. TRANSMIT OUPUT PULSE TEMPLATE FOR DS3 AS PER BELLCORE GR-499
D S 3 P u ls e T e m p la te
1.2
1
0.8
No rm a li z e d Am p litu d e
0.6 Lower Curve Upper Curve 0.4
0.2
0
-0.2
-1 0 1 1 2 3 1. 1 2 3 4 5 6 7 8 .9 .8 .7 .6 .5 .4 .3 .2 .1 9 1. 1. 0. 0. 0. 0. 0. 0. 0. 0. -0 -0 -0 -0 -0 -0 -0 -0 -0 0. 1. 4
T im e , in UI
26
XRT73R06
REV. 1.0.0
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT TABLE 4: DS3 PULSE MASK EQUATIONS
TIME IN UNIT INTERVALS LOWER CURVE -0.85 < T < -0.36 -0.36 - 0.03 NORMALIZED AMPLITUDE
ac
< T < 0.36
* T- 0.5 1 + sin -- 1 + ---------- - 0.03 2 0.18
- 0.03 UPPER CURVE
0.36 < T < 1.4
-0.85 < T < -0.68 -0.68 < T < 0.36
0.03
* T- 0.5 1 + sin -- 1 + ---------- + 0.03 0.34 2 0.08 + 0.407 x e-1.84[T-0.36]
0.36 < T < 1.4
TABLE 5: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499)
PARAMETER MIN TYP MAX UNITS
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS Transmit Output Pulse Amplitude (measured with TxLEV = 0) Transmit Output Pulse Amplitude (measured with TxLEV = 1) Transmit Output Pulse Width Transmit Output Pulse Amplitude Ratio Transmit Intrinsic Jitter RECEIVER LINE SIDE INPUT CHARACTERISTICS Receiver Sensitivity (length of cable) Jitter Tolerance @ 400 KHz (Cat II) Signal Level to Declare Loss of Signal Signal Level to Clear Loss of Signal 900 0.15 Refer to Table 10 Refer to Table 10 1100 feet UIpp 10.10 0.90 11.18 1.00 0.02 12.28 1.10 0.05 UIpp ns 0.90 1.00 1.10 Vpk 0.65 0.75 0.85 Vpk
NOTE: The above values are at TA = 250C and VDD = 3.3V 5%.
27
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 3.6 Transmit Drive Monitor
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XRT73R06
REV. 1.0.0
This feature is used for monitoring the transmit line for occurrence of fault conditions such as a short circuit on the line or a defective line driver. To activate this function, connect MTIP_n pins to the TTIP_n lines via a 270 resistor and MRing_n pins to TRing_n lines via 270 resistor as shown in Figure 17. FIGURE 17. TRANSMIT DRIVER MONITOR SET-UP.
R1
TTIP(n)
31.6 +1%
R2
R3 75 1:1
TxPOS(n) TxNEG(n) TxLineClk(n)
TRing(n)
TPData(n) TNData(n) TxClk(n)
31.6 + 1%
R1
MTIP(n)
270
R2
MRing(n)
270
When the MTIP_n and MRing_n are connected to the TTIP_n and TRing_n lines, the drive monitor circuit monitors the line for transitions. The DMO_n (Drive Monitor Output) will be asserted "Low" as long as the transitions on the line are detected via MTIP_n and MRing_n. If no transitions on the line are detected for 128 32 TxClk_n periods, the DMO_n output toggles "High" and when the transitions are detected again, DMO_n toggles "Low".
NOTE: The Drive Monitor Circuit is only for diagnostic purpose and does not have to be used to operate the transmitter.
3.7
Transmitter Section On/Off
The transmitter section of each channel can either be turned on or off. To turn on the transmitter, set the input pin TxON to "High" and write a "1" to the TxON_n control bit. When the transmitter is turned off, TTIP_n and TRing_n are tri-stated.
NOTES: 1. This feature provides support for Redundancy. 2. To permit a system designed for redundancy to quickly shut-off the defective line card and turn on the back-up line card, writing a "1" to the TxON_n control bits transfers the control to TxON pin.
28
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REV. 1.0.0
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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29
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 4.0 THE RECEIVER SECTION
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XRT73R06
REV. 1.0.0
The receiver is designed so that the LIU can recover clock and data from an attenuated line signal caused by cable loss or flat loss according to industry specifications. Once data is recovered, it is processed and presented at the receiver outputs according to the format chosen to interface with a Framer/Mapper or ASIC. This section describes the detailed operation of various blocks within the receive path. A simplified block diagram of the receive path is shown in Figure 18. FIGURE 18. RECEIVE PATH BLOCK DIAGRAM
Peak Detector AGC/ Equalizer Slicer Clock & Data Recovery LOS Detector Channel n Jitter Attenuator HDB3/ B3ZS Decoder RxClk_n RxPOS_n RxNEG/LCV_n RLOS_n
RTIP_n RRing_n
MUX
4.1
Receive Line Interface
Physical Layer devices are AC coupled to a line interface through a 1:1 transformer. The transformer provides isolation and a level shift by blocking the DC offset of the incoming data stream. The typical medium for the line interface is a 75 coxial cable. Whether using E3, DS-3 or STS-1, the LIU requires the same bill of materials, see Figure 19. FIGURE 19. RECEIVE LINE INTERFACECONNECTION
1:1 RTIP_n Receiver 75 RRing_n
DS-3/E3/STS-1
37.5
37.5
0.01F RLOS_n
30
XRT73R06
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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4.2
Adaptive Gain Control (AGC)
The Adaptive Gain Control circuit amplifies the incoming analog signal and compensates for the various flat losses and also for the loss at one-half symbol rate. The AGC has a dynamic range of 30 dB. The peak detector provides feedback to the equalizer before slicing occurs. 4.3 Receive Equalizer The Equalizer restores the integrity of the signal and compensates for the frequency dependent attenuation of up to 900 feet of coaxial cable (1300 feet for E3). The Equalizer also boosts the high frequency content of the signal to reduce Inter-Symbol Interference (ISI) so that the slicer slices the signal at 50% of peak voltage to generate Positive and Negative data. The equalizer can be disabled by programming the appropriate register. FIGURE 20. ACG/EQUALIZER BLOCK DIAGRAM
Peak Detector AGC/ Equalizer Slicer LOS Detector
RTIP_n RRing_n
4.3.1
Recommendations for Equalizer Settings
The Equalizer has two gain settings to provide optimum equalization. In the case of normally shaped DS3/ STS-1 pulses (pulses that meet the template requirements) that has been driven through 0 to 900 feet of cable, the Equalizer can be enabled. However, for square-shaped pulses such as E3 or for DS3/STS-1 high pulses (that does not meet the pulse template requirements), it is recommended that the Equalizer be disabled for cable length less than 300 feet. This would help to prevent over-equalization of the signal and thus optimize the performance in terms of better jitter transfer characteristics. The Equalizer also contains an additional 20 dB gain stage to provide the line monitoring capability of the resistively attenuated signals which may have 20dB flat loss. The equalizer gain mode can be enabled by programming the appropriate register.
NOTE: The results of extensive testing indicate that even when the Equalizer was enabled, regardless of the cable length, the integrity of the E3 signal was restored properly over 0 to 12 dB cable loss at Industrial Temperature.
4.4
Clock and Data Recovery
The Clock and Data Recovery Circuit extracts the embedded clock, RxClk_n from the sliced digital data stream and provides the retimed data to the B3ZS (HDB3) decoder. The Clock Recovery PLL can be in one of the following two modes: 4.4.1 Data/Clock Recovery Mode In the presence of input line signals on the RTIP_n and RRing_n input pins and when the frequency difference between the recovered clock signal and the reference clock signal is less than 0.5%, the clock that is output on the RxClk_n out pins is the Recovered Clock signal. 4.4.2 Training Mode In the absence of input signals at RTIP_n and RRing_n pins, or when the frequency difference between the recovered line clock signal and the reference clock applied on the ExClk_n input pins exceed 0.5%, a Loss of Lock condition is declared by toggling RLOL_n output pin "High" or setting the RLOL_n bit to "1" in the control register. Also, the clock output on the RxClk_n pins are the same as the reference channel clock.
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 4.5 4.5.1 LOS (Loss of Signal) Detector DS3/STS-1 LOS Condition
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A Digital Loss of SIgnal (DLOS) condition occurs when a string of 175 75 consecutive zeros occur on the line. When the DLOS condition occurs, the DLOS_n bit is set to "1" in the status control register. DLOS condition is cleared when the detected average pulse density is greater than 33% for 175 75 pulses. Analog Loss of Signal (ALOS) condition occurs when the amplitude of the incoming line signal is below the threshold as shown in the Table 6.The status of the ALOS condition is reflected in the ALOS_n status control register. RLOS is the logical OR of the DLOS and ALOS states. When the RLOS condition occurs the RLOS_n output pin is toggled "High" and the RLOS_n bit is set to "1" in the status control register. TABLE 6: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS)
APPLICATION REQEN SETTING LOSTHR SETTING DS3 0 1 0 1 STS-1 0 1 0 1 0 0 1 1 0 0 1 1 SIGNAL LEVEL TO DECLARE ALOS DEFECT < 75mVpk < 45mVpk < 120mVpk < 55mVpk < 120mVpk < 50mVpk < 125mVpk < 55mVpk SIGNAL LEVEL TO CLEAR ALOS DEFECT > 130mVpk > 60mVpk > 45mVpk > 180mVpk > 170mVpk > 75mVpk > 205mVpk > 90mVpk
4.5.2
Disabling ALOS/DLOS Detection
For debugging purposes it is useful to disable the ALOS and/or DLOS detection. Writing a "1" to both ALOSDIS_n and DLOSDIS_n bits disables the LOS detection on a per channel basis.
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT E3 LOS Condition:
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4.5.3
If the level of incoming line signal drops below the threshold as described in the ITU-T G.775 standard, the LOS condition is detected. Loss of signal is defined as no transitions for 10 to 255 consecutive zeros. No transitions is defined as a signal level between 15 and 35 dB below the normal. This is illustrated in Figure 21. The LOS condition is cleared within 10 to 255 UI after restoration of the incoming line signal. Figure 22 shows the LOS declaration and clearance conditions. FIGURE 21. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775
0 dB
Maximum Cable Loss for E3
LOS Signal Must be Cleared
-12 dB -15dB
LOS Signal may be Cleared or Declared
-35dB
LOS Signal Must be Declared
FIGURE 22. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775.
Actual Occurrence of LOS Condition RTIP/ RRing Line Signal is Restored
10 UI
255 UI
Time Range for LOS Declaration
10 UI
255 UI
RLOS Output Pin 0 UI G.775 Compliance 0 UI Time Range for LOS Clearance G.775 Compliance
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 4.5.4 Interference Tolerance
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For E3 mode, ITU-T G.703 Recommendation specifies that the receiver be able to recover error free clock and data in the presence of a sinusoidal interfering tone signal. For DS3 and STS-1 modes, the same recommendation is being used. Figure 23 shows the configuration to test the interference margin for DS3/ STS1. Figure 24 shows the set up for E3. FIGURE 23. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1
Attenuator Sine Wave Generator N
DS3 = 22.368 MHz STS-1 = 25.92 MHz
Cable Simulator Pattern Generator 2 23 -1 PRBS S
DUT XRT75R06
Test Equipment
FIGURE 24. INTERFERENCE MARGIN TEST SET UP FOR E3.
Attenuator 1 Sine Wave Generator 17.184mHz N Attenuator 2
Signal Source 223-1 PRBS Cable Simulator S
DUT XRT75R06 Test Equipment
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TABLE 7: INTERFERENCE MARGIN TEST RESULTS
MODE CABLE LENGTH (ATTENUATION) INTERFERENCE TOLERANCE Equalizer "IN" E3 0 dB 12 dB 0 feet DS3 225 feet 450 feet 0 feet STS-1 225 feet 450 feet -17 dB -14 dB -15 dB -15 dB -14 dB -15 dB -14 dB -14 dB
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 4.5.5 Muting the Recovered Data with LOS condition:
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When the LOS condition is declared, the clock recovery circuit locks into the reference clock applied to the internal master clock outputs this clock onto the RxClk_n output pin. The data on the RxPOS_n and RxNEG_n pins can be forced to zero by setting the LOSMUT_n bits in the individual channel control register to "1".
NOTE: When the LOS condition is cleared, the recovered data is output on RxPOS_n and RxNEG_n pins.
FIGURE 25. RECEIVER DATA OUTPUT AND CODE VIOLATION TIMING
tRRX RxClk tLCVO LCV tCO RPOS or RNEG
tFRX
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
RxClk
Duty Cycle RxClk Frequency E3 DS-3 STS-1
45
50
55
%
34.368 44.736 51.84 2 2 4 4 4 2.5
MHz MHz MHz ns ns ns ns
tRRX tFRX tCO tLCVO
RxClk rise time (10% o 90%) RxClk falling time (10% to 90%) RxClk to RPOS/RNEG delay time RxClk to rising edge of LCV output delay
4.6
B3ZS/HDB3 Decoder
The decoder block takes the output from the clock and data recovery block and decodes the B3ZS (for DS3 or STS-1) or HDB3 (for E3) encoded line signal and detects any coding errors or excessive zeros in the data stream. Whenever the input signal violates the B3ZS or HDB3 coding sequence for bipolar violation or contains three (for B3ZS) or four (for HDB3) or more consecutive zeros, an active "High" pulse is generated on the RLCV_n output pins to indicate line code violation.
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5.0 JITTER There are three fundamental parameters that describe circuit performance relative to jitter
* Jitter Tolerance * Jitter Transfer * Jitter Generation
5.1 JITTER TOLERANCE Jitter tolerance is a measure of how well a Clock and Data Recovery unit can successfully recover data in the presence of various forms of jitter. It is characterized by the amount of jitter required to produce a specified bit error rate. The tolerance depends on the frequency content of the jitter. Jitter Tolerance is measured as the jitter amplitude over a jitter spectrum for which the clock and data recovery unit achieves a specified bit error rate (BER). To measure the jitter tolerance as shown in Figure 26, jitter is introduced by the sinusoidal modulation of the serial data bit sequence. Input jitter tolerance requirements are specified in terms of compliance with jitter mask which is represented as a combination of points. Each point corresponds to a minimum amplitude of sinusoidal jitter at a given jitter frequency. FIGURE 26. JITTER TOLERANCE MEASUREMENTS
Pattern Generator
Data
DUT XRT73R06
Error Detector
Clock Modulation Freq.
FREQ Synthesizer
5.1.1
DS3/STS-1 Jitter Tolerance Requirements
Bellcore GR-499 CORE specifies the minimum requirement of jitter tolerance for Category I and Category II. The jitter tolerance requirement for Category II is the most stringent. Figure 27 shows the jitter tolerance curve as per GR-499 specification.
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT FIGURE 27. INPUT JITTER TOLERANCE FOR DS3/STS-1
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64 41 15 JITTER AMPLITUDE (UI) pp 10 5 1.5 0.3 0.15 0.1
GR-253 STS-1 GR-499 Cat II GR-499 Cat I XRT73R06
0.01
0.03
0.3
2
20
100
JITTER FREQUENCY (kHz)
5.1.2
E3 Jitter Tolerance Requirements
ITU-T G.823 standard specifies that the clock and data recovery unit must be able to tolerate jitter up to certain specified limits. Figure 28 shows the tolerance curve. FIGURE 28. INPUT JITTER TOLERANCE FOR E3
64 JITTER AMPLITUDE (UI) pp 10 1.5
ITU-T G.823 XRT73R06
0.3
0.1
1 JITTER FREQUENCY (kHz)
10
800
As shown in the Figures above, in the jitter tolerance measurement, the dark line indicates the minimum level of jitter that the E3/DS3/STS-1 compliant component must tolerate. Table 8 below shows the jitter amplitude versus the modulation frequency for various standards.
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT TABLE 8: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE)
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BIT RATE (KB/S) 34368 44736 44736 51840
INPUT JITTER AMPLITUDE (UI P-P) STANDARD A1 ITU-T G.823 GR-499 CORE Cat I GR-499 CORE Cat II GR-253 CORE Cat II 1.5 5 10 15 A2 0.15 0.1 0.3 1.5 A3 0.15
F1(HZ)
MODULATION FREQUENCY
F2(HZ) F3(KHZ) F4(KHZ) F5(KHZ)
100 10 10 10
1000 2.3k 669 30
10 60 22.3 300
800 300 300 2
20
5.2
JITTER TRANSFER
Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input versus frequency. There are two distinct characteristics in jitter transfer, jitter gain (jitter peaking) defined as the highest ratio above 0dB and jitter transfer bandwidth. The overall jitter transfer bandwidth is controlled by a low bandwidth loop, typically using a voltage-controlled crystal oscillator (VCXO). The jitter transfer function is a ratio between the jitter output and jitter input for a component, or system often expressed in dB. A negative dB jitter transfer indicates the element removed jitter. A positive dB jitter transfer indicates the element added jitter. A zero dB jitter transfer indicates the element had no effect on jitter. Table 9 shows the jitter transfer characteristics and/or jitter attenuation specifications for various data rates: TABLE 9: JITTER TRANSFER SPECIFICATION/REFERENCES
E3 ETSI TBR-24 DS3 GR-499 CORE section 7.3.2 Category I and Category II STS-1 GR-253 CORE section 5.6.2.1
NOTE: The above specifications can be met only with a jitter attenuator that supports E3/DS3/STS-1 rates.
TABLE 10: JITTER TRANSFER PASS MASKS
RATE (KBITS) 34368 44736 MASK G.823 ETSI-TBR-24 GR-499, Cat I GR-499, Cat II GR-253 CORE GR-253 CORE F1 (HZ) 100 F2 (HZ) 300 F3 (HZ) 3K F4 (KHZ) 800K A1(dB) 0.5 A2(dB) -19.5
10 10 10 10
10k 56.6k 40 40k
-
15k 300k 15k 400k
0.1 0.1 0.1 0.1
-
51840
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT FIGURE 29. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE
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J IT T E R A M P L IT U D E
A1 A2
F1
F2
F3
F4
J IT T E R F R E Q U E N C Y ( k H z )
5.2.1
JITTER GENERATION
Jitter Generation is defined as the process whereby jitter appears at the output port of the digital equipment in the absence of applied input jitter. Jitter Generation is measured by sending jitter free data to the clock and data recovery circuit and measuring the amount of jitter on the output clock or the re-timed data. Since this is essentially a noise measurement, it requires a definition of bandwidth to be meaningful. The bandwidth is set according to the data rate. In general, the jitter is measured over a band of frequencies.
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6.0 DIAGNOSTIC FEATURES 6.1 PRBS Generator and Detector The XRT73R06 contains an on-chip Pseudo Random Binary Sequence (PRBS) generator and detector for diagnostic purpose. With the PRBSEN_n bit = "1", the transmitter will send out PRBS of 223-1 in E3 rate or 215-1 in STS-1/DS3 rate. At the same time, the receiver PRBS detector is also enabled. When the correct PRBS pattern is detected by the receiver, the RNEG/LCV pin will go "Low" to indicate PRBS synchronization has been achieved. When the PRBS detector is not in sync the PRBSLS bit will be set to "1" and RNEG/LCV pin will go "High". With the PRBS mode enabled, the user can also insert a single bit error by toggling "INSPRBS" bit. This is done by writing a "1" to INSPRBS bit. The receiver at RNEG/LCV pin will pulse "High" for one RxClk cycle for every bit error detected. Any subsequent single bit error insertion must be done by first writing a "0" to INSPRBS bit and followed by a "1". Figure 30 shows the status of RNEG/LCV pin when the XRT73R06 is configured in PRBS mode.
NOTE: In PRBS mode, the device is forced to operate in Single-Rail Mode.
FIGURE 30. PRBS MODE
RxClk
SYNC LOSS
RxNEG/LCV
PRBS SYNC Single Bit Error
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 6.2 LOOPBACKS
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The XRT73R06 offers three loopback modes for diagnostic purposes. The loopback modes are selected via the RLB_n and LLB_n bits n the Channel control registers select the loopback modes. 6.2.1 ANALOG LOOPBACK In this mode, the transmitter outputs TTIP_n and TRing_n are internally connected to the receiver inputs RTIP_n and RRing_n as shown in Figure 31. Data and clock are output at RxClk_n, RxPOS_n and RxNEG_n pins for the corresponding transceiver. Analog loopback exercises most of the functional blocks of the device including the jitter attenuator which can be selected in either the transmit or receive path.
NOTES: 1. In the Analog loopback mode, data is also output via TTIP_n and TRing_n pins. 2. Signals on the RTIP_n and RRing_n pins are ignored during analog loopback.
FIGURE 31. ANALOG LOOPBACK
TxClk TxPOS TxNEG HDB3/B3ZS ENCODER
JITTER ATTENUATOR
TIMING CONTROL
TTIP Tx TRing
RxClk RxPOS RxNEG HDB3/B3ZS DECODER
JITTER ATTENUATOR
DATA & CLOCK RECOVERY
RTIP Rx RRing
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6.2.2
When the Digital Loopback is selected, the transmit clock TxClk_n and transmit data inputs (TxPOS_n & TxNEG_n are looped back and output onto the RxClk_n, RxPOS_n and RxNEG_n pins as shown in Figure 32. FIGURE 32. DIGITAL LOOPBACK
JITTER ATTENUATOR
TxCLK TxPOS TxNEG HDB3/B3ZS ENCODER
TIMING CONTROL
TTIP Tx TRing
RxCLK RxPOS RxNEG HDB3/B3ZS DECODER
JITTER ATTENUATOR
DATA & CLOCK RECOVERY
RTIP Rx RRing
6.2.3
REMOTE LOOPBACK
With Remote loopback activated as shown in Figure 33, the receive data on RTIP and RRing is looped back after the jitter attenuator (if selected in receive or transmit path) to the transmit path using RxClk as transmit timing. The receive data is also output via the RxPOS and RxNEG pins.
NOTE: Input signals on TxClk, TxPOS and TxNEG are ignored during Remote loopback.
FIGURE 33. REMOTE LOOPBACK
TxCLK TxPOS TxNEG HDB3/B3ZS ENCODER
JITTER ATTENUATOR
TIMING CONTROL
TTIP Tx TRing
RxCLK RxPOS RxNEG HDB3/B3ZS DECODER
JITTER ATTENUATOR
DATA & CLOCK RECOVERY
RTIP Rx RRing
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 6.3 TRANSMIT ALL ONES (TAOS)
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Transmit All Ones (TAOS) can be set by setting the TAOS_n control bits to "1" in the Channel control registers. When the TAOS is set, the Transmit Section generates and transmits a continuous AMI all "1's" pattern on TTIP_n and TRing_n pins. The frequency of this ones pattern is determined by TxClk_n. the TAOS data path is shown in Figure 34. TAOS does not operate in Analog loopback or Remote loopback modes, however will function in Digital loopback mode. FIGURE 34. TRANSMIT ALL ONES (TAOS)
JITTER ATTENUATOR
TxCLK TxPOS TxNEG HDB3/B3ZS ENCODER
TIMING CONTROL
Tx
TTIP Transmit All 1's TRing
TAOS
JITTER ATTENUATOR
RxCLK RxPOS RxNEG HDB3/B3ZS DECODER
DATA & CLOCK RECOVERY
RTIP Rx RRing
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 7.0 MICROPROCESSOR INTERFACE BLOCK
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The Microprocessor Interface section supports communication between the local microprocessor (P) and the LIU. The XRT73R06 supports a parallel interface asynchronously or synchronously timed to the LIU. The microprocessor interface is selected by the state of the Pmode input pin. Selecting the microprocessor interface mode is shown in Table 11. TABLE 11: SELECTING THE MICROPROCESSOR INTERFACE MODE
PMODE "Low" "High" MICROPROCESSOR MODE Asynchronous Mode Synchronous Mode
The local P configures the LIU by writing data into specific addressable, on-chip Read/Write registers. The P provides the signals which are required for a general purpose microprocessor to read or write data into these registers. The P also supports polled and interrupt driven environments. A simplified block diagram of the microprocessor is shown in Figure 35. FIGURE 35. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK
CS WR RD
Addr[7:0] D[7:0] PCLK Pmode RESET RDY INT
Microprocessor Interface
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7.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS The LIU may be configured into different operating modes and have its performance monitored by software through a standard microprocessor using data, address and control signals. These interface signals are described below in Table 12. The microprocessor interface can be configured to operate in Asynchronous mode or Synchronous mode. TABLE 12: XRT73R06 MICROPROCESSOR INTERFACE SIGNALS
PIN NAME TYPE I I/O I DESCRIPTION Microprocessor Interface Mode Select Input pin This pin is used to specify the microprocessor interface mode. Bi-Directional Data Bus for register "Read" or "Write" Operations. Eight-Bit Address Bus Inputs The XRT73R06 LIU microprocessor interface uses a direct address bus. This address bus is provided to permit the user to select an on-chip register for Read/Write access. Chip Select Input This active low signal selects the microprocessor interface of the XRT73R06 LIU and enables Read/Write operations with the on-chip register locations. Read Signal This active low input functions as the read signal from the local P. When this pin is pulled "Low" (if CS is "Low") the LIU is informed that a read operation has been requested and begins the process of the read cycle. Write Signal This active low input functions as the write signal from the local P. When this pin is pulled "Low" (if CS is "Low") the LIU is informed that a write operation has been requested and begins the process of the write cycle. Ready Output This active low signal is provided by the LIU device. It indicates that the current read or write cycle is complete, and the LIU is waiting for the next command. Interrupt Output This active low signal is provided by the LIU to alert the local mP that a change in alarm status has occured. This pin is Reset Upon Read (RUR) once the alarm status registers have been cleared. Reset Input This active low input pin is used to Reset the LIU.
Pmode
D[7:0] Addr[7:0]
CS
I
RD
I
WR
I
RDY INT
O O
RESET
I
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7.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION Whether the LIU is configured for Asynchronous or Synchronous mode, the following descriptions apply. The synchronous mode requires an input clock (PCLK) to be used as the microprocessor timing reference. Read and Write operations are described below. Read Cycle (For Pmode = "0" or "1") Whenever the local P wishes to read the contents of a register, it should do the following. 1. Place the address of the target register on the address bus input pins Addr[7:0]. 2. While the P is placing this address value on the address bus, the address decoding circuitry should assert the CS pin of the LIU, by toggling it "Low". This action enables communication between the P and the LIU microprocessor interface block. 3. Next, the P should indicate that this current bus cycle is a Read operation by toggling the RD input pin "Low". This action enables the bi-directional data bus output drivers of the LIU. 4. After the P toggles the Read signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this to inform the P that the data is available to be read by the P and that it is ready for the next command. , 5. After the P detects the RDY signal and has read the data, it can terminate the Read Cycle by toggling the RD input pin "High". 6. The CS input pin must be pulled "High" before a new command can be issued. Write Cycle (For Pmode = "0" or "1") Whenever a local P wishes to write a byte or word of data into a register within the LIU, it should do the following. 1. Place the address of the target register on the address bus input pins Addr[7:0]. 2. While the P is placing this address value on the address bus, the address decoding circuitry should assert the CS pin of the LIU, by toggling it "Low". This action enables communication between the P and the LIU microprocessor interface block. 3. The P should then place the byte or word that it intends to write into the target register, on the bi-directional data bus D[7:0]. 4. Next, the P should indicate that this current bus cycle is a Write operation by toggling the WR input pin "Low". This action enables the bi-directional data bus input drivers of the LIU. 5. After the P toggles the Write signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this to inform the P that the data has been written into the internal register location, and that it is ready for the next command. 6. The CS input pin must be pulled "High" before a new command can be issued.
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FIGURE 36. ASYNCHRONOUS P INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
READ OPERATION
t0 Addr[7:0] Valid Address t0 Valid Address
WRITE OPERATION
CS
D[7:0] t1 RD
Valid Data for Readback
Data Available to Write Into the LIU
t3 WR t2 t4 RDY
TABLE 13: ASYNCHRONOUS TIMING SPECIFICATIONS
SYMBOL t0 t1 t2 NA t3 t4 NA PARAMETER Valid Address to CS Falling Edge CS Falling Edge to RD Assert RD Assert to RDY Assert RD Pulse Width (t2) CS Falling Edge to WR Assert WR Assert to RDY Assert WR Pulse Width (t4) MIN 0 0 70 0 70 MAX 65 65 ns ns ns ns ns ns ns UNITS
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FIGURE 37. SYNCHRONOUS P INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
READ OPERATION
PCLK t0 Addr[7:0] Valid Address t0 Valid Address
WRITE OPERATION
CS
D[7:0] t1 RD
Valid Data for Readback
Data Available to Write Into the LIU
t3 WR t2 t4 RDY
TABLE 14: SYNCHRONOUS TIMING SPECIFICATIONS
SYMBOL t0 t1 t2 NA t3 t4 NA PARAMETER Valid Address to CS Falling Edge CS Falling Edge to RD Assert RD Assert to RDY Assert RD Pulse Width (t2) CS Falling Edge to WR Assert WR Assert to RDY Assert WR Pulse Width (t4) PCLK Period PCLK Duty Cycle PCLK "High/Low" time MIN 0 0 40 0 40 15 MAX 35 35 ns ns ns, see note 1 ns ns ns, see note 1 ns ns UNITS
NOTE: 1. This timing parameter is based on the frequency of the synchronous clock (PCLK). To determine the access time, use the following formula: (PCLKperiod * 2) + 5ns
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FIGURE 38. INTERRUPT PROCESS
ERROR CONDITION OCCURS
Interrupt enable bits at 0x60 and 0xn1 set?
NO
YES
Interrupt status bits at 0x61 and 0xn2 set.
Interrupt Generated INT pin goes "Low"
Interrupt Service Routine reads the status register at 0x61
Interrupt Service Routine reads the status register at 0xn2
Interrupt is being serviced.
YES
Interrupt Pending ?
NO
INT pin goes "High" Normal Operation
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7.2.1 Hardware Reset: The hardware reset is initiated by pulling the RESET pin "Low" for a minimum of 5 s. After the RESET pin is released, the register values are put in default states.
TABLE 15: REGISTER MAP AND BIT NAMES
ADDRESS (HEX) 0x00 0x08 0x60 0x61 0x62 0x6D 0x6E 0x6F Chip_id (read only) Chip_revision _id (read only) 0 1 1 0 PARAMETER NAME APS/Redundancy #1 APS/ Redundancy #2 Interrupt Enable (read/write) Interrupt Status (read only) DATA BITS 7 Reserved Reserved Reserved Reserved 6 5 TxON_5 RxON_5 4 TxON_4 RxON_4 3 TxON_3 RxON_3 2 TxON_2 RxON_2 1 TxON-1 RxON_1 0 TxON_0 RxON_0
INTEN_5 INTEN_4 INTEN_3 INTEN_2 INTEN_1 INTEN_0 INTST_5 INTST_4 INTST_3 INTST_2 INTST_1 INTST_0
Reserved 0 1 0 1
Chip version number
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ADDRESS (HEX) 0x00
TYPE R/W
REGISTER NAME APS # 1
SYMBOL TxON_n
DESCRIPTION Table below shows the status of the transmitter based on the bit and pin setting.
DEFAULT VALUE 0
Bit 0 0 1 1 0x08 0x60 0x61 R/W R/W ROR APS # 2 Interrupt Enable Interrupt Status RxON_n INTEN_n INTST_n
Pin 0 1 0 1
Transmitter Status OFF OFF OFF ON 0 0 0
Set this bit to turn on individual Receiver. Set this bit to enable the interrupts on per channel basis. Bits are set when an interrupt occurs.The respective source level interrupt status registers are read to determine the cause of interrupt. Reserved
0x62 0x6D 0x6E 0x6F R R Device _ id Version Number Chip_id
This read only register contains device id.
0110101
Chip_version This read only register contains chip version number
TABLE 17: REGISTER MAP AND BIT NAMES - CHANNEL N REGISTERS (N = 0,1,2,3,4,5)
ADDRESS (HEX) 0x01 (ch 0) 0x11 (ch 1) 0x21 (ch 2) 0x31 (ch 3) 0x41 (ch 4) 0x51 (ch 5) PARAMETER NAME Interrupt Enable (read/write) DATA BITS 7 Reserved 6 5 4 3 2 1 0
PRBSER PRBSERI Reserved RLOLIE_n RLOSIE_ DMOIE_n CNTIE_n E_n n
0x02 (ch 0) Interrupt 0x12 (ch 1) Status 0x22 (ch 2) (reset on read) 0x32 (ch 3) 0x42 (ch 4) ox52 (ch 5)
Reserved
PRBSER PRBSERI Reserved RLOLIS_n RLOSIS_ DMOIS_n CNTIS_n S_n n
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT TABLE 17: REGISTER MAP AND BIT NAMES - CHANNEL N REGISTERS (N = 0,1,2,3,4,5)
ADDRESS (HEX) 0x03 (ch 0) 0x13 (ch 1) 0x23 (ch 2) 0x33 (ch 3) 0x43 (ch 4) 0x53 (ch 5) 0x04 (ch 0) 0x14 (ch 1) 0x24 (ch 2) 0x34 (ch 3) 0x44 (ch 4) 0x54 (ch 5) 0x05 (ch 0) 0x15 (ch 1) 0x25 (ch 2) 0x35 (ch 3) 0x45 (ch 4) 0x55 (ch 5) 0x06 (ch 0) 0x16 (ch 1) 0x26 (ch 2) 0x36 (ch 3) 0x46 (ch 4) 0x56 (ch 5) 0x07 (ch 0) 0x17 (ch 1) 0x27 (ch 2) 0x37 (ch 3) 0x47 (ch 4) 0x57 (ch 5) 0x0A (ch 0) 0x1A (ch 1) 0x2A (ch 2) 0x3A (ch 3) 0x4A (ch 4) 0x5A (ch 5) 0x0B (ch 0) 0x1B (ch 1) 0x2B (ch 2) 0x3B (ch 3) 0x4B (ch 4) 0x5B (ch 5) PARAMETER NAME DATA BITS 7 6 5 4 ALOS_n 3 Reserved 2 RLOL_n 1 RLOS_n
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XRT73R06
REV. 1.0.0
0 DMO_n
Alarm Status Reserved PRBSLS_n DLOS_n (read only)
Transmit Control (read/write)
Reserved
TxMON_n INSPRBS Reserved _n
TAOS_n
TxCLKINV TxLEV_n _n
Receive Control (read/write)
Reserved
DLOSDIS ALOSDIS RxCLKIN LOSMUT_ RxMON_n REQEN_ _n _n V_n n n
Block Control Reserved CLKOUTE PRBSEN_ (read/write) N_n 0
RLB_n
LLB_n
E3_n
STS1/ DS3_n
SR/DR_n
Jitter Attenuator Control (read/write)
Reserved
Reserved Reserved Reserved Reserved Reserved
PRBS Error Count Reg. MSB
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
PRBS Error Count Reg. LSB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0C (ch 0) PRBS Error 0x1C (ch 1) Count Holding 0x2C (ch 2) Register 0x3C (ch 3) 0x4C (ch 4) 0x5C (ch 5)
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XRT73R06
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N
ADDRESS (HEX) TYPE REGISTER NAME BIT# D0 SYMBOL DMOIE_n DESCRIPTION If the Driver Monitor (connected to the output of the channel) detects the absence of pulses for 128 consecutive cycles, it will set the interrupt flag if this bit has been set. DEFAULT VALUE 0
D1 0x01 (ch 0) 0x11 (ch 1) 0x21 (ch 2) 0x31 (ch 3) 0x41 (ch 4) 0x51 (ch 5) R/W Interrupt Enable (source level)
RLOSIE_n This flag will allow a loss of receive signal(for that channel) to send an interrupt to the Host when this bit is set. RLOLIE_n This flag will allow a loss of lock condition to send an interrupt to the Host when this bit is set. Reserved This bit is Reserved.
0
D2 D3 D4 D5 D6-D7 D0
0 0 0 0
PRBSERIE Set this bit to enable the interrupt when the PRBS _n error is detected. PRBSERC Set this bit to enable the interrupt when the PRBS NTIE_n error count register saturates. Reserved DMOIS_n If the Drive monitor circuot detects the absence of pulses for 128 consecutive cycles, t will set this interrupt status flag (if enabled) This bit is set on a change of state of the DMO circuit.
0
D1 0x02 (ch 0) Reset Interrupt 0x12 (ch 1) on Status 0x22 (ch 2) Read (source 0x32 (ch 3) level) 0x42 (ch 4) 0x52 (ch 5) D2
RLOSIS_n This flag will indicate a change of "loss of Receive signal" to the Host when this bit is set. RLOLIS_n This flag will allow a change in the loss of lock condition to send an interrupt to the Host when this bit is enabled.Loss of lock is defined as a difference of greater than 0.5% between the recovered clock and the channel's reference clock. Any change (return to lock) will trigger the interrupt status flag again. Reserved This bit is Reserved.
0 0
D3 D4 D5 D7-D6
0 0 0
PRBSERIS This bit is set when the PRBS error occurs. _n PRBSERC This bit is set when the PRBS error count register NTIS_n saturates. Reserved
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N
ADDRESS (HEX) TYPE REGISTER NAME BIT# D0 SYMBOL DMO_n DESCRIPTION This bit is set when no transitions on the TTIP/ TRING have been detected for 128 32 TxCLK periods.It will be cleared when pulses resume. This bit is set every time the receiver declares an LOS condition.It will be cleared when the signal is recognized again. This bit is set when the detected clock is greater than 0.5% oof frequency from the reference clock.By definition, the two frequencies are "not in lock" with each other. It will be cleared when they are "in lock" again.. This bit is Reserved. This bit is set when the receiver declares that the Analog signal has degraded to the point that the signal has been lost. This bit is set when no input signals have been received for 10 to 255 bit times in E3 or 100 to 250 bit times in DS3 or STS-1 modes.This is a complete lack of incoming pulses rather than signal attenuation (ALOS). It should be noted that this time period is built into the Analog detector for E3 mode. Even though DS3/STS-1 mode does not require analog detection level, but it is provided and could help to determine the "quality of the line" for DS/STS-1 applications.
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XRT73R06
REV. 1.0.0
DEFAULT VALUE 0
D1
RLOS_n
0
D2 0x03 (ch 0) 0x13 (ch 1) 0x23 (ch 2) 0x33 (ch 3) 0x43 (ch 4) 0x53 (ch 5) Read Alarm StaOnly tus
RLOL_n
0
D3 D4
Reserved ALOS_n
0 0
D5
DLOS_n
0
D6
PRBSLS_n This bit is set when the PRBS detector has been enabled and it is not in sync with the incoming data pattern. Once the sync is achieved, it will be cleared. Reserved
0
D7
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N
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DEFAULT VALUE 0
ADDRESS (HEX)
TYPE
REGISTER NAME
BIT# D0
SYMBOL TxLEV_n
DESCRIPTION This bit should be set when the transmitter is driving a line greater than 225 feet in the DS3 or STS-1 modes. It is not active in E3 mode.
D1
TxCLKINV Set this bit to sample the data on TPOS/TNEG pins _n on the rising edge of TxCLK.Default is to sample on the falling edge of TxCLK. TAOS_n This bit should be set to transmit a continuous "all ones" data pattern. Timing will come from TxCLK if available otherwise from channel refernce clock. Reserved INSPRBS_ This bit causes a single bit error to be inserted in the n transmitted PRBS pattern if the PRBS generator/ detector has been enabled. TxMON_n When set, this bit enables the DMO circuit to monitor its own channel's transmit driver. Otherwise, it uses the MTIP/MRING pins to monitor another channel or device. Reserved REQEN_n This bit enables the Receiver Equalizer. When set, the equalizer boosts the high frequency components of the signal to make up for cable losses. NOTE: See section 5.01 for detailed description. RxMON_n Set this bit to place the Receiver in the monitoring mode. In this mode, it can process signals (at RTIP/ RRING) with 20dB of flat loss. This mode allows the channel to act as monitor of aline without loading the circuit. LOSMUT_ When set, the data on RPOS/RNEG is forced to n zero when LOS occurs. Thus any residual noise on the line is not output as spurious data. NOTE: If this bit has been set, it will remain set evan after the LOS condition is cleared. RxCLKINV When this bit is set, RPOS and RNEG will change _n on the falling edge of RCLK.Default is for the data to change on the rising edge of RCLK and be sampled by the terminal equipment on the falling edge of RCLK. ALOSDIS_ This bit is set to disable the ALOS detector. This flag n and the DLOSDIS are normally used in diagnostic mode. Normal operation of DS3 and STS-1 would have ALOS disabled. DLOSDIS_ This bit disables the digital LOS detector. This would n normally be disabled in E3 mode as E3 is a function of the level of the input. Reserved
0
0x04 (ch 0) 0x14 (ch 1) 0x24 (ch 2) 0x34 (ch 3) 0x44 (ch 4) 0x54 (ch 5)
R/W
Transmit Control
D2
0
D3 D4
0
D5
0
D7-D6 D0
0
D1 0x05 (ch 0) 0x15 (ch 1) 0x25 (ch 2) 0x35 (ch 3) 0x45 (ch 4) 0x55 (ch 5) R/W Receive Control D2
0
0
D3
0
D4
0
D5
0
D7-D6
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N
ADDRESS (HEX) TYPE REGISTER NAME BIT# D0 SYMBOL SR/DR_n DESCRIPTION Setting this bit configures the Receiver and Transmitter in Single-Rail (NRZ) mode. NOTE: See section 4.0 for detailed description. Setting this bit configures the channel into STS-1 mode. NOTE: This bit field is ignored if the channel is configured to operate in E3 mode. Setting this bit configures the channel in E3 mode. Setting this bit configures the channel in Local Loopback mode. This bit along with LLB_n determine the diagnostic mode as shown in the table below.
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XRT73R06
REV. 1.0.0
DEFAULT VALUE 0
D1
STS-1/ DS3_n
0
D2 0x06 (ch 0) 0x16 (ch 1) 0x26 (ch 2) 0x36 (ch 3) 0x46 (ch 4) 0x56 (ch 5) R/W Block Control D3 D4
E3_n LLB_n RLB_n
0 0 0
RLB_n 0 0 1 1
LLB_n 0 1 0 1
Loopback Mode Normal Operation Analog Local Remote Digital
D5
PRBSEN_ Setting this bit enables the PRBS generator/detecn tor. When in E3 mode, an unframed 223-1 pattern is used. For DS3 and STS-1, unframed 215-1 pattern is used. This mode of operation will use TCLK for timing. One should insure that a stable frequency is provided. Looping this signal back to its own receive channel and using RCLK to generate TCLK will cause an unstable condition and should be avoided. CLKOUTE Set this bit to enable the CLKOUTs on a per channel N_n basis. The frequency of the output clock is dependent on the configuration of the channels, either E3, DS3 or STS-1. Reserved
0
D6
0
D7
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N
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DEFAULT VALUE 0 0 0 0 0
ADDRESS (HEX)
TYPE
REGISTER NAME
BIT# D0 D1 D2 D3
SYMBOL Reserved Reserved Reserved Reserved Reserved
DESCRIPTION This bit is Reserved. This bit is Reserved. This bit is Reserved. This bit is Reserved. This bit is Reserved. Reserved
0x07 (ch 0) 0x17 (ch 1) 0x27 (ch 2) 0x37 (ch 3) 0x47 (ch 4) 0x57 (ch 5)
R/W
D4 Jitter Attenuator D7-D5
59
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT 8.0 ELECTRICAL CHARACTERISTICS TABLE 19: ABSOLUTE MAXIMUM RATINGS
SYMBOL
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XRT73R06
REV. 1.0.0
PARAMETER Supply Voltage Input Voltage at any Pin Input current at any pin Storage Temperature Ambient Operating Temperature Thermal Resistance
MIN
MAX
UNITS
COMMENTS
VDD VIN IIN STEMP ATEMP Theta JA
-0.5 -0.5
6.0 5.5 100
V V mA
0 0 0
Note 1 Note 1 Note 1 Note 1 linear airflow 0 ft./min linear air flow 0ft/min (See Note 3 below)
-65 -40
150 85 23
C C
C/W
MLEVL
Exposure to Moisture
4
level
EIA/JEDEC JESD22-A112-A
ESD
ESD Rating
2000
V
Note 2
NOTES: 1. Exposure to or operating near the Min or Max values for extended period may cause permanent failure and impair reliability of the device. 2. ESD testing method is per MIL-STD-883D,M-3015.7 3. With Linear Air flow of 200 ft/min, reduce Theta JA by 20%, Theta JC is unchanged.
TABLE 20: DC ELECTRICAL CHARACTERISTICS:
SYMBOL
PARAMETER Digital Supply Voltage Analog Supply Voltage Supply current requirements Power Dissipation Input Low Voltage Input High Voltage Output Low Voltage, IOUT = - 4mA Output High Voltage, IOUT = 4 mA Input Leakage Current1 Input Capacitance Load Capacitance
MIN.
TYP.
MAX.
UNITS
DVDD AVDD ICC PDD VIL VIH VOL VOH IL CI CL
3.135 3.135
3.3 3.3 725 2.64
3.465 3.465 850 2.93 0.8
V V mA W V V V V
2.0
5.5 0.4
2.4 10 10 10
A pF pF
NOTES: 1. Not applicable for pins with pull-up or pull-down resistors. 2. The Digital inputs are TTL 5V compliant.
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XRT73R06
REV. 1.0.0
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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XRT73R06
REV. 1.0.0
APPENDIX A
TABLE 21: TRANSFORMER RECOMMENDATIONS
PARAMETER VALUE
Turns Ratio Primary Inductance Isolation Voltage Leakage Inductance
1:1 40 H 1500 Vrms 0.6 H
TABLE 22: TRANSFORMER DETAILS
PART NUMBER VENDOR INSULATION PACKAGE TYPE
PE-68629 PE-65966 PE-65967 T 3001 TG01-0406NS TTI 7601-SM
PULSE PULSE PULSE PULSE HALO TransPower
3000 V 1500 V 1500 V 1500 V 1500 V 1500 V
Large Thru-hole Small Thru-hole SMT SMT SMT SMT
TRANSFORMER VENDOR INFORMATION Pulse Corporate Office 12220 World Trade Drive San Diego, CA 92128 Tel: (858)-674-8100 FAX: (858)-674-8262 Europe 1 & 2 Huxley Road The Surrey Research Park Guildford, Surrey GU2 5RE United Kingdom Tel: 44-1483-401700 FAX: 44-1483-401701
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XRT73R06
REV. 1.0.0
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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Asia 150 Kampong Ampat #07-01/02 KA Centre Singapore 368324 Tel: 65-287-8998 Website: http://www.pulseeng.com Halo Electronics Corporate Office P.O. Box 5826 Redwood City, CA 94063 Tel: (650)568-5800 FAX: (650)568-6165 Email: info@haloelectronics.com Website: http://www.haloelectronics.com Transpower Technologies, Inc. Corporate Office Park Center West Building 9805 Double R Blvd, Suite # 100 Reno, NV 89511 (800)500-5930 or (775)852-0140 Email: info@trans-power.com Website: http://www.trans-power.com
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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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XRT73R06
REV. 1.0.0
ORDERING INFORMATION
PART NUMBER XRT73R06IB PACKAGE 217 Lead BGA (23 x 23 mm) OPERATING TEMPERATURE RANGE - 40C to + 85C
PACKAGE DIMENSIONS - 23 X 23 MM 217 LEAD BGA PACKAGE
BOTTOM VIEW (A1 corner feature is mfger option)
Note: The control dimension is in millimeter.
INCHES MIN MAX 0.067 0.098 0.016 0.028 0.012 0.024 0.039 0.047 0.898 0.913 0.800 BSC 0.780 0.795 0.024 0.035 0.050 BSC 10 20 MILLIMETERS MIN MAX 1.70 2.50 0.40 0.70 0.30 0.60 1.00 1.20 22.80 23.20 20.32 BSC 19.80 20.20 0.60 0.90 1.27 BSC 10 20
SYMBOL A A1 A2 A3 D D1 D2 b e
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XRT73R06
REV. 1.0.0
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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REVISIONS
REVISION P1.0.0 1.0.0 DATE 07/15/04 12/16/04 COMMENTS First release of the preliminary datasheet. Release to production. Added Power Dissapation and Power Supply Current to electrical.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2004 EXAR Corporation Datasheet December 2004. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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