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Low Power PCM Line Interface
October 2000-1
XRT56L85
FEATURES D Low Power (Typical 14mA) D Single +5V Supply D Up to 2.048 Mbps Operation in Both TX and RX Directions D Receiver Input can be: Balanced Transformer Coupled Capacitively (Twisted Pair) Single Coaxial Capacitive Coupling
APPLICATIONS D T1 and CEPT Interfaces D CPI D DMI
GENERAL DESCRIPTION The XRT56L85 is a PCM line interface chip. It consists of both transmit and receive circuitry in a DIL 18 pin package. The maximum bit rate the chip can handle is 2.048 Mbps and the signal level to the received can be ORDERING INFORMATION
Part No. XRT56L85P XRT56L85D
attenuated by 10dB of cable loss at half the bit rate. Total current consumption is between 12-16mA at +5V.
Package 18 Lead 300 Mil PDIP 18 Lead 300 Mil JEDEC SOIC
Operating Temperature Range -40C to +85C -40C to +85C
BLOCK DIAGRAM
PDC 1 Positive Threshold Comparator + - Negative Threshold Comparator - +
TTL Buffer 11 RPOS TTL Buffer 8 4 RCLK TE
RXDATA+ 2 RXDATA- 3
Peak Detector
TTL Buffer
10 RNEG 6 TANK BIAS
Bias RXVCC 9 RXGND 7 TXVCC 18 TPOS 17 TCLK 16 TNEG 12 TXGND 14
Bias TTL Buffer
5
BIAS
15 TXDATA+ TTL Buffer 13 TXDATA-
Figure 1. Block Diagram
Rev. 2.11
E2000
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017 1
XRT56L85
PIN CONFIGURATION
PDC RXDATA+ RXDATATE BIAS TANK BIAS RXGND RCLK RXVCC
1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10
TXVCC TPOS TCLK TXDATA+ TXGND TXDATATNEG RPOS RNEG
PDC RXDATA+ RXDATATE BIAS TANK BIAS RXGND RCLK RXVCC
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
TXVCC TPOS TCLK TXDATA+ TXGND TXDATATNEG RPOS RNEG
18 Lead PDIP (0.300")
18 Lead SOIC (Jedec, 0.300")
PIN DESCRIPTION
Pin # 1 2 Symbol PDC RXDATA+ I Type Description Peak Detector Capacitor. This pin should be connected to a 0.1F capacitor Receive Analog Input Positive. The AMI signal received from the line is applied at this and the RX DATA(-) pin. Data and clock from the signal applied at these two pins recovered and output on the RPOS, RNEG, and RCLK pins, respectively. Receive Analog Input Negative. See the description for RX DATA(+). LC Tank Excitation Output. This output connects to one side of the tank circuitry. Bias. This pin should be tied to ground through a 0.1F capacitor. Tank Reference. The tank circuitry is biased via this output. Receiver Ground. To minimize ground interference a separate pin is used to ground the receiver section. O Recovered Receive Clock. Recovered clock signal from the AMI signal received at the RX DATA(+) and RX DATA(-) pins. This signal is output to the terminal equipment. Receive Supply Voltage. 5V supply voltage for the Receive Section. O Receive Negative Data Output. A signal at this pin corresponds to the receipt of a negative pulse on the RX DATA(+)/RX DATA(-) pins. This TTL compatible signal is output to the terminal equipment. Receive Positive Data Output. A signal at this pin corresponds to the receipt of a positive pulse on the RX DATA(+)/RX DATA pins. This TTL compatible signal is outputed to the terminal equipment. Transmit Negative Data Input. TTL input for a negative polarity pulse (the negative portion of the AMI pulse train) to be transmitted to the line via the TX DATA(+) and TX DATA pins. Transmit Negative Data Output. This pin, along with the TX DATA(+) pin, forms a differential driver output, this is used to drive AMI data down the line via a transformer. Note: This is an open-collector output. Transmit Ground. O I I Transmit Positive Data Output. Please see description for TX DATA(-). Transmit Clock. TPOS and TNEG are sampled on the rising edge of TCLK. Transmit Positive Data Input. TTL input for a positive polarity pulse (the positive portion of the AMI pulse train) to be transmitted to the line via the TX DATA(+) and TX DATA(-) pins. Transmit Supply Voltage. 5V supply voltage to the transmit section.
3 4 5 6 7 8 9 10
RXDATATE BIAS TANK BIAS RXGND RCLK RXVCC RNEG
I O O
11
RPOS
O
12 13
TNEG TXDATA-
I O
14 15 16 17 18
TXGND TXDATA+ TCLK TPOS TXVcc
Rev. 2.11 2
XRT56L85
ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = 5V 5%, TA = -40C to +85C, Unless Otherwise Specified
Parameters DC Electrical Characteristics Supply Voltage Supply Current Receiver Section Tank Drive Current Clock Output Low Clock Output High Data Output Low Data Output High Transmitter Section Driver Output Low Output Leakage Current Input High Voltage Input Low Voltage Input Low Current Input High Current Output Low Current AC Electrical Characteristices Receiver Section Input Level Loss Input Signal Alarm Level Input Impedance at 2.048MHz Clock Duty Cycle Clock Rise & Fall Time Data Pulse Width 35 35 6 0.6 2.5 50 20 50 65 40 75 6.6 Vpp Vpp k % ns % of clock period ns ns ns ns Measured Between Pin 2 & 3 Measured Between Pin 2 & 3 Alarm on Pull Data/Clock Output High Measured Between Pin 2 & 3 With Sinewave Input Measured at Pin 8 at 2.0V DC Level Measured at Pin 8, CL = 15pF Measured at Pin 10 & 11 At 1V DC Level, Cable Loss = dB 2.2 0.8 -1.6 40 -30 0.6 0.9 1.2 100 V A V V mA A mA Measured at Pin 13 & 15, IOL =-40mA Measured in Off State Output Pull-up to +20V Measured at Pin 12, 16 & 17 IOL = -40mA, VOL = 1.0V Measured at Pin 12, 16 & 17 Output Off Measured at Pin 12, 16 & 17 Input Low Voltage = 0.4V Measured at Pin 12, 16 & 17 Input Low Voltage = 0.4V Measured at Pin 13 & 15 VOL= 1.0V 3.0 3.0 300 500 0.3 3.6 0.3 3.6 0.6 700 0.6 A V V V V Measured at Pin 4, VCC= 5V Measured at Pin 8, IOL = 1.6mA Measured at Pin 8, IOH =400A Measured at Pin 10 & 11, IOL =1.6mA Measured at Pin 10 & 11, IOH =400A 4.75 5 14 5.25 16 V mA Total Current to Pin 9 & Pin 18 (Transmitter Outputs Open and All Ones Pattern) Min. Typ. Max. Unit Conditions
Transmitter Section Pulse Width at 2.048MHz Output Rise Time Output Fall Time Output Fall Imbalance Rev. 2.11 3 234 244 12 12 2.5 264 25 25 Measured at Pin 13 & 15 Figure 3 Figure 3 Figure 3 At 50% Output Level
XRT56L85
ABSOLUTE MAXIMUM RATINGS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20V SYSTEM DESCRIPTION The Receiver The incoming bipolar PCM signal, which is attenuated and distorted by the cable is applied to the receiver input, consisting of the RX DATA(+) and RX DATA(-) pins, either through a balanced transformer, a balanced capacitively coupled terminal or a single-ended coaxial cable (see Figure 5). A peak detector following the input generates a DC reference for the positive and negative threshold comparator (to extract the positive and negative data pulses). Information on the positive and negative data pulses is outputed as TTL compatible signals at pins RPOS and RNEG, respectively. More specifically, an output signal present at the RPOS pin indicates that a positive pulse was received at the RX DATA(+)/RX DATA(-) pins, from the incoming bipolar data stream. Likewise an output signal present at the RNEG pin indicates that a negative pulse was received at the RX DATA(+)/RX DATA(-) pins. This conversion from the bipolar signal to TTL compatible signals allows for digital processing of the clock and data signals by the terminal equipment. An example of the waveforms of the TTL compatible recovered clock and data as output by the receiver portion of the chip is presented in Figure 2, Figure 3 and Figure 5. A tank circuit tuned to the Storage Temperature . . . . . . . . . . . . . -65C to 150C . appropriate frequency is added externally to provide the appropriate frequency-selective filtering of the received clock signal. The Transmitter The transmitter portion of the chip receives TTL compatible signals and transmits a corresponding bipolar data stream down the line (See Figure 5). TPOS and TNEG are TTL compatible signals that dictate the polarity of the pulse to be generated and transmitted on the output bipolar data stream. Both TPOS and TNEG inputs are sampled by the rising edge of the transmit clock, TCLK. The TX DATA(+) and TX DATA(-) pins form a differential driver output, this is used to drive AMI data down the line via a transformer. The TX DATA(+) and TX DATA(-) pins are open-collector outputs. When a logic "high" signal is applied to the TPOS pin, a positive pulse (the positive portion of the bipolar data stream) will be transmitted to the line via the TX DATA(+) O/P and TX DATA(-) O/P pins. Likewise, when a logic "high" signal is applied to the TNEG pin, a negative pulse will be transmitted to the line via the TX DATA(+) and TX DATA(-) pins. An illustration of the key waveforms involved in this TTL to AMI conversion process, in the Transmitter portion of the chip is presented in Figure 4.
Rev. 2.11 4
XRT56L85
VCC=5V
0.1F
100 Output CL=15pF
Pin 13 & 15 2.048Mbps Pulse Generator Input Pin 9 &18
XRT56L85
Pin 12, 16, 17 Pin 7 &14 0V 0V
Figure 2.
244ns <5ns 90% Input Pulse from Generator 1.5V 10% 90% 1.5V 10% 15ns Typ. Output from Pin 13 or Pin 15 15ns Typ. +5V 0V <5ns
3V
Vol Fall Time Pulse Width Rise Time
Figure 3.
Rev. 2.11 5
XRT56L85
RXDATA+
RCLK Output At Pin 8 RPOS Output At Pin 11 RNEG Output At Pin 10
TCLK Clock To Pin 16 TPOS To Pin 17
TNEG To Pin 12
Bipolar Signal At Transformer Output
Figure 4. Receiver Timing Diagram With 1-1-1-1-1-1 Pattern
Rev. 2.11 6
XRT56L85
RCACON
2 0.1F 75 0.1F 3 5 0.1F 2 3 T1 120 RING 1:1 0.1F 3 5 6 4.7F TANK BIAS TCLK 16 TPOS 17 12 TNEG 11 RPOS 10 RNEG RCLK 8 TCLK TPOS TNEG RPOS RNEG RCLK L C 5 2 4 18 2 3 5 RXDATA+ RXDATABIAS T.E. VCC TXDATA+ TXDATA15 56 13 56 PE65415 1:1:1 T2 TIP RING VCC
TIP
XRT56L85
TGND
14
TIP 120 RING 0.1F 0.1F 0.1F
2
VCC 0.1F 0.1F 9 RVCC 1 PDC 7 RGND U1 56L85TA
3 5
0.1F
L=Tank Coil AIE 415-0804 (1.544 and 2.048 Mbs) Device L C 1.544Mbs 60H 175pF 2.048Mbs 60H 100pF
Figure 5. Application Circuit for XRT56L85
Rev. 2.11 7
XRT56L85
18 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP)
Rev. 1.00
18 1 D A L
10 9 E1 E
A2
Seating Plane
A1 B e B1
eA eB
C
INCHES SYMBOL A A1 A2 B B1 C D E E1 e eA eB L MIN 0.145 0.015 0.115 0.014 0.030 0.008 0.845 0.300 0.240 MAX 0.210 0.070 0.195 0.024 0.070 0.014 0.925 0.325 0.280
MILLIMETERS MIN 3.68 0.38 2.92 0.36 0.76 0.20 21.46 7.62 6.10 MAX 5.33 1.78 4.95 0.56 1.78 0.38 23.50 8.26 7.11
0.100 BSC 0.300 BSC 0.310 0.115 0 0.430 0.160 15
2.54 BSC 7.62 BSC 7.87 2.92 0 10.92 4.06 15
Note: The control dimension is the inch column
Rev. 2.11 8
XRT56L85
18 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC)
Rev. 1.00
D
18
10
E
1 9
H
C Seating Plane e B A1 L A
INCHES SYMBOL A A1 B C D E e H L MIN 0.093 0.004 0.013 0.009 0.447 0.291 0.394 0.016 0 MAX 0.104 0.012 0.020 0.013 0.463 0.299 0.419 0.050 8
MILLIMETERS MIN 2.35 0.10 0.33 0.23 11.35 7.40 10.00 0.40 0 MAX 2.65 0.30 0.51 0.32 11.75 7.60 10.65 1.27 8
0.050 BSC
1.27 BSC
Note: The control dimension is the millimeter column
Rev. 2.11 9
XRT56L85 Notes
Rev. 2.11 10
XRT56L85 Notes
Rev. 2.11 11
XRT56L85
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2000 EXAR Corporation Datasheet October 2000 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.11 12

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