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MC74LVX259 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter
with LSTTL-Compatible Inputs
The MC74LVX259 is an 8-bit Addressable Latch fabricated with silicon gate CMOS technology. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The LVX259 is designed for general purpose storage applications in digital systems. The device has four modes of operation as shown in the mode selection table. In the addressable latch mode, the data on Data In is written into the addressed latch. The addressed latch follows the data input with all non-addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the Data or Address inputs. In the one-of-eight decoding or demultiplexing mode, the addressed output follows the state of Data In with all other outputs in the LOW state. In the Reset mode, all outputs are LOW and unaffected by the address and data inputs. When operating the LVX259 as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode. The MC74LVX259 input structure provides protection when voltages up to 7.0 V are applied, regardless of the supply voltage. This allows the MC74LVX259 to be used to interface 5.0 V circuits to 3.0 V circuits.
Features http://onsemi.com MARKING DIAGRAMS
16 SOIC-16 D SUFFIX CASE 751B 1 LVX259 AWLYWW
16 TSSOP-16 DT SUFFIX CASE 948F 1 LVX 259 ALYW
16 SOEIAJ-16 M SUFFIX CASE 966 1 LVX259 ALYW
* * * * * * * * * *
High Speed: tPD = 7.0 ns (Typ) at VCC = 3.3 V Low Power Dissipation: ICC = 2 mA (Max) at TA = 25C High Noise Immunity: VNIH = VNIL = 28% VCC CMOS-Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model > 2000 V; Machine Model > 200 V Pb-Free Packages are Available*
A WL or L Y WW or W
= = = =
Assembly Location Wafer Lot Year Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
March, 2005 - Rev. 2
Publication Order Number: MC74LVX259/D
MC74LVX259
A0 A1 A2 Q0 Q1 Q2 Q3 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC A0 RESET ENABLE A2 DATA IN Q7 Q6 Q5 Q4 RESET ENABLE 15 14 DATA IN 13 ADDRESS INPUTS A1 4 1 2 3 5 6 7 9 10 11 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS
PIN 16 = VCC PIN 8 = GND
Figure 1. Pin Assignment
Figure 2. Logic Diagram
A0 A1 A2
1 2 3
BIN/OCT 1 2 4 0 1 2 3 4
4 5 6 7 8 10 11 12
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
A0 A1 A2
1 2 3
DMUX 0 0 G 7 2 0 1 2 3 4
4 5 6 7 8 10 11 12
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
13 14 15
ID EN R
5 6 7
13 14 15
ID EN R
5 6 7
Figure 3. IEC Logic Symbol
MODE SELECTION TABLE Enable
L H L H
LATCH SELECTION TABLE Address Inputs
C L L L L H H H H B L L H H L L H H A L H L H L H L H
Reset
H H L L
Mode
Addressable Latch Memory 8-Line Demultiplexer Reset
Latch Addressed
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
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MC74LVX259
DATA INPUT
13
D
4
Q0
D
5
Q1
D
6
Q2
D A0
7
Q3
ADDRESS INPUTS
A1
3 TO 8 DECODER D 9 Q4
A2
D ENABLE 14
10
Q5
D
11
Q6
D
12
Q7
RESET
15
Figure 4. Expanded Logic Diagram
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MC74LVX259
MAXIMUM RATINGS
Symbol VCC VIN VOUT IIK IOK IOUT ICC PD TSTG VESD Positive DC Supply Voltage Digital Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Range ESD Withstand Voltage Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) Above VCC and Below GND at 125C (Note 4) SOIC Package TSSOP SOIC Package TSSOP Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC +0.5 -20 $20 $25 $75 200 180 -65 to +150 >2000 >200 >2000 $300 143 164 Unit V V V mA mA mA mA mW C V
ILATCHUP qJA
Latchup Performance Thermal Resistance, Junction-to-Ambient
mA C/W
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Tested to EIA/JESD22-A114-A 2. Tested to EIA/JESD22-A115-A 3. Tested to JESD22-C101-A 4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN VOUT TA tr, tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature Range, all Package Types Input Rise or Fall Time VCC = 3.3 V + 0.3 V Characteristics Min 2.0 0 0 -40 0 Max 3.6 5.5 VCC 85 100 Unit V V V C ns/V
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MC74LVX259
DC CHARACTERISTICS (Voltages Referenced to GND)
VCC Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage High-Level Output Voltage IOH = -50 mA IOH = -50 mA IOH = -4 mA VOL Low-Level Output Voltage IOL = 50 mA IOL = 50 mA IOL = 4 mA IIN ICC Input Leakage Current Maximum Quiescent Supply Current (per package) VIN = 5.5 V or GND VIN = VCC or GND Condition (V) 2.0 3.0 3.6 2.0 3.0 3.6 2.0 3.0 3.0 2.0 3.0 3.0 0 to 3.6 3.6 Min 0.75 VCC 0.7 VCC 0.7 VCC - - - 1.9 2.9 2.58 - - - - 1.0 TA = 25C Typ - - - - - - 2.0 3.0 - 0.0 0.0 - - 1.0 Max - - - 0.25 VCC 0.3 VCC 0.3 VCC - - - 0.1 0.1 0.36 0.1 2.0 -40C TA 85C Min 0.75 VCC 0.7 VCC 0.7 VCC - - - 1.9 2.9 2.48 - - - - - Max - - - 0.25 VCC 0.3 VCC 0.3 VCC - - - 0.1 0.1 0.44 1.0 - mA mA V Unit V
VIL
V
VOH
V
II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III I II III I I I I IIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III I I III I I I I I I II III I II III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III I II III II III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III I I IIIIIIIIIIIIIIIIIIIIIIII I II III I II III I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III I I II II III I II III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III I II III I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I II III I II III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns
Symbol tPLH, tPHL Parameter Test Conditions TA = 25C Typ 6.3 9.0 5.6 8.0 6.3 9.0 5.6 8.0 6.3 9.0 5.6 8.0 6.3 9.0 5.6 8.0 6 -40C TA 85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 - Max Min - - - - - - - - - - - - - - - - - Max Unit ns Maximum Propagation Delay, Data to Output (Figures 5 and 9) VCC = 2.7 V CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF CL = 15pF CL = 50pF 9.0 14.0 8.0 12.0 9.0 14.0 8.0 12.0 9.0 14.0 9.0 12.0 9.0 14.0 9.0 12.0 10 12.0 15.0 VCC = 3.3 V 0.3 V VCC = 2.7 V 11.0 14.0 tPLH, tPHL Maximum Propagation Delay, Address Select to Output (Figures 6 and 9) 12.0 15.0 ns VCC = 3.3 V 0.3 V VCC = 2.7 V 11.0 14.0 tPLH, tPHL Maximum Propagation Delay, Enable to Output (Figures 7 and 9) 12.0 15.0 ns VCC = 3.3 V 0.3 V VCC = 2.7 V 11.0 14.0 tPHL Maximum Propogation Delay, Reset to Output (Figures 7 and 9) 12.0 15.0 ns VCC = 3.3 V 0.3 V 11.0 14.0 10 CIN Maximum Input Capacitance pF Typical @ 25C, VCC = 3.3 V 30 CPD Power Dissipation Capacitance (Note 5) pF 5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
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MC74LVX259
TIMING REQUIREMENTS Input tr = tf = 3.0 ns
III I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIII II II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIII IIIIIIIIIIIIIIIIIIIIIIIII I III I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III III IIIIIIIIIIIIIIIIIIIIIIIII IIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III III IIIIIIIIIIIIIIIIIIIIIIIII IIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III III IIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I III III IIIIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIII IIIII I II I I I I I
TA = 25C Typ TA = 85CIII Max Unit Symbol tw Parameter Test Conditions Min 4.5 4.5 4.0 3.0 2.0 2.0 Max Min Minimum Pulse Width, Reset or Enable (Figure 8) VCC = 2.7 V -III 5.0III ns - - -III 5.0III - - VCC = 3.3 V 0.3 V VCC = 2.7 V VCC = 3.3 V 0.3 V VCC = 2.7 V VCC = 3.3 V 0.3 V VCC = 2.7 V VCC = 3.3 V 0.3 V tsu Minimum Setup Time, Address or Data to Enable (Figure 8) Minimum Hold Time, Enable to Address or Data (Figure 7 or 8) Maximum Input, Rise and Fall Times (Figure 5) -III 4.0III ns - - -III 3.0III - - th -III 2.0III ns - - -III 2.0III - - - - tr, tf , -III 400 -III -III 300 -III ns 300III 300III VCC tr 50% DATA IN GND tPLH 50% OUTPUT Q OUTPUT Q tPHL 50% tPHL 50% tPHL tf DATA IN GND VCC GND VCC GND VCC ADDRESS SELECT 50%
Figure 5. Switching Waveform
VCC DATA IN tw ENABLE 50% tPHL OUTPUT Q 50% 50% tPHL GN D tw GND VCC
Figure 6. Switching Waveform
VCC DATA IN tw RESET 50% GND tPHL OUTPUT Q 50% GND VCC
Figure 7. Switching Waveform
Figure 8. Switching Waveform
TEST POINT DATA IN OR ADDRESS SELECT VCC 50% th(H) tsu ENABLE 50% GND *Includes all probe and jig capacitance tsu th(H) GND VCC DEVICE UNDER TEST OUTPUT CL *
Figure 9. Switching Waveform
Figure 10. Test Circuit
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MC74LVX259
ORDERING INFORMATION
Device MC74LVX259D MC74LVX259DG MC74LVX259DR2 MC74LVX259DR2G MC74LVX259DT MC74LVX259DTR2 MC74LVX259M MC74LVX259MG MC74LVX259MEL MC74LVX259MELG Package SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) TSSOP-16* TSSOP-16* SOEIAJ-16 SOEIAJ-16 (Pb-Free) SOEIAJ-16 SOEIAJ-16 (Pb-Free) Shipping 48 Units / Rail 48 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel 50 Units / Rail 50 Units / Rail 2000 Tape & Reel 2000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
EMBOSSED CARRIER DIMENSIONS (See Notes 6 and 7)
Tape Size
8 mm
B1 Max
4.35 mm (0.179")
D
1.5 mm + 0.1 -0.0 (0.059" ( 0 004 +0.004 -0.0)
D1
1.0 mm Min (0.179") 1.5 mm Min (0.060)
E
1.75 mm 0.1 (0.069 0.004") )
F
3.5 mm 0.5 (1.38 0.002") 5.5 mm 0.5 (0.217 0.002")
K
2.4 mm Max (0.094") 6.4 mm Max (0.252")
P
4.0 mm 0.10 (0.157 0.004") 4.0 mm 0.10 (0.157 0.004") 8.0 mm 0.10 (0.315 0.004") 4.0 mm 0.10 (0.157 0.004") 8.0 mm 0.10 (0.315 0.004") 12.0 mm 0.10 (0.472 0.004") 16.0 mm 0.10 (0.63 0.004")
P0
4.0 mm 0.1 (0.157 0.004") )
P2
2.0 mm 0.1 (0.079 0.004") )
R
25 mm (0.98")
T
0.6 mm (0.024)
W
8.3 mm (0.327)
12 mm
8.2 mm (0.323")
30 mm (1.18")
12.0 mm 0.3 (0.470 0.012")
16 mm
12.1 mm (0.476")
7.5 mm 0.10 (0.295 0.004")
7.9 mm Max (0.311")
16.3 mm (0.642)
24 mm
20.1 mm (0.791")
11.5 mm 0.10 (0.453 0.004")
11.9 mm Max (0.468")
24.3 mm (0.957)
6. Metric Dimensions Govern-English are in parentheses for reference only. 7. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. The component cannot rotate more than 10 within the determined cavity
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MC74LVX259
PACKAGE DIMENSIONS
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE A
16X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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EEE CCC EEE CCC
SECTION N-N
-W-
DIM A B C D F G H J J1 K K1 L M
MC74LVX259
SOEIAJ-16 M SUFFIX CASE 966-01 ISSUE O
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74LVX259
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC74LVX259/D

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