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EM65570S
68COM/98SEG 65K Color STN LCD Drivers
Product Specification
DOC. VERSION 1.0
ELAN MICROELECTRONICS CORP.
April 2006
Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation.
Copyright (c) 2006 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, TAIWAN 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA: Elan Information Technology Group (U.S.A.) 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel: +1 408 366-8225 Fax: +1 408 366-8220
Europe: Elan Microelectronics Corp. (Europe) Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com
Shanghai: Elan Microelectronics Shanghai , Ltd. 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 21 5080-3866 Fax: +86 21 5080-4600
Contents
Contents
1 2 3 4 5 6 General Description .................................................................................................. 1 Feature ....................................................................................................................... 1 Applications............................................................................................................... 2 Pin Configuration ...................................................................................................... 3 Functional Block Diagram...................................................................................... 13 5.1 System Block Diagram ..................................................................................... 13 Pin Descriptions...................................................................................................... 14 6.1 6.2 6.3 6.4 7 Power Supply Pins ........................................................................................... 14 LCD Power Supply Circuit Pins........................................................................ 14 System Bus Pins .............................................................................................. 15 LCD Drive Circuit Signals................................................................................. 16
6.5 Oscillating Circuit Pin ....................................................................................... 16 Function Description .............................................................................................. 17 7.1 MPU Interface .................................................................................................. 17
7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 Reset Pin Description (RESB) ..........................................................................17 Interface Type Selection....................................................................................17 Parallel Input .....................................................................................................17 Read/Write functions of Register and display RAM ..........................................17 Serial Interface ..................................................................................................18 4-wire Serial Interface .......................................................................................18 3-wire Type Serial Interface...............................................................................18
7.2 7.3 7.4 7.5 7.6 7.7 7.8
Data Write to Display RAM and Control Register............................................. 19 Display RAM Read and Control Register Read ............................................... 19 16-bit Data Access to Display RAM.................................................................. 20 Fast Burst RAM Write Function ........................................................................ 21 Common Output Mode Selection ..................................................................... 21 Display RAM Access Using Windows Function................................................ 22 Relationship between Display RAM and Address ............................................ 23
7.8.1 7.8.2 7.8.3 Gradation Mode (256 Color), (C256=1, 65K=0)................................................23 Gradation Mode (4096 colors), (C256=0, 65K=0).............................................24 Gradation mode (65K Color), (C256=0, 65K=1) ...............................................26
7.9
Display Data Structure and Gradation Control ................................................. 27
7.10 Gradation LSB Control .................................................................................... 27 7.11 Generation of the Alternate Signal (M) ............................................................ 27 7.12 Output Timing of LCD Driver ........................................................................... 28 7.13 Oscillating Circuit............................................................................................. 28 7.14 Power Supply Circuit ....................................................................................... 29 7.15 Booster Circuit................................................................................................. 29
Product Specification (V1.0) 04.18.2006 * iii
Contents
7.16 Electronic Volume............................................................................................ 29 7.17 Voltage Generation Circuit .............................................................................. 30 7.18 2-D Graphic Acceleration Engine .................................................................... 31 7.19 OTP Function .................................................................................................. 36 7.20 Partial Display Function................................................................................... 38 7.21 Discharge Circuit ............................................................................................. 39 7.22 Scroll Function................................................................................................. 39 7.23 Initialization...................................................................................................... 44 7.24 Precaution when Setting Power ON and Power OFF ..................................... 44
7.24.1 When Using the Built-in Power Supply .............................................................44 7.24.2 Power Supply Rising Time ................................................................................45
7.25 Example of Registers Setting .......................................................................... 45
7.25.1 Initialization........................................................................................................45 7.25.2 Display Data ......................................................................................................46 7.25.3 Power OFF ........................................................................................................46
8
Control Registers .................................................................................................... 47 8.1 8.2 Control Register ............................................................................................... 47 Control Registers Functions ............................................................................. 53
8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.8 8.2.9 8.2.10 8.2.11 8.2.12 8.2.13 8.2.14 8.2.15 8.2.16 8.2.17 8.2.18 8.2.19 8.2.20 8.2.21 8.2.22 8.2.23 8.2.24 8.2.25 8.2.26 8.2.27 8.2.28 X Address Register (AX) ...................................................................................53 Y Address Register (AY)....................................................................................53 n Line Alternate Register (N).............................................................................54 Display Control (1) Register ..............................................................................55 Display Control (2) Register ..............................................................................56 LCD Duty (DS) ..................................................................................................60 Booster Setup (VU) ...........................................................................................61 Bias Setting Register (B)...................................................................................61 Register Access Control....................................................................................61 Graphic Start X Address ....................................................................................62 Graphic End X Address.....................................................................................62 Graphic Start Y Address ....................................................................................62 Graphic End Y Address .....................................................................................62 Draw Rectangle Control ....................................................................................63 Line Color R ......................................................................................................64 Line Color G ......................................................................................................64 Line Color B.......................................................................................................64 Fill Color R.........................................................................................................65 Fill Color G ........................................................................................................65 Fill Color B.........................................................................................................65 Dim, Copy & Clear Functions Control ...............................................................66 Copy Destination X Address .............................................................................67 Copy Destination Y Address..............................................................................67 Scroll Top Address.............................................................................................67 Scroll Bottom Address .......................................................................................67 Scroll Specified Address....................................................................................68
Product Specification (V1.0) 04.18.2006
iv *
Contents
8.2.29 8.2.30 8.2.31 8.2.32 8.2.33 8.2.34 8.2.35 8.2.36 8.2.37 8.2.38 8.2.39 8.2.40 8.2.41 8.2.42 8.2.43 8.2.44 8.2.45 8.2.46 8.2.47
Scroll Start Address ...........................................................................................68 Scroll Mode Select ............................................................................................69 RAM Data Writing Select Control ......................................................................69 Display Start Common.......................................................................................71 Temperature Compensation Set .......................................................................71 Display Select Control .......................................................................................72 RAM Data Length Set .......................................................................................73 Electronic Volume Register ...............................................................................73 Internal Register Read Address ........................................................................74 RC Oscillator Resistance Ratio.........................................................................75 Booster Frequency Control ...............................................................................75 Windows End X Address...................................................................................76 Windows End Y Address ...................................................................................76 Line Reverse Start Address...............................................................................77 Line Reverse End Address................................................................................77 Line Reverse Control.........................................................................................77 Regulator Multiple Ratio Control .......................................................................79 OTP Mode Select Register................................................................................79 Vop Calibration Offset Register.........................................................................80
9
Absolute Maximum Rating ..................................................................................... 81 9.1 Absolute Maximum Ratings.............................................................................. 81 9.2 Recommended Operating Conditions .............................................................. 81 DC electrical characteristics .................................................................................. 82 Ac Electrical Characteristics.................................................................................. 85 11.1 80-family MCU write timing ............................................................................. 85 11.2 80-family MCU Read Timing ........................................................................... 86 11.3 68-family MCU Write Timing............................................................................ 88 11.4 68-family MCU Read Timing ........................................................................... 89 11.5 Serial Interface Timing Diagram ...................................................................... 90 11.6 Clock input timing ............................................................................................ 92 11.7 Reset Timing ................................................................................................... 92 Application Circuit .................................................................................................. 93 12.1 Connection to 80-family MCU ......................................................................... 93 12.2 Connection to 68-family MCU ......................................................................... 93 12.3 Connection to the MCU with Serial Interface .................................................. 94 Tray Information ...................................................................................................... 95 13.1 Tray Outline Dimensions ................................................................................. 95
10 11
12
13
Product Specification (V1.0) 04.18.2006
*v
Contents
Specification Revision History
Doc. Version 0.1 Initial version 1. Modified the pad drawing and pad sequence 0.2 2. Modified the Serial mode AC timing 3. Modified the DC electrical characteristics 4. Modified the pin dimensions table 1. Corrected the error in the Control Register Table 0.3 2. Modified the OTP programming time 3. Modified the AC timing 1.0 Removed the Preliminary mark on the background of every page. 2006/4/18 2006/04/15 2006/01/04 Revision Description Date 2005/12/06
vi *
Product Specification (V1.0) 04.18.2006
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
1
General Description
EM65570S is one of the industry's most advanced wide-screen STN-LCD drivers for 65K-color display. It also has a built-in display RAM, a power supply circuit for LCD drive, an LCD controller circuit, support for LCD cell tolerance compensation of VLCD and temperature compensation. It also supports OTP function for programming information to tune VLCD offset voltage to get the best contrast, hence enhancing the compact system design. Its partial display function"1 contributes to the reduction of power consumption.
2
Feature
65K-color display LCD outputs: Segment 98RGB (294 outputs); Common 68 outputs Display RAM capacity: 98x68x16=106624 bits Built-in display RAM and power supply circuit Partial display functions Bus connection with 80-family/68-family MPU/ELAN MPU Logic power supply voltage: 2.2 to 3.3 V Analog power supply voltage: 2.4 to 3.3 V LCD driving voltage: 4.5 to 16 V Booster: 2 to 5 times Fast burst-RAM write function Screen scroll function Graphic function OTP function for tuning LCD operating voltage Vop System Write cycle: 200 ns Package:
Part Number EM65570SAGH Package Gold bumped chip Description NA Package Information NA
Note: The EM65570S series has the following sub-codes, depending on their shapes. H: Bare chip (Aluminum pad without bump); GH: Gold bumped chip F: COF package; T: TAB (TCP) package
Example: EM65570SAGH EM65570S: Elan number; A: Package Version; GH: Gold bumped chip
1
A function that allows the device to utilize only part of the screen, thus reducing power consumption. *1
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
3
Applications
Mobile phone DECT phone Cordless phone Toy & Game display
2*
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
4
Pin Configuration
With the Elan logo at the left corner (as shown in the figure), Pin 1 is at the bottom left corner.
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
Figure 1 Pin Configuration NOTE *3
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
Mark U-Left D-Left
Coordinate (X, Y) -7043, 290.27 -7043, -289.58
Mark U-Right D-Right
Coordinate (X, Y) 7042.5, 290.27 7042.5, -289.58
D-Left and U-Right:
U-Left and D-Right:
40 100m 20 40 100m 40 20 40 100m 100m
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Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers Pin Dimensions
Item Chip Size 1 , 126 , 133 , 513 2 ~ 4 , 6 , 10 , 29 ~ 35 , 124 ~ 125 , 134 ~ 512 5 , 7 ~ 9 , 11 ~ 27 28 Bump Size 36 ~ 39 , 42 , 45 , 48 ~ 58 , 61 ~ 62 , 65 , 68 , 71 ~ 123 40 ~ 41 , 43 ~ 44 , 46 ~ 47 , 59 ~ 60 , 63 ~ 64 , 66 ~ 67 , 69 ~ 70 129 , 130 , 516 , 517 127 , 132 , 514 , 519 128 , 131 , 515 , 518 7 ~ 9 , 11 ~ 27 29 ~ 35 36 ~ 37 , 38 ~ 39 , 48 ~ 50 , 51 ~ 55 , 56 ~ 58 , 61 ~ 62 , 71 ~ 72 , 73 ~ 77 , 78 ~ 82 , 83 ~ 91 , 92 ~ 96 , 97 ~ 123 Pad Pitch 40 ~ 41 , 43 ~ 44 , 46 ~ 47 , 59 ~ 60 , 63 ~ 64 , 66 ~ 67 , 69 ~ 70 135 ~ 168 , 170 ~ 361 , 363 ~ 464 , 478 ~ 511 465 ~ 476 Minimum pitch Die thickness (excluding bumps) Bump Height Bump coplanar within die Minimum Bump Gap Coordinate Origin 20 1 mil (500 25 m) 17 3 m 2m 13 m Chip center 75 30 210 30 85 Pad No. X 14680 17 17 49 81 70 60 165 93 93 64 32 m Size Y 1170 94 165 94 94 43 43 17 94 27 Unit
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
*5
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
Recommended COG ITO Traces Resistor
Interface V0~V4 CAP1+,CAP1-,CAP2+,CAP2-,CAP3+, CAP3-, CAP4+, V2x, Vout VDD1~VDD3,VEE VSS1~VSS5 WRB, RDB, CSB,..., D0~D7 RESB Max=3K Max=5~10K Max=50 ITO Traces Resistances
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Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
Coordinate X Y -7153.28 -466 -6970.2 -430.645 -6760.2 -430.645 -6673 -427.145 -6625 -462.35 -6577 -427.145 -6529 -462.35 -6465 -462.35 -6401 -462.35 -6353 -427.145 -6305 -462.35 -6241 -462.35 -6177 -462.35 -6113 -462.35 -6049 -462.35 -5985 -462.35 -5921 -462.35 -5857 -462.35 -5793 -462.35 -5729 -462.35 -5665 -462.35 -5601 -462.35 -5537 -462.35 -5473 -462.35 -5409 -462.35 -5345 -462.35 -5281 -462.35 -5201 -462.35 -5137 -427.145 -5105 -427.145 -5073 -427.145 -5041 -427.145 -5009 -427.145 -4977 -427.145 -4945 -427.145 -4878.25 -487.5 -4793.25 -487.5 -4360.61 -487.5 -4275.61 -487.5 -4195.61 -487.5 -4120.61 -487.5 -3715.08 -487.5 -3635.08 -487.5 -3560.08 -487.5 -3154.8 -487.5 -3074.8 -487.5 -2999.8 -487.5 -2536.96 -487.5 -2451.96 -487.5 -2366.96 -487.5 Coordinate X Y -2032.37 -487.5 -1947.37 -487.5 -1862.37 -487.5 -1777.37 -487.5 -1692.37 -487.5 -1357.78 -487.5 -1272.78 -487.5 -1187.78 -487.5 -1107.78 -487.5 -1032.78 -487.5 -629.01 -487.5 -544.01 -487.5 -138.48 -487.5 -63.48 -487.5 16.52 -487.5 422.05 -487.5 497.05 -487.5 577.05 -487.5 1101.5 -487.5 1176.5 -487.5 1256.5 -487.5 1341.5 -487.5 1695.05 -487.5 1780.05 -487.5 1865.05 -487.5 1950.05 -487.5 2035.05 -487.5 2392.78 -487.5 2477.78 -487.5 2562.78 -487.5 2647.78 -487.5 2732.78 -487.5 3213.75 -487.5 3298.75 -487.5 3383.75 -487.5 3468.75 -487.5 3553.75 -487.5 3638.75 -487.5 3723.75 -487.5 3808.75 -487.5 3893.75 -487.5 3989.45 -487.5 4074.45 -487.5 4159.45 -487.5 4244.45 -487.5 4329.45 -487.5 4425.45 -487.5 4510.45 -487.5 4595.45 -487.5 4680.45 -487.5
Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Pad Name NC1 NC2 NC3 NC4 CSB RESB RS CK WRB VSS2 RDB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VDD1 PS CSL M86 CKS TEST VSS2 DUMMY VOUT VOUT VOUT VOUT NC5 NC6 NC7 NC8 NC9 NC10 CAP3+ CAP3+ CAP3+ CAP3CAP3-
Pin No 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Pad Name CAP3CAP3CAP3CAP2CAP2CAP2CAP2CAP2CAP2+ CAP2+ CAP2+ CAP4+ CAP4+ CAP4+ NC11 NC12 NC13 CAP1+ CAP1+ CAP1+ CAP1CAP1CAP1CAP1CAP1V2X V2X V2X V2X V2X VEE VEE VEE VEE VDD2 VDD3 VSS1 VSS1 VSS1 VSS1 VSS1 VSS2 VSS2 VSS3 VSS3 VSS4 VSS5 VSS5 VSS5 VSS5
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
*7
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
Coordinate X Y 4765.45 -487.5 4850.45 -487.5 4935.45 -487.5 5020.45 -487.5 5105.45 -487.5 5190.45 -487.5 5275.45 -487.5 5360.45 -487.5 5445.45 -487.5 5530.45 -487.5 5615.45 -487.5 5700.45 -487.5 5785.45 -487.5 5870.45 -487.5 5955.45 -487.5 6040.45 -487.5 6125.45 -487.5 6210.45 -487.5 6295.45 -487.5 6380.45 -487.5 6465.45 -487.5 6550.45 -487.5 6635.45 -487.5 6760.2 -430.645 6970.2 -430.645 7153.28 -466 7221.39 -466.25 7221.39 -392.98 7185.645 -135 7185.645 135 7221.39 392.98 7221.39 466.25 7153.28 466 7000.2 430.645 6820.2 430.645 6790.2 430.645 6760.2 430.645 6730.2 430.645 6700.2 430.645 6670.2 430.645 6640.2 430.645 6610.2 430.645 6580.2 430.645 6550.2 430.645 6520.2 430.645 6490.2 430.645 6460.2 430.645 6430.2 430.645 6400.2 430.645 6370.2 430.645 Coordinate X Y 6340.2 430.645 6310.2 430.645 6280.2 430.645 6250.2 430.645 6220.2 430.645 6190.2 430.645 6160.2 430.645 6130.2 430.645 6100.2 430.645 6070.2 430.645 6040.2 430.645 6010.2 430.645 5980.2 430.645 5950.2 430.645 5920.2 430.645 5890.2 430.645 5860.2 430.645 5830.2 430.645 5795.7 430.645 5761.2 430.645 5731.2 430.645 5701.2 430.645 5671.2 430.645 5641.2 430.645 5611.2 430.645 5581.2 430.645 5551.2 430.645 5521.2 430.645 5491.2 430.645 5461.2 430.645 5431.2 430.645 5401.2 430.645 5371.2 430.645 5341.2 430.645 5311.2 430.645 5281.2 430.645 5251.2 430.645 5221.2 430.645 5191.2 430.645 5161.2 430.645 5131.2 430.645 5101.2 430.645 5071.2 430.645 5041.2 430.645 5011.2 430.645 4981.2 430.645 4951.2 430.645 4921.2 430.645 4891.2 430.645 4861.2 430.645
Pin No 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Pad Name V0 V0 V0 V0 V0 V0 V0 V1 V1 V1 V1 V1 V1 V2 V2 V2 V3 V3 V3 V4 V4 V4 V4 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 COM66 COM64 COM62 COM60 COM58 COM56 COM54 COM52 COM50 COM48 COM46 COM44 COM42 COM40 COM38 COM36
Pin No 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Pad Name COM34 COM32 COM30 COM28 COM26 COM24 COM22 COM20 COM18 COM16 COM14 COM12 COM10 COM8 COM6 COM4 COM2 COM0 NC25 SEGA0 SEGB0 SEGC0 SEGA1 SEGB1 SEGC1 SEGA2 SEGB2 SEGC2 SEGA3 SEGB3 SEGC3 SEGA4 SEGB4 SEGC4 SEGA5 SEGB5 SEGC5 SEGA6 SEGB6 SEGC6 SEGA7 SEGB7 SEGC7 SEGA8 SEGB8 SEGC8 SEGA9 SEGB9 SEGC9 SEGA10
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Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
Coordinate X Y 4831.2 430.645 4801.2 430.645 4771.2 430.645 4741.2 430.645 4711.2 430.645 4681.2 430.645 4651.2 430.645 4621.2 430.645 4591.2 430.645 4561.2 430.645 4531.2 430.645 4501.2 430.645 4471.2 430.645 4441.2 430.645 4411.2 430.645 4381.2 430.645 4351.2 430.645 4321.2 430.645 4291.2 430.645 4261.2 430.645 4231.2 430.645 4201.2 430.645 4171.2 430.645 4141.2 430.645 4111.2 430.645 4081.2 430.645 4051.2 430.645 4021.2 430.645 3991.2 430.645 3961.2 430.645 3931.2 430.645 3901.2 430.645 3871.2 430.645 3841.2 430.645 3811.2 430.645 3781.2 430.645 3751.2 430.645 3721.2 430.645 3691.2 430.645 3661.2 430.645 3631.2 430.645 3601.2 430.645 3571.2 430.645 3541.2 430.645 3511.2 430.645 3481.2 430.645 3451.2 430.645 3421.2 430.645 3391.2 430.645 3361.2 430.645 Coordinate X Y 3331.2 430.645 3301.2 430.645 3271.2 430.645 3241.2 430.645 3211.2 430.645 3181.2 430.645 3151.2 430.645 3121.2 430.645 3091.2 430.645 3061.2 430.645 3031.2 430.645 3001.2 430.645 2971.2 430.645 2941.2 430.645 2911.2 430.645 2881.2 430.645 2851.2 430.645 2821.2 430.645 2791.2 430.645 2761.2 430.645 2731.2 430.645 2701.2 430.645 2671.2 430.645 2641.2 430.645 2611.2 430.645 2581.2 430.645 2551.2 430.645 2521.2 430.645 2491.2 430.645 2461.2 430.645 2431.2 430.645 2401.2 430.645 2371.2 430.645 2341.2 430.645 2311.2 430.645 2281.2 430.645 2251.2 430.645 2221.2 430.645 2191.2 430.645 2161.2 430.645 2131.2 430.645 2101.2 430.645 2071.2 430.645 2041.2 430.645 2011.2 430.645 1981.2 430.645 1951.2 430.645 1921.2 430.645 1891.2 430.645 1861.2 430.645 *9
Pin No 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250
Pad Name SEGB10 SEGC10 SEGA11 SEGB11 SEGC11 SEGA12 SEGB12 SEGC12 SEGA13 SEGB13 SEGC13 SEGA14 SEGB14 SEGC14 SEGA15 SEGB15 SEGC15 SEGA16 SEGB16 SEGC16 SEGA17 SEGB17 SEGC17 SEGA18 SEGB18 SEGC18 SEGA19 SEGB19 SEGC19 SEGA20 SEGB20 SEGC20 SEGA21 SEGB21 SEGC21 SEGA22 SEGB22 SEGC22 SEGA23 SEGB23 SEGC23 SEGA24 SEGB24 SEGC24 SEGA25 SEGB25 SEGC25 SEGA26 SEGB26 SEGC26
PIN NO 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300
Pad Name SEGA27 SEGB27 SEGC27 SEGA28 SEGB28 SEGC28 SEGA29 SEGB29 SEGC29 SEGA30 SEGB30 SEGC30 SEGA31 SEGB31 SEGC31 SEGA32 SEGB32 SEGC32 SEGA33 SEGB33 SEGC33 SEGA34 SEGB34 SEGC34 SEGA35 SEGB35 SEGC35 SEGA36 SEGB36 SEGC36 SEGA37 SEGB37 SEGC37 SEGA38 SEGB38 SEGC38 SEGA39 SEGB39 SEGC39 SEGA40 SEGB40 SEGC40 SEGA41 SEGB41 SEGC41 SEGA42 SEGB42 SEGC42 SEGA43 SEGB43
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
Coordinate X Y 1831.2 430.645 1801.2 430.645 1771.2 430.645 1741.2 430.645 1711.2 430.645 1681.2 430.645 1651.2 430.645 1621.2 430.645 1591.2 430.645 1561.2 430.645 1531.2 430.645 1501.2 430.645 1471.2 430.645 1441.2 430.645 1411.2 430.645 1381.2 430.645 1351.2 430.645 1321.2 430.645 1291.2 430.645 1261.2 430.645 1231.2 430.645 1201.2 430.645 1171.2 430.645 1141.2 430.645 1111.2 430.645 1081.2 430.645 1051.2 430.645 1021.2 430.645 991.2 430.645 961.2 430.645 931.2 430.645 901.2 430.645 871.2 430.645 841.2 430.645 811.2 430.645 781.2 430.645 751.2 430.645 721.2 430.645 691.2 430.645 661.2 430.645 631.2 430.645 601.2 430.645 571.2 430.645 541.2 430.645 511.2 430.645 481.2 430.645 451.2 430.645 421.2 430.645 391.2 430.645 361.2 430.645 Coordinate X 331.2 301.2 271.2 241.2 211.2 181.2 151.2 121.2 91.2 61.2 31.2 0 -31.2 -61.2 -91.2 -121.2 -151.2 -181.2 -211.2 -241.2 -271.2 -301.2 -331.2 -361.2 -391.2 -421.2 -451.2 -481.2 -511.2 -541.2 -571.2 -601.2 -631.2 -661.2 -691.2 -721.2 -751.2 -781.2 -811.2 -841.2 -871.2 -901.2 -931.2 -961.2 -991.2 -1021.2 -1051.2 -1081.2 -1111.2 -1141.2
Pin No 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 10 *
Pad Name SEGC43 SEGA44 SEGB44 SEGC44 SEGA45 SEGB45 SEGC45 SEGA46 SEGB46 SEGC46 SEGA47 SEGB47 SEGC47 SEGA48 SEGB48 SEGC48 SEGA49 SEGB49 SEGC49 SEGA50 SEGB50 SEGC50 SEGA51 SEGB51 SEGC51 SEGA52 SEGB52 SEGC52 SEGA53 SEGB53 SEGC53 SEGA54 SEGB54 SEGC54 SEGA55 SEGB55 SEGC55 SEGA56 SEGB56 SEGC56 SEGA57 SEGB57 SEGC57 SEGA58 SEGB58 SEGC58 SEGA59 SEGB59 SEGC59 SEGA60
Pin No 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400
Pad Name SEGB60 SEGC60 SEGA61 SEGB61 SEGC61 SEGA62 SEGB62 SEGC62 SEGA63 SEGB63 SEGC63 NC26 SEGA64 SEGB64 SEGC64 SEGA65 SEGB65 SEGC65 SEGA66 SEGB66 SEGC66 SEGA67 SEGB67 SEGC67 SEGA68 SEGB68 SEGC68 SEGA69 SEGB69 SEGC69 SEGA70 SEGB70 SEGC70 SEGA71 SEGB71 SEGC71 SEGA72 SEGB72 SEGC72 SEGA73 SEGB73 SEGC73 SEGA74 SEGB74 SEGC74 SEGA75 SEGB75 SEGC75 SEGA76 SEGB76
Y 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
Coordinate X Y -1171.2 430.645 -1201.2 430.645 -1231.2 430.645 -1261.2 430.645 -1291.2 430.645 -1321.2 430.645 -1351.2 430.645 -1381.2 430.645 -1411.2 430.645 -1441.2 430.645 -1471.2 430.645 -1501.2 430.645 -1531.2 430.645 -1561.2 430.645 -1591.2 430.645 -1621.2 430.645 -1651.2 430.645 -1681.2 430.645 -1711.2 430.645 -1741.2 430.645 -1771.2 430.645 -1801.2 430.645 -1831.2 430.645 -1861.2 430.645 -1891.2 430.645 -1921.2 430.645 -1951.2 430.645 -1981.2 430.645 -2011.2 430.645 -2041.2 430.645 -2071.2 430.645 -2101.2 430.645 -2131.2 430.645 -2161.2 430.645 -2191.2 430.645 -2221.2 430.645 -2251.2 430.645 -2281.2 430.645 -2311.2 430.645 -2341.2 430.645 -2371.2 430.645 -2401.2 430.645 -2431.2 430.645 -2461.2 430.645 -2491.2 430.645 -2521.2 430.645 -2551.2 430.645 -2581.2 430.645 -2611.2 430.645 -2641.2 430.645 Coordinate X Y -2671.2 430.645 -2701.2 430.645 -2731.2 430.645 -2761.2 430.645 -2791.2 430.645 -2821.2 430.645 -2851.2 430.645 -2881.2 430.645 -2911.2 430.645 -2941.2 430.645 -2971.2 430.645 -3001.2 430.645 -3031.2 430.645 -3061.2 430.645 -3271.2 430.645 -3481.2 430.645 -3691.2 430.645 -3901.2 430.645 -4111.2 430.645 -4321.2 430.645 -4531.2 430.645 -4741.2 430.645 -4951.2 430.645 -5161.2 430.645 -5371.2 430.645 -5581.2 430.645 -5795.7 430.645 -5830.2 430.645 -5860.2 430.645 -5890.2 430.645 -5920.2 430.645 -5950.2 430.645 -5980.2 430.645 -6010.2 430.645 -6040.2 430.645 -6070.2 430.645 -6100.2 430.645 -6130.2 430.645 -6160.2 430.645 -6190.2 430.645 -6220.2 430.645 -6250.2 430.645 -6280.2 430.645 -6310.2 430.645 -6340.2 430.645 -6370.2 430.645 -6400.2 430.645 -6430.2 430.645 -6460.2 430.645 -6490.2 430.645 * 11
Pin No 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450
Pad Name SEGC76 SEGA77 SEGB77 SEGC77 SEGA78 SEGB78 SEGC78 SEGA79 SEGB79 SEGC79 SEGA80 SEGB80 SEGC80 SEGA81 SEGB81 SEGC81 SEGA82 SEGB82 SEGC82 SEGA83 SEGB83 SEGC83 SEGA84 SEGB84 SEGC84 SEGA85 SEGB85 SEGC85 SEGA86 SEGB86 SEGC86 SEGA87 SEGB87 SEGC87 SEGA88 SEGB88 SEGC88 SEGA89 SEGB89 SEGC89 SEGA90 SEGB90 SEGC90 SEGA91 SEGB91 SEGC91 SEGA92 SEGB92 SEGC92 SEGA93
Pin No 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500
Pad Name SEGB93 SEGC93 SEGA94 SEGB94 SEGC94 SEGA95 SEGB95 SEGC95 SEGA96 SEGB96 SEGC96 SEGA97 SEGB97 SEGC97 NC27 NC28 NC29 NC30 NC31 NC32 NC33 NC34 NC35 NC36 NC37 NC38 NC39 COM1 COM3 COM5 COM7 COM9 COM11 COM13 COM15 COM17 COM19 COM21 COM23 COM25 COM27 COM29 COM31 COM33 COM35 COM37 COM39 COM41 COM43 COM45
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
Coordinate X -6520.2 -6550.2 -6580.2 -6610.2 -6640.2 -6670.2 -6700.2 -6730.2 -6760.2 -6790.2 -6820.2 -7000.2 -7153.28 -7221.39 -7221.39 -7185.645 -7185.645 -7221.39 -7221.39 Y 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 430.645 466 466.25 392.98 135 -135 -392.98 -466.25 Coordinate X Y
Pin No 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519
Pad Name COM47 COM49 COM51 COM53 COM55 COM57 COM59 COM61 COM63 COM65 COM67 NC40 NC41 NC42 NC43 NC44 NC45 NC46 NC47
Pin No
Pad Name
12 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
5
Functional Block Diagram
5.1 System Block Diagram
SEGC97 SEGB97 SEGA97 SEGC0 SEGB0 SEGA0 COM0 COM67
VDD V0 V1 V2 V3 V4 VSS (VSSH,VSSL) CAP1CAP1+ CAP2CAP2+ CAP3CAP3+ CAP4+ V2X VOUT VEE
Common Driver Shift Register
Segment Driver Gradation Selection Circuit Data Latch
Line Address Decoder
Display Line Register
Display Line Counter
Y Address Decoder
Y Address Register
Y Address Counter
Voltage Converter
Booster Circuit
Display RAM (DDRAM) 98 X 68 X (5+6+5) bits
X Address Decoder RAM Interface D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4/SPOL D3/SMODE D2 D1/SDA D0/SCL X Address Counter Input/Output Buffer
X Address Register
Alternation Circuit
Bus Holder
Instruction Decoder
Register Read
MPU Interface
OSC
Display Timing Gen.
CSL CSB RS RDB WRB P/S M86 RESB TEST (E) (R/WB)
CK CKS
Figure 5 System Block Diagram
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
* 13
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
6
Pin Descriptions
6.1 Power Supply Pins
Symbol I/O Power Supply Power Supply Power Supply Power Supply Description Power supply pin for logic circuit to +2.2 to 3.3V Ground pin for logic circuit, connect to 0V Ground pin for high voltage circuit, connected to 0V Bias power supply pin for LCD drive voltage When the internal power supply circuit is active, these voltages are generated by the built-in booster and voltage converter. Then, must connect capacitor each to VSS.
VDD1-VDD3 VSS2-VSS4 VSS1 VSS5 V0-V4
6.2 LCD Power Supply Circuit Pins
Symbol CAP1+ CAP1CAP2+ CAP2CAP3+ CAP3CAP4+ VEE VOUT V2X I/O O O O O O O O Power Supply O O Description Connecting pin for the built in booster's capacitor + side. The capacitor is connected between CAP1- and CAP1+. Connecting pin for the built in booster's capacitor - side. The capacitor is connected between CAP1- and CAP1+. Connecting pin for the built in booster's capacitor + side. The capacitor is connected between CAP2- and CAP2+. Connecting pin for the built in booster's capacitor - side. The capacitor is connected between CAP2- and CAP2+. Connecting pin for the built in booster's capacitor + side. The capacitor is connected between CAP3- and CAP3+. Connecting pin for the built in booster's capacitor - side. The capacitor is connected between CAP3- and CAP3+. Connecting pin for the built in booster's capacitor + side. The capacitor is connected between CAP2- and CAP4+. Voltage supply pin for booster circuit. Usually the same voltage level as VDD. In the case of TCP, draw it as a separate terminal. Output pin of boosted voltage in the built-in booster. The capacitor must be connected between this pin and VSS. Output pin which is equal to 2 x VEE. The capacitor must be connected between this pin and VSS.
14 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
6.3 System Bus Pins
Symbol RESB I/O I Description Reset input pin. When RESB is "L", initialization is executed. Data bus / Signal interface related pins. When parallel interface is selected (P/S = "H"), The D7-D0 are 8-bits bi-directional data bus, connect to MPU data bus. When serial interface is selected (P/S = "L"), D0 and D1 (SCL, SDA) are used as serial interface pins. SCL: Input pin for data transfer clock SDA: Serial data input pin SMODE: Serial transfer mode select pin SPOL: RS pole select pin when 3-wires serial interface is selected. SDA data is latched at the rising edge of SCL. Internal serial/parallel conversion into 8-bit data occurs at the rising edge of 8th clock of SCL After completing data transferring, or when making no access, be sure to set SCL to "L". Useless pins (D7~D0) must be fixed to "H" or "L" on serial transfer mode. 8-bit bi-directional bus. Connected to MPU data bus. Used as data bus for upper 8-pins in the 16-bits access mode. Useless pins (D15~D8) must be fixed to "H" or "L" on 8-bits access mode. Chip Select input pin. CSB = "L": accepts access from MPU CSB = "H": denies access from MPU RAM/Register select input pin. RS = "0": D7-D0 are display RAM data RS = "1": D7-D0 are control register data Read/Write control pin Select 80-family MPU type (M86 = "L") The RDB is a data read signal. When RDB is "L", D7-D0 are in an output status. Select 68-family MPU type (M86 = "H") R/WB = "H": When E is "H", D7-D0 are in an output status. R/WB = "L": The data on D7-D0 are latched at falling edge of the E signal. Read/Write control pin Select 80-family MPU type (M86 = "L") The WRB is a data write signal. The data on D7-D0 are latched at rising edge of the WRB signal. Select 68-family MPU type (M86 = "H") Read/Write control input pin. R/W = "H": Read R/W = "L": Write MPU interface type selecting input pin. M86 = "H": 68-family interface M86 = "L": 80-family interface Fixed at either "H" or "L" For testing. Fix to "L". "Floating" Parallel/Serial interface select pin. P/S P/S I Chip select Data identification Data Read/Write Serial clock H CSB RS D0-D7 RDB, WRB L CSB RS SDA Write only SCL P/S = "H": For parallel interface. P/S = "L": For serial interface. Fix D15-D5 pins are Hi-Z, RDB and WRB pins to either "H" or "L". Common output mode selecting input pin. CSL = "H": COM0, COM2, COM4, ... , COM66 & COM1, COM3, COM5, ... , COM67 CSL = "L": COM0, COM1, COM2, ... , COM65, COM66, COM67 * 15
D0/SCL D1/SDA D2 D3/SMODE D4/SPOL D5-D7
I/O
D8-D15
I/O
CSB
I
RS
I
RDB (E)
I
WRB (R/WB)
I
M86 TEST DUMMY
I I
I
CSL
I
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
6.4 LCD Drive Circuit Signals
Symbol I/O Description Segment output pins for LCD drives. According to the data of the Display RAM data, non-lighted at "0", lighted at "1" (Normal Mode). non-lighted at "1", lighted at "0" (Reverse Mode) and, by a combination of M signal and display data, one signal level among V0,V2,V3 and VSS signal levels are selected. SEGA0-A97 SEGB0-B97 SEGC0-C97 O
M Signal (internal) Display RAM Data Normal Mode Reverse Mode V2 V0 V0 V2 V3 VSS VSS V3
Common output pins for LCD drivers. By a combination of the scanning data and M signal, one signal level among V0, V1, V4 and VSS signal level is selected. Data COM0COM67 O H L H L M H H L L Output level VSS V1 V0 V4
6.5 Oscillating Circuit Pin
Symbol CKS I/O I Description Display timing clock source select input pin. CKS = "H": Use external clock from CK pin. CKS = "L": Use internal oscillated clock. External clock input pin for display timing (CKS=1) or internal clock output pin for display timing (CKS=0). When using internal oscillated clock, CK must be floating (CKS=0)
CK
I/O
16 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
7
Function Description
7.1 MPU Interface
7.1.1 Reset Pin Description (RESB)
Holding the RESB low for at least 150s, then EM65570S accept this reset command.
RESB
TL > 150 uS
7.1.2 Interface Type Selection
The EM65570S transfers data through 8-bit parallel I/O (D7-D0), 16-bit parallel I/O (D15-D0) or serial data input (SDA, SCL). The parallel interface or serial interface can select by state of P/S pin. When serial interface is selected, data reading cannot be performed, only data writing can operate.
P/S H L I/F Type Parallel Serial CSB CSB CSB RS RS RS RDB RDB WRB WRB M86 M86 SDA SDA SCL SCL Data D7~D0 (D15~D0) -
7.1.3 Parallel Input
When parallel interface is selected with the P/S pin, the EM65570S allows data to be transferred in parallel to an 8-bit/16-bit MPU through the data bus. For the 8-bit/16-bit MPU, either the 80-family MPU interface or the 68-family MPU interface can be selected with the M86 pin.
M86 H L MPU Type 68-family MPU 80-family MPU CSB CSB CSB RS RS RS RDB E RDB WRB R/WB WRB Data D7~D0 (D15~D0) D0~D7 (D15~D0)
7.1.4 Read/Write functions of Register and display RAM
The EM65570S have four read/write functions at parallel interface mode. Each read/write function selecting by combinations of RS, RDB and WRB signals.
RS 1 1 0 0 68-family R/WB 1 0 1 0 0 1 0 1 80-family RDB WRB 1 0 1 0 Read internal Register Write internal Register Read display data Write display data * 17 Function
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
7.1.5 Serial Interface
EM65570S has two types serial interface, namely, 3-wire type serial interface; and 4-wire type serial interface, both are determined by the SMODE pin. SMODE = "L": 4-wires serial interface SMODE = "H": 3-wires serial interface
7.1.6 4-wire Serial Interface
When chip select is active (CSB = "L"), 4-wires type serial interface can work through the SDA and SCL input pins. When chip select is inactive (CSB = "H"), the internal shift register and counter are reset in the initial condition. Serial data SDA are input sequentially in order of D7 to D0 at the rising of serial clock (SCL) and are converted into 8-bit parallel data (by serial to parallel conversion) at the rising edge of the 8th serial clock, being processed in accordance with the data. The identification whether are serial data inputs (SDA) are display data or control register data is judged by input to RS pin. RS = "L": display RAM data RS = "H": control register data After completing 8-bit data transfer, or when making no access, be sure to set serial clock input (SCL) to "L". Cares of SDA and SCL signals against external noise should be taken in board writing. To prevent transfer error due to external noise, release chip select (CSB = "H") every completion of 8-bit data transferring.
CSB RS SDA SCL
1 2 3 4 5 6 7 8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 7-1 4-wire Type Serial Interface
7.1.7 3-wire Type Serial Interface
When chip select is active (CSB = "L"), 3-wires type serial interface can work through the SDA and SCL input pins. When chip select is inactive (CSB = "H"), the internal shift register and counter are reset in the initial condition. Serial data SDA are input sequentially in order of RS, D7 to D0 at the rising edge of serial clock (SCL) and are converter into 9-bit parallel data (by serial to parallel conversion) at the rising edge of the 9th serial clock.
18 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
The identification whether the serial data inputs (SDA) are display data or control register data is determined by first serial input data (RS) and SPOL pin as follows:
SPOL = "0" RS 0 1 Display RAM/Register Display RAM Data Control Register Data RS 0 1 SPOL = "1" Display RAM/Register Control Register Data Display RAM Data
After completing 9-bits data transfer, or when making no access, be sure to set serial clock input (SCL) to "L". Cares of SDA and SCL signals against external noise should be taken in board wiring. To prevent transfer error due to external noise, release chip select (CSB = "H") every completion of 9-bit data transferring.
CSB SDA SCL
1 2 3 4 5 6 7 8 9
RS
D7
D6
D5
D4
D3
D2
D1
D0
Figure 7-2 3-Wires Type Serial Interface
7.2 Data Write to Display RAM and Control Register
The data write to display RAM and Control Register use almost same procedure, only different setting of RS that select access object. RS = "L": Display RAM data RS = "H": Control register data In the case of the 80-family MPU, the data is written at the rising edge of WRB. In the case of the 68-family MPU, the data is written at the falling edge of signal E.
D0~D7 (D0~D15) WRB RS Wrie to which Wrie to control register Wrie to display RAM
Data0 Data1 Data2 Data3 Data4
Figure 7-3 Data write operation
7.3 Display RAM Read and Control Register Read
In the case of display RAM read operation, need dummy read one time. The designated address data are not output to read operation immediately after the address set to AX or AY register, but are output when the second data read. Dummy read is always required one time after address set and write cycle.
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
* 19
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
Read display RAM operation
W RB D0~D7 (D0~D15) RDB RS
n
Address set (AX,AY) Address = n
***
Dummy Read
n
Data Read Address=n
n+1
Data Read Address=n+1
n+2
Data Read Address=n+2
Figure 7-4 Read display RAM operation
The EM65570S can read the control registers, in case of control register read operation, data bus upper nibble (D7-D4) use for register address (0 to FH). In maximum, 16 registers can access directly. But number of register is more than 16 registers. Therefore, EM65570S has register bank control. The RE register is set bank number to access. And the RE address is 0FH, in any bank can access RE register. It is need 4-steps to read the specific register in maximum case. (1) Write 04H to RE register for access to RA register. (2) Writes specific register address to RA register. (3) Write specific register bank to RE register. (4) Read specific register contents.
WRB D0~D7 RDB RS
Figure 7-5 Register Read Operation
04H
Bank number write to RE for RA
addr
Address write to RA
bank
Bank number write to RE
data
read specific register
7.4 16-bit Data Access to Display RAM
The EM65570S correspond to 8-bits and 16-bits bus size access. The data bus size can select by WLS register. WLS = "0": 8-bit bus size WLS = "1": 16-bit bus size For 6-bit access mode, low-byte data bus (D7~D0) is used to access the control register. High byte data bus (D15~D8) are not used in internal circuit. When the control register is read using 16-bit bus, register values output to D3-D0 and D15-D4 output "H".
20 * Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
7.5 Fast Burst RAM Write Function
The EM65570S has built-in fast burst RAM write function, because the burst mode transfer which transfers 32-bits data block at once, so it can decrease half the access time needed for common standard RAM write function (16 bits data bus). The burst RAM write function is suitable for frequently data rewriting such as displaying color animation.
Microcontroller databus [0:15] EM65573S EM65570 Internal Buffer 1 Internal Buffer 2 databus [0:31] 0x00H 0x01H 0x02H 0x03H .......
2 bytes
2 bytes
Display RAM
Figure 7-6 Burst RAM Write Operation
NOTE Fast Burst RAM Write Function is used effectively only in horizontal RAM data writing mode, that is, RDWS[2]=0
7.6 Common Output Mode Selection
The EM65570S has two common output modes. You can select the correct common output mode to fit LCM ITO layout type. The common output mode can select by `CSL' pin option. CSL="0": COM0, COM1, COM2, ... , COM65, COM66, COM67 CSL="1": COM0, COM2, ... , COM66 & COM1, COM3, ... , COM67
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
* 21
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
7.7 Display RAM Access Using Windows Function
The EM65570S has window area setting command for specified display RAM area access. In using the window function, it is required to set up two positions, X and Y address. It is also needed to set up auto increment mode (AXI="1", AYI="1"). Two position means window start position and window end position. The window start position's X and Y address set to normal X address (AX) and Y address (AY) registers. The window end position's X and Y address set to Window X End Address (EX) and Window Y End Address (EY) register. In window function access, can use modify write access with set to AIM="1". In case of using window function access, the following registers should be set before accessing the RAM. WIN = "1", AXI="1", AYI="1" X Address, Y Address, Window X End Address, Window Y End Address The following address conditions should also be kept. Window end X address (EX) Window end Y address (EY) Window start X address (AX) Window start Y address (AY)
X Direction
The Window accessed area X,Y Start Address
Y D ir ec ti on
X,Y End Address
The entire RAM display area (shaded + Window accessed areas)
22 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
7.8 Relationship between Display RAM and Address
The EM65570S execute address conversion that depends on control register setting. In case of auto increment mode, usually AX register is added one. For instance when REF and AXI are both "1", AX register is added one, but effective X address seems decrement because of address conversion. The effective Y address uses AY register values as it is.
7.8.1 Gradation Mode (256 Color), (C256=1, 65K=0)
8-bit mode (WLS=0)
HSW ABS REF SWAP * * * * 0 1 0 1 D0 D1 D2 X Address / Data Bus / Segment Assignment X=00H X=61H D3 D4 D5 D6 D7 D0 D1 D2 X=61H X=00H D3 D4 D5 D6 D6 SEG A97 SEG B97 SEG B96 SEG C96 * 23 SEG C97 SEG C97 D4 D5 D7 D7
SEG A0
SEG B0
SEG C0
SEG A97
HSW ABS REF * * * * 0 1
SWAP 1 0 D0 D1 D2
X Address / Data Bus / Segment Assignment X=00H X=61H D3 D4 D5 D6 D7 D0 D1 D2 SEG C96 SEG C97 X=61H X=00H D3 SEG B97 X=30H X=00H D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 SEG A97 SEG B97 SEG A96 SEG A97
SEG C0
SEG B0
16-bit mode(WLS=1)
HSW ABS REF SWAP * * 0 0 * * 1 1 X Address / Data Bus / Segment Assignment X=00H X=30H X=30H X=00H D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 SEG A96 SEG B96
SEG A0
SEG B0
SEG C0
SEG A1
SEG B1
HSW ABS * * * *
REF SWAP 0 1 1 0
X Address / Data Bus / Segment Assign X=00H X=30H D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
SEG A1
SEG B1
SEG C1
SEG A0
SEG B0
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
SEG C0
SEG C1
SEG A0
SEG C97
SEG B97
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
7.8.2 Gradation Mode (4096 colors), (C256=0, 65K=0)
8 bits mode (WLS="0")
HSW ABS REF SWAP 0 0 * * 0 1 0 1 D0 X=00H X=C2H D1 D2 D3 D0 D1 D2 X Address / Data Bus / Segment Assign X=01H X=C3H D3 D4 D5 D6 D7 D0 X=C2H X=00H D1 D2 D3 D0 D1 D2 X=C3H X=01H D3 D4 D5 D5 D5 D1 D5 D6 D6 D6 D2 D6 D7 D7 D3 D7 D7
SEG A0
SEG B0
SEG C0
SEG A97
SEG B97
HSW ABS REF SWAP 0 0 * * 0 1 1 0 D0 X=00H X=C2H D1 D2 D3 D0 D1
X Address / Data Bus / Segment Assign X=01H X=C3H D2 D3 D4 D5 D6 D7 D0 X=C2H X=00H D1 D2 D3 D0 D1 D2 X=C3H X=01H D3 D3 D7 D3 D4 D4 D0 D4
SEG C97
SEG B97
SEG C0
SEG B0
HSW ABS REF SWAP 1 * 0 0 D0 D1 D2 X=00H D3 D4 D5
X Address / Data Bus / Segment Assign X=01H D6 D7 D0 D1 D2 D3 D4 X=91H D5 D6 D7 D0 D1 D2 X=92H
SEG A0
SEG B0
SEG C0
SEG A0
SEG A97
SEG B97
HSW ABS REF SWAP 1 * 1 1 D4 X=91H D5 D6 D7 D0 D1
X Address / Data bus / Segment assign X=92H D2 D3 D4 D5 D6 D7 D0 D1 D2 X=00H D3 D4 D5 D6 X=01H
SEG A0
SEG B0
SEG C0
SEG A97
SEG B97
HSW ABS REF SWAP 1 * 0 1 D0 D1 D2 X=00H D3 D4 D5
X Address / Data Bus / Segment Assign X=01H D6 D7 D0 D1 D2 D3 D4 X=91H D5 D6 D7 D0 D1 D2 X=92H
SEG C97
SEG B97
SEG C0
SEG B0
24 *
SEG A0
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
SEG A97
SEG C97
SEG C97
SEG A97
SEG C97
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
HSW ABS REF SWAP 1 * 1 0 D4 X=91H D5 D6 D7 D0 D1
X Address / Data Bus / Segment Assign X=92H D2 D3 D4 D5 D6 D7 D0 D1 D2 X=00H D3 D4 D5 D6 D7 D0 X=01H D1 D13 D13 D9 D9 D2 D14 D14 D10 D10 D3 D11 * 25 D11 D15 D15
SEG C97
SEG B97
SEG C0
SEG B0
16 bits mode (WLS="1")
HSW ABS REF SWAP
* *
0 0
0 1
0 1 D1 D2 D3 D4 D7
X Address / Data Bus / Segment Assign X=00H X=61H X=61H X=00H D10 D12 D13 D14 D15 D10 D10 D7 D12 D12 D8 D8 D8 D9 D1 D2 D3 D4 D7 D8 D9
SEG A0
SEG B0
SEG C0
SEG A0
SEG A97
SEG B97
HSW ABS REF SWAP
* *
0 0
0 1
1 0 D1 D2 D3 D4 D7
X Address / Data Bus / Segment Assign X=00H X=61H X=61H X=00H D10 D12 D13 D14 D15 D8 D9 D1 D2 D3 D4 D7 D8 D9
SEG C97
SEG B97
SEG C0
SEG B0
HSW ABS REF
SWAP
* *
1 1
0 1
0 1 D0 D1 D2 D3 D4
X Address / Data Bus / Segment Assign X=00H X=61H X=61H X=00H D10 D11 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 D5 D6
SEG A0
SEG B0
SEG C0
SEG A0
SEG A97
SEG B97
HSW ABS REF SWAP
* *
1 1
0 1
1 0 D0 D1 D2 D3
X Address / Data Bus / Segment Assign X=00H X=61H X=61H X=00H D10 D11 D4 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 D5 D6 D7 SEG B97
SEG C97
SEG C0
SEG B0
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
SEG A0
SEG A97
SEG C97
SEG A97
SEG C97
SEG A97
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
7.8.3 Gradation mode (65K Color), (C256=0, 65K=1)
8-bit mode (WLS=0)
HSW ABS REF SWAP
* *
* *
0 1
0 1
X=00H X=C2H
X Address / Data Bus / Segment Assign X=01H X=C2H X=C3H X=00H
X=C3H X=01H
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 SEG A0 SEG B0 SEG C0
SEG A97
SEG B97
HSW ABS * * * *
REF SWAP 0 1 1 0
X=00H X=C2H
X Address / Data Bus / Segment Assign X=01H X=C2H X=C3H X=00H
X=C3H X=01H
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
SEG C0
SEG B0
SEG A0
SEG C97
SEG B97
16-bit mode (WLS=1)
HSW ABS REF SWAP * * 0 0 * * 1 1 X Address / Data Bus / Segment Assign X=00H X=61H X=61H X=00H D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 SEG A97 SEG B97 SEG C97 SEG B97 Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
SEG A0
SEG B0
SEG C0
HSW ABS REF SWAP * * 0 1 * * 1 0
X Address / Data Bus / Segment Assign X=00H X=61H X=61H X=00H D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 SEG A97
SEG C0
SEG B0
26 *
SEG A0
SEG C97
SEG A97
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
SEG C97
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
7.9 Display Data Structure and Gradation Control
For the purpose of gradation control, one pixel requires multiple bits of display RAM. The EM65570S has 5-bit data per output to achieve the gradation display. The three outputs of the segment driver are used for one pixel of RGB, and the EM65570S is connected to an STN color LCD panel. It can display 98*68 pixels with 65K colors (5 bits * 6 bits [5+FRC] * 5 bits). In this case, since the gradation display data is processed by a single access to the memory, the data can be rewritten fast and naturally. The weighting for each data bit is dependent on the status of the SWAP bit that is selected when data is written to the display RAM.
7.10 Gradation LSB Control
In 256 color mode (C256=1), the EM65570S provides segment driver output for 8-gradation display using 3-bits and that for 4-gradation display using 2-bits. The segment driver output for the 4-gradation display uses 2-bits written to the corresponding RAM area and 1-bit supplemented by the gradation LSB circuit, and then selects 4-gradation from 8-gradation. In 256 color mode (C256=1), the segment driver output for the 4-gradation display result in a gradation level of 0 regardless of the gradation LSB, when 2-bits of data on the display RAM are "00". When 2-bits of data on the display RAM is "11",a gradation level of 7/7 is selected regardless of the bit information of the gradation LSB. The other gradation levels are selected depending on 2-bits of data on the display RAM and the gradation LSB bits. One bit of data is supplemented by setting the gradation LSB register (GLSB). The Gradation LSB control bit applied to all 4-gradation segment drivers. Gradation LSB = "0": Selects 0 as the LSB information on the RAM for 4-gradation segment drivers. Gradation LSB = "1": Selects 1 as the LSB information on the RAM for 4-gradation segment drivers.
7.11 Generation of the Alternate Signal (M)
LCD alternated signal (M) is generated by the display clock (D_CK). The M generates alternated drive waveform to the LCD drive circuit. Normally, the M generates alternated drive waveform every frame (Frame-signal level is reversed every one frame). However, by setting up data (n-1) in an n-line reverse register and n-line alternated control bit (NLIN) at "1", n-line reverse waveform is generated. When NLIN = "H" : EOR=0 EOR=1 M always reverses on the nth raster row regardless of whether the end of a frame is reached. M reverses at the nth raster row and restarts the raster row count at the start of every frame.
* 27
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
7.12 Output Timing of LCD Driver
Display timing in Normal mode (not reverse mode), 1/64 duty.
63 D_CK M V0 V1 COM0 V4 VSS V0 V1 COM1 V4 VSS V0 V2 SEG0 V3 VSS V0 V2 SEG1 V3 V2 V3 VSS V3 V2 V3 V0 V4 V1 V1 V4 VSS 64 1 2 3 64 1 2 3 64 1
7.13 Oscillating Circuit
The EM65570S has an RC oscillator. The output from this oscillator is used as the timing signal source of the display and the boosting clock to the booster. When external clock is used, feed the clock to CK pin. The duty cycle of the external clock must be 50%. The resistance ratio of CR oscillator is programmable. If change this ratio, also change frame frequency for display.
28 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
7.14 Power Supply Circuit
This circuit supplies voltages necessary to drive an LCD. The circuit consists of booster and voltage converter. Boosted voltage from the booster is fed to the voltage converter that converts this input voltage into V0, V1, V2, V3 and V4 that are used to drive the LCD. This internal power supply should not be used to drive a large LCD panel containing many pixels. Otherwise, display quality will degrade considerably. The power circuit can be control by power circuit related register.
DCON AMPON 0 1 0 1 Booster Circuit disable enable Voltage Conversion Circuit disable enable
7.15 Booster Circuit
Placing capacitor C1 across CAP1+ and CAP1-, across CAP2+ and CAP2-, across CAP3+ and CAP3-, across CAP4+ and CAP2- and across VOUT and VSS boosts the voltage coming from VEE and VSS n-times and outputs the boosted voltage to VOUT pin. The twice, third, fourth or fifth boosted voltages are output to the VOUT pin by the boost step register set. The boost step registers set by the command. When use built-in booster circuit, output voltage (VOUT) must less than recommended operating voltage (19 Volt). If output voltage (VOUT) is beyond the recommended operating voltage, proper function of the IC cannot be guaranteed.
VOUT=15V VOUT=9V VEE=3V VSS=0V Boosted 3 times VEE=3V VSS=0V Boosted 5 times
7.16 Electronic Volume
The voltage conversion circuit has built-in an electronic volume, which allows VEV to be controlled with DV register setting. The DV registers are 7-bits, so can select 128 voltage values for the VEV voltage. The relationship between VEV and DV is given by follows equation: VEV=K * (373 + (DV+CV)) ----------------------------------------------------- (1) DV: Electronic volume setting value CV: Vop offset setting value of OTP K: Coefficient 4.005 * 10-3
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
* 29
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
7.17 Voltage Generation Circuit
The voltage converter contains the voltage generation circuit. The LCD drive voltages other than V0, i.e., V1, V2, V3 and V4 are obtained by dividing V0 through a resistor network. The LCD drive voltage from EM65570S is biased at 1/4, 1/5, 1/6, 1/7, 1/8, 1/9. When using the internal power supply, connect a stabilizing capacitor C2 to each of pins V0 to V4. The capacitance of C2 should be determined while observing the LCD panel to be used.
VDD
VDD VEE
VDD
VDD VEE
CAP3+ CAP3CAP2CAP2+ CAP4+ CAP1+ C1 CAP1C1 V2X C1 vss C2 C2 C2 C2 C2 VOUT V0 V1 V2 V3 V4 vss C1
CAP3+ CAP3CAP2CAP2+ CAP4+ CAP1+ C1 CAP1C1 V2X C1 vss C2 C2 C2 C2 C2 VOUT V0 V1 V2 V3 V4
vss
vss
vss
When using internal power circuit. (2 times boosting)
When using internal power circuit. (3 times boosting)
30 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
VDD
VDD VEE
VDD
VDD VEE
C1 C1
CAP3+ CAP3CAP2CAP2+ CAP4+
C1 C1 C1
CAP3+ CAP3CAP2CAP2+ CAP4+
vss vss
CAP1+ C1 CAP1C1 V2X C1 C2 C2 C2 C2 C2 VOUT V0 V1 V2 V3 V4
vss vss
CAP1+ C1 CAP1C1 V2X C1 C2 C2 C2 C2 C2 VOUT V0 V1 V2 V3 V4
vss
vss
When using internal power circuit (4 times boosting)
When using internal power circuit (5 times boosting)
Recommended value
C1 C2 1.0 to 1.5 f 1.0 to 1.5 f
7.18 2-D Graphic Acceleration Engine
EM65570S has 2-D graphic acceleration engine to support graphic functions including "Draw Rectangle", "Dim function", "Copy function", and "Clear function". User must generate clock yourself to support to graphic engine in all graphic function. Hardware will write data to display RAM at rising edge of GCK signal. The GCK signal can be `WRB', `E', `SCL' as shown below:
Interface Parallel 80-family Parallel 68-family Serial GCK Signal Definition WRB E SCL
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
* 31
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
NOTE 1: Time of `H' or `L' level of GCK must be larger than 200 ns. 2: The sequence of generating clock code must be setting GCK to `0' first, then setting to `1'. That is, GCK=0 GCK=1 GCK=0 GCK=1 ......
The RAM writing mode of graphic function is fixed to column address increasing and row address increasing, that is RDWS[2:0]=000 of RAM writing mode. It is unconcerned with the RAM writing mode user selected. (1) Draw Rectangle Give the starting point (X1, Y1) and the ending point (X2, Y2), then set line color and fill color, graphic engine will draw rectangle with the specified line color and fill color. If `FILL' control bit is disabled, the enclosed area will not be filled. Remarks: X1<= X2; Y1<= Y2; X2 <= 97; Y2 <= 67 It should be noted that the generated clock numbers for graphic engine must be based on the rectangle size, the pixel numbers are also enclosed by a rectangle area, the formula is shown below: Draw rectangle & fill enable GCK clock numbers = (End X - Start X + 1) * (End Y - Start Y + 1) + dummy clock numbers ......equation (1) Draw rectangle & fill disable GCK clock numbers = [(End X - Start X + 1) + (End Y - Start Y + 1)] * 2 + dummy clock numbers ......equation (2) The required dummy clock numbers for graphic function is shown below:
Function FILL & RECT COPY DIM CLR RECT Dummy Clock Numbers 7 1 1 1 2
32 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
NOTE 1. When drawing is completed, GCK signal must be disabled to prevent other un-wanted data writing. 2. The sequence of hardware operation is "fill color" "draw `a'" "draw `c'" "draw `b'" "draw `d'" 3. The draw rectangle and fill function can use mixed, but fill color only but not to draw rectangle is not permitted.
Fill 0 0 1 1
Rect 0 1 0 1
Condition Initial value Draw rectangle but not fill color Inhibited to use Draw rectangle and fill color
Graphic start X address (Bank1 [0H, 1H]), Graphic Start Y address (Bank1 [4H, 5H])
Line color R=11111 Line color G=000000 Line color B=00000
Fill color R=00000 Fill color G=111111 Fill color B=00000
Graphic end X address (Bank 1 [2H, 3H]), Graphic end Y address (Bank1 [6H, 7H])
Sample code: ---- set starting point (X1,Y1) and ending point (X2,Y2)------WRITE 0xF1 WRITE 0x10 WRITE 0x00 WRITE 0x30 WRITE 0x26 WRITE 0x50 WRITE 0x40 WRITE 0x70 WRITE 0x66 //Bank 1 //Graphic start X address (up nibble) //Graphic start X address (low nibble) //Graphic end X address (up nibble) //Graphic end X address (low nibble) //Graphic start Y address (up nibble) //Graphic start Y address (low nibble) //Graphic end Y address (up nibble) //Graphic end Y address (low nibble)
------------- set line color RGB -----------------------WRITE 0xA1 //Line color R (up nibble)
* 33
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers WRITE 0x9F WRITE 0xC0 WRITE 0xB0 WRITE 0xE0 WRITE 0xD0 //Line color R (low nibble) //Line color G (up nibble) //Line color G (low nibble) //Line color B (up nibble) //Line color B (low nibble)
---------------- set fill color RGB ------------------WRITE 0xF2 WRITE 0x10 WRITE 0x00 WRITE 0x33 WRITE 0x2F WRITE 0x50 WRITE 0x40 //Bank 2 //Fill color R (up nibble) //Fill color R (low nibble) //Fill color G (up nibble) //Fill color G (low nibble) //Fill color B (up nibble) //Fill color B (low nibble)
--- set FILL enable/disable and RECT enable to start drawing -WRITE 0xF1 //Bank 1
WRITE 0x83 //Fill enable; Draw rectangle enable (hardware start drawing operation
-------- generate graphic engine timing clock(WRB/E/SCL) --------
WRB=0 WRB=1
WRB=0 WRB=1
......... .........
WRB=0 WRB=1
Total 49 + 7 pairs of WRB/E/SCL clock
-------------------- Disable WRB signal ------------------WRB=1 //WRB signal disable to prevent other un-wanted data writing
34 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
(2) Dim When the `DIM' control bit of Bank 2 [6H] is set to 1, this function will dim the window area specify by starting point (X1, Y1) and the ending point (X2, Y2). After Dimming operation, the selected window area will be dimmed by 50% black or 50% white according to `DBW' control bit of Bank 2[6H]. DIM=0, Dim function disable ; DIM=1, Dim function enable DBW=0, dim 50% black ; DBW=1, dim 50% white It should be noted that the needed clock numbers generated is the same as that in equation (1) (3) Copy
When `COPY' control bit of Bank 2 [6H] is set to 1, copy function will copy the rectangle defined by the starting point (X1, Y1) and the ending point (X2,Y2) to the destination point (X3,Y3). Remarks: X1 <= X2; Y1 <= Y2; X2 <= 127; Y2 <= 127
NOTE 1: As long as the copy destination address area (or in RAM) by copy function. 2: When the rectangle area exceeds the display panel area (or RAM) using copy function, the parts that exceeded will not be displayed. 3: The needed clock numbers generated is the same with equation (1) 0, user can copy to anywhere on the display
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
* 35
EM65570S
68COM/98SEG 65K Color STN LCD Drivers (4) Clear When `CLR' control bit of Bank 2 [6H] is set to 1, this function will clear the window area display defined by starting point (X1, Y1) and the ending point (X2, Y2). The Display RAM contents of the window will be set to 0. It should be noted that the needed clock numbers generated is the same as that in equation (1)
7.19 OTP Function
EM65570S supports OTP function to tune (1) LCD operating voltage Vop. It can also select OTP operating mode, and OTP power from internal or external. In OTP select register (Bank5 [AH]), using (M1, M0) to select the operating mode for OTP, (M1, M0)=00 Read information from OTP; (M1, M0)=01 Program information to OTP; (M1, M0)=10 Reserved; (M1, M0)=11 OTP standby mode.
(M1, M0) 00 01 10 11 OTP Operating Mode Read Program Reserve Standby
In program mode, the delay time needed is more than 1 ms. Vop calibration offset voltage can be achieved by setting the Vop calibration offset register (Bank 5 [BH & EH]).
CV5~CV0 011111 011110 ... 000001 000000 100000 100001 ... 111111 Calibration Offset +31 +30 ... +1 0 -32 -31 ... -1
VEV=K*(373+(DV+CV)) V0 = VEV * N
K=4.005 * 10-3 N : RM register setting
36 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers The program flow chart of reading the OTP to get the correct Vop offset voltage are shown as follows:
set CV5~CV4 (high nibble register) set CV3~CV0 (low nibble register) Set OTP Program power Set cnt=6 Write Bank (5)
Setting the OTP Program power 1. Set RM= 4X 2. Set DV= 20H (Let V0=6~7V) 3. Display OFF
program start : (M1,M0) set 01
Delay 1mS
program end: (M1,M0) set 11
Caution: 1. Power setting must be set right, else OTP program will not succeed. 2. Don't write other commands (ex. Bank5) while writing "OTP program start and end" command.
cnt=cnt-1
N
cnt=0 ? Y Reset
Get the correct Vop offset voltage
Program Read
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
* 37
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
7.20 Partial Display Function
The EM65570S has a partial display function, which can display part of the graphic display area. This function is used be set lower bias ratio, lower boost step, and lower LCD drive voltage. Since setting partial display function, EM65570S provides low power consumption. Partial display function is the most suitable for clock indication or calendar indication when a portable equipment is stand-by.
ELAN LCD DRIVER Low Power and Low Voltage Normal Display
LCD DRIVER
Partial Display Figure 7-7 Image of Partial Display
When using the partial display function, it is necessary to keep following sequence.
Any display condition Display off (ON/OFF= "0") Power circuit off (DCON= "0", AMPON= "0") WAIT
Setting Power Function * Boost step set * Electronic volume set * Bias Ratio set
Power circuit on (DCON= "1", AMPON= "1") WAIT
Setting Display Function * Duty Ratio set * Display start common
Display on (ON/OFF= "1") Partial Display
Select a display duty ratio for the partial display from 1/8 to 1/72 using the DS (LCD duty ratio) register. Set the most suitable values for LCD drive bias ratio, LCD drive voltage, electronic volume, the number of boosting steps, and others according to the actually used LCD panel and the selected duty ratio.
38 * Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
7.21 Discharge Circuit
The EM65570S has built-in the discharge circuit, which discharges electricity from capacitors for a stability of power sources (V0~V4). The discharge circuit is valid, while the DIS register is set to "1". When the built-in power supply is used, should be set DIS="1" after the power source is turned off (DCON, AMPON)=(0, 0). And don't turn on both the built-in power source and the external power source (V0~V4, VOUT) while DIS="1".
7.22 Scroll Function
This function specifies the portion of screen for scrolling. It sets scroll top address, scroll bottom address, scroll specified address, scroll mode of the area scrolling, and scroll start address. Please be noted that the scroll top address should be smaller than the scroll bottom address. Remarks: 0 <= scroll top address, scroll bottom address, scroll specified address <= 67; scroll top address <= scroll start address <= scroll bottom address.
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
* 39
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
Sample code: -----------------set duty ratio=1/72 --------------------WRITE 0xF0 WRITE 0xC6
40 *
//Bank 0 //duty=1/72
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
--------------- scroll function setting -----------------WRITE 0xF3 WRITE 0x10 WRITE 0x02 WRITE 0x34 WRITE 0x21 WRITE 0x54 WRITE 0x41 WRITE 0x80 //Bank 3 //Scroll top address (up nibble) //Scroll top address (low nibble) //Scroll bottom address (up nibble) //Scroll bottom address (low nibble) //Scroll specified address (up nibble) //Scroll specified address (low nibble) //Center scroll mode
-------------------- scroll start -----------------MOV MOV A, #2 INDEX1, A
LOOP1: WRITE (0x70) WRITE (0x60 + INDEX1) INC_INDEX_1: INC MOV JLE MOV MOV LOOP2: MOV MOV LOOP3: WRITE (0x70 + INDEX2) WRITE (0x60 + INDEX1) INC_INDEX_2: INC MOV INDEX1 A, INDEX1
* 41
INDEX1 A, INDEX1 A, #15, LOOP1 A, #1 INDEX2, A
A, #0 INDEX1, A
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers JLE INC MOV JLE MOV MOV LOOP4: WRITE (0x77) WRITE (0x60 + INDEX1) INC_INDEX_3: INC MOV JLE INDEX1 A, INDEX1 A, #13, LOOP4
NOTE Set the scroll top address and scroll bottom address to define the area of scrolling data in RAM.
A, #15, LOOP3 INDEX2 A, INDEX2 A, #3, LOOP2 A, #0 INDEX1, A
Example
NOTE Set the scroll specified address according to panel size and duty selection, to define the address where to jump or to scroll bottom address. Then display the bottom fixed data area. Remark: Scroll specified address = scroll top address + panel scroll area - 1 Ex: (98RGB x 68 Line panel; 1/32 duty, partial display)
42 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
Attention: If the scroll specified address is not set or wrongly set, unpredictable scrolling results may occur.
NOTE Set the scroll top address, scroll bottom address, scroll specified address, and scroll start address carefully when using scroll function. In case of error, follow the rules shown below: Scroll top address <= Scroll bottom address Scroll specified address = Scroll top address + panel scroll area - 1 Scroll top address <= Scroll start address <= Scroll bottom address
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
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EM65570S
68COM/98SEG 65K Color STN LCD Drivers
7.23 Initialization
Setting RESB pin to "L" initializes the EM65570S. Normally, RESB pin is initialized together with MPU by connecting to the reset pin of MPU. When power ON, be sure to make RESB="L". 65K color mode
Item Display RAM X Address Y Address Display starting common Display ON/OFF Display Normal/Reverse n-line alternated (BF1,BF0) Common shift direction Increment mode Data SWAP Mode Register in electronic volume Power Supply Display mode Gradation LSB RAM access data length Discharge Register Initial Value Not fixed 00H set 00H set Set at the first common (0H) Display OFF Normal Every frame unit (0, 1) COM0 COM67 Increment OFF OFF (0, 0, 0, 0, 0, 0, 0) OFF 65K color mode 0 8-bit mode 0
7.24 Precaution when Setting Power ON and Power OFF
High current may flow if a voltage is supplied to the LCD driver power supply while the system power supply is floating and may permanently damage this LSI. The detailed description is as follows.
7.24.1 When Using the Built-in Power Supply
Procedure in Setting the Power ON Logic system (VDD) power ON Booster circuit system (VEE) power ON Reset the operation, booster and voltage conversion circuit enable. If VDD and VEE voltages aren't same potential, power on logic system (VDD) first. Procedure in Setting the Power OFF Set the HALT register to "1" or make reset operation. Set the Booster circuit system (VEE) power OFF. Set the Logic system (VDD) power OFF. If VDD and VEE are not of the same potential, cut off VEE first. After VEE, VOUT, V0, V1, V2, V3 and V4 voltages are below LCD ON voltage (threshold voltage for Liquid crystal turn on), power off logic system (VDD).
44 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
7.24.2 Power Supply Rising Time
Though usually there is no constraint on the rising time of the power supply, the following tr (rising time) is recommended in this practical use.
VDD,VEE tr
Item tr Recommended Rising Time 30 s ~10 ms Applicable Power VDD, VEE
Note: The rising time is initially from 10% of VDD, VEE to 90%
7.25 Example of Registers Setting
7.25.1 Initialization
Power ON (VDD,VEE-VSS) Power will stable RESET W AIT
Setting Operational Functions * Electrical volume set * Bias Ratio set
Setting Operational Functions * Setting power control (DCON= "1", AMPON= "1")
End of initialization
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
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EM65570S
68COM/98SEG 65K Color STN LCD Drivers
7.25.2 Display Data
End of initialization
Setting Operational Functions * Setting display start common * Setting address increment control * Setting X address * Setting Y address
Setting Operational Functions * Write dsiplay data
Setting Operational Functions * Setting display on/off control (ON/OFF= "1")
End of display data setting
7.25.3 Power OFF
Any condition
Setting Operational Functions * Setting HALT=1 or make reset operation (LCD driver output VSS level) * Setting DIS= "1" (Discharge V0-V4 capacitor)
WAIT
Power OFF ( VEE,VDD)
46 *
Product Specification (V1.0) 04.18.2006
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EM65570S
68COM/98SEG 65K Color STN LCD Drivers
8
Control Registers
8.1 Control Register
Control Register Table (Bank 0)
Control Register Pins (for 80-family) & Bank Address & Code CSB RS WRB RDB RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 [0H] [1H] [2H] [3H] [4H] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 D0 Function Set of X direction Address in display RAM Set of X direction Address in display RAM Set of Y direction Address in display RAM Set of Y direction Address in display RAM Reserved Reserved [5H] 1* 0 N3 1 N7 * N2 N6 * N1 N5 * N0 N4 Set the number of alternated reverse line Set the number of alternated reverse line SHIFT: Select common shift direction 65K: Select 65K gradation ALLON: All display ON ON/OFF: Display ON or OFF REV: Display normal/reverse NLIN: n line reverse control SWAP: Display data swapping WIN: Select window. AIM: Select increment mode AYI: Y increment, AXI: X increment AMPON: Internal AMP. ON HALT: Power saving DCON: Boosting circuit ON ACL: Resetting Set LCD drive duty ratio
X Address (Lower nibble) X Address (Upper nibble) Y Address (Lower nibble) Y Address (Upper nibble) Reserved Reserved n-line alternation (Lower nibble) n-line alternation (Upper nibble) Display control (1)
0 AX3 AX2 AX1 AX0 1 AX7 AX6 AX5 AX4 0 AY3 AY2 AY1 AY0 1 AY7 AY6 AY5 AY4 0* * * *
[6H] [7H]
[8H] Display control (2) [9H] Increment control [AH] Power control [BH] LCD Duty Ratio [CH] Booster Bias ratio control Register Access Control [DH] [EH] [FH]
0
1
0
1
0
0
0
1
0
0
SHI ALL ON/ 0 FT 65K ON OFF SW 1 REV NLIN AP REF
0
1
0
1
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0 WIN AIM AYI AXI
0 0 0 0 0
1 1 1 1 1
0 0 0 0 0
1 1 1 1
0 0 0 0
0 0 0 0
0 0 0 0
1 1 1 1 1
0 1 1 1 1
1 0 0 1 1
AMP HA 1 ON LT
DC ON
ACL
0 DS3 DS2 DS1 DS0 Set number of boosting step for 1 SHP VU2 VU1 VU0 booster circuit Set bias ratio 0 B3 B2 B1 B0 for LCD driving voltage TS TST0: for LS1 test,must set to "0" 1 T0 RE2 RE1 RE0 RE: set register bank number
1 0/1 0/1 0/1
NOTE The " " mark means "don't care" Parentheses [ ] shows address for control register.
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
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EM65570S
68COM/98SEG 65K Color STN LCD Drivers Control Register Table (Bank 1)
Control Register Graphic start X address (Lower nibble) Graphic start X address (Upper nibble) Graphic end X address (Lower nibble) Graphic end X address (Upper nibble) Graphic start Y address (Lower nibble) Graphic start Y address (Upper nibble) Graphic end Y address (Lower nibble) Graphic end Y address (Upper nibble) Draw rectangle control Line color R (Lower nibble) Line color R (Upper nibble) Line color G (Lower nibble) Line color G (Upper nibble) Line color B (Lower nibble) Line color B (Upper nibble) Register Access Control [0H] [1H] [2H] [3H] [4H] [5H] [6H] [7H] [8H] [9H] [AH] [BH] [CH] [DH] [EH] [FH] Pins (for 80-family) & Bank Address & Code CSBRS WRBRDBRE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Function Set graphic function X start address 0 GSX3GSX2GSX1GSX0 Set graphic function X start address 1* GSX6GSX5GSX4 Set graphic function X end address 0 GEX3GEX2GEX1GEX0 Set graphic function X end address 1* GEX6GEX5GEX4 Set graphic function Y start address 0 GSY3GSY2GSY1GSY0 Set graphic function Y start address 1 GSY7GSY6GSY5GSY4 Set graphic function Y end address 0 GEY3GEY2GEY1GEY0 Set graphic function Y end address 1 GEY7GEY6GEY5GEY4 0* * Fill color enable FILL RECT Draw rectangle enable Set line color R of rectangle LR1 LR0 Set line color R of rectangle * LR4 Set line color G of rectangle LG1 LG0 Set line color G of rectangle LG5 LG4 Set line color B of rectangle LB1 LB0 Set line color B of rectangle * LB4 TST0:for LS1 test,must set to "0" RE1 RE0 RE:set register bank number
D0
1 LR3 LR2 0* *
1 LG3 LG2 0* *
1 LB3 LB2 0* TS 1 T0 * RE2
1 0/1 0/1 0/1
NOTE The " " mark means "don't care" Parentheses [ ] shows address for control register.
48 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers Control Register Table (Bank 2)
Control Register Fill color R (Lower nibble) [0H] Fill color R (Upper nibble) [1H] Fill color G (Lower nibble) [2H] Fill color G (Upper nibble) [3H] Fill color B (Lower nibble) [4H] Fill color B (Upper nibble) [5H] Dim&Copy&Clear function control [6H] Copy destination X address (Lower nibble) [7H] Copy destination X address (Upper nibble) [8H] Copy destination Y address (Lower nibble) [9H] Copy destination Y address (Upper nibble) [AH] Reserved [BH] Reserved [CH] Reserved [DH] Reserved [EH] Register Access Control [FH] Pins (for 80-family) & Bank Address & Code CSBRS WRBRDBRE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 Function Set fill color R of rectangle 0 FR3 FR2 FR1 FR0 Set fill color R of rectangle 1* * * FR4 Set fill color G of rectangle 0 FG3 FG2 FG1 FG0 Set fill color G of rectangle 1* * FG5 FG4 Set fill color B of rectangle 0 FB3 FB2 FB1 FB0 Set fill color B of rectangle 1* * * FB4 Dim & Copy & Clear function 0 CLR COPYDBW DIM control Set destination X address of 1 CDX3CDX2CDX1CDX0 copy function Set destination X address of 0* CDX6CDX5CDX4 copy function Set destination Y address of 1 CDY3CDY2CDY1CDY0 copy function Set destination Y address of 0 CDY7CDY6CDY5CDY4 copy function Reserved 1* * * * Reserved 0* * * * Reserved 1* * * * Reserved 0* * * * TS TST0:for LS1 test,must set to "0" 1 T0 RE2 RE1 RE0 RE:set register bank number
1 0/1 0/1 0/1
NOTE The " " mark means "don't care" Parentheses [ ] shows address for control register.
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
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EM65570S
68COM/98SEG 65K Color STN LCD Drivers Control Register Table (Bank 3)
Control Register Scroll top address (Lower nibble) Scroll top address (Upper nibble) Scroll bottom address (Lower nibble) Scroll bottom address (Upper nibble) Scroll specified address (Lower nibble) Scroll specified address (Upper nibble) Scroll start address (Lower nibble) Scroll start address (Upper nibble) Scroll mode select Reserved [9H] Reserved [AH] Reserved [BH] Reserved [CH] Reserved [DH] Reserved [EH] Register Access Control [FH] 0 1 0 1 0/1 0/1 0/1 1 1 1 0 1 0 1 0 1 1 1 1 1 0* TS 1 T0 * * * 0 1 0 1 0 1 1 1 1 0 1* * * * Reserved TST0:for LS1 test,must set to "0" RE2 RE1 RE0 RE:set register bank number 0 1 0 1 0 1 1 1 1 0 0* * * * Reserved 0 1 0 1 0 1 1 1 0 1 1* * * * Reserved 0 1 0 1 0 1 1 1 0 1 0* * * * Reserved 0 1 0 1 0 1 1 1 0 0 1* * * * Reserved [0H] [1H] [2H] [3H] [4H] [5H] [6H] [7H] [8H] Pins (for 80-family) & Bank Address & Code CSB RS WRB RDB RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 Function Set scroll top address 0 STA3 STA2 STA1 STA0 Set scroll top address 1 STA7 STA6 STA5 STA4 Set scroll bottom address 0 SBA3 SBA2 SBA1 SBA0 Set scroll bottom address 1 SBA7 SBA6 SBA5 SBA4 Set scroll specified address 0 SSA3 SSA2 SSA1 SSA0 Set scroll specified address 1 SSA7 SSA6 SSA5 SSA4 Set scroll start address 0 SAY3 SAY2 SAY1 SAY0 Set scroll start address 1 SAY7 SAY6 SAY5 SAY4 Scroll mode select 0* * SM1 SM0 Reserved
D0
NOTE The " " mark means "don't care" Parentheses [ ] shows address for control register.
50 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
Control Register Table (Bank 4)
Control Register Reserved [0H] Reserved [1H] Reserved [2H] RAM data writing select Control Reserved Reserved [5H] Display start common [6H] Temperature Compensation [7H] Display Select Control [8H] RAM Data length set [9H] Electronic Volume (Lower nibble) [AH] Electronic Volume (Upper nibble) [BH] Register read control [CH] Select RF [DH] Booster Frequency control [EH] Register Access Control [FH] 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0/1 1 1 1 1 1 1 1 1 1 0/1 0 0 0 0 0 0 0 0 0 0/1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 SC3 SC2 SC1 SC0 Set Common Driver Start Line Temperature Compensation set 1* * TCS1 TCS0 Set Gradation LSB bit of 256 color * mode 0* GLSB* Set data length on RAM access 1 C256 HSW ABS WLS 8-bit access or 16-bit access Set electronic volume register 0 DV3 DV2 DV1 DV0 Set electronic volume register 1* DV6 DV5 DV4 Set register address for read 0 RA3 RA2 RA1 RA0 Select RF ratio of OSC circuit 1 RF3 RF2 RF1 RF0 Set booster frequnecy 0 BF1 BF0 HPM DIS Discharge capacitances of V0~V4 TS TST0:for LS1 test,must set to "0" 1 T0 RE2 RE1 RE0 RE:set register bank number 0 1 0 1 1 0 0 0 1 0 [3H] [4H] 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 1 0 0 0 0 0 1* 0* * * * 0 1 0 1 1 0 0 0 0 0 0* * * * Reserved Reserved * * * RD RD RD Set RAM data writing mode 1 WBS WS2 WS1 WS0 Reserved 0* * * * * Reserved 1* * * * Pins (for 80-family) & Bank Address & Code CSB RS WRB RDB RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0 Reserved Function
NOTE The " " mark means "don't care" Parentheses [ ] shows address for control register.
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
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EM65570S
68COM/98SEG 65K Color STN LCD Drivers
Control Register Table (Bank 5)
Control Register Window X End Address (Lower nibble) Window X End Address (Upper nibble) Window Y End Address (Lower nibble) Window Y End Address (Upper nibble) Start address for line reverse (Lower nibble) Start address for line reverse (Upper nibble) End address for line reverse (Lower nibble) End address for line reverse (Upper nibble) Line reverse control Burst RAM write control Regulator multiple ratio control register OTP mode select Vop calibration offset (Lower nibble) Reserved Reserved [DH] Vop calibration offset (Upper nibble) [EH] Register Access Control [FH] 0 0 0 1 1 1 0 0 0 1 1 1 0/1 1 1 0/1 0 0 0/1 1 1 1 1 1 1 1 1 0 1 1 [0H] [1H] [2H] [3H] [4H] [5H] [6H] [7H] [8H] [9H] [AH] [BH] [CH] Pins (for 80-family) & Bank Address & Code CSB RS WRB RDB RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D0 Function Set X end address for window 0 EX3 EX2 EX1 EX0 function Set X end address for window 1 EX7 EX6 EX5 EX4 function Set Y end address for window 0 EY3 EY2 EY1 EY0 function Set Y end address for window 1 EY7 EY6 EY5 EY4 function set start line for line 0 LS3 LS2 LS1 LS0 reverse display set start line for line 1 LS7 LS6 LS5 LS4 reverse display set end line for line 0 LE3 LE2 LE1 LE0 reverse display set end line for line 1 LE7 LE6 LE5 LE4 reverse display set line reverse control, 0 EOR BST BT LREV burst RAM write control set regulator multiple ratio 1 RM3 RM2 RM1 RM0 _ EEPROM mode select 0 M1 M0 * * Vop calibration offset select 1 CV3 CV2 CV1 CV0 Reserved 0* * * * Reserved 1* * * * Vop calibration offset select 0* * CV5 CV4 TS TST0:for LS1 test,must set to "0" 1 T0 RE2 RE1 RE0 RE:set register bank number
NOTE The " " mark means "don't care" Parentheses [ ] shows address for control register.
52 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
8.2 Control Registers Functions
The EM65570S has many control registers. In case of control register access, upper nibble of data bus (D7~D4) represent register address, lower nibble of data bus (D3~D0) represent data. The access example is shown in the following. The Pins (CSB, RS, RDB, WRB) setting is for 80-family MPU interface. Only the setting of terminal (RDB, WRB) is different, when it is accessed by the 68-fanily MPU. (Example) X Address
D7 0 D6 0 D5 0 D4 0 D3 AX3 D2 AX2 D1 AX1 D0 AX0 CSB 0 RS 1 RDB 1 WRB 0 RE2 0 RE1 0 RE0 0
Register address
Data
Pins setting
Register Bank
In the writing to the control register, it is used directly as addressing D7~D4 of the data bus. In case of register read, first set RA register for specific register address, next can read specific register. Therefore, it is need 2-step for register read. Then, specific register output to D3~D0 of data bus. Except D3~D0 of data bus are all "H". Prohibit access to undefined register address area. When RS is "L", all read/write operations are accessed to display RAM. Then data bus doesn't include register address. In case of write, D3~D0 data is written to the register designated at D7~D4 in rising edge of the WRB signal. In case of read, register can output to data bus is RDB active period. Control register and display RAM are the equal access timing.
8.2.1 X Address Register (AX)
D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0 AX3 AX2 AX1 AX0
(At the time of reset: {AX3, AX2, AX1, AX0}= 0H, read address: 0H)
D7 0 D6 0 D5 0 D4 1 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0 AX7 AX6 AX5 AX4
(At the time of reset: {AX7, AX6, AX5, AX4}= 0H, read address: 1H) The AX register set to X-direction address of display RAM. In data setting, lower place and upper place are divided with 4-bit and 4-bit respectively. 00H to 61H are applicable to the values for AX7 to AX0, and 62H to FFH are not permitted.
8.2.2 Y Address Register (AY)
D7 0 D6 0 D5 1 D4 0 D3 D2 D1 D0 CSB RS 0 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0 AY3 AY2 AY1 AY0
(At the time of reset: {AY3, AY2, AY1, AY0}=0H, read address: 2H)
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
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EM65570S
68COM/98SEG 65K Color STN LCD Drivers
D7 0
D6 0
D5 1
D4 1
D3
D2
D1
D0
CSB 0
RS 1
RDB WRB RE2 RE1 RE0 1 0 0 0 0
AY7 AY6 AY5 AY4
(At the time of reset: {AY7, AY6, AY5, AY4}=0H, read address: 3H) Mark shows "Don't care" The AY register set to Y-direction address of display RAM. In data setting, lower place and upper place are divided with 4-bit and 4-bit respectively. 00H to 43H are applicable to the values for AY7 to AY0, and 44H to FFH are not permitted.
8.2.3 n Line Alternate Register (N)
D7 0 D6 1 D5 1 D4 0 D3 N3 D2 N2 D1 N1 D0 N0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0
(At the time of reset: {N3, N2, N1, N0}=0H, read address: 6H)
D7 0 D6 1 D5 1 D4 1 D3 N7 D2 N6 D1 N5 D0 N4 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0
(At the time of reset: {N7, N6, N5, N4}=0H, read address: 7H) Mark shows "Don't care" The reverse line number of LCD alternated drive is required to set in the register. The line number has a limit, must keeps between from 2 to 67 lines. The values set up by the alternated register become enable when NLIN control bit is "1". When NLIN control bit is "0", alternated drive waveform reverses by each frame is generated.
N7 0 0 N6 0 0 N5 0 0 N4 0 0 N3 0 0 N2 0 0 N1 0 0 N0 0 1 Line Address Inhibit to use 2
0
1
0
0
0
0
1
0
67
54 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers Alternate Timing NLIN="0" (in case of 1/64 DUTY Display)
NLIN="1"
8.2.4 Display Control (1) Register
D7 1 D6 0 D5 0 D4 0 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 0 0 ALL ON/ ON OFF
SHIFT 65K
(At the time of reset: {SHIFT, 65K, ALLON, ON/OFF}=4H, read address: 8H) ALLON Regardless of the data for display, all is on. This control has priority over display normal/reverse commands. ALLON = "0": Normal display ALLON = "1": All display lighted 65K Select 65K gradation display 65K="0": 4096 or 256 gradation display, decided by C256 control bit. 65K="1": 65K gradation display mode.
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
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EM65570S
68COM/98SEG 65K Color STN LCD Drivers SHIFT The shift direction of display scanning data in the common driver output is selected. SHIFT = "0": COM0 COM67 shift-scan SHIFT = "1": COM67 COM0 shift-scan ON/OFF This register controls whether to turning on the LCD panel or not. ON/OFF ="0": Display OFF ON/OFF ="1": Display ON
8.2.5 Display Control (2) Register
D7 D6 D5 D4 1 0 0 1 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 0 0 REV NLIN SWAP REF
(At the time of reset: {REV, NLIN, SWAP, REF}=0H, read address: 9H)
REV
Corresponding to the data of display RAM, the lighting or not-lighting of the display is set up. REV ="0": When RAM data at "H", LCD at ON voltage (normal) REV ="1": When RAM data at "L", LCD at ON voltage (reverse)
NLIN
The NLIN control n-line alternated drive. NLIN = "0": n-line alternated drive OFF. In each frame, the alternated signals (M) are reversed. NLIN ="1": n-line alternated drive ON. According to data set up in n-line alternated register, the alternation is made.
REF, SWAP
The REF control the reverse of display or not REF="0" : Normal mode. REF='"1": Reverse of display, Exchange display data of R and B The SWAP control the display data of R and B exchange or not. SWAP = "0": Normal mode. SWAP = "1": Exchange display data of R and B.
56 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
REF 0 0 1 1
SWAP 0 1 0 1
Effect on the Panel Normal display Exchange display data of R and B. Reverse display, Exchange display data of R and B Reverse display
8.2.6 Increment Control Register Set
D7 1 D6 0 D5 1 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0 WIN AIM AYI AXI
(At the time of reset: {WIN, AIM, AYI, AXI}=0H, read address: AH) This register controls the increment mode and window function when accessing to display RAM. The increment operation of AX and AY register can control by AIM, AYI and AXI registers setting and every write access or every read access to display RAM. The AY register directly connects to display RAM as Y address. The AX register connect to address converter, and that output to display RAM as X address in the auto increment mode, AX and AY register are increment, not directly increment X and Y address. In setting to this control register, the increment operation of address can be made without setting successive addresses for writing data or for reading data to display RAM from MPU. The WIN register used for window function control. WIN="0": Normal RAM access WIN="1": Window function access In case of using window function access, should be set following register before access to RAM. WIN="1", AXI="1", AYI="1" X Address, Y Address, Window X End Address, Window Y End Address Moreover, should be keep following address condition. Window end X address Window end Y address Window start X address Window start Y address
The increment control of X and Y addresses by AIM, AYI and AXI registers are as follows.
AIM 0 1 Address Increment Timing When writing to Display RAM or reading from Display RAM This is effective when access to successive address area Only when writing to Display RAM This is effective the case of "Read Modify Write * 57
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
AYI 0 0 1 1
AXI 0 1 0 1
Select Address Increment Operation Address is not increment X-Address is increment Y-Address is increment X and Y both are increment
Remark (1) (2) (3) (4)
(1) Regardless of AIM, no increment for AX and AY register. (2) According to the setting-up of AIM, automatically change X address.
Transition of AX Register
Transition of X Address Same as AX register
NOTE maxH: The internal maximum X-address in each access mode.
(3) According to the setting-up of AIM, automatically change Y address.
Transition of AY Register
Transition of Y Address Same as AY register
(4) According to the setting-up of AIM, cooperative change X and Y address. When the X address exceed maxH, Y address increment occurs.
Transition of AX and AY Register
Transition of X and Y Address
Same as AX and AY register
NOTE maxH: The internal maximum X-address in each access mode.
58 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers Following shows address increment in window function access.
Transition of AX and AY Register
Transition of X and Y Address
Same as AX and AY register
NOTE maxH: The internal maximum X-address in each access mode.
In each operation mode, the following increment operation is performed: When gradation display mode and 8-bit access are selected Address is incremented as described above. When gradation display mode and 16-bit access are selected: Accessing the RAM once accesses two bytes. The X-addresses increment in the order of 00H,01H,...5FH,60H and 61H.
8.2.7 Power Control Register
D7 D6 D5 D4 1 0 1 1 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 0 0 AMPON HALT DCON ACL
(At the tine of reset: {AMPON, HALT, DCON, ACL}=0H, read address: BH)
ACL
The internal circuit can be initialized. ACL = "0": Normal operation ACL = "1": Initialization ON When the reset operation begins internally after ACL register sets to "1", the ACL register is automatically cleared to "0". The internal reset signal has been generated with a clock (built-in oscillation circuit or CK input) for the display. Therefore, install the WAIT period for the display clock two cycles at least. After WAIT period, next operation can handle.
DCON
The internal booster circuit is set ON/OFF DCON = "0": Booster circuit OFF DCON="1": Booster circuit ON
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
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HALT
The conditions of power saving are set ON/OFF by this command. HALT = "0": Normal operation HALT="1": Power-saving operation When setting in the power-saving state, the consumed current can be reduced to a value near to the standby current. The internal condition at power saving are as follows. The oscillating circuit and power supply circuit are stopped. The LCD drive is stopped, and output of the segment driver and common driver are VSS level. The clock input from CK pin is inhibited. The contents of Display RAM data are maintained. The operational mode maintains the state of command execution before executing power saving command.
AMPON
The internal OP-AMP circuit block (voltage regulator, electronic volume, and voltage conversion circuit) is set ON/OFF by this command. AMPON = "0": The internal OP-AMP circuit OFF AMPON = "1": The internal OP-AMP circuit ON
8.2.8 LCD Duty (DS)
D7 1 D6 1 D5 0 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0 DS3 DS2 DS1 DS0
(At the time of reset: {DS3, DS2, DS1, DS0}=CH, read address: CH) mark means "Don't care" The DS register set to LCD display duty.
DS3 0 0 0 0 0 0 0 1 DS2 0 0 0 0 1 1 1 1 DS1 0 0 1 1 0 0 1 0 DS0 0 1 0 1 0 1 0 0 Display width and Duty 1/8 duty 1/16 duty 1/24 duty 1/32 duty 1/48 duty 1/64 duty 1/72 duty Reserved
Partial display can be made possible by setting an arbitrary duty ratio.
60 * Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
8.2.9 Booster Setup (VU)
D7 1 D6 1 D5 0 D4 1 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 0 0 SHP VU2 VU1 VU0
(At the time of reset: {SHP, VU2, VU1, VU0}=5H, read address: DH) mark means "Don't care" The booster steps set to VU register
.VU2 0 0 0 0 1 1 VU1 0 0 1 1 0 0 VU0 0 1 0 1 0 1 Booster Operation Booster disable (No operation) 2 times voltage output 3 times voltage output 4 times voltage output 5 times voltage output Reserved
8.2.10 Bias Setting Register (B)
D7 1 D6 1 D5 1 D4 0 D3 B3 D2 B2 D1 B1 D0 B0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 0 0 0
(At the time of reset: {B3, B2, B1, B0}=8H, read address: EH) mark means "Don't care" This register is used to set a bias ratio. A bias ratio can be selected from 1/5 to 1/9 by setting B3, B2, B1, and B0.
B3 0 0 0 0 0 1 B2 0 0 0 0 1 0 B1 0 0 1 1 0 0 B0 0 1 0 1 0 0 Bias 1/5 Bias 1/6 Bias 1/7 Bias 1/8 Bias 1/9 Bias Reserved
8.2.11 Register Access Control
D7 D6 D5 D4 1 1 1 1 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0/1 0/1 0/1 TST0 RE2 RE1 RE0
(At the time of reset: {TST0, RE2, RE1, RE0}=0H, read address: FH) mark means "Don't care" The RE register set to number of register bank. Access to each control register, set RE register at first. The TST0 register use for test of LSI, Therefore this register must be set to "0"
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
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8.2.12 Graphic Start X Address
D7 0 D6 0 D5 0 D4 0 D3
GSX3
D2
GSX2
D1
GSX1
D0
GSX0
CSB
RS
RDB
WRB
RE2
RE1
RE0
0
1
1
0
0
0
1
(At the time of reset: {GSX3, GSX2, GSX1, GSX0} = 0H, read address: 0H)
D7 0 D6 0 D5 0 D4 1 D3 * D2
GSX6
D1
GSX5
D0
GSX4
CSB
RS
RDB
WRB
RE2
RE1
RE0
0
1
1
0
0
0
1
(At the time of reset: {GSX6, GSX5, GSX4} = 0H, read address: 1H) mark means "Don't care" Set X start address of the rectangle. 0 <= X <= 97 ; Graphic start X address <= Graphic end X address
8.2.13 Graphic End X Address
D7 D6 D5 D4 D3
GEX3
D2
GEX2
D1
GEX1
D0
GEX0
CSB
RS
RDB
WRB
RE2
RE1
RE0
0
0
1
0
0
1
1
0
0
0
1
(At the time of reset: {GEX3, GEX2, GEX1, GEX0} = 0H, read address: 2H)
D7 D6 D5 D4 D3 D2 GEX6 D1 GEX5 D0 GEX4
CSB RS RDB WRB RE2 RE1 RE0
0
0
1
1
*
0
1
1
0
0
0
1
(At the time of reset: {GEX6, GEX5, GEX4} = 0H, read address: 3H) mark means "Don't care" Set X end address of the rectangle. 0 <= X <= 97 ; Graphic start X address <= Graphic end X address
8.2.14 Graphic Start Y Address
D7 D6 D5 D4 D3
GSY3
D2
GSY2
D1
GSY1
D0
GSY0
CSB
RS
RDB
WRB
RE2
RE1
RE0
0
1
0
0
0
1
1
0
0
0
1
(At the time of reset: {GSY3, GSY2, GSY1, GSY0} = 0H, read address: 4H)
D7 D6 D5 D4 D3
GSY7
D2
GSY6
D1
GSY5
D0
GSY4
CSB
RS
RDB
WRB
RE2
RE1
RE0
0
1
0
1
0
1
1
0
0
0
1
(At the time of reset: {GSY7, GSY6, GSY5, GSY4} = 0H, read address: 5H) mark means "Don't care" Set Y start address of rectangle. 0 <= Y <= 67 ; Graphic start Y address <= Graphic end Y address
8.2.15 Graphic End Y Address
D7 D6 D5 D4 D3
GEY3
D2
GEY2
D1
GEY1
D0
GEY0
CSB
RS
RDB
WRB
RE2
RE1
RE0
0
1
1
0
0
1
1
0
0
0
1
(At the time of reset: {GEY3, GEY2, GEY1, GEY0} = 0H, read address: 6H)
62 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
D7
D6
D5
D4
D3
GEY7
D2
GEY6
D1
GEY5
D0
GEY4
CSB
RS
RDB
WRB
RE2
RE1
RE0
0
1
1
1
0
1
1
0
0
0
1
(At the time of reset: {GEY7, GEY6, GEY5, GEY4} = 0H, read address: 7H) ,ark means "Don't care" Set Y end address of rectangle. 0 <= Y <= 67 ; Graphic start Y address <= Graphic end Y address
8.2.16 Draw Rectangle Control
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
0
0
0
*
*
FILL
RECT
0
1
1
0
0
0
1
(At the time of reset: {FILL, RECT} = 0H, read address: 8H) mark means "Don't care" The FILL bit control filling color in the interior of rectangle enable or disable. FILL="0", fill function disable. FILL="1", fill function enable. The RECT bit control drawing rectangle enable or disable. RECT="0", draw rectangle disable. RECT="1", draw rectangle enable.
FILL 0 0 1 1 RECT 0 1 0 1 Initial value Draw rectangle but not fill color Inhibited for use Draw rectangle and fill color Condition
NOTE When RECT=1, hardware starts the drawing operation, and when finished Drawing operation, RECT will be cleared to `0' automatically by hardware.
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
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8.2.17 Line Color R
D7 D6 D5 D4 D3
LR3
D2
LR2
D1
LR1
D0
LR0
CSB
RS
RDB
WRB
RE2
RE1
RE0
1
0
0
1
0
1
1
0
0
0
1
(At the time of reset: {LR3, LR2, LR1, LR0} = 0H, read address: 9H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
0
0
1
*
*
*
LR4
0
1
1
0
0
0
1
(At the time of reset: {LR4} = 0H, read address: AH) mark means "Don't care" Set line color R of rectangle.
NOTE When in 256 color mode, LR3 don't care ; when 4k or 256 color mode, LR4 don't care
8.2.18 Line Color G
D7 D6 D5 D4 D3
LG3
D2
LG2
D1
LG1
D0
LG0
CSB
RS
RDB
WRB
RE2
RE1
RE0
1
0
1
1
0
1
1
0
0
0
1
(At the time of reset: {LG3, LG2, LG1, LG0} = 0H, read address: BH)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
1
0
0
*
*
LG5
LG4
0
1
1
0
0
0
1
(At the time of reset: {LG5,LG4} = 0H, read address: CH) mark means "Don't care" Set line color G of the rectangle.
NOTE When 256 color mode, LG3 don't care ; when 4k or 256 color mode, LG5 and LG4 don't care
8.2.19 Line Color B
D7 D6 D5 D4 D3
LB3
D2
LB2
D1
LB1
D0
LB0
CSB
RS
RDB
WRB
RE2
RE1
RE0
1
1
0
1
0
1
1
0
0
0
1
(At the time of reset: {LB3, LB2, LB1, LB0} = 0H, read address: DH)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
1
1
0
*
*
*
LB4
0
1
1
0
0
0
1
(At the time of reset: {LB4} = 0H, read address: EH) mark means "Don't care" Set line color B of rectangle.
64 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
NOTE When in 256 color mode, LB3 and LB2 don't care ; when 4k or 256 color mode, LB4 don't care
8.2.20 Fill Color R
D7 D6 D5 D4 D3
FR3
D2
FR2
D1
FR1
D0
FR0
CSB
RS
RDB
WRB
RE2
RE1
RE0
0
0
0
0
0
1
1
0
0
1
0
(At the time of reset: {FR3, FR2, FR1, FR0} = 0H, read address: 0H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
0
0
1
*
*
*
FR4
0
1
1
0
0
1
0
(At the time of reset: {FR4} = 0H, read address: 1H) mark means "Don't care" Set fill color R of rectangle.
NOTE When in 256 color mode, FR3 don't care ; when 4k or 256 color mode, FR4 don't care
8.2.21 Fill Color G
D7 D6 D5 D4 D3
FG3
D2
FG2
D1
FG1
D0
FG0
CSB
RS
RDB
WRB
RE2
RE1
RE0
0
0
1
0
0
1
1
0
0
1
0
(At the time of reset: {FG3, FG2, FG1, FG0} = 0H, read address: 2H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
0
1
1
*
*
FG5
FG4
0
1
1
0
0
1
0
(At the time of reset: {FG5, FG4} = 0H, read address: 3H) mark means "Don't care" Set fill color G of rectangle.
NOTE When in 256 color mode, FG3 don't care ; when 4k or 256 color mode, FG4 and FG5 don't care
8.2.22 Fill Color B
D7 D6 D5 D4 D3
FB3
D2
FB2
D1
FB1
D0
FB0
CSB
RS
RDB
WRB
RE2
RE1
RE0
0
1
0
0
0
1
1
0
0
1
0
(At the time of reset: {FB3, FB2, FB1, FB0} = 0H, read address: 4H)
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
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68COM/98SEG 65K Color STN LCD Drivers
D7
D6
D5
D4
D3
D2
D1
D0
CSB
RS
RDB
WRB
RE2
RE1
RE0
0
1
0
1
*
*
*
FB4
0
1
1
0
0
1
0
(At the time of reset: {FB4} = 0H, read address: 5H) mark means "Don't care" Set fill color B of rectangle.
NOTE When in 256 color mode, FB2 and FB3 don't care ; when 4k or 256 color mode, FB4 don't care
8.2.23 Dim, Copy & Clear Functions Control
D7 0 D6 1 D5 1 D4 0 D3 CLR D2 COPY D1 DBW D0 DIM CSB 0 RS 1 RDB 1 WRB 0 RE2 0 RE1 1 RE0 0
(At the time of reset: {CLR, COPY, DBW, DIM} = 0H, read address: 6H) mark means "Don't care" Clear function will clear the RAM data to `0' enclosed by rectangle area. The CLR bit control clear function enable or disable. CLR="0", clear function disable. CLR="1", clear function enable. Copy function will copy the specified rectangle to another destination. The COPY bit control copy function enable or disable. COPY="0", copy function disable. COPY="1", copy function enable. Dim function will dim the rectangle area to 50% black or 50% white. The DIM bit controls the dim function enable or disable. The DBW bit select dimming to 50% black or 50% white. DIM="0", dim function disable. DIM="1", dim function enable. DBW="0", dim to 50% black. DBW="1", dim to 50% white.
66 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
8.2.24 Copy Destination X Address
D7 0 D6 1 D5 1 D4 1 D3 CDX3 D2 CDX2 D1 CDX1 D0 CDX0 CSB 0 RS 1 RDB 1 WRB RE2 RE1 0 0 1 RE0 0
(At the time of reset: {CDX3, CDX2, CDX1, CDX0} = 0H, read address: 7H)
D7 1 D6 0 D5 0 D4 0 D3 * D2 CDX6 D1 CDX5 D0 CDX4 CSB RS RDB WRB RE2 RE1 RE0
0
1
1
0
0
1
0
(At the time of reset: {CDX6, CDX5, CDX4} = 0H, read address: 8H) mark means "Don't care" Set destination X address of copying rectangle. 0<= X <= 97
8.2.25 Copy Destination Y Address
D7 1 D6 0 D5 0 D4 1 D3 CDY3 D2 CDY2 D1 CDY1 D0 CDY0 CSB RS RDB WRB RE2 RE1 RE0
0
1
1
0
0
1
0
(At the time of reset: {CDY3, CDY2, CDY1, CDY0} = 0H, read address: 9H)
D7 1 D6 0 D5 1 D4 0 D3 CDY7 D2 CDY6 D1 CDY5 D0 CDY4 CSB 0 RS 1 RDB 1 WRB 0 RE2 0 RE1 1 RE0 0
(At the time of reset: {CDY7, CDY6, CDY5, CDY4} = 0H, read address: AH) mark means "Don't care" Set destination Y address of copying rectangle. 0<= Y <= 67
8.2.26 Scroll Top Address
D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 1 1
STA3 STA2 STA1 STA0
(At the time of reset: {STA3, STA2, STA1, STA0} = 0H, read address: 0H)
D7 0 D6 0 D5 0 D4 1 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 1 1
STA7 STA6 STA5 STA4
(At the time of reset: {STA7, STA6, STA5, STA4} = 0H, read address: 1H) mark means "Don't care" Set top address of scroll data area in RAM. 0 <= Scroll top address <= 67 ; Scroll top address must < Scroll bottom address
8.2.27 Scroll Bottom Address
D7 0 D6 0 D5 1 D4 0 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 1 1
SBA3 SBA2 SBA1 SBA0
(At the time of reset: {SBA3, SBA2, SBA1, SBA0} = FH, read address: 2H)
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
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D7 0
D6 0
D5 1
D4 1
D3
D2
D1
D0
CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 1 1
SBA7 SBA6 SBA5 SBA4
(At the time of reset: {SBA7, SBA6, SBA5, SBA4} = 9H, read address: 3H) mark means "Don't care" Set bottom address of scroll data area in RAM. 0 <= Scroll bottom address <= 67 ; Scroll top address must < Scroll bottom address
8.2.28 Scroll Specified Address
D7 0 D6 1 D5 0 D4 0 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 1 1
SSA3 SSA2 SSA1 SSA0
(At the time of reset: {SSA3, SSA2, SSA1, SSA0} = FH, read address: 4H)
D7 0 D6 1 D5 0 D4 1 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 1 1
SSA7 SSA6 SSA5 SSA4
(At the time of reset: {SSA7, SSA6, SSA5, SSA4} = 9H, read address: 5H) mark means "Don't care" According to the display panel size or the duty ratio selection, set the specified address in RAM where to jump to the scroll bottom address and then show the fixed data area. Scroll specified address = scroll top address + panel scroll area - 1
8.2.29 Scroll Start Address
D7 0 D6 1 D5 1 D4 0 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 1 1
SAY3 SAY2 SAY1 SAY0
(At the time of reset: {SAY3, SAY2, SAY1, SAY0} = 0H, read address: 6H)
D7 0 D6 1 D5 1 D4 1 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 1 1
SAY7 SAY6 SAY5 SAY4
(At the time of reset: {SAY7, SAY6, SAY5, SAY4} = 0H, read address: 7H) mark means "Don't care" Set the starting address of the area scrolling and then executes the area scroll operation. The scroll start address must be in the scrolling area. Scroll top address <= Scroll start address <= Scroll bottom address Note: The setting sequence of Scroll start address registers must be setting SAY[7:4] (Bank 3[7H]) first, then setting SAY[3:0] (Bank 3[6H]), to prevent error.
68 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
8.2.30 Scroll Mode Select
D7 1 D6 0 D5 0 D4 0 D3 * D2 * D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 0 1 1 SM1 SM0
(At the time of reset: {SM1, SM0} = 3H, read address: 8H) mark means "Don't care"
SM1 0 0 1 1 SM0 0 1 0 1 Type of Area Scroll Center screen scroll Top screen scroll Bottom screen scroll Whole screen scroll
8.2.31 RAM Data Writing Select Control
D7 D6 D5 D4 0 0 1 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 1 0 0 1 WBS RDWS2 RDWS1 RDWS0
(At the time of reset: {WBS, RDWS2, RDWS1, RDWS0} = 0H, read address: 3H) mark means "Don't care" The WBS bit select byte writing sequence while display data writing. WBS=0, low byte writing first WBS=1, high byte writing first The RDWS[2:0] select RAM data writing mode shown as follow:
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
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70 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
8.2.32 Display Start Common
D7 0 D6 1 D5 1 D4 0 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 1 0 0 SC3 SC2 SC1 SC0
(Read address=6H) (At the time of reset:{SC3,SC2,SC1,SC0}=0H) mark means "Don't care" The SC register set up the scanning start output of the common driver.
SC3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 SC2 0 0 0 0 1 1 1 0 0 0 1 1 1 1 SC1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 SC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Display Starting Common when SHIFT=0 COM0~ COM10~ COM20~ COM30~ COM40~ COM50~ COM60~ COM67~ COM59~ COM49~ COM39~ COM29~ COM19~ COM9~ Display Starting Common when SHIFT=1
SHIFT="0": COM0 to COM67 shift-scan SHIFT="1": COM67 down to COM0 shift-scan
8.2.33 Temperature Compensation Set
D7 0 D6 1 D5 1 D4 1 D3 * D2 * D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 1 0 0 TCS1 TCS0
(At the time of reset:{ TCS1,TCS0 }=0H, read address: 7H) mark means "Don't care"
TCS1 0 0 1 1 TCS0 0 1 0 1 Temperature Compensation Slope -0.05% per C -0.1% per C -0.15% per C -0.2% per C
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
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68COM/98SEG 65K Color STN LCD Drivers K (T) (Temperature compensation output voltage) is control by TCS1, TCS0 and formerly environment temperature T.
K REF (T ) = K [(1 + TCS (T - 250C )]
TCS is selected by TCS1 and TCS0 K = 4.005*10^(-3) at 25C
Figure 8-1 Temperature Compensation Slope
8.2.34 Display Select Control
D7 1 D6 0 D5 0 D4 0 D3 * D2 GLSB D1 * D0 * CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 1 0 0
(At the time of reset: {GLSB} = 0H, read address: 8H) mark means "Don't care" GLSB In 256 color mode, for the segment driver of 4-gradation display, select 4 gradations from 8 gradations using the 2 bits written to the corresponding RAM area and the 1 bit supplemented by the gradation LSB circuit. Supplement the 1 bit of data by setting the gradation LSB register (GLSB). Gradation LSB = "0": Selects 0 as the LSB information on the RAM for 4-gradation segment driver. Gradation LSB = "1": Selects 1 as the LSB information on the RAM for 4-gradation segment driver.
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Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
8.2.35 RAM Data Length Set
D7 1 D6 0 D5 0 D4 1 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 1 0 0 C256 HSW ABS WLS
(At the time of reset: {C256, HSW, ABS, WLS} = 0H, read address: 9H) mark means "Don't care" The WLS register select data bus size for access from MPU WLS = "0": The data bus size is 8-bits width WLS = "1": The data bus size is 16-bits width When MPU access to control register using 16-bits bus size , high byte data is ignored. ABS ABS= "0": normal mode ABS= "1": change corresponding bit from input data bus HSW HSW="0": High speed writing mode off HSW="1": High speed writing mode on accessing the 8-bit data RAM *HSW is only used for horizontal direction (X-direction) of multi-RAM data write mode. C256 C256= "0": 4096-color mode C256= "1": 256-color mode *IF 65K=1, C256 is prohibited control bit.
8.2.36 Electronic Volume Register
D7 1 D6 0 D5 1 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0 DV3 DV2 DV1 DV0
(Read address: AH)
D7 1 D6 0 D5 1 D4 1 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0
DV6 DV5 DV4
(Read address: BH) (At the time of reset: {DV6~DV0} = 00H) mark means "Don't care" The DV register can control VEV voltage.
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
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The DV register has 7 bits, so can select 128 level voltage.
DV6 0 0 DV5 0 0 DV4 0 0 DV3 0 0 DV2 0 0 DV1 0 0 DV0 0 1 Output Voltage Smaller
1 1
1 1
1 1
1 1
1 1
1 1
0 1 Larger
The output voltage at VEV is specified by equation (1). VEV = K * (373+(DV+CV))-----------------------(1) (K: 4.005 * 10-3 temperature compensation coefficient, CV: Vop offset setting value of OTP) VEV range form 1.5V to 2V at 25 C The LCD drive voltage V0 is determined by VEV level and RM register value equation V0 = VEV * N --------------------------(2) (N = RM register value) In order to prevent transient voltage from generating when an electronic volume code is set, the circuit design is such that the set value is not reflected as a level immediately after only the upper bits (DV6-DV4) of the electronic code have been set. The set value becomes valid when the lower bits (DV3-DV0) of the electronic control volume code have also been set.
NOTE When writing code to set the electronic volume register, set DV6~DV4 first, then set DV3~DV0.
8.2.37 Internal Register Read Address
D7 1 D6 1 D5 0 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0 RA3 RA2 RA1 RA0
(At the time of reset: {RA3, RA2, RA1, RA0} = CH) The RA register set to specify the address for register read operation. The EM65570S has many registers and a register bank. Hence, a maximum of 4-steps are necessary to read a specific register. (1) Write 04H to RE register for access to RA register. (2) Writes specific register address to RA register. (3) Write specific register bank to RE register. (4) Read specific contents.
74 * Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
8.2.38 RC Oscillator Resistance Ratio
D7 1 D6 1 D5 0 D4 1 D3 D2 D1 D0 CSB RS 0 1 RDB WRB RE2 RE1 RE0 1 0 1 0 0 RF3 RF2 RF1 RF0
(At the time of reset: {RF3, RF2, RF1, RF0} = 0H, read address: DH) mark shows "Don't care" The RF registers can control the resistance ratio of RC oscillator. Hence, the frame frequency can change the RF registers setting. When change RF registers value, should be need to check LCD display quality.
RF3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RF2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RF1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RF0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Operation Initial Resistance Ratio 0.72 times of initial Resistance Ratio 0.86 times of initial Resistance Ratio 1.14 times of initial Resistance Ratio 1.28 times of initial Resistance Ratio 0.65 times of initial Resistance Ratio 0.79 times of initial Resistance Ratio 0.93 times of initial Resistance Ratio 1.07 times of initial Resistance Ratio 1.21 times of initial Resistance Ratio 1.35 times of initial Resistance Ratio 1.42 times of initial Resistance Ratio 1.49 times of initial Resistance Ratio 1.56 times of initial Resistance Ratio 1.63 times of initial Resistance Ratio 1.7 times of initial Resistance Ratio
8.2.39 Booster Frequency Control
D7 D6 D5 D4 1 1 1 0 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 1 0 0 BF1 BF0 HPM DIS
(At the time of reset: {BF1, BF0, HPM, DIS}=4H;read address: EH) The DIS register can control capacitors discharged that connected between the power supply V0-V4 for LCD drive voltage and VSS. When using this register, refer to 7-21 (Discharge circuit). DIS = "0": Discharge OFF DIS = "1": Discharge start
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
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The HPM register is the power control for the power supply circuit for liquid crystal drive. HPM= "H": High power mode HPM= "L": Normal mode BF1~BF0: The operating frequency in the booster is selected. When the boosting frequency is high, the driving ability of booster become high, but the current consumption is increased. Adjust the boosting frequency considering the external capacitors and the current consumption.
BF1 0 0 1 1 BF0 0 1 0 1 Booster Operating Clock Frequency 3kHz * 4 3kHz * 2 3kHz 3kHz * 8
8.2.40 Windows End X Address
D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 1 EX3 EX2 EX1 EX0
(At the time of reset: {EX3, EX2, EX1, EX0} = 0H, read address: 0H)
D7 0 D6 0 D5 0 D4 1 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 1
EX7 EX6 EX5 EX4
(At the time of reset: {EX7, EX6, EX5, EX4} = 0H, read address: 1H) Mark shows "Don't care" The EX registers set to X direction end address for window function.
8.2.41 Windows End Y Address
D7 0 D6 0 D5 1 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 1 EY3 EY2 EY1 EY0
(At the time of reset: {EY3, EY2, EY1, EY0} = 0H, read address: 2H)
D7 0 D6 0 D5 1 D4 1 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 1
EY7 EY6 EY5 EY4
(At the time of reset: {EY7, EY6, EY5, EY4} = 0H, read address: 3H) mark means "Don't care" The EY registers set to Y direction end address for window function.
76 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
8.2.42 Line Reverse Start Address
D7 D6 D5 D4 0 1 0 0 D3 D2 D1 D0 CSB RS 0 1 RDB 1 WRB 0 RE2 RE1 RE0 1 0 1 LS3 LS2 LS1 LS0
(At the time of reset: {LS3, LS2, LS1, LS0} = 0H, read address: 4H)
D7 D6 D5 D4 0 1 0 1 D3 D2 D1 D0 CSB RS 0 1 RDB 1 WRB 0 RE2 RE1 RE0 1 0 1
LS7 LS6 LS5 LS4
(At the time of reset: {LS7, LS6, LS5, LS4} = 0H, read address: 5H) mark means "Don't care" The LS registers set to line reverse start address. Moreover, must keep following two conditions. (1)
(2)
00H LS
LS
43H
LE LE: Line reverse end address
8.2.43 Line Reverse End Address
D7 0 D6 1 D5 1 D4 0 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 1 LE3 LE2 LE1 LE0
(At the time of reset: {LE3, LE2, LE1, LE0} = 0H, read address: 6H)
D7 0 D6 1 D5 1 D4 1 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 1
LE7 LE6 LE5 LE4
(At the time of reset: {LE7, LE6, LE5, LE4} = 0H, read address: 7H) mark means "Don't care" The LE registers set to line reverse end address. Moreover, must keep following two conditions.
(1)
00H LS
LS
43H
(2)
LE LS: Line reverse start address
8.2.44 Line Reverse Control
D7 D6 D5 D4 1 0 0 0 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 1 0 1 EOR BST BT LREV
(At the time of reset: {EOR, BST, BT, LREV} = 0H, read address: 8H) mark means "Don't care" The EOR control n-line alternated drive. EOR=0 EOR=1 M always reverses on the nth raster row regardless of whether the end of a frame is reached. M reverses at the nth raster row and restarts the raster row count at the start of every frame.
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EM65570S
68COM/98SEG 65K Color STN LCD Drivers The BST register controls the Fast Burst RAM write function BST = "0": Burst RAM write function OFF BST = "1": Burst RAM write function ON The LREV registers control line reverse display function. LREV = "0": Normal display (Not reverse). LREV = "1": Line reverse display enable. The area specified by Line Reverse Start/End Register reverse display. The reverse type is selectable by BT register. When using Line Reverse Display function, LS and LE registers must be kept in following relation. LS LE
The BT register controls the line reverse type. This is an option of line reverse display function. This BTs setting is only available in case of LREV="1" BT = "0": Reverse display BT = "1": Reverse display for every 32 frames.
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Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
8.2.45 Regulator Multiple Ratio Control
D7 D6 D5 D4 1 0 0 1 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 1 0 1 RM3 RM2 RM1 RM0
(At the time of reset: {RM3, RM2, RM1, RM0} = 5H, read address: 9H) mark means "Don't care" The booster steps set to RM register
RM3 0 0 0 0 0 0 1 RM2 0 0 0 0 1 1 0 RM1 0 0 1 1 0 0 0 RM0 0 1 0 1 0 1 0 Regulator Multiple Ratio Control 3.0 times voltage output 4.5 times voltage output 6.0 times voltage output 7.5 times voltage output 8.0 times voltage output 8.5 times voltage output 4.0 times voltage output
8.2.46 OTP Mode Select Register
D7 D6 D5 D4 D3 1 0 1 0 D2 D1 D0 * CSB RS RDB WRB RE2 RE1 RE0 0 1 1 0 1 0 1 M1 M0 VPP_EXT
(At the time of reset: {M1, M0, VPP_EXT, *} = CH, read address: AH) The (M1, M0) register control OTP mode
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(M1, M0) 00 01 10 11
OTP Operating Mode Read Program Reserve Standby
Delay Time -
NOTE 1. When using OTP Program function, RM must be 1000 (4 times) 2. In program mode, the delay time necessary is more than 1ms
8.2.47 Vop Calibration Offset Register
D7 1 D6 0 D5 1 D4 1 D3 D2 D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 1 CV3 CV2 CV1 CV0
(read address: BH)
D7 1 D6 1 D5 1 D4 0 D3 * D2 * D1 D0 CSB 0 RS 1 RDB WRB RE2 RE1 RE0 1 0 1 0 1
CV5 CV4
(read address: EH) The CV5~CV0 register control Vop calibration offset voltage selection VEV = K*(373+(DV+CV))
CV5~CV0 011111 011110 ... 000001 000000 100000 100001 ... 111111
K=4.005*10-3
Calibration Offset +31 +30 ... +1 0 -32 -31 ... -1
NOTE 1. if CV5~CV0 has not been programmed (OTP programming) , then CV5~CV0 will be equal to 3FH (-1) at the time of reset. 2. if CV5~CV0 have been programmed (OTP programming), then CV5~CV0 will be equal to the programming-value at the time of reset.
80 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
9
Absolute Maximum Rating
9.1 Absolute Maximum Ratings
Item Symbol VDD VEE VOUT VEV V0 V1,V2,V3,V4 VI Tstg Ta=25 C Condition Pin Used VDD VEE VOUT VEV V0 V1,V2,V3,V4 *1 Rating -0.3 ~ + 4.0 -0.3 ~ + 4.0 --0.3 ~ + 19 1.5 ~ + 2.0 -0.3 ~ + 18.5 -0.3 ~ V0+ 0.3 -0.3 ~ VDD+ 0.3 -45 ~ +125 Unit V V V V V V V C
Supply voltage (1) Supply voltage (2) Supply voltage (3) Supply voltage (4) Supply voltage (5) Supply voltage (6) Input voltage Storage temperature
9.2 Recommended Operating Conditions
Item Supply voltage Symbol VDD1 VDD2 VDD3 VEE Operating voltage V0 VOUT VEV Operating temperature Topr Pin VDD VDD VEE V0 VOUT VEV -30 1.5 Min. 2.2 2.4 2.4 4.5 Typ. Max. 3.3 3.3 3.3 18.5 19 2.0 85 Unit Note V V V V V V C *1 *2 *3 *4 *5
NOTE 1. Power supply for logic circuit 2. Power supply for analog circuit. 3. Power supply for internal boosting circuit. If applied voltage same as VDD, connect to VDD. 4. Voltage V0>V1>V2>V3>V4>VSS must always satisfied. 5. Voltage VOUT > V0 must always satisfy.
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10 DC electrical Characteristics
VSS=0V, VDD = 2.2 ~3.3V, Ta = -30 ~85 C
Item High level input voltage Low level input voltage High level output current Low level output current High level output current Low level output current Input leakage current Output leakage current LCD driver output resistance Standby current through VDD pin Oscillator frequency (48 gradation mode) Oscillator frequency (16 gradation mode) Oscillator frequency (8 gradation mode) Symbol VIH VIL IOH1 IOL1 IOH2 IOL2 ILI1 ILO Condition VOH = VDD-0.4V VOL= 0.4V VOH = VDD-0.4V VOL= 0.4V VI = VSS or VDD VI = VSS or VDD |Von| = 0.5V V0=10V V0=6V Min. 0.8VDD 0 -2.7 2.7 -0.8 0.8 -2 -2 1.0 1.2 Typ. 0.9VDD 0.1VDD -3.2 3.2 -1.0 1.0 0 0 1.3 1.7 5 Max. VDD 0.2VDD -3.5 3.5 -1.2 1.2 2 2 1.6 2.2 15 A 7 Unit V V mA mA mA mA A A Pin Used 1 1 2 2 3 3 4 5
RON
K
6
ISTB
CK=0, CSB=VDD, Ta=25 C, VDD=3V VDD=3V, Ta=25 C,
Fosc1
Rf setting = (Rf2,Rf1,Rf0)=(000) VDD=3V, Ta=25 C,
731
754
776
kHz
8
Fosc2
Rf setting = (Rf2,Rf1,Rf0)=(000) VDD=3V , Ta=25 C,
365
377
388
kHz
9
Fosc3
Rf setting = (Rf2,Rf1,Rf0)=(000)
182
188
193
kHz
10
Booster output Five times boosting VOUT1 5*VEE *0.95 5*VEE *0.98 5*VEE *0.99 voltage on VOUT RL = 500K (VOUT-VSS) pin Four times boosting VOUT2 4*VEE *0.95 4*VEE *0.98 4*VEE *0.99 RL = 500K (VOUT-VSS) VOUT3 Three times boosting RL = 500K (VOUT-VSS) 3*VEE *0.95 3*VEE *0.98 3*VEE *0.99
V V V
11 12 13
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Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
Item
Symbol
Condition Two times boosting
Min.
Typ.
Max.
Unit
Pin Used 14
VOUT4
RL = 500K (VOUT-VSS) VDD = 3.0V, 5 times booster, All ON pattern VDD = 3.0V, 5 times booster, Checker pattern VDD =2.4V~3.3V VDD = 2.4 ~ 3.3V
2*VEE *0.95 2*VEE *0.98 2*VEE *0.99
V
Current Consumption VEV output voltage V0 output voltage
IDD1 IDD2 VEV V0
1.5 0.99*V0
350 400 2.0 V0 1.01*V0
A A V V
15 16 17
Relationship between oscillating frequency (fosc) and external clock frequency (fCK) to LCD frame frequency (fFLM) is each display mode
Original Oscillating Clock When use built-in oscillating circuit (fosc) Display Duty Cycle Ratio (1/D) Display Mode 1/72 to 1/48 Simple gradation (65K color) Simple gradation (4096 color) Simple gradation (256 color) Simple gradation (65K color) fosc/(4*31*D) fosc/(4*15*D) fosc/(4*7*D) fCK/(4*31*D) fCK/(4*15*D) fCK/(4*7*D) 1/32 to 1/24 fosc/(8*31*D) fosc/(8*15*D) fosc/(8*7*D) fCK/(8*31*D) fCK/(8*15*D) fCK/(8*7*D) 1/16 fosc/(16*31*D) fosc/(16*15*D) fosc/(16*7*D) fCK/(16*31*D) fCK/(16*15*D) fCK/(16*7*D) 1/8 fosc/(32*31*D) fosc/(32*15*D) fosc/(32*7*D) fCK/(32*31*D) fCK/(32*15*D) fCK/(32*7*D)
When use external Simple gradation clock from (4096 color) CK pin. (fCK) Simple gradation (256 color)
Pin used: 1 2 3 4 5 6 D0-D15, CSB, RS, M/S, M86, RDB, WRB, CK, CKS, P/S, RESB, TEST pins. D0~D15 pins CLK pins CSB, RS, M/S, M86, RDB, WRB, CK, CKS, P/S, RESB, TEST pins Applied when D0~D15 are in the state of high impedance. SEGA0~SEGA97, SEGB0~SEGB97, SEGC0~SEGC97, COM0~COM67 pins Resistance when being applied 0.5V between each output pin and each power supply (V0, V1, V2, V3, V4) and when being applied 1/14 bias. VDD pin, VDD pin current without load at the stoppage of original oscillating clock and at non-select (CSB=VDD)
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Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
8 9 10 11
Oscillating frequency, when using the built-in oscillating circuit (48 gradation display mode) Oscillating frequency, when using the built-in oscillating circuit (16 gradation display mode) Oscillating frequency, when using the built-in oscillating circuit (8 gradation display mode) VOUT pin. When using the built-in oscillating circuit, the built-in power supply is used, and boosting 5 times is used, this pin is applied. VEE=2.4~3.3 V, The electronic control is preset (The code is ("1 1 1 1 1 1 1")). Measuring conditions: bias=1/4~1/9, 1/72 duty, without load. RL=500 K (between VOUT and VSS), C1=C2=1.0F, C3=0.1F, DCON=AMPON="1", BF="11" VOUT pin. When using the built-in oscillating circuit, the built-in power supply is used, and boosting 4 times is used, this pin is applied. VEE=2.4~3.3 V, The electronic control is preset (The code is ("1 1 1 1 1 1 1")). Measuring conditions: bias=1/4~1/9, 1/72 duty, without load. RL=500 K (between VOUT and VSS), C1=C2=1.0F, C3=0.1F, DCON=AMPON="1", BF="11" VOUT pin. When using the built-in oscillating circuit, the built-in power supply is used, and boosting 3 times is used, this pin is applied. VEE=2.4~3.3 V, The electronic control is preset (The code is ("1 1 1 1 1 1 1")). Measuring conditions: bias=1/4~1/9, 1/72 duty, without load. RL=500 K (between VOUT and VSS), C1=C2=1.0F, C3=0.1F, DCON=AMPON="1", BF="11" VOUT pin. When using the built-in oscillating circuit, the built-in power supply is used, and boosting 2 times is used, this pin is applied. VEE=2.4~3.3 V, The electronic control is preset (The code is ("1 1 1 1 1 1 1")). Measuring conditions: bias=1/4~1/9, 1/72 duty, without load. RL=500 K (between VOUT and VSS), C1=C2=1.0F, C3=0.1F, DCON=AMPON="1", BF="11" VDD, VEE pin. When the built-in oscillating circuit and built-in power supply are used and there is no access from MPU. This pin is applied. Boosting 5 times is used the electronic control is preset (The code is ("1 1 1 1 1 1 1")). Display ALL ON pattern {Rf2, Rf1, Rf0 = ("0 0 0 ") } and LCD driver pin with no load. Measuring conditions: VDD=VEE , C1=C2=1.0F, C3=0.1F, DV=7FH, RM=02H, DCON=AMPON="1" , NLIN="0", (BF1,BF0)=(1,1),1/72 duty , 1/7 bias , BF="11" VDD, VEE pin. When the built-in oscillating circuit and built-in power supply are used and there is no access from MPU. This pin is applied. Boosting 5 times is used the electronic control is preset (The code is ("1 1 1 1 1 1 1")). Display a checkered pattern, {Rf2, Rf1, Rf0 = ("0 0 0 ") } and LCD driver pin with no load. Measuring conditions: VDD=VEE, C1=C2=1.0F, C3=0.1F, DV=7FH, RM=02H, DCON=AMPON="1" , NLIN="0" ,(BF1,BF0)=(1,1) ,1/72 duty , 1/7 bias, BF="11"
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
12
13
14
15
16
84 *
EM65570S
68COM/98SEG 65K Color STN LCD Drivers 17 VEV pin. Measuring conditions: N times boosting (N=2~8), electronic control = "1 1 1 1 1 1 1" , Display a checkered pattern , DCON=AMPON="1" , NLIN="0" ,1/72 duty , VDD=VEE , C1=C2=1.0F, C3=0.1F , no load
NOTE The capacitor C1 is use for booster related pin. CAP1+, CAP1-, CAP2+, CAP2-, CAP3+, CAP3- , CAP4+ , CAP2- and VOUT, VSS The capacitor C2 is use for bias related pin. V0, V1, V2, V3, V4
11 Ac Electrical Characteristics
11.1 80-family MCU write timing
tAS8 tAH8
CSB RS
tW RLW 8 W RB tDS8 tW RHW 8 tDH8
D0-D15
tCYCW R8
VSS=0V, VDD = 2.7~3.3V, Ta = -30~+85 C
Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCWR8 tWRLW8 tWRHW8 tDS8 tDH8 Condition Min. 20 20 330 50 250 20 20 Typ. Max. Unit ns ns ns ns ns ns ns Pin Used CSB RS WRB (R/WB)
D0~D15
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(This specification is subject to change without further notice)
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VSS=0V, VDD = 2.4~2.7V, Ta = -30~+85 C
Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCWR8 tWRLW8 tWRHW8 tDS8 tDH8 Condition Min. 40 40 400 70 300 40 40 Typ. Max. Unit ns ns ns ns ns ns ns Pin Used CSB RS WRB (R/WB)
D0~D15
VSS=0V, VDD = 2.2~2.4V, Ta = -30~+85 C
Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCWR8 tWRLW8 tWRHW8 tDS8 tDH8 Condition Min. 40 40 500 100 350 40 40 Typ. Max. Unit ns ns ns ns ns ns ns Pin Used CSB RS WRB (R/WB)
D0~D15
NOTE All the timings must be specified relative to 20% and 80% of VDD voltage.
11.2 80-family MCU Read Timing
tAS8 CSB RS tAH8
RDB
tRDLW 8 tRDHW 8 tRDH8
tRDD8 D0-D15
tCYCRD8
86 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers VSS=0V, VDD = 2.7~3.3V, Ta = -30~+85 C
Item Address hold time Address setup time System cycle time in read Read pulse "L" width Read pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCRD8 tRDLW8 tRDHW8 tRDD8 tRDH8 CL = 80 pF 20 Condition Min. 20 20 530 220 280 230 Typ. Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
VSS=0V, VDD = 2.4~2.7V, Ta = -30~+85 C
Item Address hold time Address setup time System cycle time in read Read pulse "L" width Read pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCRD8 tRDLW8 tRDHW8 tRDD8 tRDH8 CL = 80 pF 40 Condition Min. 40 40 620 260 330 270 Typ. Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
VSS=0V, VDD = 2.2~2.4V, Ta = -30~+85 C
Item Address hold time Address setup time System cycle time in read Read pulse "L" width Read pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCRD8 tRDLW8 tRDHW8 tRDD8 tRDH8 CL = 80 pF 40 Condition Min. 40 40 720 290 390 300 Typ. Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
NOTE All the timings must be specified relative to 20% and 80% of VDD voltage.
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
* 87
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
11.3 68-family MCU Write Timing
tAS6 CSB RS tAH6
R/W B (W RB)
E (RDB)
tEHW 6
tELW 6
tDS6
tDH6
D0-D15
tCYCW R6
VSS=0V, VDD = 2.7 ~3.3V, Ta = -30~+85 C
Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCWR6 tELW6 tEHW6 tDS6 tDH6 Condition Min. 20 20 330 250 50 20 20 Typ. Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
VSS=0V, VDD = 2.4 ~2.7V, Ta = -30~+85 C
Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCWR6 tELW6 tEHW6 tDS6 tDH6 Condition Min. 40 40 400 300 70 40 40 Typ. Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
88 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
VSS=0V, VDD = 2.2 ~2.4V, Ta = -30~+85 C
Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCWR6 tELW6 tEHW6 tDS6 tDH6 Condition Min. 40 40 500 350 100 40 40 Typ. Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
NOTE All the timings must be specified relative to 20% and 80% of VDD voltage.
11.4 68-family MCU Read Timing
tAS6 CSB RS tAH6
R/W B (W RB)
E (RDB)
tEHW 6
tELW 6
tRDD6
tRDH6
D0-D15
tCYCRD6
VSS=0V, VDD = 2.7~3.3V, Ta = -30~+85 C
Item Address hold time Address setup time System cycle time in read Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCRD6 tELW6 tEHW6 tRDD6 tRDH6 CL=50pF Condition Min. 20 20 530 220 280 230 20 Typ. Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
* 89
EM65570S
68COM/98SEG 65K Color STN LCD Drivers VSS=0V, VDD = 2.4~2.7V, Ta = -30~+85 C
Item Address hold time Address setup time System cycle time in read Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCRD6 tELW6 tEHW6 tRDD6 tRDH6 Condition CL=50pF Min. 40 40 620 260 330 270 40 Typ. Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
VSS=0V, VDD = 2.2~2.4V, Ta = -30~+85 C
Item Address hold time Address setup time System cycle time in read Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCRD6 tELW6 tEHW6 tRDD6 tRDH6 CL=50pF Condition Min. 40 40 720 290 390 300 40 Typ. Max. Unit ns ns ns ns ns ns ns D0~D15 RDB(E) Pin Used CSB RS
NOTE All the timings must be specified relative to 20% and 80% of VDD voltage.
11.5 Serial Interface Timing Diagram
tCSS CSB tCSH
RS tASS tSLW SCL tDSS tSHW tAHS
tDHS
SDA
1st bit
tCYCS
7rd bit
90 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers VSS=0V, VDD = 2.7~3.3V, Ta = -30~+85 C
Item Serial clock period SCL pulse "H" width SCL pulse "L" width Address setup time Address hold time Data setup time Data hold time CSB-SCL time CSB hold time Symbol tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH Condition Min. 100 40 40 20 20 40 40 20 20 Typ. Max. Unit ns ns ns ns ns ns ns ns ns RS SCL Pin Used
SDA
CSB
VSS=0V, VDD = 2.4~2.7V, Ta = -30~+85 C
Item Serial clock period SCL pulse "H" width SCL pulse "L" width Address setup time Address hold time Data setup time Data hold time CSB-SCL time CSB hold time Symbol tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH Condition Min. 150 60 60 40 40 60 60 40 40 Typ. Max. Unit ns ns ns ns ns ns ns ns ns RS SCL Pin Used
SDA
CSB
VSS=0V, VDD = 2.2~2.4V, Ta = -30~+85 C
Item Serial clock period SCL pulse "H" width SCL pulse "L" width Address setup time Address hold time Data setup time Data hold time CSB-SCL time CSB hold time Symbol tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH Condition Min. 200 80 80 40 40 80 80 40 40 Typ. Max. Unit ns ns ns ns ns ns ns ns ns RS SCL Pin used
SDA
CSB
NOTE All the timings must be specified relative to 20% and 80% of VDD voltage.
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
* 91
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
11.6 Clock Input Timing
tCKLW CK tCKHW
VSS=0V, VDD = 2.2~3.3V, Ta = -30~+85 C
Item CK pulse "H" width CK pulse "L" width Symbol tTCKHW2 tCKLW2 Condition Min. 5.4 5.4 Typ. Max. 6.5 6.5 Unit s s Pin Used CK 1
1 Applied when the gradation display mode 65K="1"
11.7 Reset Timing
RESB
internal state
reset m ode
norm al dsiplay
VSS=0V, VDD = 2.2~3.3V, Ta = -30~+85 C
Item Reset time Reset pulse "L" width Symbol tR tRW 150 Condition Min. Typ. Max. 1 Unit s s RESB Pin Used
NOTE All the timings must be specified relative to 20% and 80% of VDD voltage.
92 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
12 Application Circuit
12.1 Connection to 80-family MCU
VCC A0 A1 to A7 80 family MPU Decoder /IORQ D0 to D15 /RD /WR /RES GND CSB RS
VDD
D0 to D15 RDB WRB RESB VSS
12.2 Connection to 68-family MCU
VCC A0 A1 to A15 68 family MPU Decoder VMA D0 to D15 E R/W /RES GND CSB RS
VDD
D0 to D15 RDB(E) WRB(R/W) RESB VSS
EM65570S
EM65570S
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
* 93
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
12.3 Connection to the MCU with Serial Interface
VCC A0 A1 to A7 MPU RS CSB
VDD
Decoder
PORT1 PORT2 /RES GND
SDA SCL RESB VSS
94 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
EM65570S
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
13 Tray Information
13.1 Tray Outline Dimensions
Symbol L1 L2 L3 T Sx Sy S X Y Dimensions in mm 50.75 45.50 45.70 4.00 15.40 4.16 15.95 14.78 0.05 1.27 0.05 Symbol Z Px Py Nx Ny N P1 P2 Dimensions in mm 0.61 0.05 20.00 1.77 2 25 50 1.76 1.60
Unit : mm
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)
* 95
EM65570S
68COM/98SEG 65K Color STN LCD Drivers
96 *
Product Specification (V1.0) 04.18.2006
(This specification is subject to change without further notice)

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