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TB62300FG
TOSHIBA BiCD IC Silicon Monolithic
TB62300FG
Dual Full-Bridge Driver for DC Motor
The TB62300FG is a dual brushed DC motors driver IC employing a chopper-based forward/reverse full-bridge mechanism. It controls two brushed DC motors at high precision. The motor supply voltage is up to 40 V and the VDD supply voltage is 5.0 V.
Features
* * * * * * * * * * * * * A single IC can drive two brushed DC motors. Monolithic Bi-CMOS IC Low ON-resistance (Ron) = 0.3 (Tj = 25C at 2.0 A typ.) Selectable current control: PWM current control using the PHASE pin or serial control Weight: 0.79 g (typ.)
5-bit DA converter for specifying current value and 2-bit DA converter for determining torque MIXED DECAY mode enables specification of current decay rate in four steps. Self-oscillation chopping frequency with external resistor and capacitor High-speed chopping at 100 kHz or higher ISD, TSD, and POR (VDD/VM) protection circuits Charge pump circuit (two external capacitors) for driving output 36-pin package: HSOP36 with heat sink Output voltage: 40 V (max) Output current: 2.5 A max (in steady-state phase) or 8 A max (pulsed output) Note: The values specified in this document are designed values, which are not guaranteed.
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TB62300FG
Block Diagram
1. Overview (for single axis)
VDD Sleep Current control data logic circuit Circuits used to set current value
DATA CLK STROBE Mixed decay timming, table logic circuit Current range controller (2-bit D/A) Chopping reference circuit 16-bit latch Chopping waveform generator circuit Waveform squaring circuit
Vref
Current value controller (5-bit D/A)
Current feedback circuit
RS
VRS circuit
RS comparator circuit
Output control circuit Mixed decay control Output pre driver
VM
Ccp 2 Charge pump circuit Ccp 1
ISD circuit
TSD circuit
Output circuit (H-bridge)
VDDR/VMR circuit Protection circuit
Out X
Brushed DC Motor
High-voltage (VM) Logic data Analog data IC pin
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CR
16-bit shift register
MODE PHASE ENABLE BRAKE
TB62300FG
Pin Assignment
RS A VREF A VREF B CR VM Ccp 1 Ccp 2 Ccp 3 VDD
1 2 3 4 5 6 7 8 9
36 RS B 35 SLEEP 34 ENABLE B 33 ENABLE A 32 PHASE B 31 PHASE A 30 DATA B 29 DATA A 28 CLK B
LGND
LGND
NC 10 TSTO 11 TSTI 12 BRAKE A 13 BRAKE B 14 NC 15 OUT A - 16 PGND 17 OUT A + 18
27 CLK A 26 STROBE B 25 STROBE A 24 MODE B 23 MODE A 22 NC 21 OUT B - 20 PGND 19 OUT B +
Note: When designing a ground line, make sure that all ground pins are connected to the same ground trail and remember to take heat radiation into account. When pins that are used to toggle between modes are controlled by a switch, pull up or down the pins to avoid high impedance. The IC may be destroyed due to short circuit between outputs, to supply, or to ground. Design output lines, VDD (VM) lines and ground lines with great care. When power supply pins (VM, RS, OUT, P-GND, VSS and CCP) that are exposed to high current, or logic input pins are not connected correctly, excessive current or malfunction may cause the IC to break down.
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TB62300FG
Pin Description
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 FIN1 FIN2 RS A VREF A VREF B CR VM Ccp 1 Ccp 2 Ccp 3 VDD NC TSTO TSTI BRAKE A BRAKE B NC OUT A - PGND OUT A + OUT B + PGND OUT B - NC MODE A MODE B STROBE A STROBE B CLK A CLK B DATA A DATA B PHASE A PHASE B ENABLE A ENABLE B SLEEP RS B LGND LGND Symbol Function A-ch output power supply pin (current detection pin) A-ch reference voltage input pin B-ch reference voltage input pin External chopping reference pin Supply voltage monitor pin Charge pump capacitor pin Charge pump capacitor pin Charge pump capacitor pin Logic power supply NC pin Test pin (usually not used) Test pin (usually not used) A-ch brake mode pin B-ch brake mode pin NC pin A-ch negative output pin VM ground A-ch positive output pin B-ch positive output pin VM ground B-ch negative output pin NC pin A-ch data mode switching pin B-ch data mode switching pin A-ch latch signal input pin B-ch latch signal input pin A-ch clock input pin B-ch clock input pin A-ch data input pin B-ch data input pin A-ch phase switching pin B-ch phase switching pin A-ch output forced OFF pin B-ch output forced OFF pin Operation stopped mode B-ch output power supply pin (current detection pin) Logic ground Logic ground Remarks Reference pin for A-axis supply voltage Reference power supply pin for A-axis current Reference power supply pin for B-axis current Pin used to set the chopping frequency Monitor (reference) pin for motor supply voltage Pin for connecting a charge pump capacitor Pin for connecting a charge pump capacitor Pin for connecting a charge pump capacitor Logic supply current input pin Note: Usually, leave this pin open. Note: Usually, leave this pin open. Note: Usually, connect this pin to LGND. Forced brake mode Forced brake mode Note: Usually, leave this pin open. A - output pin Power ground A + output pin B + output pin Power ground B - output pin Note: Usually, leave this pin open. Pin used to toggle between serial input and PWM control Pin used to toggle between serial input and PWM control Data input: latched on rising edge Data input: latched on rising edge Data input: referred to rising edge Data input: referred to rising edge Data input: Data input: PWM signal input pin: PWM signal input pin:: L: output stopped L: output stopped Internal logic cleared and charge pump stopped Reference pin for B-axis supply voltage Logic ground Logic ground
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Pin Description (Supplementary)
Pull-up/pull-down status and operation within the IC for input pins
Pin Number 10 Symbol NC Internal Pull-up/down Open Output Operation at High Does not affect normal operation of the IC. Does not affect normal operation of the IC (with the same withstand voltage as for VDD). Toshiba test mode Output Operation at Low Does not affect normal operation of the IC. Does not affect normal operation of the IC. Normal operation mode
11
TSTO
Output pin (usually low) Input pin (no pull-up or down) No pull-up or down No pull-up or down Open Open No pull-up or down No pull-up or down No pull-up or down No pull-up or down No pull-up or down No pull-up or down No pull-up or down No pull-up or down No pull-up or down No pull-up or down No pull-up or down No pull-up or down Pull-down with a 50-k resistor
12 13 14 15 22 23 24 25 26 27 28 29 30 31 32 33 34 35
TSTI BRAKE A BRAKE B NC NC MODE A MODE B STROBE A STROBE B CLK A CLK B DATA A DATA B PHASE A PHASE B ENABLE A ENABLE B SLEEP
Does not affect normal operation of the IC. Does not affect normal operation of the IC.
Does not affect normal operation of the IC. Does not affect normal operation of the IC.
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Truth Table (1)
Pin logic overview
Pin Number 23 24 25 26 31 32 Symbol MODE A MODE B STROBE A STROBE B PHASE A PHASE B Function A-ch data mode switching pin B-ch data mode switching pin A-ch latch signal input pin B-ch latch signal input pin A-ch phase switching pin B-ch phase switching pin Logic H : Serial signal input control L : PWM control Note: When PWM control is selected, serial data bits D0 to D6 are valid while D7 to D13 are invalid. H : Latched on rising edge L : Pass-through H : Positive phase L : Negative phase H : Sleep released 35 SLEEP Operation stopped mode L : Sleep state All internal circuits, including charge pumps, are stopped. H : Output enabled Output transistors turned on L : Output disabled Output transistors turned off H : Brake applied PHASE and ENABLE pins disabled L : Brake released
33 34 13 14
ENABLE A ENABLE B BRAKE A BRAKE B
A-ch output forced OFF pin B-ch output forced OFF pin A-ch brake mode pin B-ch brake mode pin
Truth Table (2)
Overall logic
External Pins SLEEP 0 1 ENABLE A/B X 0 1 BRAKE A/B X X 1 0 MODE A/B X X X 0 0 1 1 PHASE A/B X X X 1 0 X X Serial PHASE X X X X X 1 0 Sleep mode Disable mode Breake ON Forward Reverse Forward Reverse Status
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IC State for Each Function
Function SLEEP ENABLE POR ISD TSD Internal Logic Reset Maintained Reset Reset Reset Output OFF OFF OFF OFF OFF Charge Pump OFF Operating OFF OFF OFF OSC OFF Operating OFF OFF OFF Recovery Time tONG = 2.0 ms (typ.)/4.0 ms (max) N/A tONG = 2.0 ms (typ.)/4.0 ms (max) tONG = 2.0 ms (typ.)/4.0 ms (max) tONG = 2.0 ms (typ.)/4.0 ms (max)
Serial Input Signals
Order of data input Data Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Strobe Data Clock Register A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Name TBlank 0 TBlank 1 TBlank 2 Torque 0 Torque 1 Decay mode 0 Decay mode 1 Current 0 Current 1 Current 2 Current 3 Current 4 Phase

Function
Initial Value 0
Initial State
When PWM is Operating
Set blanking time to prevent false detection due to noise
1 1
1 / fchop / 16 x 7
Enabled
Set current range
0 0 1 0 1 1
25% Mixed decay mode (37.5%)
Enabled
Set decay mode
Enabled
Set current
1 1 1
100%
Disabled
Switch phase

0

Negative

Disabled

D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Notes on TBlank Setting
When using PWM control and serial control simultaneously, constant-current chopping may be disabled depending on the TBlank setting. Using constant-current chopping requires the following phase width in Fast Decay mode: (TBlank setting + 2/fcr) x 2
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Setting Table (1): D0, D1, D2
Blanking time settings
Data Bit 0 1 2 Name TBlank 0 TBlank 1 TBlank 2 Function Set blanking time to prevent false detection due to noise TBlank 2 0 0 0 0 1 1 1 1 TBlank 1 0 0 1 1 0 0 1 1 TBlank 0 0 1 0 1 0 1 0 1 Setting TBlank (typ.) 1 / fChop / 16 x 1 1 / fChop / 16 x 2 1 / fChop / 16 x 3 1 / fChop / 16 x 4 1 / fChop / 16 x 5 1 / fChop / 16 x 6 1 / fChop / 16 x 7 1 / fChop / 16 x 8
Setting Table (2): D3, D4
Torque settings
Data Bit 3 4 Name Torque 0 Torque 1 Function Set current range Torque 1 0 0 1 1 Torque 0 0 1 0 1 Setting Torque (typ.) 25% 50% 75% 100%
Setting Table (3): D5, D6
Decay mode settings
Data Bit 5 6 Name Decay mode 0 Decay mode 1 Function Set decay mode Torque Mode 1 0 0 1 1 Torque Mode 0 0 1 0 1 Setting Decay Mode Slow decay mode Mixed decay mode: 37.5% Mixed decay mode: 75.0% Fast decay mode
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Setting Table (4): D7, D8, D9, D10, D11
Current settings
Data Bit 7 8 9 10 11 Name Current 0 Current 1 Current 2 Current 3 Current 4 Function Set current Current 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Current 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Current 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Current 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Current 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Setting Current 0% 3% 6% 9% 12% 16% 19% 22% 25% 29% 32% 35% 38% 41% 45% 48% 51% 54% 58% 61% 64% 67% 70% 74% 77% 80% 83% 87% 90% 93% 96% 100%
Setting Table (5): D12
Phase settings
Data Bit 12 Name Phase Function Switch phase Phase 0 1 Negative Positive Setting Phase
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PWM Operation
1 fCR (fchop*16) PHASE Internal reset signal Phase Blank Time Serial Blanking Time Total Blanking Time Example: 1/fcr*2 + 1/fcr*TBlank Output control signal 2 3 4 5 6
Input range for fcr clock 1/fcr*2 Example: 1/fcr*2 1/fcr*TBlank
Notes: fcr is 16 times the fchop frequency. PHASE is an external signal. The internal reset signal resets the internal clocks and counters. Phase Blank Time is time between either edge of the external PHASE signal and the leading edge of serial blanking time.
Description
The output H bridge is driven by an external PHASE signal. It, however, also uses the fcr signal, generated with external CR, to generate blanking time and Mixed Decay time. The above logic is configured to handle the two signals, PHASE and fcr, which are asynchronous to each other. The logic generates internal reset signal edges from external PHASE edges, resulting in the width equal to two fcr cycles. The fcr-based counter assumes the first fcr falling edge following the PHASE edge as the first count. The maximum phase difference between the PHASE and fcr signals is, therefore, one fcr cycle. The serial blanking time starts at the second count based on the fcr clock (The first three samples of serial blanking time signal must be 000). The last stage output is switched by the edge of the external PHASE signal. That means there is an interval of two fcr cycles before the set blanking time starts. To cover the interval, the logic generates the time between the PHASE signal edge and blanking time start as phase blank time, during which comparison is masked off in the same way as in blanking time. Consequently, the blanking time as viewed from outside the IC is within the range from one fcr cycle (TBlank (000)) to eight fcr cycles (TBlank (111)) + I phase difference between PHASE and fcr (up to two fcr cycles).
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Absolute Maximum Ratings (Topr = 25C)
Characteristics Logic supply voltage Maximum output voltage Peak output current (Note: preliminary specification) Continuous output current Logic input voltage Current detection pin voltage Symbol VDD VM IOUT (Peak) IOUT (Cont) VIN VRS IC alone Power dissipation PD When mounted on a board (Note)

Test Condition

Rating
-0.4 to 7.0
Unit V V A A V V W W C C C
40 8.0
tW 500 ns

2.5
-0.5 to VDD
VM 4.5 V 1.4 3.2
-40 to 85 -55 to 150
Operating temperature Storage temperature Junction temperature
Topr Tstg Tj
150
Note: When Topr = 45C, Tj = 150C and ja = 32C
Recommended Operating Conditions (Topr = 0 to 85C)
Characteristics Supply voltage Output voltage (Note 1) (Note 1) Symbol VDD VM IOUT (Peak) IOUT (Cont) VIN fCLK fchop Vref VRS Tj COSC ROSC CCPA CCPB (Note 2) tri/tfi VDD = 5.0 V VDD = 5.0 V VM = 24.0 V, TORQUE = 100% VDD = 5.0 V

Test Condition
Min 4.5 18.0

Typ. 5.0 24.0 6.4 1.5
Max 5.5 33.0 7.2 1.8 VDD 25.0 150 VDD
1.5
Unit V V A A V MHz kHz V V C pF k
F F s
VDD = 5.0 V VM = 33.0 V, tw 500 ns VM = 33.0 V
Output current (Note: preliminary specification) Logic input voltage range Clock frequency Chopping frequency Vref reference voltage Current detection pin voltage Junction temperature Oscillator capacitor Oscillator resistor Charge pump capacitor A Charge pump capacitor B Input rise and fall rate
0 1.0 20 2.0 0

30 3.0
1.0
120

270 3.9 0.22 0.022 0.1
5.0
Note 1: Do not reduce VDD to 0 V (ground) while VM voltage is applied. Such an attempt may damage the IC because there is a current path from the VM pin to VDD pin and the internal logic is undefined when VDD is not applied. Leaving VDD open (Hi-Z) is less likely to damage the IC, although it is not recommended. Note 2: The circuit configuration of this IC cannot handle extremely slow data input (on pins BREAK A, BREAK B, SLEEP, ENABLE A, ENABLE B, PHASE A, PHASE B, DATA A, DATA B, CLK A, CLK B, STROBE A, STROBE B, MODE A, and MODE B). Applying a slow signal having a period longer than 5 s may cause the IC to oscillate. (1) (2) Calculating the current IOUT = 1/3 x Vref (V) x (Torque (%) / RRS () ) x Current (%) where 1/3 is the Vref (GAIN):Vref attenuation ratio. Calculating the oscillation frequency fCR = 1/(KA) x (C x R + KB x C)) x [Hz] KA = 0.523, KB = 600, fchop = fCR/16 [Hz] [Example] When COSC = 270 pF and ROSC = 3.9 k: fCR = 1.57 MHz and fchop = 1.57/16 = 98.4 kHz
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Electrical Characteristics 1 DC Characteristics (unless otherwise specified, VM = 24 V, VDD = 5.0 V, Topr = 25 )
Characteristics High Input voltage Low Symbol VIH VIL IIH1 IIL1 IIH2 SLEEP pin IIL2 Current consumed by logic power supply IDD1 IDD2 DC VDD = 5.0 V, fcr stopped In SLEEP mode Output open, fCLK = 1 kHz, logic operating, VDD = 5 V, VM = 24 V, all output stages stopped, charge pump charged VM current consumption IM2 DC Output open, fCLK = 4 kHz, internal logic operating (100-kHz chopping), output stages operating without load, charge pump charged In SLEEP mode VRS = VM = 24 V, Vout = 0 V, ENABLE = Low, DATA = All low DC VRS = VM = 24 V, Vout = 24 V, ENABLE = Low, DATA = All low Output leakage current Lower IOL VRS = VM = Ccp A = Vout
= 24 V, SLEEP= Low A
Test Circuit DC
Test Condition CLK, STROBE, DATA, MODE, PHASE, ENABLE and PHASE pins CLK, STROBE, DATA, MODE, PHASE, ENABLE and PHASE pins
Min 2.0

Typ.

Max
Unit
V
0.8 1.0
A

3.0 0.3
1.0 200.0
A
Input current
DC
1.0 4.5 mA 1.0
IM1
4.3
7.0
mA 20.0 28.0
IM3
0.5
1.0
Output standby current
Upper
IOH
-400
Output bias current
Upper
IOB
-200
1.0
High Mid High Mid Low Low
VRS (H)
Vref = 3.0 V, Vref (gain) = 1/3.0 TORQUE = 11 = 100% set Vref = 3.0 V, Vref (gain) = 1/3.0 TORQUE = 10 = 75% set Vref = 3.0 V, Vref (gain) = 1/3.0 TORQUE = 01 = 50% set Vref = 3.0 V, Vref (gain) = 1/3.0 TORQUE = 00 = 25% set
100
Comparator reference voltage ratio
VRS (MH) DC VRS (ML)
73
75
77 %
48
50
52
VRS (L)
23
25
27
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TB62300FG
Electrical Characteristics 2 DC Characteristics (unless otherwise specified, VM = 24 V, VDD = 5.0 V, Topr = 25 )
Characteristics Output current interchannel error Output current setting error RS pin current Symbol
IOUT1 IOUT2
Test Circuit DC DC DC
Test Condition Error in output current between channels (IOUT = 1.5 A) IOUT = 1.5 A
Min
-5.0 -5.0
Typ.

Max 5.0 5.0
Unit % %
A
IRS RON1
IOUT = 1.5 A, VDD = 5.0 V, Tj = 25 C, forward direction IOUT = 1.5 A, VDD = 5.0 V, Tj = 25 C, reverse direction IOUT = 1.5 A, VDD = 5.0 V, Tj = 105 C, forward direction IOUT = 1.5 A, VDD = 5.0 V, Tj = 105 C, reverse direction DC VM = 24 V, VDD = 5.0 V, ENABLE, output operation Vref = 3.0 V, VM = 24 V, VDD = 5.0 V, SLEEP
0.3
0.4
RON1 Output transistor drain-source ON-resistance RON2 DC
0.3
0.4
0.4
0.55
RON2
0.4
0.55
VREF input voltage
Vref
2.0
VDD
V
VREF input current
Iref
DC
100
A
VREF attenuation ratio
Vref (GAIN) (Note 1) TjTSD ISD Vpor (VDD) Vpor (VM)
DC
Vref = 3.0 V, VM = 24 V, VDD = 5.0 V, SLEEP
1/2.82
1/3
1/3.18
TSD operating temperature Overcurrent protection circuit operating current
DC DC
VDD = 5 V, VM = 24 V VDD = 5 V, VM = 24 V VM = 24 V VDD = 5 V
130

170

C A
6.0
DC DC
3.0 15.0
Output OFF mode supply voltage
V
Note 1: Thermal shutdown (TSD) circuit When the IC junction temperature reaches the specified value and the TSD circuit is activated, the internal reset circuit turns output off. The TSD activation temperature can be set within the range from 130C (min) to 170C (max). Once the TSD circuit is activated, output is stopped until a pulse (L to H to L) is subsequently applied to the SLEEP pin. The charge pump is halted while the TSD circuit is active. The TSD circuit does not include hysteresis. Applying a pulse (L to H to L) to the SLEEP pin deactivates the circuit. Note 2: Overcurrent protection circuit (ISD) This circuit is activated when a current pulse exceeding the specified output value is applied for a period of 1/2fCHOP (min) to fCHOP (max). The circuit activates the internal reset circuit to turn output off. Once it is activated, output is stopped until a pulse (L to H to L) is subsequently applied to the SLEEP pin. While the ISD circuit is active, the IC is placed in SLEEP mode with the charge pump halted.
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AC Characteristics (Topr = 25C, VM = 24 V, VDD = 5 V with load of 6.8 mH/5.7 )
Characteristics Clock frequency Symbol fCLK tw (tCLK) Minimum clock pulse width twp twn tWSTROBE Minimum STROBE pulse width tSTROBE (H) tSTROBE (L) Minimum SLEEP pulse width Phase difference between PHASE signal and fcr Blanking time for preventing false detection Data setup time tWSTROBE tp AC AC AC AC Test Circuit
Test Condition
Min 1.0 40.0 20.0 20.0 40.0 20.0 20.0 tONG
Typ.

Max 25.0

Unit MHz
ns
ns
ns ns
1/fCR
tBLNIK tsSIN-CLK tsST-CLK
(Note 1)
300

ns
20.0 AC 20.0 AC AC AC 20.0 20.0 20.0 20.0

ns
Data hold time STROBE setup time (relative to CLK) STROBE hold time (relative to CLK)
thSIN-CLK thST-CLK tsSSB-CLK thSB-CLK tf tf tpLH
ns
ns
40.0 40.0 100 580 100 350 1000 350 1.3
100 100 200 1000 ns 200 700 2000 700 1.5 MHz
Output transistor switching time
tpHL tpLZ tpHZ tpZL tpZH
AC

CR reference signal oscillation frequency
fCR fchop (min)
Cosc = 270 pF, Rosc = 3.9 k
1.1
Chopping frequency
fchop (typ.) fchop (max)
20.0
150.0
kHz
Oscillation frequency Charge pump rise time
fchop tONG AC
When fCR = 480 kHz

30.0 2.0
kHz ms
4.0
Note 1: The blanking time is internally fixed but it can be elongated by applying a serial blanking time signal.
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TB62300FG
Test Circuit (DC)
IDD1 IDD2 A
5V
VDD CR
Iref Vref A A
Vref 3V 1 F
Rosc = 3.6 k Cosc = 560 pF 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V A A A A A STROBE A CLK A DATA A STROBE B CLK B DATA B SLEEP LGND (FIN) PHASE A PHASE B ENABLE A ENABLE B MODE A MODE B BRAKE A BRAKE B Ccp 1 Ccp 2
LGND
Iref Vref B A
Vref
LGND
3V
A
LGND VM A IM1, IM2, IM3 IOL IOH IOB RRS A 0.22 IOUT1, 2 M DC Motor A
V VRS RRS A A A
A
LGND 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V A A A A A A A A
B B RRS B A IRS
M DC Motor
RRS B 0.22
P-GND PGND Ccp 3
100 F 24 V
SGND
V LGND
Ccp 1 0.22 F
Ccp 2 0.022 F
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1 F
TB62300FG
Test Circuit (AC)
fCLK, tw (tCLK), twp, twn, twSTROBE, tSTROBE (H), tSTROBE (L), tsSIN-CLK, tsST-CLK, thSIN-CLK, thST-CLK fchop, fosc
5V
VDD Rosc = 3.6 k CR Cosc = 560 pF 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V LGND 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V A A A A A A A A STROBE A CLK A DATA A STROBE B CLK B DATA B SLEEP VSS (FIN) PHASE A PHASE B ENABLE A ENABLE B MODE A MODE B BRAKE A BRAKE B Ccp 1 Ccp 2
Iref Vref A A
Vref 3V 1 F
SGND
LGND Vref B
Vref 3V 1 F
LGND VM V VRS RRS A A A IOL IOH IOB RRS A IOUT1, 2 M DC Motor B B RRS B A IRS RRS B 1.0 M DC Motor 1.0 A
tBLNIK
P-GND
PGND
100 F 24 V
Ccp 3
PGND
V
Ccp 1 0.22 F
Ccp 2 0.022 F
tONG
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TB62300FG
AC Test Waveforms
DATA
DATA 15 thDATA
50%
DATA 0 tw (tCLK) 50%
DATA 1
CLOCK
tsDATA
tsSTROBE STROBE 50% twSTROBE SLEEP
tdCLOOK
twn
twn
50% twSLEEP
PHASE
50%
Out A tpLH tpHL
PHASE
ENABLE
50%
Out A tpZH tpHZ
tpZL
tpLZ
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TB62300FG
Waveform in Mixed Decay Mode (Current Waveform)
fchop Internal CR CLK signal fchop
IOUT Set current value 25% Mixed Decay Mode Set current value NF
NF
RNF MDT (Mixed Decay Timming) point
Output Transistor Operating Mode
VM RRS RS pin U1 ON (Note) U2 OFF U1 OFF (Note) VM RRS RS pin U2 OFF U1 OFF (Note) VM RRS RS pin U2 ON
Load L1 OFF L2 ON L1 ON
Load L2 ON L1 ON
Load L2 OFF
PGND Charge mode
PGND Slow mode
PGND Fast mode
Output Transistor Operation Functions
CLK Charge Slow Fast U1 ON OFF OFF U2 OFF OFF ON L1 OFF ON ON L2 ON ON OFF
Note: The above table is an example where current flows in the direction of the arrows in the above figures. When the current flows in the opposite direction of the arrows, see the table below.
CLK Charge Slow Fast U1 OFF OFF ON U2 ON OFF OFF L1 ON ON OFF L2 OFF ON ON
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Power Supply Sequence (Recommended)
VDD (max) VDD (min) VDD VDDR
GND VM VM (min) VMR GND Non-reset Internal reset Reset
VM
SLEEP input (Note1)
H L Takes up to tONG until operable Non-operable area
Note 1: If VDD drops to the level of the VDDR or below while the specified voltage is applied to the VM pin, the IC is internally reset. This is a protective measure against malfunction. Likewise, if VM drops to the level of VMR or below while regulation voltage is applied to VDD, the IC is internally reset as a protective measure against malfunction. To avoid malfunction, when turning on VM or VDD, applying a signal to the SLEEP pin at the above timing is recommended. It takes time for the output control charge pump circuit to stabilize. Wait up to tONG time after power on before driving a motor. Note 2: When the VM value is between 3.3 to 5.5 V, the internal reset is released, thus output may be active. In such a case, the charge pump circuit cannot operate properly because of insufficient voltage. The IC should be held in SLEEP mode until VM reaches 13 V or more. Note 3: Since VDD = 0 V and VM = voltage within the rating are applied, output is turned off by internal reset. At that time, a current of several mA flows due to a current path between VM and VDD. When the output voltage is high, make sure that the specified voltage is applied to VDD.
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TB62300FG
PD - Ta (Package power dissipation)
PD - Ta
3.5 3 (2)
(W) Power dissipation PD
2.5 2 1.5 1 0.5 0 0 (1)
25
50
75
100
125
150
Ambient temperature
Ta (C)
Transient thermal resistance (1) HSOP36 Rth (j-a) without a board (96C/W) (2) When mounted on a board (140 mm x 70 mm x 1.6 mm: 38C/W: typ.) Note: Rth (j-a): 8.5C/W
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TB62300FG
Relationship between VM and VH (charge pump voltage)
Note: VDD = 5 V Ccp 1 = 0.22 F, Ccp 2 = 0.022 F, fchop = 150 kHz (Care must be taken about the temperature charges of charge pump capacitor.)
VM - VH (& Vcharge UP)
50
VH voltage
Charge up voltage
VM voltage
40 Charge pump output voltage
Apply SLEEP signal.
VH voltage, charge up voltage (V)
30
VM voltage VMR
20
Maximum rating
10
Recommended operation area Usable area
0 0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Charge pump voltage VH = VDD + VM (= Ccp A) (V) (Maximum rating is VDD (7 V) + VM (40 V))
Supply voltage
VM
(V)
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TB62300FG
Operation of Charge Pump Circuit
RRS VDD = 5 V RS VM
VM = 24 V
VH i2 Output Comparator and Controller Output H switch Tr1 Tr2 Vz Di3 Di2 Di1 (1) i1
Ccp A
7
(2)
Ccp B Ccp 2 0.022 F Ccp C
(2)
Ccp 1 0.22 F
R1
VH = VM + VDD = charge pump voltage i1 = charge pump current i2 = gate block power dissipation
* Initial charging When RESET is released, Tr1 is turned on and Tr2 turned off. Ccp 2 is charged from VM via Di1. After Tr1 is turned off and Tr2 is turned on, and Ccp 1 is charged from Ccp 2 via Di2. When the voltage difference between VM and VH (Ccp A pin voltage = charge pump voltage) reaches VDD or higher, operation halts (in the steady-state phase). * Actual operation (4) (5) The charge of Ccp 1 charge is used at fchop switching and the potential of VH drops. The circuit is charged up by the operations of (1) and (2) above. (1) (2) (3)
Output switching Initial charging Steady-state phase
VH VM (1) (2) (3) t (4) (5) (4) (5)
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TB62300FG
Charge Pump Rise Time
VDD + VM VM + (VDD x 90%)
Ccp 1 voltage
VM
5V STANDBY 0V tONG 50%
tONG: Time taken for capacitor Ccp 2 (charging capacitor) to fill up Ccp 1 (storing capacitor) to VM + VDD after a reset is released. The internal circuits cannot drive the gates correctly until the voltage of Ccp 1 reaches VM + VDD. Be sure to wait for tONG or longer before driving the motors. Basically, the larger the Ccp 1 capacitance is, the smaller the voltage fluctuation is, though the initial charge up time is longer. The smaller the Ccp 1 capacitance is, the shorter the initial charge-up time is, but the voltage fluctuation is larger. Depending on the combination of capacitors (especially with small capacitance), voltage may not be sufficiently boosted. When the voltage does not increase sufficiently, RON of output DMOS becomes lower than the reference value, which raises the temperature. Thus, use the capacitors under the capacitor combination conditions (Ccp 1 = 0.22 F, Ccp 2 = 0.022 F) recommended by Toshiba.
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TB62300FG
External Capacitor for Charge Pump
When driving a motor while VDD = 5 V, fchop = 150 kHz, L = 10 mH under the conditions of VM = 27 V and 2.0 A, the logical values for Ccp 1 and Ccp 2 are as shown in the graph below:
Ccp 1 - Ccp 2
0.05 0.045 0.04 Applicable range
(F) Ccp 2 capacitance
0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Recommended value
Ccp 1 capacitance
(F)
Choose Ccp 1 and Ccp 2 to be combined from the above applicable range. We recommend Ccp 1:Ccp 2 at 10:1 or more. (If our recommended values (Ccp = 0.22 F, Ccp 2 = 0.022 F) are used, the drive conditions in the specification sheet are satisfied. (There is no capacitor temperature characteristic as a condition.) When setting the constants, make sure that the charge pump voltage is not below the specified value and set the constants with a margin (the larger Ccp 1 and Ccp 2, the more the margin). Some capacitors exhibit a large change in capacitance according to the temperature. Make sure the above capacitance is obtained under the IC ambient temperature.
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TB62300FG
Recommended Application Circuit
The values of external constants are example recommended values. For values under different input conditions, see the above-mentioned recommended operating conditions. (The following shows an example when fcho = 501 Hz (CR frequency = 800 kHz and constant-current limiter = 2.27 A) with serial signals placed in initial status.)
VDD
10 F 5V
Rosc = 3.6 k CR Cosc = 560 pF STROBE A CLK A DATA A STROBE B CLK B DATA B SLEEP LGND (FIN) PHASE A PHASE B ENABLE A ENABLE B MODE A MODE B BRAKE A BRAKE B Ccp 1 Ccp 2
Vref A
Vref 3V 1 F
SGND 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V
LGND Vref B
VM
RRS A A A
RRS A 0.11
LGND 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V 5V 0V
M DC Motor
B B RRS B
M DC Motor
RRS B 0.11
P-GND PGND Ccp 3
100 F 24 V
LGND
Ccp 1 0.22 F LGND
Ccp 2 0.022 F
Note: It is recommended to add bypass capacitors as required. Make sure that all gound pins are connected to the same ground rail. STROBE, CLK, and DATA must be tied to LGND if serial input is not used for settings or motor control. Because there may be short circuits between outputs, to supply, or to ground, be careful when designing output lines, VDD (VM) lines, and ground lines.
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TB62300FG
Connection Diagram (when external forced PWM mode is used)
0.5
10 F 3 V 3 V
1 RS A 2 VREF A 3 VREF B 4 CR 5 VM
RS B 36 SLEEP 35 ENABLE B 34 ENABLE A 33 PHASE B 32 PHASE A 31 DATA B 30 DATA A 29 CLK B 28
0.5
10 F 3.9 k 270 pF
100 F
24 V
6 Ccp 1 0.022 F 7 Ccp 2 0.22 F 8 Ccp 3 9 VDD
10 F 5V
5V
LGND
LGND
NC 10 TEST A NC 11 TEST B 12 TEST C 13 BRAKE A 14 BRAKE B 15 NC 16 OUT A - M 17 PGND 18 OUT A +
CLK A 27 STROBE B 26 STROBE A 25 MODE B 24 MODE A 23 NC 22 OUT B - 21 PGND 20 OUT B + 19 M
: Signal from central unit
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TB62300FG
Package Dimensions
HSOP36-P-450-0.65 Unit: mm
Weight: 0.79 g (typ.)
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TB62300FG
RESTRICTIONS ON PRODUCT USE
* The information contained herein is subject to change without notice.
030619EBA
* The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations.
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2005-04-04

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