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MC74LVX4052 Analog Multiplexer/ Demultiplexer
High-Performance Silicon-Gate CMOS
The MC74LVX4052 utilizes silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. This analog multiplexer/demultiplexer controls analog voltages that may vary across the complete power supply range (from VCC to VEE). The LVX4052 is similar in pinout to the high-speed HC4052A and the metal-gate MC14052B. The Channel-Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off. The Channel-Select and Enable inputs are compatible with standard CMOS outputs; with pull-up resistors, they are compatible with LSTTL outputs. This device has been designed so the ON resistance (RON) is more linear over input voltage than the RON of metal-gate CMOS analog switches and High-Speed CMOS analog switches.
http://onsemi.com MARKING DIAGRAMS
16 9
SO-16 D SUFFIX CASE 751B
LVX4052 AWLYYWW
1 8
16
9
* * * * *
TSSOP-16 DT SUFFIX CASE 948F
LVX 4052 AWLYWW
1 8
Fast Switching and Propagation Speeds Low Crosstalk Between Switches Analog Power Supply Range (VCC - VEE) = *3.0 V to )3.0 V Digital (Control) Power Supply Range (VCC - GND) = 2.5 to 6.0 V Improved Linearity and Lower ON Resistance Than Metal-Gate, HSL, or VHC Counterparts Low Noise
SO EIAJ-16 M SUFFIX CASE 966
16
9
LVX4052 ALYW
1 8
* * Designed to Operate on a Single Supply with VEE = GND, or Using *
Split Supplies up to $ 3.0 V Break-Before-Make Circuitry
A L, WL Y, YY W, WW
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device MC74LVX4052D MC74LVX4052DR2 MC74LVX4052DT Package SO-16 SO-16 TSSOP-16 Shipping 48 Units/Rail 2500 Units/Reel 96 Units/Rail
MC74LVX4052DTR2 TSSOP-16 2500 Units/Reel MC74LVX4052M MC74LVX4052MEL SO EIAJ-16 48 Units/Rail
SO EIAJ-16 2000 Units/Reel
(c) Semiconductor Components Industries, LLC, 2002
1
January, 2002 - Rev. 4
Publication Order Number: MC74LVX4052/D
MC74LVX4052
FUNCTION TABLE
VCC 16 X2 15 X1 14 X 13 X0 12 X3 11 A 10 B 9 Control Inputs Select Enable L L L L H X = Don't Care B L L H H X A L H L H X ON Channels Y0 Y1 Y2 Y3 NONE X0 X1 X2 X3
1 Y0
2 Y2
3 Y
4 Y3
5 Y1
6 7 Enable VEE
8 GND
Figure 1. Pin Connection and Marking Diagram (Top View)
Double-Pole, 4-Position Plus Common Off
X0 14 X1 15 X2 11 X3 Y0 Y1 Y2 Y3 A B
1 5 2 4 10 9 6 12
X SWITCH
13
X COMMON OUTPUTS/INPUTS
ANALOG INPUTS/OUTPUTS
Y SWITCH
3
Y
CHANNEL SELECT INPUTS
ENABLE
PIN 16 = VCC PIN 7 = VEE PIN 8 = GND
NOTE: This device allows independent control of each switch. Channel-Select Input A controls the X-Switch, Input B controls the Y-Switch.
Figure 2. Logic Diagram
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MC74LVX4052
NORMALIZED FAILURE RATE
TJ = 130_C
TJ = 120_C
TJ = 90_C
80 90 100 110 120 130 140
1,032,200 419,300 178,700 79,600 37,000 17,800 8,900
117.8 47.9 20.4 9.4 4.2 2.0 1.0
1 1 10 TIME, YEARS 100 1000
Figure 3. Failure Rate vs. Time Junction Temperature
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TJ = 80_C
Time, Hours
Time, Years
TJ = 100_C
TJ = 110_C
II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS (Note 1)
Symbol Parameter Value Unit V V V V VEE Negative DC Supply Voltage Positive DC Supply Voltage Analog Input Voltage Digital Input Voltage (Referenced to GND) VCC VIS (Referenced to GND) (Referenced to VEE)
*7.0 to )0.5 *0.5 to )7.0 *0.5 to )7.0 *0.5 to 7.0
$20
VEE *0.5 to VCC )0.5
VIN I
(Referenced to GND)
DC Current, Into or Out of Any Pin Storage Temperature Range
mA _C _C _C
TSTG TL TJ
*65 to )150
260 )150 143 164 500 450
Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature under Bias Thermal Resistance
qJA PD
SOIC TSSOP SOIC TSSOP
C/W mW
Power Dissipation in Still Air, Moisture Sensitivity
MSL FR
Level 1
Flammability Rating
Oxygen Index: 30% - 35%
UL-94-VO (0.125 in) u2000 u200 u1000 $300
VESD
ESD Withstand Voltage
Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4)
V
ILATCH-UP
Latch-Up Performance
Above VCC and Below GND at 125C (Note 5)
mA
1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum-rated conditions is not implied. 2. Tested to EIA/JESD22-A114-A. 3. Tested to EIA/JESD22-A115-A. 4. Tested to JESD22-C101-A. 5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol VEE Negative DC Supply Voltage Positive DC Supply Voltage Analog Input Voltage Digital Input Voltage Parameter (Referenced to GND) Min Max GND 6.0 6.0 Unit V V V V
II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III III II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I
VCC VIS TA (Referenced to GND) (Referenced to VEE) 2.5 2.5 VEE 0 VCC 6.0 125 100 20 VIN (Note 6) (Referenced to GND) VCC = 3.0 V $ 0.3 V VCC = 5.0 V $ 0.5 V Operating Temperature Range, All Package Types
*6.0
*55
0 0
_C
tr, tf
Input Rise/Fall Time (Channel Select or Enable Inputs)
ns/V
6. Unused inputs may not be left open. All inputs must be tied to a high-logic voltage level or a low-logic input voltage level.
DEVICE JUNCTION TEMPERATURE VERSUS TIME TO 0.1% BOND FAILURES
Junction Temperature C
FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR
MC74LVX4052
DC CHARACTERISTICS - Digital Section (Voltages Referenced to GND)
VCC V 2.5 3.0 4.5 6.0 2.5 3.0 4.5 6.0 VIN = 6.0 or GND Channel Select, Enable and VIS = VCC or GND 0 V to 6.0 V 6.0 Guaranteed Limit *55 to 25C 1.90 2.10 3.15 4.2 0.6 0.9 1.35 1.8 $0.1 4.0 v85C 1.90 2.10 3.15 4.2 0.6 0.9 1.35 1.8 $1.0 40 v125C 1.90 2.10 3.15 4.2 0.6 0.9 1.35 1.8 $1.0 80 Unit V
Symbol VIH
Parameter Minimum High-Level Input Voltage, Channel-Select or Enable Inputs
Condition
VIL
Maximum Low-Level Input Voltage, Channel-Select or Enable Inputs
V
IIN ICC
Maximum Input Leakage Current, Channel-Select or Enable Inputs Maximum Quiescent Supply Current (per Package)
mA mA
DC ELECTRICAL CHARACTERISTICS - Analog Section
II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I II I I I I II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I II I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I
SymbolIIIIIIII Parameter RON Maximum "ON" Resistance Test Conditions VCC V 3.0 4.5 3.0 3.0 4.5 3.0 Guaranteed Limit VEE *55 to 25C v85_C v125_C VIIIII 0 0 86 37 26 15 13 10 108 46 33 20 18 15 120 55 37 20 18 15 Unit W VIN = VIL or VIH VIS = 1/2 (VCC - VEE) |IS| = 2.0 mA (Figure 4) VIN = VIL or VIH VIS = 1/2 (VCC - VEE) |IS| = 2.0 mA
*3.0
0 0
RON
Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package
W
*3.0
0 -3.0 0 -3.0 0 -3.0
Ioff
Maximum Off-Channel Leakage Current, Any One Channel Maximum Off-Channel Leakage Current, Common Channel
Vin = VIL or VIH; VIO = VCC or GND; Switch Off (Figure 3) Vin = VIL or VIH; VIO = VCC or GND; Switch Off (Figure 4)
5.5 +3.0 5.5 +3.0 5.5 +3.0
0.1 0.1 0.2 0.2 0.2 0.2
0.5 0.5 2.0 2.0 2.0 2.0
1.0 1.0 4.0 4.0 4.0 4.0
mA
Ion
Maximum On-Channel Leakage Current, Channel-to-Channel
Vin = VIL or VIH; Switch-to-Switch = VCC or GND; (Figure 5)
mA
II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I I I I II I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I
Guaranteed Limit Symbol Parameter Test Conditions VCC V 3.0 4.5 3.0 VEE V 0.0 0.0 *55 to 25_C Typ* 6.5 5.0 3.5 Min 1.0 1.0 1.0 v85_C - - - v125_C - - - Unit ns tBBM Minimum Break-Before-Make Time VIN = VIL or VIH VIS = VCC RL = 300 W, CL = 35 pF (Figures 12 and 13)
AC CHARACTERISTICS (Input tr = tf = 3 ns)
*3.0
*Typical Characteristics are at 25_C.
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MC74LVX4052
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 3 ns)
Guaranteed Limit VCC V 2.5 3.0 4.5 3.0 2.5 3.0 4.5 3.0 2.5 3.0 4.5 3.0 VEE V 0 0 0 0 0 0 0 0 0
*55 to 25C
Min Typ Max 40 28 23 23 40 28 23 23 40 28 23 23
v85C Min Max 45 30 25 25 45 30 25 25 45 30 25 25
v125C Min Max 50 35 30 28 50 35 30 28 50 35 30 28 Unit ns
Symbol tPLH, tPHL
Parameter Maximum Propagation Delay, Channel-Select to Analog Output (Figures 16 and 17) Maximum Propagation Delay, Enable to Analog Output (Figures 14 and 15) Maximum Propagation Delay, Enable to Analog Output (Figures 14 and 15)
*3.0
tPLZ, tPHZ
ns
*3.0
tPZL, tPZH
ns
*3.0
Typical @ 25C, VCC = 5.0 V, VEE = 0V CPD CIN CI/O Power Dissipation Capacitance (Figure 18) (Note 7) Maximum Input Capacitance, Channel-Select or Enable Inputs Maximum Capacitance (All Switches Off) Analog I/O Common O/I Feedthrough 45 10 10 10 1.0 pF pF
pF
7. Used to determine the no-load dynamic power consumption: PD = CPD VCC2 f + ICC VCC .
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
VCC V 3.0 4.5 6.0 3.0 3.0 4.5 6.0 3.0 3.0 4.5 6.0 3.0 5.0 3.0 VEE V 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 Typ 25C 80 80 80 80 Unit MHz
Symbol BW
Parameter Maximum On-Channel Bandwidth or Minimum Frequency Response Off-Channel Feedthrough Isolation
Condition VIS = 1/2 (VCC - VEE) Ref and Test Attn = 10 dB Source Amplitude = 0 dB (Figure 7) f = 1 MHz; VIS = 1/2 (VCC - VEE) Adjust Network Analyzer output to 10 dBm on each output from the power splitter. (Figures 8 and 9) VIS = 1/2 (VCC - VEE) Adjust Network Analyzer output to 10 dBm on each output from the power splitter. (Figure 11) VIN = VCC to VEE, fIS = 1 kHz, tr = tf = 3 ns RIS = 0 W, CL= 1000 pF, Q = CL * VOUT (Figure 10) fIS = 1 MHz, RL = 10 KW, CL = 50 pF, VIS = 5.0 VPP sine wave VIS = 6.0 VPP sine wave (Figure 19)
*3.0
VISO
*3.0
*70 *70 *70 *70 *2 *2 *2 *2
9.0 12
dB
VONL
Maximum Feedthrough On Loss
dB
*3.0 *3.0
Q
Charge Injection
pC
THD
Total Harmonic Distortion THD + Noise
% 6.0 3.0
*3.0
0.0
0.10 0.05
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MC74LVX4052
PLOTTER
PROGRAMMABLE POWER SUPPLY * )
MINI COMPUTER
DC ANALYZER VCC
DEVICE UNDER TEST ANALOG IN COMMON OUT
GND
GND
Figure 4. On Resistance, Test Set-Up
VCC VCC VEE OFF VCC A NC OFF A COMMON O/I 16 VCC VEE VCC ANALOG I/O VIL VIH VEE 6 7 8 VEE 6 7 8 A ON OFF N/C COMMON O/I 16 VCC
Figure 5. Maximum Off Channel Leakage Current, Any One Channel, Test Set-Up
Figure 6. Maximum On Channel Leakage Current, Channel to Channel, Test Set-Up
HP4195A Network Anl S1 R1 T1
0.1 mF
HP11667B Pwr Splitter 0.1 mF
VIS
100 KW ON OFF
VCC
All untested Analog I/O pins 50 KW VEE 6 7 8
9 - 11
Channel Selects connected to address pins on HP4195A and appropriately configured to test each switch.
Figure 7. Maximum On Channel Bandwidth, Test Set-Up
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MC74LVX4052
HP4195A Network Anl S1 R1 T1
0.1 mF
HP11667B Pwr Splitter 0.1 mF
VIS 100 KW 16 OFF
VCC
All untested Analog I/O pins 50 KW VEE 6 7 8
ON
9 - 11
Channel Selects connected to address pins on HP4195A and appropriately configured to test each switch.
Config = Network Format = T/R (dB) CAL = Trans Cal VISO(dB) = 20 log (VT1/VR1) Display = Rectan X*A)B Scale Ref = Auto Scale View = Off, Off, Off Trig = Cont Mode Source Amplitude = )13 dB Reference Attenuation = 20 dB Test Attenuation = 0 dB
Figure 8. Maximum Off Channel Feedthrough Isolation, Test Set-Up
HP4195A Network Anl S1 R1 T1
0.1 mF
HP11667B Pwr Splitter 0.1 mF
VIS 100 KW VCC
16 OFF 50 KW All untested Analog I/O pins 50 W VEE 6 7 8 Channel Selects connected to address pins on HP4195A and appropriately configured to test each switch. ON
9 - 11
Config = Network Format = T/R (dB) CAL = Trans Cal Display = Rectan X*A)B Scale Ref = Auto Scale View = Off, Off, Off Trig = Cont Mode Source Amplitude = )13 dB Reference Attenuation = 20 dB Test Attenuation = 0 dB
VISOC(dB) = 20 log (VT1/VR1)
Figure 9. Maximum Common-Channel Feedthrough Isolation, Test Set-Up
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MC74LVX4052
VCC 16 ON/OFF VOUT OFF/ON Enable VEE VIN RIS 6 7 8 9 - 11 Bias Channel Selects to test each combination of analog inputs to common analog output. CL *
*Includes all probe and jig capacitance.
VIH VIS VIL Q = CL * DVOUT VOUT DVOUT
Figure 10. Charge Injection, Test Set-Up
HP4195A Network Anl S1 R1 T1
0.1 mF
HP11667B Pwr Splitter 0.1 mF
VIS
100 KW
16
VCC
ON All untested Analog I/O pins 50 W VEE 6 7 8 OFF
9 - 11
Config = Network Format = T/R (dB) CAL = Trans Cal Display = Rectan X*A)B Scale Ref = Auto Scale View = Off, Off, Off Trig = Cont Mode Source Amplitude = )13 dB Reference Attenuation = 20 dB Test Attenuation = 20 dB
Channel Selects connected to address pins on HP4195A and appropriately configured to test each switch.
VONL(dB) = 20 log (VT1/VR1)
Figure 11. Maximum On Channel Feedthrough On Loss, Test Set-Up
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MC74LVX4052
Tek 11801B DSO COM INPUT VCC
VCC
VIN VOH 80% 80% of VOH
16
OFF ON RL CL Channel Selects connected to VIN and appropriately configured to test each switch. 9 - 11 50 W VIN tBBM GND
VEE
6 7 8
Figure 12. Break-Before-Make, Test Set-Up
Figure 13. Break-Before-Make Time
VCC VCC CHANNEL SELECT 50% GND tPLH tPHL 6 7 8 ANALOG I/O OFF/ON ON/OFF
VCC 16 COMMON O/I TEST POINT CL *
ANALOG OUT
50%
CHANNEL SELECT *Includes all probe and jig capacitance.
Figure 14. Propagation Delays, Channel Select to Analog Out
Figure 15. Propagation Delay, Test Set-Up Channel Select to Analog Out
tf ENABLE tPZL ANALOG OUT tPZH ANALOG OUT 50% 50% tPLZ
tr 90% 50% 10% VCC GND HIGH IMPEDANCE 10% tPHZ 90% VOL VOH HIGH IMPEDANCE
GND POSITION 1 WHEN TESTING tPHZ AND tPZH 1 POSITION 2 WHEN TESTING tPLZ AND tPZL 2 VCC 1 2 ANALOG I/O ON/OFF VCC 16 1 K TEST POINT CL * ENABLE 6 7 8
Figure 16. Propagation Delays, Enable to Analog Out
Figure 17. Propagation Delay, Test Set-Up Enable to Analog Out http://onsemi.com
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MC74LVX4052
VCC A VCC ON/OFF NC OFF/ON VIL 15 12 10 - 11, 13 - 14 Channel Select
Figure 18. Power Dissipation Capacitance, Test Set-Up
HP3466 DMM
)V COM )V COM
HP3466 DMM
HP E3630A DC Pwr Supply COM )20 V *20 V
HP 339 Distortion Measurement Set Analyzer Input COM Oscillator Output COM
16
ON 50 KW 6 7 8 OFF RL CL
9 - 11
Channel Selects connected to DC bias supply or ground and appropriately configured to test each switch.
Figure 19. Total Harmonic Distortion, Test Set-Up
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MC74LVX4052
APPLICATIONS INFORMATION The Channel Select and Enable control pins should be at VCC or GND logic levels. VCC being recognized as a logic high and GND being recognized as a logic low. In this example: VCC = )5 V = logic high GND = 0 V = logic low The maximum analog voltage swing is determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In this example, the difference between VCC and VEE is five volts. Therefore, using the configuration of Figure 21, a maximum analog signal of five volts peak-to-peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). However, tying unused analog inputs and
+3.0 V +3.0 V -3.0 V ANALOG SIGNAL ON 16 ANALOG SIGNAL +5 V +3.0 V -3.0 V GND ANALOG SIGNAL ON 16 ANALOG SIGNAL
outputs to VCC or GND through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that: VEE - GND = 0 to *6 volts VCC - GND = 2.5 to 6 volts VCC - VEE = 2.5 to 6 volts and VEE v GND When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external Germanium or Schottky diodes (Dx) are recommended as shown in Figure 22. These diodes should be able to absorb the maximum anticipated current surges during clipping.
+5 V +5 V GND
-3.0 V
6 7 8
11 10 9
TO EXTERNAL CMOS CIRCUITRY 0 to 3.0 V DIGITAL SIGNALS
6 7 8
11 10 9
TO EXTERNAL CMOS CIRCUITRY 0 to 5 V DIGITAL SIGNALS
Figure 20. Application Example
Figure 21. Application Example
VCC Dx
VCC 16 ON/OFF
VCC Dx
Dx VEE
Dx VEE
VEE
7 8
Figure 22. External Germanium or Schottky Clipping Diodes
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MC74LVX4052
A
10
LEVEL SHIFTER
12
X0
14
X1
B
9
LEVEL SHIFTER
15
X2
11 13 ENABLE 6 LEVEL SHIFTER 1
X3 X Y0
5
Y1
2
Y2
4
Y3
3
Y
Figure 23. Function Diagram, LVX4052
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MC74LVX4052
PACKAGE DIMENSIONS
SOIC-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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MC74LVX4052
PACKAGE DIMENSIONS
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K
16
2X
L/2
9
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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CC EE CC EE CC
K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
MC74LVX4052
PACKAGE DIMENSIONS
SOIC EIAJ-16 M SUFFIX CASE 966-01 ISSUE O
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z D e A VIEW P
c
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.78 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.031
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74LVX4052
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MC74LVX4052/D

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