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LH168A
LH168A
DESCRIPTION
The LH168A is a 384-output TFT-LCD source driver IC which can simultaneously display 262 144 colors in 64 gray scales.
384-output TFT-LCD Source Driver IC
PIN CONNECTIONS
444-PIN TCP TOP VIEW
FEATURES
* Number of LCD drive outputs : 384 * Built-in 6-bit digital input DAC * 2-port input for each circuit of data inputs R, G and B, and it is possible to sample and hold display data of two pixels at the same time * Possible to display 262 144 colors in 64 gray scales with reference voltage input of 10 gray scales : This reference voltage input corresponds to correction and intermediate reference voltage input can be abbreviated * Cascade connection * Sampling sequence : Output shift direction can be selected XO1, YO1, ZO1/XO128, YO128, ZO128 or ZO128, YO128, XO128/ZO1, YO1, XO1 * Shift clock frequency : 55 MHz (MAX.) * Supply voltages - VCC (for logic system) : +2.7 to +3.6 V - VLS (for LCD drive system) : +3.0 to +5.5 V * Package : 444-pin TCP (Tape Carrier Package)
XO1 1 YO1 2 ZO1 3
444 443 442 441
GNDA VLS TESTB XA5
436 XA0 435 YA5 430 YA0 429 ZA5 424 423 422 421 420 419 418 417 416 415 414 413 412 411 410 409 408 407 406 ZA0 SPOI GNDL POL1 POL2 CK VCC V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 SPIO XB5
CHIP SURFACE
401 XB0 400 YB5 395 YB0 394 ZB5 389 388 387 386 385 ZB0 LS LBR VLS GNDA
XO128 382 YO128 383 ZO128 384
NOTE :
Doesn't prescribe TCP outline.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
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LH168A
PIN DESCRIPTION
PIN NO. 1 to 384 385, 444 386, 443 387 388 389 to 394 395 to 400 401 to 406 407 408 to 417 418 419 420, 421 422 423 424 to 429 430 to 435 436 to 441 442 SYMBOL XO1-ZO128 GNDA VLS LBR LS ZB0-ZB5 YB0-YB5 XB0-XB5 SPIO V10-V1 VCC CK POL2, POL1 GNDL SPOI ZA0-ZA5 YA0-YA5 XA0-XA5 TESTB I/O O - - I I I I I I/O I - I I - I/O I I I I DESCRIPTION LCD drive output pins Ground pins for analog circuit Power supply pins for analog circuit Shift direction selection input pin Latch input pin Data input pins Data input pins Data input pins Start pulse input/cascade output pin Reference voltage input pins Power supply pin for digital circuit Shift clock input pin Input data polarity exchange input pins Ground pin for digital circuit Start pulse input/cascade output pin Data input pins Data input pins Data input pins IC test pin
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LH168A
BLOCK DIAGRAM
VCC GNDL 418 422 GNDA GNDA 385 444
LBR 387 SPIO 407 CK 419 POL1 421 XA0 436 401 XA5 441 406 YA0 430 395 YA5 435 400 ZA0 424 389 ZA5 429 394 POL2 420 LS 388 6x2 V1 417 V2 416 V3 415 V4 414 V5 413 V6 412 V7 411 V8 410 V9 409 V10 408 1 2 3 382 383 384 XO128 YO128 ZO128 OUTPUT CIRCUIT REFERENCE VOLTAGE GENERATION CIRCUIT 64 6x2 6x2 6x2 LEVEL SHIFTER 6x2 XB0 XB5 YB0 YB5 ZB0 6x2 ZB5 6x2 6x2 HOLD MEMORY 6x2 386 VLS 443 VLS 6x2 DATA LATCH 6x2 6x2 442 TESTB 12 64 SHIFT REGISTER 423 SPOI
SAMPLING MEMORY
DA CONVERTER
XO1 YO1 ZO1
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LH168A
FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK Shift Register Data Latch Sampling Memory Hold Memory Level Shifter Reference Voltage Generation Circuit DA Converter Output Circuit FUNCTION Used as a bi-directional shift register which performs the shifting operation by CK and selects bits for data sampling. Used to temporary latch the input data which is sent to the sampling memory. Used to sample the data to be entered by time sharing. Used for temporary latch processing of data in the sampling memory by LS input. Used to shift the data in the hold memory to the power supply level of the analog circuit unit and sends the shifted data to DA converter. Used to generate a gamma-corrected 64-level voltage by the resistor dividing circuit. Used to generate an analog signal according to the display data and sends the signal to the output circuit. Used as a voltage follower, configured with an operational amplifier and an output buffer, which outputs analog signals of 64 gray scales to LCD drive output pin.
INPUT/OUTPUT CIRCUITS
VCC
I
To Internal Circuit
GNDL
Applicable pins CK, LS, LBR, XA0-XA5, XB0-XB5, YA0-YA5, YB0-YB5, ZA0-ZA5, ZB0-ZB5
Fig. 1 Input Circuit (1)
VCC
I
To Internal Circuit
GNDL
GNDL
Applicable pins POL1, POL2
Fig. 2 Input Circuit (2)
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LH168A
VCC
VCC
I
To Internal Circuit
GNDL
Applicable pin TESTB
Fig. 3 Input Circuit (3)
Pch Tr
VCC
I
O
Output Signal
Output Control Signal Nch Tr GNDL
VCC
To Internal Circuit
GNDL
Applicable pins SPIO, SPOI
Fig. 4 Input/Output Circuit
VLS
Operational Amplifier O
+ -
From Internal Circuit
GNDA
Applicable pins XO1-XO128, YO1-YO128, ZO1-ZO128
Fig. 5 Output Circuit
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LH168A
FUNCTIONAL DESCRIPTION Pin Functions
SYMBOL VCC VLS GNDL GNDA SPIO SPOI FUNCTIONS Used as power supply pin for digital circuit, connected to +2.7 to +3.6 V. Used as power supply pin for analog circuit, connected to +3.0 to +5.5 V. Used as ground pin for logic circuit, connected to 0 V. Used as ground pin for LCD drive circuit, connected to 0 V. Used as input pins of start pulse and also used as output pins for cascade connection. When "H" is input into start pulse input pin, data sampling is started. On completion of sampling, "H" pulse is output to output pin for cascade connection. Pin functions are selected by LBR. For selecting, refer to "Functional Operations". Used as input pin for selecting the shift register direction. For selecting, refer to "Functional Operations". Used as input pin for parallel transfer from sampling memory to hold memory. Data is transferred at the rising edge and output from LCD drive output pin. Used as shift clock input pin. Data is latched into sampling memory from data input pin at the rising edge. Used as reference voltage input pins. Hold the reference voltage fixed during the period of V1-V10 LCD drive output. For relation between input data and output voltage values, refer to "Output Voltage Value". For internal gamma correction, refer to "Gamma Correction Value". Used as data input pins of R, G, and B colors. 6-bit x 2-pixel data are input from data pins at the rising edge of CK. For relation between input data and output voltage values, refer to "Functional Operations" and "Output Voltage Value". Select the data to be entered into X, Y, and Z according to picture element arrays of the panel. Used as LCD drive output pins which output the voltage corresponding to the input of data XO1-XO128, YO1-YO128, ZO1-ZO128 input pins (XA0 to XA5, XB0 to XB5, YA0 to YA5, YB0 to YB5, ZA0 to ZA5, ZB0 to ZB5). Data of XO1 to XO128 correspond to XA0 to XA5 and XB0 to XB5. Data of YO1 to YO128 correspond to YA0 to YA5 and YB0 to YB5, and data of ZO1 to ZO128 correspond to ZA0 to ZA5 and ZB0 to ZB5. For relation between input data and output voltage values, refer to "Functional Operations" and "Output Voltage Value". POL1 POL2 TESTB Used as input pins for input data polarity exchange. When "L" is entered, display data becomes normal mode. When "H" is entered, input data becomes polarity exchange mode (POL1 = A system, POL2 = B system). For relation between input data and output voltage values, refer to "Output Voltage Value". Must be connected to 0 V or opened. Used as pin for IC testing. Must be connected to VCC or opened.
LBR LS CK
XA0-XA5, YA0-YA5 ZA0-ZA5, XB0-XB5 YB0-YB5, ZB0-ZB5
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LH168A
Functional Operations
The following describes the relation between data input pin and output direction.
Data input pin XA0-XA5 YA0-YA5 ZA0-ZA5 XB0-XB5 YB0-YB5 ZB0-ZB5 Output direction XO1 YO1 ZO1 XO2 YO2 ZO2 XB0-XB5 YB0-YB5 ZB0-ZB5 XO128 YO128 ZO128
The following describes the relation between LBR pin, SPOI pin, SPIO pin and output direction.
OUTPUT DIRECTION RIGHT SHIFT (XO1, YO1, ZO1/XO128, YO128, ZO128) H Input Output LEFT SHIFT (ZO128, YO128, XO128/ZO1, YO1, XO1) L Output Input
PIN LBR SPOI SPIO
NOTE :
Color data corresponding to X, Y, and Z vary depending on the output direction.
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LH168A
Output Voltage Value
Two voltages are selected from all of the reference voltages (V1-V10) by the upper 3-bit data (D5, D4 and D3) of the 6-bit input data (D5, D4, D3, D2, D1 and D0) taken by time sharing, and intermediate
INPUT DATA 0 1 2 3 4 5 6 7 8 9 A B C D E F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F OUTPUT VOLTAGE POL1, POL2 = "L" V1 V2 + (V1 - V2) x 6/7 V2 + (V1 - V2) x 5/7 V2 + (V1 - V2) x 4/7 V2 + (V1 - V2) x 3/7 V2 + (V1 - V2) x 2/7 V2 + (V1 - V2) x 1/7 V2 V3 + (V2 - V3) x 7/8 V3 + (V2 - V3) x 6/8 V3 + (V2 - V3) x 5/8 V3 + (V2 - V3) x 4/8 V3 + (V2 - V3) x 3/8 V3 + (V2 - V3) x 2/8 V3 + (V2 - V3) x 1/8 V3 V4 + (V3 - V4) x 7/8 V4 + (V3 - V4) x 6/8 V4 + (V3 - V4) x 5/8 V4 + (V3 - V4) x 4/8 V4 + (V3 - V4) x 3/8 V4 + (V3 - V4) x 2/8 V4 + (V3 - V4) x 1/8 V4 V5 + (V4 - V5) x 7/8 V5 + (V4 - V5) x 6/8 V5 + (V4 - V5) x 5/8 V5 + (V4 - V5) x 4/8 V5 + (V4 - V5) x 3/8 V5 + (V4 - V5) x 2/8 V5 + (V4 - V5) x 1/8 V5 POL1, POL2 = "H" V10 V9 V9 + (V8 - V9) x 1/7 V9 + (V8 - V9) x 2/7 V9 + (V8 - V9) x 3/7 V9 + (V8 - V9) x 4/7 V9 + (V8 - V9) x 5/7 V9 + (V8 - V9) x 6/7 V8 V8 + (V7 - V8) x 1/8 V8 + (V7 - V8) x 2/8 V8 + (V7 - V8) x 3/8 V8 + (V7 - V8) x 4/8 V8 + (V7 - V8) x 5/8 V8 + (V7 - V8) x 6/8 V8 + (V7 - V8) x 7/8 V7 V7 + (V6 - V7) x 1/8 V7 + (V6 - V7) x 2/8 V7 + (V6 - V7) x 3/8 V7 + (V6 - V7) x 4/8 V7 + (V6 - V7) x 5/8 V7 + (V6 - V7) x 6/8 V7 + (V6 - V7) x 7/8 V6 V6 + (V5 - V6) x 1/8 V6 + (V5 - V6) x 2/8 V6 + (V5 - V6) x 3/8 V6 + (V5 - V6) x 4/8 V6 + (V5 - V6) x 5/8 V6 + (V5 - V6) x 6/8 V6 + (V5 - V6) x 7/8
value is determined by the lower 3-bit data (D2, D1 and D0). Relation between input data and output voltage values is shown below.
INPUT DATA 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F OUTPUT VOLTAGE POL1, POL2 = "L" V6 + (V5 - V6) x 7/8 V6 + (V5 - V6) x 6/8 V6 + (V5 - V6) x 5/8 V6 + (V5 - V6) x 4/8 V6 + (V5 - V6) x 3/8 V6 + (V5 - V6) x 2/8 V6 + (V5 - V6) x 1/8 V6 V7 + (V6 - V7) x 7/8 V7 + (V6 - V7) x 6/8 V7 + (V6 - V7) x 5/8 V7 + (V6 - V7) x 4/8 V7 + (V6 - V7) x 3/8 V7 + (V6 - V7) x 2/8 V7 + (V6 - V7) x 1/8 V7 V8 + (V7 - V8) x 7/8 V8 + (V7 - V8) x 6/8 V8 + (V7 - V8) x 5/8 V8 + (V7 - V8) x 4/8 V8 + (V7 - V8) x 3/8 V8 + (V7 - V8) x 2/8 V8 + (V7 - V8) x 1/8 V8 V9 + (V8 - V9) x 6/7 V9 + (V8 - V9) x 5/7 V9 + (V8 - V9) x 4/7 V9 + (V8 - V9) x 3/7 V9 + (V8 - V9) x 2/7 V9 + (V8 - V9) x 1/7 V9 V10 POL1, POL2 = "H" V5 V5 + (V4 - V5) x 1/8 V5 + (V4 - V5) x 2/8 V5 + (V4 - V5) x 3/8 V5 + (V4 - V5) x 4/8 V5 + (V4 - V5) x 5/8 V5 + (V4 - V5) x 6/8 V5 + (V4 - V5) x 7/8 V4 V4 + (V3 - V4) x 1/8 V4 + (V3 - V4) x 2/8 V4 + (V3 - V4) x 3/8 V4 + (V3 - V4) x 4/8 V4 + (V3 - V4) x 5/8 V4 + (V3 - V4) x 6/8 V4 + (V3 - V4) x 7/8 V3 V3 + (V2 - V3) x 1/8 V3 + (V2 - V3) x 2/8 V3 + (V2 - V3) x 3/8 V3 + (V2 - V3) x 4/8 V3 + (V2 - V3) x 5/8 V3 + (V2 - V3) x 6/8 V3 + (V2 - V3) x 7/8 V2 V2 + (V1 - V2) x 1/7 V2 + (V1 - V2) x 2/7 V2 + (V1 - V2) x 3/7 V2 + (V1 - V2) x 4/7 V2 + (V1 - V2) x 5/7 V2 + (V1 - V2) x 6/7 V1
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LH168A
(gamma) Correction Value
Between reference voltage input pins, 7 or 8 resistors of the same resistance value are connected in series. When the resistance ratio between respective reference voltage input pins matches the reference voltages (V2 to V9) for correction of LCD panel, the external power supply of the intermediate voltages (for V2 to V9 pins) is not required.
LH168A V1 V2 V3 R1 R2 R3 R4 R5 R6 R7 R8 R9 7 equal parts 8 equal parts 8 equal parts 8 equal parts 8 equal parts 8 equal parts 8 equal parts 7 equal parts
External Reference Voltage
V4 V5 V6 V7 V8 V9 V10
The following shows the ratio of correction resistance.
R9 R8 R7 R6 R5 R4 R3 R2 R1 7.85 1.98 1.32 0.99 0.91 1.24 1.08 2.15 2.48
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LH168A
PRECAUTIONS
Precautions when connecting or disconnecting the power supply This IC has some power supply pins, so it may be permanently damaged by a high current which may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating. Therefore, when connecting the power supply, observe the following sequence. VCC / logic input / VLS, V1-V10 When disconnecting the power supply, follow the reverse sequence. Reference voltage input The relation of the reference voltage input is shown here. GNDA < V1 V2 V9 V10 < VLS or VLS > V1 V2 V9 V10 > GNDA Maximum ratings When connecting or disconnecting the power supply, this IC must be used within the range of the absolute maximum ratings. Target output load This IC is designed for a 70 pF output load capacity. When using this IC for other than 70 pF panels, confirm the device is having no problem before using it.
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage SYMBOL VCC VLS VI VI VO VO TSTG APPLICABLE PINS VCC VLS V1-V10 SPIO, SPOI, CK, LS, LBR, POL1, POL2, TESTB, XA0-XA5, XB0-XB5, YA0-YA5, YB0-YB5, ZA0-ZA5, ZB0-ZB5 SPIO, SPOI XO1-ZO128 RATING -0.3 to +7.0 -0.3 to +7.0 -0.3 to VLS + 0.3 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -0.3 to VLS + 0.3 -45 to +125 UNIT V V V V V V C NOTE
Input voltage
1, 2
Output voltage Storage temperature
NOTES :
1. TA = +25 C 2. The maximum applicable voltage on any pin with respect to GNDL and GNDA (0 V).
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC Supply voltage VLS Reference voltage input V1-V10 Clock frequency fCK LCD drive output load capacity CL TOPR Operating temperature PARAMETER MIN. +2.7 +3.0 0 TYP. MAX. +3.6 +5.5 VLS 55 70 +75 UNIT V V V MHz pF C NOTE 1
-20
NOTE :
1. The applicable voltage on any pin with respect to GNDL and GNDA (0 V).
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LH168A
ELECTRICAL CHARACTERISTICS DC Characteristics
PARAMETER Input "Low" voltage Input "High" voltage Output "Low" voltage Output "High" voltage Input "Low" current
(VCC = +2.7 to +3.6 V, VLS = +3.0 to +5.5 V, TOPR = -20 to +75 C)
NOTE
SYMBOL CONDITIONS
Input "High" current
Supply current (In operation mode) Supply current (In standby mode) Supply current (In operation mode) Supply current (In standby mode)
Output voltage range Deviations between VOD output voltage pins Output current IO1, IO2 Resistance between RGMA reference voltage input pins
APPLICABLE PINS MIN. TYP. MAX. UNIT XA0-XA5, YA0-YA5, ZA0-ZA5, GNDL 0.3VCC V VIL XB0-XB5, YB0-YB5, ZB0-ZB5, VCC V VIH SPIO, SPOI, CK, LS, LBR 0.7VCC VOL IOL = 0.3 mA GNDL GNDL + 0.4 V SPIO, SPOI VOH IOH = -0.3 mA VCC - 0.4 VCC V XA0-XA5, YA0-YA5, ZA0-ZA5, XB0-XB5, YB0-YB5, ZB0-ZB5, 1 A IILL SPIO, SPOI, CK, LS, LBR, POL1, POL2 XA0-XA5, YA0-YA5, ZA0-ZA5, 1 A IILH1 XB0-XB5, YB0-YB5, ZB0-ZB5, SPIO, SPOI, CK, LS, LBR POL1, POL2 400 A IILH2 fCK = 55 MHz VCC-GNDL 12 mA fLS = 50 kHz ICC1 (Data sampling state) fCK = 55 MHz fLS = 50 kHz VCC-GNDL 4 mA ICC2 SPI = GND is fixed. (Standby state) fCK = 55 MHz 10 mA VLS-GNDA fLS = 50 kHz ILS1 (Data sampling state) fCK = 55 MHz fLS = 50 kHz VLS-GNDA 9 mA ILS2 SPI = GND is fixed. (Standby state) GNDA + 0.1 VLS - 0.1 V VOUT XO1-ZO128 -20 20 V1-V10 10 50 30 20 mV A k$
1 2
NOTES :
1. Criterion of evaluating voltage deviations. (a) Between output voltage pins Measuring values : Output voltage value at the time after 10 s at the rising edge of LS. (Average of several times) (Conditions) Output load capacity is 70 pF. In a state when the reference voltage is fixed. Expecting values : Calculated following these specifications. (Conditions) In a state when the reference voltage is fixed. (b) Between LCD drivers Measuring values : Applicable to (a). (Conditions) Applicable to (a). Expecting values : Applicable to (a). (Conditions) Applicable to (a). Each input voltage between the LCD drivers must be made perfectly equal by connecting corresponding reference voltage input pins. 2. IO1 : Applied voltage = 3.0 V for output pins XO1 to ZO128. Output voltage = 2.5 V for output pins XO1 to ZO128. VLS = 5.0 V IO2 : Applied voltage = 2.0 V for output pins XO1 to ZO128. Output voltage = 2.5 V for output pins XO1 to ZO128. VLS = 5.0 V
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LH168A
AC Characteristics
PARAMETER Clock frequency "H" level pulse width "L" level pulse width Input rise time Input fall time Data setup time Data hold time Start pulse setup time Start pulse hold time Start pulse width Start pulse output delay time LCD drive output delay time 1 LCD drive output delay time 2 LS signal-SPI signal set up time LS signal-CK signal hold time LS signal "H" level width
(VCC = +2.7 to +3.6 V, VLS = +3.0 to +5.5 V, TOPR = -20 to +75 C)
APPLICABLE PINS MIN. 4 CK 4 4 4 XA0-XA5, YA0-YA5, ZA0-ZA5, XB0-XB5, YB0-YB5, ZB0-ZB5, POL1, POL2 4 0 4 0 SPIO, SPOI CL = 10 pF CL = 70 pF XO1-ZO128 CL = 70 pF 1 -------fCK LS 9 1 -------fCK 1 -------fCK 12 3 10 TYP. MAX. 55 UNIT MHz ns ns ns ns ns ns ns ns ns ns s s ns ns ns
SYMBOL CONDITIONS fCK tCWH tCWL tCR tCF tSUD tHD tSUSP tHSP tWSP tDSP tDO1 tDO2 tLSSP tHLS tWLS
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LH168A
Timing Chart
1 fCK CK tSUSP SPIO Input (SPOI) XA0-XA5 XB0-XB5 YA0-YA5 YB0-YB5 ZA0-ZA5 ZB0-ZB5 POL1 POL2 tWSP tSUD tHD tHSP tCR tCWH 1 tCF tCWL 2
1
2
CK
LAST - 1 tDSP
LAST
SPIO Output (SPOI) tHLS LS tLSSP SPIO Input (SPOI) tDO1 XO1-ZO128 tDO2 Target voltage (6-bit accuracy) Target voltage (VLS x 0.1) tSUSP tHSP tWLS
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LH168AF
17.00.7 [31.0] [28.6 (E.L.)] 1.0 (SL) 27.6 (Backside PI coating) [0.80] 13.6 (SR)
NC GNDA COM4 COM3
Film center Device center 48.1750.2 44.86 0.200.03 0.20 0.350.03
0.20
0.03
0.20
0.350.03 14.0 (SL) 13.6 (SR) 27.1 (SL) 27.0 (SL) [P0.090 x (296 - 1) = 26.55 W0.045] 1.420.05
NC COM4 COM3 GNDA VLS LBR LS ZB0 ZB1 ZB2 ZB3 ZB4 ZB5 YB0 YB1 YB2 YB3 YB4 YB5 XB0 XB1 XB2 XB3 XB4 XB5 SPIO V10 V9 V8 V7 V6 V5 V4 V3 V2 V1 NC VCC CK POL2 POL1 GNDL SPOI ZA0 ZA1 ZA2 ZA3 ZA4 ZA5 YA0 YA1 YA2 YA3 YA4 YA5 XA0 XA1 XA2 XA3 XA4 XA5 VLS GNDA COM2 COM1 NC
PACKAGE
[0.80] 14.0 (SL) 1.0 (SL) 9.5 (SL) 1.420.05 0.200.03 1.4 (Backside PI coating) 25.60.05 (Holes) P0.40 x (64 - 1) = 25.20.04 W0.0200.03 5.6 (SL) 5.6 (SL) 10.0 (SL) 5.0 (SL) 5.0 (SL) 9.5 (SL) 1.5 (SL) 4.750.05 2-O1.0 (PI) 2-R0.8 (SR) Flexible slit O2.0 (Good device hole)
COM2
GNDA
COM1
NC
0.6 (SL)
1.5 (SL)
0.8 (SL)
UPILEX is a trademark of UBE INDUSTRIES, LTD..
Sprocket center 1.8 2.8 (SL) 4.3 (SL) 3.1 Chip center
2.1 (SL)
5.00.7 5.350.05(Hole) 6.9 (SR) 7.2 (SL) [9.2 (E.L.)] [16.8 (E.L.)] [10.0] 10.875 (SL)
14
20.4
MAX.
3.4 (SL)
4.8 (SR)
PACKAGES FOR LCD DRIVERS
0.400.02 0.600.02
0.600.02 0.400.02
6.60.05(Mark) [7.6 (E.L.)] (Resin area) P0.065 x (404 - 1) = 26.1950.04 W0.032 [P0.065 x (410 - 1) = 26.5850.04 W0.032] 27.0 (SL) 0.04 (Mark) 27.2 13.7 (SR) 27.6 (Backside PI coating) [28.6 (E.L.)] [31.0] 13.7 (SR) 1.4 (Backside PI coating)
4.5MAX. (Resin area) 2.1MAX. (Resin area) 2.4MAX. (Resin area)
8.3 (SR)
0.8 (SL)
[2.8TYP. (2.5MIN.)]
0.2MAX. Pattern side Flexible slit
0.75MAX. Backside
1.1MAX. Total
COM4 COM4 COM4 COM3 COM3 COM3 NC NC NC NC ZO128 YO128 XO128
o Tape Specification
Tape width Tape type Perforation pitch 48 mm Super wide 5 pitches
ZO1 YO1 XO1 NC NC NC NC COM2 COM2 COM2 COM1 COM1 COM1
o Tape Material
Substrate UPILEX S75 Adhesive #7100 USLP 18 m Cu foil [thickness] Solder resist Epoxy resin/Polyimide (Unit : mm)
[0.60]

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