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| SQ930C High-Speed USB 2.0 Video Camera Controller Brief Specification Version 1.3 - April 22nd , 2005 SERVICE & QUALITY TECHNOLOGY CO., LTD. 6F, No.150, Sec.4 Chengde Rd., Shrlin Chiu 111, Taipei, Taiwan, R.O.C. Tel: 886-2-66111177 Fax: 886-2-66106777 http://www.sq.com.tw/ Service & Quality Technology All Rights Reserved. High-Speed USB 2.0 Video Camera Controller SQ930C REVISION HISTORY Document NO: BE049302 REVISION # 1.0 1.1 DATE Aug 12 , 2004 Sep 17 , 2004 th th DESCRIPTION Formal release Revise 1.2 Features due to a software enhancement of JPEG decoding capability: 20 fps 30fps at VGA format PAGE P. 4 1.2 Nov 17th , 2004 Revise Table 2-10 8032 CPU Interface Pins (LQFP 128): description of port CPU_P3.0 P. 16 1.3 April 22 , 2005 nd 1. 2. Update 1.1 General Description Correct Figure 4-1 LFBGA 64-pin Package: bottom view - dimension 7.2 5.6 (mm) P. 4 P. 18 3. Correct Figure 4-2 LQFP 80-pin Package Diagram P. 19 Subject to Change Without Notice. PAGE 2 Version 1.3 - April 22nd , 2005 High-Speed USB 2.0 Video Camera Controller SQ930C TABLE OF CONTENTS 1. INTRODUCTION .......................................................................................................4 1.1 1.2 GENERAL DESCRIPTION...................................................................................................... 4 FEATURES ......................................................................................................................... 4 BLOCK DIAGRAM................................................................................................................ 6 LFBGA 64-PIN .................................................................................................................. 7 2.2.1 2.2.2 2.2.3 2.3 2.3.1 2.3.2 2.3.3 LFBGA 64 Pin Assignment ................................................................................. 7 LFBGA 64 Pin List .............................................................................................. 8 LFBGA 64 Pin Descriptions ................................................................................ 9 LQFP 80 Pin Assignment.................................................................................. 11 LQFP 80 Pin List............................................................................................... 12 LQFP 80 Pin Descriptions ................................................................................ 14 2. SYSTEM OVERVIEW................................................................................................6 2.1 2.2 LQFP 80-PIN................................................................................................................... 11 3. ELECTRICAL CHARACTERISTIC...........................................................................17 3.1 3.2 OPERATION CONDITIONS .................................................................................................. 17 DC CHARACTERISTICS ..................................................................................................... 17 LFBGA 64-PIN PACKAGE ................................................................................................. 18 LQFP 80-PIN PACKAGE.................................................................................................... 19 ORDERING INFORMATION.................................................................................................. 20 4. PACKAGING ...........................................................................................................18 4.1 4.2 4.3 Subject to Change Without Notice. PAGE 3 Version 1.3 - April 22nd , 2005 High-Speed USB 2.0 Video Camera Controller SQ930C 1. INTRODUCTION 1.1 General Description The SQ930C High-Speed USB 2.0 Video Camera Controller is a highly integrated and cost-effective solution designed for USB 2.0 PC Camera based applications. sensors with VGA / 1.3M pixels. The SQ930C is designed for USB 2.0, the mainstream specification of personal computers. Without the restrictions of USB 1.1 PC camera on USB band width, the SQ930C controller fully expresses the advantage of USB 2.0 on band width (about 40X times faster than USB 1.1). USB 1.1 specification. It is also fully compliant with The SQ930C utilizes lossless compression to achieve the best image quality. Based on SQ years of experiences in image processing technology, the It can interface to major brands of CMOS With an embedded high-efficient JPEG encoder engine; the transmission rate can achieve 30 frames per second at VGA raw data mode. SQ930C will be the best solution for PC camera manufacturers. 1.2 Features Hardware Fully compliant with high-speed USB 2.0 specification and 1.1 specification Supports varieties of CMOS sensor Movie mode (@ 60MHz) JPEG 30fps @ VGA (USB1.1/2.0) Raw data 30fps @ VGA (USB 2.0) Built-in JPEG encoder Embedded SRAM for image buffer to save overall system cost Supports global/color gain control Supports Operation Bias(OB) 8032 CPU Compatible with industry standard 803x/805x Standard 8051 instruction set Control signals for standard 803x/805x I/O ports 4 clocks/instruction cycle Embedded 256 bytes SRAM for CPU Embedded 32K bytes ROM for CPU One button shot (still image capture) Supports external EEPROM for PID/VID Uses USB bus power Operation clock: USB PIE & CPU at 30Mhz, others at 60Mhz Subject to Change Without Notice. PAGE 4 Version 1.3 - April 22nd , 2005 High-Speed USB 2.0 Video Camera Controller SQ930C Operation voltage: 3.3V IO 2.5 Core logic Firmware Supports Auto Exposure (AE) Supports Auto White Balance (AWB) Supports Auto Gain Control (AGC) Software Supports still image capture TWAIN/WDM software driver Compatible with Windows98SE/2000/ME/XP CMOS Sensors Supported CMOS sensor 1.3M: Micron MI1300 Omnivision OV9630 VGA: ICMedia ICM-105C Hynix HV7131E, HV7131R Micron MI0360 Omnivision OV7660 Subject to Change Without Notice. PAGE 5 Version 1.3 - April 22nd , 2005 High-Speed USB 2.0 Video Camera Controller SQ930C 2. SYSTEM OVERVIEW The SQ930C contains an image processor, a JPEG encoder, a PIE, a SRAM controller, and a SRAM buffer for video use. 2.1 Block Diagram Figure 2-1 shows the internal block diagram. EEPROM (PID/VID/other information) Serial interface 8032 CPU Image Processor JPEG Encoder ROM CMOS Sensor DMA Engine PIE USB 2.0/1.1 PC SRAM Controller SRAM FIGURE 2-1: SQ930C INTERNAL BLOCK DIAGRAM Subject to Change Without Notice. PAGE 6 Version 1.3 - April 22nd , 2005 High-Speed USB 2.0 Video Camera Controller SQ930C 2.2 2.2.1 LFBGA 64-pin LFBGA 64 Pin Assignment A B C D E F G H 1 2 3 4 5 6 7 8 FIGURE 2-2: LFBGA 64 PIN ASSIGNMENT DIAGRAM Subject to Change Without Notice. PAGE 7 Version 1.3 - April 22nd , 2005 High-Speed USB 2.0 Video Camera Controller SQ930C 2.2.2 LFBGA 64 Pin List TABLE 2-1: PIN LIST (LFBGA 64) PIN NO C3 B1 C1 C2 D2 C4 D3 C5 D5 E3 E1 F1 E2 F2 G1 H1 H2 G2 F3 H3 G3 B5 D6 C6 H4 G4 G5 H5 F5 G6 H6 H7 NAME AGND2 RPU DMRS DPRS AVCC2 AGND3 AVCC3 VCCIO GND CPU_P2.6 CPU_P2.5 CPU_P2.4 CPU_P2.3 CPU_P2.2 CPU_P2.1 CPU_P2.0 CPU_PSEN CPU_P1.3 CPU_P1.2 CPU_P1.1 CPU_P1.0 VCCK GND VCCIO CPU_P0.7 CPU_P0.6 CPU_P0.5 CPU_P0.4 CPU_P0.3 CPU_P0.2 CPU_P0.1 CPU_P0.0 PIN NO H8 G7 G8 F6 F7 F8 E6 E7 E8 D7 D8 F4 D4 C8 C7 B8 A8 A7 B7 A6 A5 E5 D1 B6 E4 A4 A3 B3 B4 A2 B2 A1 NAME CPU_ALE SEN_DATA0 SEN_DATA1 SEN_DATA2 SEN_DATA3 SEN_DATA4 SEN_DATA5 SEN_DATA6 SEN_DATA7 SUSPEND N.C ZREGO2.5 ZREGO3.3 SEN_CLK_OUT SEN_HCLK SEN_HSYNC SEN_VSYNC SEN_DATA9 SEN_DATA8 NRES USB_POWER GND CPU_P3.1 VCCK GND XOSCI XOSCO AVCC1 AGND1 RREF DM DP Subject to Change Without Notice. PAGE 8 Version 1.3 - April 22nd , 2005 High-Speed USB 2.0 Video Camera Controller SQ930C 2.2.3 LFBGA 64 Pin Descriptions TABLE 2-2: POWER SUPPLY PINS (LFBGA 64) PIN NO C3 D2 C4 D3 C5 D5 B5 D6 C6 D4 F4 E5 B6 E4 B3 B4 NAME AGND2 AVCC2 AGND3 AVCC3 VCCIO GND VCCK GND VCCIO ZREGO3.3 ZREGO2.5 GND VCCK GND AVCC1 AGND1 I/O PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR DESCRIPTION Analog ground Power, Analog AVCC=3.3 Analog ground Power, Analog AVCC=3.3 Power, Digital VCC=3.3 Digital ground Power, Digital VCCK=2.5 Digital ground Power, Digital VCC=3.3 Power, Digital VCC=3.3 Power, Digital VCCK=2.5 Digital ground Power, Digital VCCK=2.5 Digital ground Analog AVCC=3.3 Analog ground TABLE 2-3: SYSTEM PINS (LFBGA 64) PIN NO A6 A4 A3 NAME NRES XOSCI XOSCO I/O I I O DESCRIPTION Digital input Pull high to force ASIC normal action, low will into reset state. 12M Crystal in 12M Crystal out TABLE 2-4: 8032 CPU INTERFACE PINS (LFBGA 64) PIN NO D1 E3, E1, F1, E2, F2, G1, H1 H2 G2, F3, H3, G3 NAME CPU_P3.1 CPU_P2.6~ CPU_P2.0 CPU_PSEN CPU_P1.3~ CPU_P1.0 H4, G4, G5, H5, F5, G6, H6, H7 H8 CPU_P0.7~ CPU_P0.0 CPU_ALE O Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. I/O Microprocessor Data / Low Address Bus O I/O Program Store Enable is the read strobe to external program memory. Port 1.3~ Port 1.0 is an 4-bit bi-directional I/O port I/O I/O O DESCRIPTION Port 3.1 bi-directional I/O port Microprocessor High Address Bus Subject to Change Without Notice. PAGE 9 Version 1.3 - April 22nd , 2005 High-Speed USB 2.0 Video Camera Controller SQ930C TABLE 2-5: USB INTERFACE PINS (LFBGA 64) PIN NO B1 C1 C2 D7 A5 A2 B2 NAME RPU DMRS DPRS SUSPEND USB_POWER RREF DM I/O I I/O I/O O I I I/O DESCRIPTION Connect external resistor (1.5k 0.1%) to AVCC (Analog power 3.3V) USB1.1 data in Data negative pin terminal, connect to external resistor (39 0.1%) USB1.1 data in Data positive pin terminal, connect to external resistor (39 0.1%) Device entry normal mode when drive `L' Device entry suspend mode when high impedance Connect to the USBVCC pin of USB Connector Connect external reference resistor (12.1k 0.1%) to Analog ground USB2.0 data pin Data negative pin terminal USB2.0 data pin Data positive pin terminal A1 DP I/O TABLE 2-6: CMOS SENSOR INTERFACE PINS (LFBGA 64) PIN NO C8 C7 B8 A8 A7, B7, E8, E7, E6, F8, F7, F6, G8, G7 TABLE 2-7: CONFIGURATION PINS (LFBGA 64) PIN NO E3 E1 F1 E2 F2 G1 H1 H8 F5 H5 G5 NAME IM6 IM5 IM4 IM3 IM2 IM1 IM0 IM9 IM16 IM17 IM18 I/O I I I I I I I I I I I DESCRIPTION Connect external resistor 10k to VCCIO (3.3V) Connect external resistor 10k to GND Connect external resistor 10k to GND Connect external resistor 10k to VCCIO (3.3V) Connect external resistor 10k to VCCIO (3.3V) Connect external resistor 10k to VCCIO (3.3V) Connect external resistor 10k to VCCIO (3.3V) Connect external resistor 10k to VCCIO (3.3V) Connect external resistor 10k to GND Connect external resistor 10k to GND Connect external resistor 10k to GND NAME SEN_CLK_OUT SEN_HCLK SEN_HSYNC SEN_VSYNC SEN_DATA[9:0] I/O O I I I I DESCRIPTION CMOS Sensor Clock Output CMOS Sensor Master Clock CMOS Sensor Vertical Synchronization Signal CMOS Sensor Horizontal Synchronization Signal Sensor Image Data [9:0] Note: These configuration pins determine the SQ930C function modes. These modes are defined when ASIC entries normal operation from reset state. Subject to Change Without Notice. PAGE 10 Version 1.3 - April 22nd , 2005 High-Speed USB 2.0 Video Camera Controller SQ930C 2.3 2.3.1 LQFP 80-pin LQFP 80 Pin Assignment FIGURE 2-3: LQFP 80 PIN ASSIGNMENT DIAGRAM Subject to Change Without Notice. PAGE 11 Version 1.3 - April 22nd , 2005 High-Speed USB 2.0 Video Camera Controller SQ930C 2.3.2 LQFP 80 Pin List TABLE 2-7: PIN LIST (LQFP 80) PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 NAME AGND2 RPU DMRS DPRS AVCC2 AGND3 AVCC3 VCCIO GND CPU_P3.0 CPU_P3.1 CPU_P2.7 VCCK CPU_P2.6 CPU_P2.5 CPU_P2.4 CPU_P2.3 CPU_P2.2 CPU_P2.1 CPU_P2.0 CPU_PSEN CPU_P1.7 CPU_P1.6 CPU_P1.5 CPU_P1.4 CPU_P1.3 CPU_P1.2 CPU_P1.1 CPU_P1.0 VCCK GND VCCIO CPU_P0.7 CPU_P0.6 CPU_P0.5 PIN NO 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 NAME CPU_P0.4 CPU_P0.3 CPU_P0.2 CPU_P0.1 CPU_P0.0 GND VCCIO CPU_ALE SEN_DATA0 SEN_DATA1 SEN_DATA2 SEN_DATA3 SEN_DATA4 SEN_DATA5 SEN_DATA6 SEN_DATA7 SUSPEND VCCK VCCIO N.C GND ZREGO3.3 ZREGO2.5 SEN_CLK_OUT SEN_HCLK SEN_HSYNC SEN_VSYNC SEN_DATA9 SEN_DATA8 NRES USB_POWER VCCK GND VCCIO N.C Subject to Change Without Notice. PAGE 12 Version 1.3 - April 22nd , 2005 High-Speed USB 2.0 Video Camera Controller SQ930C PIN NO 71 72 73 74 75 NAME N.C VCCK GND XOSCI XOSCO PIN NO 76 77 78 79 80 NAME AVCC1 AGND1 RREF DM DP Subject to Change Without Notice. PAGE 13 Version 1.3 - April 22nd , 2005 High-Speed USB 2.0 Video Camera Controller SQ930C 2.3.3 LQFP 80 Pin Descriptions TABLE 2-8: POWER SUPPLY PINS (LQFP 80) PIN NO 1 5 6 7 8 9 13 30 31 32 41 42 53 54 56 57 58 67 68 69 72 73 76 77 NAME AGND2 AVCC2 AGND3 AVCC3 VCCIO GND VCCK VCCK GND VCCIO GND VCCIO VCCK VCCIO GND ZREGO3.3 ZREGO2.5 VCCK GND VCCIO VCCK GND AVCC1 AGND1 I/O PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR DESCRIPTION Analog ground Power, analog AVCC=3.3 Analog ground Power, analog AVCC=3.3 Power, digital VCC=3.3 Digital ground Power, digital VCCK=2.5 Power, digital VCCK=2.5 Digital ground Power, digital VCC=3.3 Digital ground Power, digital VCC=3.3 Power, digital VCCK=2.5 Power, digital VCC=3.3 Digital ground Power, digital VCC=3.3 Power, digital VCCK=2.5 Power, digital VCCK=2.5 Digital ground Power, digital VCC=3.3 Power, digital VCCK=2.5 Digital ground Analog AVCC=3.3 Analog ground TABLE 2-9: SYSTEM PINS (LQFP 80) PIN NO 65 74 75 NAME NRES XOSCI XOSCO I/O I I O DESCRIPTION System reset, active low 12M Crystal in 12M Crystal out Subject to Change Without Notice. PAGE 14 Version 1.3 - April 22nd , 2005 High-Speed USB 2.0 Video Camera Controller SQ930C TABLE 2-10: 8032 CPU INTERFACE PINS (LQFP 80) PIN NO 10 11 12, 14~20 NAME CPU_P3.0 CPU_P3.1 CPU_P2.7~ CPU_P2.0 21 22~29 CPU_PSEN CPU_P1.7~ CPU_P1.0 33~40 CPU_P0.7~ CPU_P0.0 43 CPU_ALE O Address Latch Enable Output pulse for latching the low byte of the address during accesses to external memory TABLE 2-11: USB INTERFACE PINS (LQFP 80) PIN NO 2 3 NAME RPU DMRS I/O I I/O DESCRIPTION Connect external resistor (1.5k 0.1%) to AVCC (Analog power 3.3V) USB1.1 data in Data negative pin terminal, connecting to external resistor (39 0.1%) 4 DPRS I/O USB1.1 data in Data positive pin terminal, connecting to external resistor (39 0.1%) 52 SUSPEND O Device entry normal mode when drive `L' Device entry suspend mode when high impedance 66 78 79 80 USB_POWER RREF DM DP I I I/O I/O Connect to the USBVCC pin of USB Connector Connect external reference resistor (12.1k 0.1%) to Analog ground USB2.0 data pin Data negative pin terminal USB2.0 data pin Data positive pin terminal I/O Microprocessor Data / Low Address Bus O I/O Program Store Enable is the read strobe to external program memory. Port 1 is an 8-bit bi-directional I/O port. I/O O I/O O DESCRIPTION Port 3 - 0, output port only Port 3 - 1, bi-directional I/O port Microprocessor High Address Bus TABLE 2-12: CMOS SENSOR INTERFACE PINS (LQFP 80) PIN NO 59 60 61 62 63, 64, 51~44 NAME SEN_CLK_OUT SEN_HCLK SEN_HSYNC SEN_VSYNC SEN_DATA[9:0] I/O O I I I I DESCRIPTION CMOS Sensor Clock Output CMOS Sensor Master Clock CMOS Sensor Vertical Synchronization Signal CMOS Sensor Horizontal Synchronization Signal Sensor Image Data [9:0] Subject to Change Without Notice. PAGE 15 Version 1.3 - April 22nd , 2005 High-Speed USB 2.0 Video Camera Controller SQ930C TABLE 2-13: CONFIGURATION PINS (LQFP 80) PIN NO 14 15 16 17 18 19 20 35 36 37 43 NAME IM6 IM5 IM4 IM3 IM2 IM1 IM0 IM18 IM17 IM16 IM9 I/O I I I I I I I I I I I DESCRIPTION Connect external resistor 10k to VCCIO (3.3V) Connect external resistor 10k to VCCIO (3.3V) Connect external resistor 10k to GND Connect external resistor 10k to VCCIO (3.3V) Connect external resistor 10k to VCCIO (3.3V) Connect external resistor 10k to VCCIO (3.3V) Connect external resistor 10k to VCCIO (3.3V) Connect external resistor 10k to GND Connect external resistor 10k to GND Connect external resistor 10k to GND Connect external resistor 10k to VCCIO (3.3V) NOTE: These configuration pins determine the SQ930C function modes. These modes are defined when ASIC entries normal operation from reset state. Subject to Change Without Notice. PAGE 16 Version 1.3 - April 22nd , 2005 High-Speed USB 2.0 Video Camera Controller SQ930C 3. ELECTRICAL CHARACTERISTIC 3.1 Operation Conditions TABLE 3-1: OPERATION CONDITIONS SYMBOL VCC VIN3 TJ PARAMETER Power Supply Input Voltage of 3.3V with 5V Tolerance I/O Junction Operating Temperature: Commercial MIN 3 0 -40 TYP 3.3 3.3 25 MAX 3.6 5.25 125 UNIT V V 3.2 DC Characteristics TABLE 3-2: DC CHARACTERISTICS OF 3.3V I/O CELLS SYMBOL VCC AVCC VCCK VIL VIH NRESNRES+ VOL VOH PARAMETER Power Supply Power Supply Power Supply Input Low Voltage Input High Voltage Schmitt Trigger Negative Going Threshold Schmitt Trigger Positive Going Threshold Output Low Voltage Output High Voltage CONDITIONS LVTTL spec. LVTTL spec. IOl = 4 mA IOH = -4 mA MIN 3.0 3.0 2.25 2 0.9 2.4 TYP 3.3 3.3 2.5 1.2 2.1 - MAX 3.6 3.6 2.75 0.8 2.5 0.4 - UNIT V V V V V V V V V Subject to Change Without Notice. PAGE 17 Version 1.3 - April 22nd , 2005 High-Speed USB 2.0 Video Camera Controller SQ930C 4. PACKAGING 4.1 LFBGA 64-pin Package Body size: 7 x 7 mm Ball pitch: 0.8 mm A1 Ba ll P a d Corne r 1.4 MAX 0.70+/- 0.02 0.32+/- 0.04 DETAIL B 7.0 SIDE VIEW 0.1 Z Z SEATING PLANE 0.1 Z Y x 7.0 DETAIL B TO P VIEW (DIE VIEW) A1 Ball Pad Corner SOLDER BALL 0.7 0.8 DETAIL A 0.10 M 0.05 M XYZ Z 5.6 0.8 0.7 DETAIL A 5.6 BOTTOM VIEW (BALL SIDE) FIGURE 4-1: LFBGA 64-PIN PACKAGE DIAGRAM Subject to Change Without Notice. PAGE 18 Version 1.3 - April 22nd , 2005 0.4 0.32TYP High-Speed USB 2.0 Video Camera Controller SQ930C 4.2 LQFP 80-pin Package Body size: 10 x 10 x 1.4 mm Symbol Dimension (mm) Min. 0.05 1.35 0.13 0.13 0.09 0.09 12.00 BSC 10.00 BSC 12.00 BSC 10.00BSC 0.40BSC 0.45 0.60 0.75 0.20 0.075 7 13 13 18 3 3 0 0 11 11 1.00 REF 0.08 0.08 0 0 11 11 3.5 12 12 1.40 0.18 0.16 Nom. Max. 1.60 0.15 1.45 0.23 019 0.20 0.16 Dimension (mil) Min. 2 53 5 5 4 4 472 BSC 394 BSC 472 BSC 394 BSC 16 BSC 24 39 REF 3.5 12 12 30 8 3 7 13 13 55 7 6 Nom. Max. 63 6 57 9 7 8 6 60 61 41 40 A A1 A2 b b1 SQ930C c c1 D D1 E E1 e L L1 R1 R2 Y 1 2 3 80 1 20 21 e b D1 E1 S Y S D 2 'X' E Base Metal 1 0.25mm A2 A b R2 A A Gage Plane R1 b1 L LL 3 Seating Plane Detailed 'X' (20/1) Width Plating Section A-A FIGURE 4-2: LQFP 80-PIN PACKAGE DIAGRAM 1. 2. Dimension D1 and C1 do not include mold protrusion. Allowable protrusion is 0.25mm Per side D1 and C1 are maximum plastic body size dimension including mold mismatch. Dimension b does not include DAMBAR protrusion. Allowable DAMBAR protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. PAGE 19 Version 1.3 - April 22nd , 2005 Subject to Change Without Notice. A1 C1 C High-Speed USB 2.0 Video Camera Controller SQ930C 4.3 Ordering Information TABLE 4-1: ORDERING INFORMATION TABLE TYPE NO SQ930C PACKAGE LFBGA64 LQFP80 DESCRIPTION Low-profile Fine-pitch Ball Grid Array Package, 64-ball Low-profile Quad Flat Package, 80-pin Subject to Change Without Notice. PAGE 20 Version 1.3 - April 22nd , 2005 |
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