View SAA8113HL_563785.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
DATA SHEET
SAA8113HL Digital PC-camera signal processor
Preliminary specification File under Integrated Circuits, IC22 1999 Sep 27
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
CONTENTS 1 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 15.5 16 17 18 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Black offset preprocessing Y, CR and CB separation RGB processing Y processing RGB to UV conversion UV processing Display function Analog output processing Measurement engine VH reference and window timing and control Pulse pattern generator Miscellaneous functions Mode control Microcontroller Audio amplifier I2C-bus interface LIMITING VALUES THERMAL CHARACTERISTICS OPERATING CHARACTERISTICS ELECTRICAL CHARACTERISTICS APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
SAA8113HL
1999 Sep 27
2
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
1 FEATURES
SAA8113HL
* High precision digital processing with 10-bit input * Medium resolution complementary mosaic CCD sensors PAL or NTSC (interlaced mode only) * Internal PPG, dedicated to SHARP, TOSHIBA and PANASONIC sensors * Integrated microcontroller (80C51) for control loops Auto Optical Black (AOB), Auto White Balance (AWB) and Auto Exposure (AE) * Black offset preprocessing * RGB separation * RGB processing (colour correction matrix, programmable knee and gamma) * Separate Y-processing (saturation concealment, programmable knee and gamma) * RGB to UV conversion (including down-sampling filters) * Noise reduction in Y and UV * Display function for system evaluation * Analog output processing, including PAL/NTSC encoder and 9-bit Video Digital-to-Analog Converter (VDAC) * Measurement engine (prepared for AE and AWB features) * Miscellaneous functions, e.g. power management, 7-bit Control DAC (CDAC) serial interface with preprocessing * VH reference and window timing for internal use * Master I2C-bus interface for communication with an external EEPROM (containing the default settings) * Slave I2C-bus interface for communication with an external microcontroller * Parallel interface for communication with an external EPROM (for ROM code debugging) * Integrated audio amplifier. 2 APPLICATIONS 3 GENERAL DESCRIPTION
The SAA8113HL is a 2nd generation camera Digital Signal Processor (DSP) designed for low-cost DTV applications. It integrates the DSP core, the Pulse Pattern Generator (PPG), the 80C51 microcontroller and the VDAC in one IC. It is the successor of the SAA8110G, dedicated to analog output cameras. The SAA8113HL must be applied together with an analog front-end that includes a Correlated Double Sampling (CDS), an Automatic Gain Control (AGC) and an Analog-to-Digital Converter (ADC). This may be the TDA8786 or the TDA8784. The PPG generates the timing pulses to drive medium resolution PAL/NTSC complementary mosaic CCD sensors (512 x 492 NTSC and 512 x 582 PAL). The input of the DSP is 10 bits with a maximum pixel frequency equal to 9.66 MHz. The DSP core processes this sensor signal to a standard video output signal. The SAA8113HL output is an analog CVBS video signal. The microcontroller provides the settings for the IC registers from EEPROM at power-up or reset and controls the AWB, AE and AOB loops. It also provides a hardware I2C-bus interface, so the microcontroller can be used as an I2C-bus slave. The software code is embedded in an internal ROM but it is also possible to use a combined data and address bus, connected to an external program EPROM. A built-in power management function allows the power dissipation to be optimized.
* Low-cost desktop video applications * Videophone systems. 4 ORDERING INFORMATION TYPE NUMBER SAA8113HL PACKAGE NAME LQFP100 DESCRIPTION plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm VERSION SOT407-1
1999 Sep 27
3
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
5 QUICK REFERENCE DATA Measured over full voltage and temperature range. SYMBOL VDDD VDDA IDD(tot) VI VO fclk Ptot Tstg Tamb Tj Note 1. This concerns pins SCL and SDA. PARAMETER digital supply voltage analog supply voltage total supply current input voltage output voltage clock frequency input duty factor of fclk total power dissipation storage temperature ambient temperature junction temperature Tamb = 70 C Tamb = 25 C VDDD = 3.3 V 3.0 V < VDDD < 3.6 V note 1 3.0 V < VDDD < 3.6 V note 1 CONDITIONS MIN. 3.0 3.0 - TYP. 3.3 3.3 60
SAA8113HL
MAX. 3.6 3.6 -
UNIT V V mA V V V V MHz % mW C C C
low-voltage TTL compatible 5 V tolerant, TTL compatible low-voltage TTL compatible 5 V tolerant, TTL compatible - - - -55 0 -40 38 50 200 - 25 - - - 250 +150 70 +125
1999 Sep 27
4
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
book, full pagewidth
1999 Sep 27
CCD9 to CCD0 85 to 94 10 M2 to M0 1 to 3 3 XIN 62 63
6
Philips Semiconductors
Digital PC-camera signal processor
BLOCK DIAGRAM
VDDD1, VDDD2 55, 96
VDDA1 to VDDA3, VDDA5 to VDDA9 DGND1 to DGND3 54, 56, 95
AGND1 to AGND4, AGND7 to AGND11 12, 19, 20, 21, 41, 60, 61, 72, 82
MICIAB, VCOMAB 24, 25
VDDA4 29
AGND5, AGND6 26, 28 27 OUTAB
2
8
13, 17, 23, 40, 57, 64, 71, 83
3
9
2
2
AUDIO BUFFER Y PROCESSING OFFSET PREPROCESSING Y AND CR, CB SEPARATION RGB PROCESSING
RGB TO UV
DISPLAY UV PROCESSING
ANALOG OUTPUT (PREPROCESSING) VDAC PAL/NTSC ENCODER
18 22
VDOBCVBS DECREF
49 to 42 MODE CONTROL AND CLOCK GENERATOR XOSC 8 50 VH REFERENCE TIMING MEASUREMENT ENGINE 32 P0 INTERNAL MICROCONTROLLER INTERFACE 39 to 33 P3 P2 7 10 11 P1 14 15 5, 6, 7, 8 8 4 100, 99, 98, 97, 84, 51, 6 30, 31 65, 66, 67, 68, 3 69, 70 4 73 79, 80, 77, 78 AD14 to AD8 P0.7 to P0.0 ALE PSEN
5
XOUT
CDACOUT RBIASCDAC
59 58 CDAC MISCELLANEOUS FUNCTIONS PPG SENSOR/PREPROCESSOR TIMING AND CONTROL P4
MICROCONTROLLER
SCLE SDAE SCL SDA KNOB3 to KNOB0
80C51
75, 74, 76
SAA8113HL
81
4 2 16, 53 T1, INT1 9 RESET 52
FCE312
KNOB4
SDATA, SCLK, STROBE, STDBY, SMP, LED, OUTBVEN, OUTGAIN
V1X, VH1X, V2X, V3X, VH3X, V4X
FH1, FH2, FR
OFDX
BCP, DCP, FS, FCDS
CLK1
EA
Preliminary specification
SAA8113HL
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
7 PINNING SYMBOL M2 M1 M0 KNOB4 KNOB3 KNOB2 KNOB1 KNOB0 RESET SCLE SDAE AGND1 VDDA1 SCL SDA T1 VDDA2 VDOBCVBS AGND2 AGND3 AGND4 DECREF VDDA3 MICIAB VCOMAB AGND5 OUTAB AGND6 VDDA4 OUTBVEN OUTGAIN PSEN AD8 AD9 AD10 AD11 AD12 AD13 AD14 VDDA5 1999 Sep 27 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O I I I I I/O I/O I/O I/O I O I/O I I I I/O I I O I I I O I I I I O I I O O O O O O O O O O I test mode control signal bit 2 test mode control signal bit 1 test mode control signal bit 0 input connected to DSP core I/O connected to internal 80C51 I/O connected to internal 80C51 I/O connected to internal 80C51 I/O connected to internal 80C51 Power-on reset master I2C-bus clock output to control EEPROM master I2C-bus data I/O to control EEPROM analog ground 1 for output buffers analog supply voltage 1 for output buffers slave I2C-bus clock input slave I2C-bus data I/O Timer 1 for internal 80C51 analog supply voltage 2 for DAC output buffer VDAC output buffer for CVBS signal analog ground 2 for DAC output buffer DESCRIPTION
SAA8113HL
analog ground 3 for analog DAC core and band gap (connected to substrate) analog ground 4 for analog DAC core and band gap (not connected to substrate) decoupled pin for reference voltage HIGH analog supply voltage 3 for analog DAC core and band gap microphone input audio buffer common voltage for audio buffer analog ground 5 for audio buffer (not connected to substrate) output audio buffer analog ground 6 for audio buffer (connected to substrate) analog supply voltage 4 for audio buffer output to enable the bias voltage of the microphone for the audio buffer output to control the gain factor of an external audio buffer program store enable; read strobe for external program memory (active LOW) address bit 8 for external program memory (PROM) address bit 9 for external program memory (PROM) address bit 10 for external program memory (PROM) address bit 11 for external program memory (PROM) address bit 12 for external program memory (PROM) address bit 13 for external program memory (PROM) address bit 14 for external program memory (PROM) analog supply voltage 5 for output buffers 6
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
SYMBOL AGND7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 ALE LED EA INT1 DGND1 VDDD1 DGND2 VDDA6 RBIASCDAC CDACOUT AGND8 AGND9 XIN XOUT VDDA7 V1X VH1X V2X V3X VH3X V4X VDDA8 AGND10 OFDX FH2 FH1 FR FS FCDS BCP DCP CLK1 1999 Sep 27
PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81
I/O I I/O I/O I/O I/O I/O I/O I/O I/O O O I I I I I I O O I I I O I O O O O O O I I O O O O O O O O O analog ground 7 for output buffers
DESCRIPTION port 0 bidirectional bit 0 for external program memory data I/O (PROM) port 0 bidirectional bit 1 for external program memory data I/O (PROM) port 0 bidirectional bit 2 for external program memory data I/O (PROM) port 0 bidirectional bit 3 for external program memory data I/O (PROM) port 0 bidirectional bit 4 for external program memory data I/O (PROM) port 0 bidirectional bit 5 for external program memory data I/O (PROM) port 0 bidirectional bit 6 for external program memory data I/O (PROM) port 0 bidirectional bit 7 for external program memory data I/O (PROM) address latch enable pulse for external latch output to drive LED external access select bit for internal 80C51 (active LOW) interrupt 1 for internal 80C51 digital ground 1 for input buffers, predrivers and the digital core digital supply voltage 1 for input buffers, predrivers and the digital core digital ground 2 for input buffers, predrivers and the digital core analog supply voltage 6 for CDAC bias resistor for CDAC output CDAC analog ground 8 for CDAC analog ground 9 for 38 MHz (fundamental) crystal oscillator oscillator input oscillator output analog supply voltage 7 for 38 MHz (fundamental) crystal oscillator vertical CCD transfer pulse 1X vertical CCD load pulse H1X vertical CCD transfer pulse 2X vertical CCD transfer pulse 3X vertical CCD load pulse H3X vertical CCD transfer pulse 4X analog supply voltage 8 for output buffers analog ground 10 for output buffers overflow drain pulse for shutter control horizontal CCD transfer pulse F2 horizontal CCD transfer pulse F1 CCD output amplifier reset pulse (TDA8786 or TDA8784) CCD output level sample and hold pulse (TDA8786 or TDA8784) reference level sample and hold pulse (TDA8786 or TDA8784) black pixel clamp pulse (TDA8786 or TDA8784) dummy pixel clamp pulse (TDA8786 or TDA8784) pixel clock to preprocessor (TDA8786 or TDA8784) 7
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
SYMBOL AGND11 VDDA9 SMP CCD9 CCD8 CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0 DGND3 VDDD2 STDBY STROBE SCLK SDATA
PIN 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
I/O I I O I I I I I I I I I I I I O O O O analog ground 11 for output buffers
DESCRIPTION analog supply voltage 9 for output buffers switch mode pulse for DC-to-DC power supply (preprocessed) AD-converted CCD signal bit 9 (preprocessed) AD-converted CCD signal bit 8 (preprocessed) AD-converted CCD signal bit 7 (preprocessed) AD-converted CCD signal bit 6 (preprocessed) AD-converted CCD signal bit 5 (preprocessed) AD-converted CCD signal bit 4 (preprocessed) AD-converted CCD signal bit 3 (preprocessed) AD-converted CCD signal bit 2 (preprocessed) AD-converted CCD signal bit 1 (preprocessed) AD-converted CCD signal bit 0 digital ground 3 for input buffers, predrivers and the digital core digital supply voltage 2 for input buffers, predrivers and the digital core standby control output to TDA8786 or TDA8784 strobe to TDA8786 or TDA8784 serial clock to TDA8786 or TDA8784 serial data to TDA8786 or TDA8784
1999 Sep 27
8
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
98 STROBE
100 SDATA
95 DGND3
96 VDDD2
97 STDBY
83 VDDA9
handbook, full pagewidth
82 AGND11
94 CCD0
93 CCD1
92 CCD2
91 CCD3
90 CCD4
89 CCD5
88 CCD6
87 CCD7
86 CCD8
85 CCD9
78 FCDS
99 SCLK
81 CLK1
84 SMP
80 DCP
79 BCP
76 FR 75 FH1 74 FH2 73 OFDX 72 AGND10 71 VDDA8 70 V4X 69 VH3X 68 V3X 67 V2X 66 VH1X 65 V1X 64 VDDA7 63 XOUT 62 XIN 61 AGND9 60 AGND8 59 CDACOUT 58 RBIASCDAC 57 VDDA6 56 DGND2 55 VDDD1 54 DGND1 53 INT1 52 EA 51 LED ALE 50
M2 M1 M0 KNOB4 KNOB3 KNOB2 KNOB1 KNOB0 RESET
1 2 3 4 5 6 7 8 9
SCLE 10 SDAE 11 AGND1 12 VDDA1 13 SCL 14 SDA 15 T1 16 VDDA2 17 VDOBCVBS 18 AGND2 19 AGND3 20 AGND4 21 DECREF 22 VDDA3 23 MICIAB 24 VCOMAB 25 AGND5 26 OUTAB 27 AGND6 28 VDDA4 29 OUTBVEN 30 OUTGAIN 31 PSEN 32 AD8 33 AD9 34 AD10 35 AD11 36 AD12 37 AD13 38 AD14 39 VDDA5 40 AGND7 41 P0.0 42 P0.1 43 P0.2 44 P0.3 45 P0.4 46 P0.5 47 P0.6 48 P0.7 49
SAA8113HL
77 FS
FCE313
Fig.2 Pin configuration.
1999 Sep 27
9
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
8 8.1 FUNCTIONAL DESCRIPTION Black offset preprocessing
SAA8113HL
advantage of the full code range. Otherwise, the black level is fixed by settings that are downloaded through the serial interface. 8.2 Y, CR and CB separation
The CCD signal contains additional pixels outside the active window, which are used to measure the reference black level. These pixels are located in the optical black window, whose position can be set through the serial interface. The optical black level can be adjusted by the microcontroller in order to proceed rapidly. In this case, the microcontroller directly adjusts the analog preprocessing clamp included in the TDA8786 or TDA8784 and takes
For each pixel value, this block (see Fig.3) generates the three components: the luminance signal Y and the two colour signals CR (2R - G) and CB (2B - G). Two line memories are required for this function. This block also provides vertical contour and white clip information.
handbook, full pagewidth
LINE MEMORY RGB COLOUR SEPARATION
Y CR
LINE MEMORY CCD inputs 10
CB white clip Yvertical contour
FCE314
Fig.3 Y, CR and CB separation diagram.
1999 Sep 27
10
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
8.3 RGB processing
SAA8113HL
* Separate gain controls for R and B signals dedicated to white balance control. The colour temperature can be adjusted independently of the colour matrix. * Knee function (compression factor and knee point are adjustable). * Adjustable gamma function to compensate for the non-linearity of display devices. The RGB path has a reduced bandwidth (less than 1 MHz), which is required for CVBS output.
The RGB processing (see Fig.4) includes several features: * Colour space matrix to handle different types of colour sensors. The result is an optimum colour reproduction through the minimization of colour errors. The default matrix coefficients (positive or negative) can be adjusted through an external interface. * Separate and adjustable black offsets for R, G and B signals.
handbook, full pagewidth
LPF Y
Rblack
Rgain
+
Gblack COLOUR MATRIX
x
KNEE
GAMMA R
LPF CR
+
Bblack Bgain
KNEE
GAMMA G
LPF CB
+
x
KNEE
GAMMA B
FCE315
Fig.4 RGB processing diagram.
1999 Sep 27
11
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
8.4 Y processing * Black offset
SAA8113HL
The separate Y processing (see Fig.5) includes the following features: * Saturation concealment to reduce the typical saturation distortion * Contour processing to improve picture sharpness * Noise reduction
* Pre-gain control to adjust the Y signal with respect to the gamma range * Knee function (compression factor and knee point are adjustable) * Adjustable gamma function * Gain control.
handbook, full pagewidth
CONTOUR PROCESSING AND NOISE REDUCTION
Yvertical contour Y SATURATION CONCEALMENT
Yblack
Ypre-gain
+
x
+
KNEE
GAMMA
Ygain
x
Y
FCE316
Fig.5 Y processing diagram.
8.5
RGB to UV conversion
8.7
Display function
After R, G and B processing, the data path is converted to U and V signals (see Fig.1). As a result of the reduced bandwidth, the Y signal is only used as an input for control loop purposes (measurement engine). 8.6 UV processing
As an optional feature and for software debugging, it is possible to visualize: * Eight display bars (assigned via the microcontroller) * Several measurement engine inputs.
The chrominance processing consists of a noise reduction by coring and the UV gain control.
1999 Sep 27
12
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
8.8 Analog output processing
SAA8113HL
twice the pixel clock and digitally prefiltered to keep the external analog filter simple. The block also contains an adjustable luminance clipper.
The analog output processing (see Fig.6) contains a PAL/NTSC encoder to transform the YUV data path to the CVBS output. The YUV input signals are up-sampled to
handbook, full pagewidth
Y U V PAL/NTSC ENCODER
Y MIX VDAC VDOBCVBS
C
sync, blank, scaling, levels
FCE317
Fig.6 Analog output processing.
8.9
Measurement engine
8.10
VH reference and window timing and control
The measurement engine performs data measurements on a field basis to get inputs for the AE and AWB control loops of the microcontroller. Up to 16 programmable windows can be used for the measurement. There are two down-samplers to prepare the data for two separate accumulators. It is possible to proceed with eight different measurements per field (odd and even fields separately). An internal RAM workspace is used for data handling operation.
This block generates internal control signals for different purposes: * Vertical, horizontal and field references (VD, HD and FI) for PAL or NTSC sensors * Specification of the active window and the optical black window * Specification of the measurement window grid with respect to the active window * Specification of the vertical position of the display bars, see Section 8.7. All these specifications can be controlled through the serial interface.
1999 Sep 27
13
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
8.11 Pulse pattern generator
SAA8113HL
The PPG is dedicated to the medium resolution sensors with complementary mosaic colour filters (512 x 492 NTSC and 512 x 582 PAL) described in Table 1. Figs. 11 and 12 show the PPG outputs.
The PPG generates timing pulses (Figs. 7 to 10) for driving the CCD sensor (including the vertical driver) and pulses for the preprocessor TDA8786 or TDA8784 (correlated double sampling and black clamping). Table 1
Medium resolution CCD sensors driven by the internal PPG; note 1 BRAND FORMAT PAL 1/4" NTSC 1/4" PAL 1/5" NTSC 1/5" LZ2423A LZ2413A LZ2523 LZ2513 TCD5391AP TCD5381AP LZ2425 LZ2415 MN37210FP MN37201FP MN37110FP MN37101FP TYPE
SHARP
TOSHIBA SHARP low voltage PANASONIC
PAL 1/4" NTSC 1/4" PAL 1/4" NTSC 1/4" PAL 1/4" PAL 1/4" NTSC 1/4" NTSC 1/4"
Note 1. All sensors are used with the vertical driver: NEC PD16510. The PPG includes special features: * A charge reset is possible in every active line during the horizontal line blanking and multiple times during the vertical blanking * A fast shutter interface is available.
1999 Sep 27
14
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
handbook, full pagewidth
4 x f pixel XIN
FH1
FH2
FCDS
FS_narrow
FS_wide
FR_wide
FR_narrow delay (typ. 7 ns) FR_narrow_delayed delay (typ. 7 ns)
FR_wide_delayed
FCE318
Fig.7 High speed pulse timing (CCD sensor and preprocessor).
1999 Sep 27
15
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
handbook, full pagewidth
NTSC line 17 PAL line 19
NTSC line 18 PAL line 20
HD V1X V2X V3X V4X VH1X VH3X NTSC line 279 PAL line 331 HD V1X V2X V3X V4X VH1X VH3X
FCE319
NTSC line 280 PAL line 332
Fig.8 SHARP and TOSHIBA CCD sensors/vertical drivers.
1999 Sep 27
16
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
handbook, full pagewidth
NTSC line 17 PAL line 19
NTSC line 18 PAL line 20
HD V1X V2X V3X V4X VH3X NTSC line 279 PAL line 331 HD V1X V2X V3X V4X VH3X
FCE320
NTSC line 280 PAL line 332
Fig.9 SHARP low-voltage CCD sensors/vertical drivers.
1999 Sep 27
17
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
handbook, full pagewidth
NTSC line 17 PAL line 19
NTSC line 18 PAL line 20
HD V1X V2X V3X V4X VH1X VH3X OFDX NTSC line 279 PAL line 331 HD V1X V2X V3X V4X VH1X VH3X OFDX
FCE321
NTSC line 280 PAL line 332
Fig.10 PANASONIC CCD sensors/vertical drivers.
1999 Sep 27
18
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
handbook, full HD pagewidth
V1X V2X V3X V4X OFDX BCP DCP
FCE322
Fig.11 SHARP, all types, PPG output.
handbook, full pagewidth HD
V1X V2X V3X V4X OFDX BCP DCP
FCE323
Fig.12 PANASONIC PPG output.
1999 Sep 27
19
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
8.12 Miscellaneous functions
SAA8113HL
* A 3-wire serial bus transfers the settings from the microcontroller to the preprocessor (TDA8786 or TDA8784). 8.13 Mode control
* Power consumption: it is possible to switch the DSP off without switching off the microcontroller. * Oscillator frequency: a 7-bit CDAC tunes the oscillator frequency according to the external quartz frequency to guarantee the typical value of 38 MHz. The control digital value is downloaded through the serial interface. Table 2 M2 0 0 0 0 Note Mode control M1 0 0 1 1 M0 0 1 0 1 EA EA; note 1 - - 0 application mode
This block controls the operational modes of the SAA8113HL: application or test modes, see Table 2. For a smooth adaptability, it is possible to bypass the main modules.
MODE application mode with bypassed PPG application mode with bypassed microcontroller application mode with bypassed PPG and microcontroller
1. EA can be high or low, according to the application (high is for internal ROM access, low for external access). 8.14 Microcontroller The microcontroller includes the following features: * 16 kbyte internal ROM * 256 byte RAM * Hardware I2C-bus interface for communication with external microcontroller: SDA and SCL * Software I2C-bus interface for communication with external EEPROM containing DSP settings: SDAE and SCLE * Four I/O pins which can be used as human interface (knobs): P1.0, P1.1, P1.2 and P1.3.
The embedded microcontroller is basically an 80C654 core (80C51 family) with four ports. Its functionality is standard, except that the core has no clock divided by 2 and the ports are dedicated input, output or I/O ports. Ports P0 and P2 are available for connection to a debugger or to an external program EPROM. The microcontroller controls the AOB, the AE and the AWB loops and downloads the settings for the DSP registers from EEPROM at power-up or reset. Table 3 lists the 80C51 Standard Function Registers.
1999 Sep 27
20
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
Table 3 SFR NAME B ACC SIADR SIDAT SISTA SICON PSW P4 IP P3 IE P2 P1 TH1 TH0 TL1 TL0 TMOD TCON PCON DPH DPL SP P0 8.15 80C51 Standard Function Registers DESCRIPTION B register accumulator serial interface address serial interface data serial interface status serial interface control program status word port 4 interrupt priority port 3 interrupt enable port 2 port 1 timer HIGH 1 timer HIGH 0 timer LOW 1 timer LOW 0 timer mode timer control power control data pointer HIGH data pointer LOW stack pointer port 0 Audio amplifier SFR ADDRESS F0H E0H DBH DAH D9H D8H D0H C7H B8H B0H A8H A0H 90H 8DH 8CH 8BH 8AH 89H 88H 87H 83H 82H 81H 80H DATA BIT 7 B7 ACC7 SA6 SD7 ST7 CR2 CY - - RDN EA AD15 SDA - - - - GATE TF1 - - - SP7 AD7 DATA BIT 6 B6 ACC6 SA5 SD6 ST6 ENS1 AC - IP6 WRN IE6 AD14 SCL - - - - C/T TR1 - - - SP6 AD6 DATA BIT 5 B5 ACC5 SA4 SD5 ST5 STA F0 - IP5 T1 IE5 AD13 SDAE - - - - M1 TF0 - - - SP5 AD5 DATA BIT 4 B4 ACC4 SA3 SD4 ST4 STO RS1 - IP4 T0 IE4 AD12 SCLE - - - - M0 TR0 - - - SP4 AD4 DATA BIT 3 B3 ACC3 SA2 SD3 ST3 SI RS0 - PT1 INT1 ET1 AD11 P1.3 - - - - Gate IE1 - - - SP3 AD3
SAA8113HL
DATA BIT 2 B2 ACC2 SA1 SD2 0 AA OV - PX1 INT0 EX1 AD10 P1.2 - - - - C/T IT1 - - - SP2 AD2
DATA BIT 1 B1 ACC1 SA0 SD1 0 CR1 - - PT0 FI ET0 AD9 P1.1 - - - - M1 IE0 PD - - SP1 AD1
DATA BIT 0 B0 ACC0 GC SD0 0 CR0 P STBY PX0 CRST EX0 AD8 P1.0 - - - - M0 IT0 IDL - - SP0 AD0
8.16
I2C-bus interface
An analog audio amplifier is integrated in the SAA8113HL. Its gain can be adjusted between a high (45 dB typical) and a low (13 dB typical) value through the serial interface.
Table 4 gives the command list of the I2C-bus interface.
1999 Sep 27
21
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
Table 4 ADD 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Command list NAME CONTROL0 CONTROL1 CONTROL2 OB_STARTL_F0 OB_STARTL_F1 OB_STARTP OB_PE_F0 OB_PO_F0 OB_PE_F1 OB_PO_F1 COL_MAT_P11 COL_MAT_P12 COL_MAT_P13 COL_MAT_P21 COL_MAT_P22 COL_MAT_P23 COL_MAT_P31 COL_MAT_P32 COL_MAT_P33 R_BLACK G_BLACK B_BLACK COL_MAT_RGAIN COL_MAT_BGAIN THR_LUM THR_COLOR Y_BLACK K1 RGB_KNEE_OFFSET Y_KNEE_OFFSET RGB_GAMMA_BALANCE Y_GAMMA_BALANCE KCOMB VCGAIN CLDLEV HCLGAIN HCHGAIN CNCLEV CONGAIN VU_VALUE 1 FUNCTION see Table 5 for explanation see Table 7 for explanation see Table 8 for explanation first line optical black window in field 0 first line optical black window in field 1 first pixel optical black window fixed optical black level for even pixel in field 0 fixed optical black level for odd pixel in field 0 fixed optical black level for even pixel in field 1 fixed optical black level for odd pixel in field 1 colour matrix coefficient p11 colour matrix coefficient p12 colour matrix coefficient p13 colour matrix coefficient p21 colour matrix coefficient p22 colour matrix coefficient p23 colour matrix coefficient p31 colour matrix coefficient p32 colour matrix coefficient p33 fixed R-black level offset fixed G-black level offset fixed B-black level offset colour matrix R-gain factor colour matrix B-gain factor threshold luminance for fader threshold colour for fader fixed Y-black level offset gain correction for Y path offset for RGB knee offset for Y knee gamma multiplication factor (for RGB data path) gamma multiplication factor (for Y data path) vertical contour comb filter coefficient (MS) vertical contour gain (LS) contour level dependency level horizontal contour BPF low gain (LS) horizontal contour BPF high gain (MS) contour noise coring level contour gain factor; see Table 9 length of VU_Bar 1 22
SAA8113HL
FORMAT byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte 6 bits 6 bits 4 bits 4 bits byte 4 bits 4 bits 6 bits 2 bits byte
RANGE n.a. n.a. n.a. [0 to 255] 256 + [0 to 255] [0 to 255] [0 to 127] [0 to 127] [0 to 127] [0 to 127] [-128 to 127]/16 [-128 to 127]/16 [-128 to 127]/16 [-128 to 127]/16 [-128 to 127]/16 [-128 to 127]/16 [-128 to 127]/16 [-128 to 127]/16 [-128 to 127]/16 [-128 to 127] [-128 to 127] [-128 to 127] [0 to 255]/128 [0 to 255]/64 [0 to 255] [0 to 255] [-128 to 127] [0 to 255]/128 [0 to 255] [0 to 255] [0 to 63]/64 [0 to 63]/64 [0 to 7]/8 [0 to 15]/16 [0 to 255]/2 [0 to 15]/16 [0 to 15]/16 [0 to 63] [0 to 63]/16 2 x [0 to 255]
1999 Sep 27
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
ADD 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
NAME VU_VALUE 2 VU_VALUE 3 VU_VALUE 4 VU_VALUE 5 VU_VALUE 6 VU_VALUE 7 VU_VALUE 8 Y_DISPLAY_OFFSET UNCLEV VNCLEV YGAIN UGAIN VGAIN CTR_UPD_LINE BURST_LEVEL A B C D E F HIGHLIGHTTHR ME_RESSCALE DISP_CNTRL YDISPLEV DMWSEL ANA_WHITECLIP PRE_SI_LSB PRE_SI_MSB SMP_CNTRL CDAC_DATA BLANKLEV BL-SETUP PRE_PROC_DEL BCP_START BCP_STOP DCP_START DCP_STOP EE_CONTROL_LSB
FUNCTION length of VU_Bar 2 length of VU_Bar 3 length of VU_Bar 4 length of VU_Bar 5 length of VU_Bar 6 length of VU_Bar 7 length of VU_Bar 8 display offset (to be used with D_Contour) U (chrominance) noise coring level V (chrominance) noise coring level Y (luminance) gain factor U (B-Y) gain factor V (R-Y) gain factor number of line for DB-update control registers burst level colour burst AWB_A (Measurement Engine) AWB_B (Measurement Engine) AWB_C (Measurement Engine) AWB_D (Measurement Engine) AWB_E (Measurement Engine) AWB_F (Measurement Engine) highlight threshold (Measurement Engine) ME sync + ME result scale (ME); see Table 10 control bits for display function; see Table 11 luminance display level in display function display measurement window select; see Table 13 white clip limiter level for analog outputs control data for analog processing control data and address for analog processing; see Table 14 control for switch mode power supply CDAC data (7-bit); see Table 15 blanking level in analog output setup level in analog output control compensation delay w.r.t. preprocessing B clamp pulse start B clamp pulse stop D clamp pulse start D clamp pulse stop E Exposure LSB 23
FORMAT byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte 6 bits 6 bits byte 4 bits byte byte byte byte byte 5 bits byte 7 bits byte byte 4 bits byte byte byte byte byte
RANGE 2 x [0 to 255] 2 x [0 to 255] 2 x [0 to 255] 2 x [0 to 255] 2 x [0 to 255] 2 x [0 to 255] 2 x [0 to 255] 4 x [0 to 255] [0 to 255]/4 [0 to 255]/4 [0 to 255]/128 [0 to 255]/128 [0 to 255]/128 [0 to 255] [0 to 255] [-128 to 127]/128 [-128 to 127]/128 [-128 to 127]/128 [-128 to 127]/128 [0 to 63] [0 to 63] [0 to 255] n.a. n.a. [0 to 255] n.a. 256 + [0 to 255] [0 to 255] [0 to 63] [0 to 255] [0 to 127] [0 to 255] [0 to 255] [0 to 15] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255]
1999 Sep 27
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
ADD 77 78 79 80 81 82 83 84 85 86 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157
NAME EE_CONTROL_MSB MISC_CONTROL FPIX_ACT LPIX_ACT_LSB FLINE_ACT_F0 LLINE_ACT_F0 FLINE_ACT_F1 LLINE_ACT_F1 ACT_LINES_MSB PPG_POL_SEL ME_DPCC_A0_H_F1 ME_DPCC_A0_L_F1 ME_DPCC_B0_H_F1 ME_DPCC_B0_L_F1 ME_DPCC_A1_H_F1 ME_DPCC_A1_L_F1 ME_DPCC_B1_H_F1 ME_DPCC_B1_L_F1 ME_DPCC_A2_H_F1 ME_DPCC_A2_L_F1 ME_DPCC_B2_H_F1 ME_DPCC_B2_L_F1 ME_DPCC_A3_H_F1 ME_DPCC_A3_L_F1 ME_DPCC_B3_H_F1 ME_DPCC_B3_L_F1 ME_DPCC_A0_H_F2 ME_DPCC_A0_L_F2 ME_DPCC_B0_H_F2 ME_DPCC_B0_L_F2 ME_DPCC_A1_H_F2 ME_DPCC_A1_L_F2 ME_DPCC_B1_H_F2 ME_DPCC_B1_L_F2 ME_DPCC_A2_H_F2 ME_DPCC_A2_L_F2 ME_DPCC_B2_H_F2 ME_DPCC_B2_L_F2 ME_DPCC_A3_H_F2 ME_DPCC_A3_L_F2 E Exposure MSB
FUNCTION miscellaneous control bits; see Table 16 number of first active pixel on a line number of last active pixel on a line number of first active line in field 0 number of last active line in field 0 number of first active line in field 1 number of last active line in field 1 MSBs of active line numbers; see Table 17 select polarity of the PPG output signals; see Table 18 ME data path control code A 0_H field 1 ME data path control code A 0_L field 1 ME data path control code B 0_H field 1 ME data path control code B 0_L field 1 ME data path control code A 1_H field 1 ME data path control code A 1_L field 1 ME data path control code B 1_H field 1 ME data path control code B 1_L field 1 ME data path control code A 2_H field 1 ME data path control code A 2_L field 1 ME data path control code B 2_H field 1 ME data path control code B 2_L field 1 ME data path control code A 3_H field 1 ME data path control code A 3_L field 1 ME data path control code B 3_H field 1 ME data path control code B 3_L field 1 ME data path control code A 0_H field 2 ME data path control code A 0_L field 2 ME data path control code B 0_H field 2 ME data path control code B 0_L field 2 ME data path control code A 1_H field 2 ME data path control code A 1_L field 2 ME data path control code B 1_H field 2 ME data path control code B 1_L field 2 ME data path control code A 2_H field 2 ME data path control code A 2_L field 2 ME data path control code B 2_H field 2 ME data path control code B 2_L field 2 ME data path control code A 3_H field 2 ME data path control code A 3_L field 2 24
FORMAT byte 5 bits byte byte byte byte byte byte byte 5 bits byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte
RANGE [0 to 255] [0 to 31] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] n.a. [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255]
1999 Sep 27
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
ADD 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198
NAME ME_DPCC_B3_H_F2 ME_DPCC_B3_L_F2 ME_RES_A0_H ME_RES_A0_L ME_RES_B0_H ME_RES_B0_L ME_RES_A1_H ME_RES_A1_L ME_RES_B1_H ME_RES_B1_L ME_RES_A2_H ME_RES_A2_L ME_RES_B2_H ME_RES_B2_L ME_RES_A3_H ME_RES_A3_L ME_RES_B3_H ME_RES_B3_L ME_SUBRES_A0_H ME_SUBRES_A0_L ME_SUBRES_B0_H ME_SUBRES_B0_L ME_SUBRES_A1_H ME_SUBRES_A1_L ME_SUBRES_B1_H ME_SUBRES_B1_L ME_SUBRES_A2_H ME_SUBRES_A2_L ME_SUBRES_B2_H ME_SUBRES_B2_L ME_SUBRES_A3_H ME_SUBRES_A3_L ME_SUBRES_B3_H ME_SUBRES_B3_L ME_WIN_START_0 ME_WIN_STOP_0 ME_WIN_START_1 ME_WIN_STOP_1 ME_WIN_START_2 ME_WIN_STOP_2 ME_WIN_START_3
FUNCTION ME data path control code B 3_H field 2 ME data path control code B 3_L field 2 ME data path result accuA 0_H ME data path result accuA 0_L ME data path result accuB 0_H ME data path result accuB 0_L ME data path result accuA 1_H ME data path result accuA 1_L ME data path result accuB 1_H ME data path result accuB 1_L ME data path result accuA 2_H ME data path result accuA 2_L ME data path result accuB 2_H ME data path result accuB 2_L ME data path result accuA 3_H ME data path result accuA 3_L ME data path result accuB 3_H ME data path result accuB 3_L ME data path sub-result accuA 0_H ME data path sub-result accuA 0_L ME data path sub-result accuB 0_H ME data path sub-result accuB 0_L ME data path sub-result accuA 1_H ME data path sub-result accuA 1_L ME data path sub-result accuB 1_H ME data path sub-result accuB 1_L ME data path sub-result accuA 2_H ME data path sub-result accuA 2_L ME data path sub-result accuB 2_H ME data path sub-result accuB 2_L ME data path sub-result accuA 3_H ME data path sub-result accuA 3_L ME data path sub-result accuB 3_H ME data path sub-result accuB 3_L simple window 0 (Vstart, Hstart) simple window 0 (Vstop, Hstop) simple window 1 (Vstart, Hstart) simple window 1 (Vstop, Hstop) simple window 2 (Vstart, Hstart) simple window 2 (Vstop, Hstop) simple window 3 (Vstart, Hstart) 25
FORMAT byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits
RANGE [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15]
1999 Sep 27
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
ADD 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 254 255
NAME ME_WIN_STOP_3 ME_WIN_START_4 ME_WIN_STOP_4 ME_WIN_START_5 ME_WIN_STOP_5 ME_WIN_START_6 ME_WIN_STOP_6 ME_WIN_START_7 ME_WIN_STOP_7 ME_WIN_START_8 ME_WIN_STOP_8 ME_WIN_START_9 ME_WIN_STOP_9 ME_WIN_START_10 ME_WIN_STOP_10 ME_WIN_START_11 ME_WIN_STOP_11 ME_WIN_START_12 ME_WIN_STOP_12 ME_WIN_START_13 ME_WIN_STOP_13 ME_WIN_START_14 ME_WIN_STOP_14 ME_RAM_DUMMY_H ME_RAM_DUMMY_L HIGHLIGHTCOUNT_H HIGHLIGHTCOUNT_L AWBCOUNT_H AWBCOUNT_L ME_OB_PO_F0 ME_OB_PE_F0 ME_OB_PO_F1 ME_OB_PE_F1 DUMMY_READ DUMMY_WRITE
FUNCTION simple window 3 (Vstop, Hstop) simple window 4 (Vstart, Hstart) simple window 4 (Vstop, Hstop) simple window 5 (Vstart, Hstart) simple window 5 (Vstop, Hstop) simple window 6 (Vstart, Hstart) simple window 6 (Vstop, Hstop) simple window 7 (Vstart, Hstart) simple window 7 (Vstop, Hstop) simple window 8 (Vstart, Hstart) simple window 8 (Vstop, Hstop) simple window 9 (Vstart, Hstart) simple window 9 (Vstop, Hstop) simple window 10 (Vstart, Hstart) simple window 10 (Vstop, Hstop) simple window 11 (Vstart, Hstart) simple window 11 (Vstop, Hstop) simple window 12 (Vstart, Hstart) simple window 12 (Vstop, Hstop) simple window 13 (Vstart, Hstart) simple window 13 (Vstop, Hstop) simple window 14 (Vstart, Hstart) simple window 14 (Vstop, Hstop) dummy read/write (additional RAM storage for 80C51) dummy read/write (additional RAM storage for 80C51) highlight counter H highlight counter L AWB counter H AWB counter L measured optical black pixel odd field 0; see Table 19 measured optical black pixel even field 0; see Table 20 measured optical black pixel odd field 1; see Table 21 measured optical black pixel even field 1; see Table 22 dummy read dummy write
FORMAT 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits 4 bits byte byte byte byte byte byte byte byte byte byte byte byte
RANGE [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15] [0 to 15] n.a. n.a. [0 to 255] [0 to 255] [0 to 255] [0 to 255] [0 to 127] [0 to 127] [0 to 127] [0 to 127] [0 to 255] [0 to 255]
1999 Sep 27
26
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
Table 5 Register details: address 0 CONTROL0 NAME not used RGB_KNEE_K RGB_KNEE_K PIX_PHASE LINE_PHASE INTERLINE_PHASE compression factor for RGB_KNEE; see Table 6 compression factor for RGB_KNEE; see Table 6 toggle phase for pixel in colour separation toggle phase for line in colour separation toggle colour filter structure (interline) not used not used FUNCTION
SAA8113HL
BIT CONTROL0.0 CONTROL0.1 CONTROL0.2 CONTROL0.3 CONTROL0.4 CONTROL0.5 CONTROL0.6 CONTROL0.7 Table 6
Truth table for bits CONTROL0.1 and CONTROL0.2 COMPRESSION FACTOR
BIT NUMBER 2 0 0 1 1 Table 7 1 0 1 0 1 Register details: address 1 CONTROL1 NAME FR_WIDE FR_SHIFT FS_WIDE DUALPOWER SHARP PAL_NTSC BCP_MODE CP_TOGGLE FR wide/narrow FR shifted/unshifted FS wide/narrow SHARP dual power/other sensor select SHARP/PANASONIC sensor select choose between PAL/NTSC select BCP mode 1/0 carrier phase toggle/not toggle FUNCTION 1/8 1/4 3/8 1/2
BIT CONTROL1.0 CONTROL1.1 CONTROL1.2 CONTROL1.3 CONTROL1.4 CONTROL1.5 CONTROL1.6 CONTROL1.7 Table 8
Register details: address 2 CONTROL2 NAME CATCH_CCD HFE_BYPASS Y_TEST MOD_BYPASS DOUBLE_C Y_SEL VCONTOUR_LPF FADER IMPL FUNCTION catch CCD data/normal operation high frequency enhancer bypass/active select y_test from RGB2(Y)UV instead of Y on/off chrominance modulator bypass/active scale chrominance with factor 2 on/off select as luminance input (F0) Yae/yn switch vertical contour LPF on/off select fader implementation n1/n2
BIT CONTROL2.0 CONTROL2.1 CONTROL2.2 CONTROL2.3 CONTROL2.4 CONTROL2.5 CONTROL2.6 CONTROL2.7
1999 Sep 27
27
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
Table 9 Register details: address 36 CONGAIN NAME CONGAIN.0 to CONGAIN.5 CONGAIN.6 contour gain factor (0 to 63/16) contour gain fading off/on FUNCTION
SAA8113HL
Table 10 Register details: address 60 ME_RESSCALE NAME MECNTRL.3 FUNCTION ME synchronization (synchronize field/frame toggle of Measurement Engine)
ME_RESSCALE.0 to ME_RESSCALE.2 ME result scaler selection (0, 2, 4, 8 and 16)
Table 11 Register details: address 61 DISP_CNTRL NAME DISP_CNTRL.0 and DISP_CNTRL.1 DISP_CNTRL.2 and DISP_CNTRL.3 DISP_CNTRL.4 DISP_CNTRL.5 to DISP_CNTRL.7 V display level U display level contrast reduction/level insertion display signal selection code; see Table 12 FUNCTION
Table 12 Truth table for bits DISP_CNTRL5 to DISP_CNTRL7] BIT NUMBER SELECT CODE 7 0 0 0 0 1 1 1 6 0 0 1 1 0 0 1 5 0 1 0 1 0 1 X no display D_VU D_WC D_AWBVAL D_HIGHLIGHT D_MWG D_CONTOUR
Table 13 Register details: address 63 DMWSEL NAME DMWSEL.0 DMWSEL.1 DMWSEL.2 DMWSEL.3 DMWSEL.4 DMWSEL.5 DMWSEL.6 DMWSEL.7 FUNCTION display measurement window A for line 0 display measurement window B for line 0 display measurement window A for line 1 display measurement window B for line 1 display measurement window A for line 2 display measurement window B for line 2 display measurement window A for line 3 display measurement window B for line 3
1999 Sep 27
28
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
Table 14 Register details: address 66 PRE_SI_MSB NAME PRE_SI_MSB.0 and PRE_SI_MSB.1 PRE_SI_MSB.2 to PRE_SI_MSB.4 control data bits d8 and d9 control address bits a0 to a2 FUNCTION
SAA8113HL
Table 15 Register details: address 68 CDAC_DATA NAME CDAC_DATA.0 to CDAC_DATA.6 CDAC data bits 0 to 6 FUNCTION
Table 16 Register details: address 78 MISC_CONTROL NAME MISC_CONTROL.0 MISC_CONTROL.1 MISC_CONTROL.2 MISC_CONTROL.3 MISC_CONTROL.4 MISC_CONTROL.5 to MISC_CONTROL.7 LED off/on audio on/off audio gain low (13 dB), high (45 dB) select 1 k mode (output impedance) standby on/off reserved for miscellaneous additional functions FUNCTION
Table 17 Register details: address 85 ACT_LINES_MSB NAME FUNCTION
ACT_LINES_MSB.0 and ACT_LINES_MSB.1 bits 8 and 9 for last active pixel number on a line ACT_LINES_MSB.2 and ACT_LINES_MSB.3 bits 8 and 9 for last active line number in field 0 ACT_LINES_MSB.4 and ACT_LINES_MSB.5 bits 8 and 9 for first active line number in field 1/frame ACT_LINES_MSB.6 and ACT_LINES_MSB.7 bits 8 and 9 for last active line number in field 1/frame Table 18 Register details: address 86 PPG_POL_SEL Name PPG_POL_SEL.0 PPG_POL_SEL.1 PPG_POL_SEL.2 PPG_POL_SEL.3 PPG_POL_SEL.4 FUNCTION select polarity of PPG output FR as inverted/non-inverted select polarity of PPG output FS as inverted/non-inverted select polarity of PPG output FCDS as inverted/non-inverted select polarity of PPG output FH1 as inverted/non-inverted select polarity of PPG output FH2 as inverted/non-inverted
Table 19 Register details: address 229 ME_OB_PO_F0 FUNCTION NAME BIT NO CCD_CATCH = 0 ME_OB_PO_F0.0 to ME_OB_PO_F0.6 ME_OB_PO_F0.7 ME_OB_PO_F00 to ME_OB_PO_F06 0 CCD_CATCH = 1 CCD2 to CCD8 CCD9
1999 Sep 27
29
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
Table 20 Register details: address 230 ME_OB_PE_F0 FUNCTION NAME BIT NO CCD_CATCH = 0 ME_OB_PE_F0.0 and ME_OB_PE_F0.1 ME_OB_PE_F0.2 to ME_OB_PE_F0.6 ME_OB_PE_F0.7 Table 21 Register details: address 231 ME_OB_PO_F1 FUNCTION NAME BIT NO CCD_CATCH = 0 ME_OB_PO_F1.0 to ME_OB_PO_F1.6 ME_OB_PO_F1.7 Table 22 Register details: address 232 ME_OB_PE_F1 FUNCTION NAME BIT NO CCD_CATCH = 01 ME_OB_PE_F1.0 to ME_OB_PE_F1.6 ME_OB_PE_F1.7 ME_OB_PE_F16 to ME_OB_PE_F10 0 ME_OB_PO_F16 to ME_OB_PO_F10 0 ME_OB_PE_F00 and ME_OB_PE_F01 ME_OB_PE_F02 to ME_OB_PE_F06 KNOB4
SAA8113HL
CCD_CATCH = 1 CCD0 and CCD1 0
CCD_CATCH = 1 `undefined'
CCD_CATCH = 1 `undefined'
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); note 1 unless otherwise specified. SYMBOL VDDDn VDDAn VDDA2 VDDA3 VDDA4 VDDA6 VDDA7 DGNDn AGNDn AGND2 AGND3 AGND4 AGND6 AGND5 AGND8 AGND9 PARAMETER digital supply voltages 1 and 2 for input buffer and pre-drivers analog supply voltages 1, 5, 8 and 9 for output buffers analog supply voltage 2 for DAC output buffer analog supply voltage 3 for analog DAC core and band gap analog supply voltage 4 for audio buffer analog supply voltage 6 for CDAC analog supply voltage 7 for 38 MHz crystal oscillator digital grounds 1, 2, and 3 for input buffer and predrivers analog grounds 1, 7, 10 and 11 for output buffers analog ground 2 for DAC output buffer analog ground 3 for analog DAC core and band gap, connected to substrate analog ground 4 for analog DAC core and band gap, not connected to substrate analog ground 6 for audio buffer connected to substrate analog ground 5 for audio buffer not connected to substrate analog ground 8 for CDAC analog ground 9 for 38 MHz crystal oscillator CONDITIONS MIN. -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 MAX. +4.0 +4.0 +4.0 +4.0 +4.0 +4.0 +4.0 +4.0 +4.0 +4.0 +4.0 +4.0 +4.0 +4.0 +4.0 +4.0 UNIT V V V V V V V V V V V V V V V V
1999 Sep 27
30
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
SYMBOL VI, VO Tstg Tamb Tj Notes input or output voltage
PARAMETER
CONDITIONS note 2
MIN. -0.5 -0.5 -55 0 -40
MAX. +5.5 +150 70 +125
UNIT V C C C
VDD + 0.5 V
storage temperature ambient temperature junction temperature
1. Stress beyond these levels may cause permanent damage to the device. 2. For 5 V-tolerant buffers. 10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 56 UNIT K/W
11 OPERATING CHARACTERISTICS VDDD = VDDA = 3.3 V 10%; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL General supplies VDDD VDDA DGND AGND IDDD IDDA Tamb digital supply voltage analog supply voltage digital ground analog ground digital supply current analog supply current ambient temperature Tamb = 25 C Tamb = 25 C 3.0 3.0 -0.3 -0.3 - - 0 3.3 3.3 0.0 0.0 45 15 25 3.6 3.6 +0.3 +0.3 - - 70 V V V V mA mA C PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Data and control inputs or I/Os (CCD9 to CCD0, M2 to M0, KNOB4 to KNOB0, RESET, EA, T1, INT1 and P0.7 to P0.0) VIL VIH LOW-level input voltage HIGH-level input voltage - 0.8VDDD - - 0.2VDDD V - V
Data and control outputs or I/Os (SMP, LED, OUTBVEN, OUTGAIN, SDATA, SCLK, SDAE, SCLE, STROBE, STNDBY, FR, OFDX, AD14 to AD8 and P0.7 to P0.0) VOL VOH VOL VOH VOL VOH LOW-level output voltage HIGH-level output voltage 0 0.85VDDD note 1 note1 - 2.2 - 2.6 - - - - - - 0.4 VDDD 0.8 - 0.8 - V V
Control outputs (FH1, FH2, FS, FCDS and CLK1) LOW-level output voltage HIGH-level output voltage V V
Control outputs (V1X, V2X, V3X, V4X, VH1X and VH3X) LOW-level output voltage HIGH-level output voltage notes 2 and 3 notes 2 and 3 V V
1999 Sep 27
31
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
SYMBOL
PARAMETER
CONDITIONS - 2.2
MIN.
TYP. - - - -
MAX.
UNIT
Control outputs (BCP and DCP) VOL VOH IO IO Notes 1. Connected to HCT (lab resources) with VIH(min) = 2.0 V and VIL(max) = 0.8 V. 2. Connected to NEC PD16510 with VIH(min) = 0.8VDD and VIL(max) = 0.3VDD. 3. Connected to ACT/HCT (lab resources) with VIH(min) = 2.0 V and VIL(max) = 0.8 V. 12 ELECTRICAL CHARACTERISTICS VDDD = VDDA = 3.3 V 10%; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL CDAC specifications LOAD RL CL VO RES DNL INL CR BA Ro tPD tst1 tst2 load resistance load capacitance 10 - at code `0' at code `127' - - - - - - - to 50% value 10% to 90% full-scale to 1 LSB - - - - - 0.00 7 - - - - 13 - - - - 100 k pF PARAMETERS CONDITIONS MIN. TYP. MAX. UNIT LOW-level output voltage HIGH-level output voltage 0.6 - - - V V
Switch Mode Pulse for DC-to-DC power supply (SMP) output current 3 mA
Output to drive the LED (LED) output current 5 mA
TRANSFER FUNCTION DC output voltage DC output voltage resolution differential non-linearity integral non-linearity conversion rate analog bandwidth output resistance 0.05 VDDD - 1/2 1 60 60 - 75 120 156 V V bit LSB LSB Hz Hz ns ns ns VDDD - 0.2 VDDD - 0.12
SWITCHING CHARACTERISTICS ON RISING FULL-SCALE STEP propagation delay time settling time settling time
1999 Sep 27
32
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
SYMBOL VDAC specifications LOAD RL
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX. UNIT
load resistance
with high impedance (1 k mode) with high impedance (1 k mode)
0.8
1
-
k
CL
load capacitance
-
-
5
pF
TRANSFER FUNCTION Vo(0) Vo(436) VRL(p-p) RES DNL INL CR fCLK BA S/N THD Ro tPD tst1 tst2 DC output voltage at code `0' DC output voltage at code `436' output voltage (436 to 0) (peak-to-peak value) resolution differential non-linearity integral non-linearity conversion rate clock frequency analog bandwidth signal-to-noise ratio total harmonic distortion output resistance dynamic note 1 0.15 1.45 1.15 - - - - - - 43 - - to 50% value 10% to 90% full-scale to 1 LSB - - - 0.212 1.55 1.288 9 - - 19 19 6.5 46 -50 2 - - - 0.30 1.75 1.6 -
1 2
V V V bit LSB LSB MHz MHz MHz dB dB ns ns ns
1 - - - - -42 3
SWITCHING CHARACTERISTICS ON RISING FULL-SCALE STEP propagation delay time settling time settling time 13 15 50
Audio amplifier specifications LOAD RL CL Vi(p-p) A1 A2 VOH(p-p) load resistance load capacitance 5 - - 43 141.2 amplification at low level nominal output level at high level (peak-to-peak value) 11 3.5 - - 5 - - - 47 223.8 14 5.0 - V dB k pF
TRANSFER FUNCTION nominal input level (peak-to-peak value) amplification at high level 5.6 44.8 173.7 12.5 4.2 0.97 mV dB
1999 Sep 27
33
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
SYMBOL VOL(rms) Vo2(p-p) Vo2(rms) Vo(max)(p-p) S/N THD Zi Zo B-3 dB BIASSING Iref
PARAMETERS nominal output level at high level (RMS value) nominal output level at low level (peak-to-peak value) nominal output level at low level (RMS value) maximum output level (peak-to-peak value) signal-to-noise ratio total harmonic distortion at high level input impedance output impedance frequency range (-3 dB)
CONDITIONS - - - 2 40 - 5 -
MIN.
TYP. 0.34 23.5 8.3 - - -60 - - - 25
MAX. UNIT - - - - - -50 - 100 20 - V mV mV V dB dB k kHz A
0.1 -
reference current
Data input/output timing; (see Fig.13) DATA INPUTS RELATED TO XIN (CCD9 TO CCD0 AND KNOB4) tsu(i)(D) th(i)(D) th(o)(D) td(o)(D) data input setup time data input hold time note 2 note 2 9.5 10.5 - - -3 -3 0 7 1 14 0 0 14 0 - - 5 3 - - 7 5.5 ns ns
DATA OUTPUTS RELATED TO XIN (OUTBVEN, OUTGAIN, SMP, LED, SDATA, SCLK, STROBE AND STNDBY) data output delay time data output hold time note 2 note 2 ns ns
PPG high speed pulse timing; CL = 10 pF (see Fig.14) td1 td2 td3 td3_delayed td4_wide td4_narrow td5 td6_wide td6_narrow td7 FH2 fall time delay w.r.t. the rising edge of FH1 FH2 rise time delay w.r.t. the falling edge of FH1 FR fall time delay w.r.t. the rising edge of FH1 FR_delayed fall time delay w.r.t. the rising edge of FH1 FCDS fall time delay w.r.t. the rising edge of FR_wide FCDS fall time delay w.r.t. the rising edge of FR_narrow FH1 fall time delay w.r.t. the rising edge of FCDS FH1 rise time delay w.r.t. the rising edge of FS_wide FH1 rise time delay w.r.t. the rising edge of FS_narrow CLK1 fall time delay w.r.t. the rising edge of FH1 34 0 0 1 8 2 15 1 1 15 1 +3 +3 2 10 3 16 2 2 16 2 ns ns ns ns ns ns ns ns ns ns
1999 Sep 27
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
SYMBOL td8 twFH1 trFH1 tfFH1 twFH2 trFH2 tfFH2 twFR_wide twFR_narrow trFR tfFR twFCDS trFCDS tfFCDS twFS_wide twFS_narrow trFS tfFS twCLK1 Notes
PARAMETERS CLK1 rise time delay w.r.t. the falling edge of FH1 FH1 pulse width FH1 rise time FH1 fall time FH2 pulse width FH2 rise time FH2 fall time FR_wide pulse width FR_narrow pulse width FR rise time FR fall time FCDS pulse width FCDS rise time FCDS fall time FS_wide pulse width FS_narrow pulse width FS rise time FS fall time CLK1 pulse width
CONDITIONS 0 - - - - - - - - - - - - - - - - - -
MIN. 1 53 4 4 53 4 4 26 13 4 4 26 4 4 40 26 4 4 53
TYP.
MAX. UNIT 2 - - - - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1. Full code swing of colour bar with maximum headroom of 16.4%. Above code `436', the DAC works but the settling time will decrease gradually. 2. The internal clock signal used in the DSP core is derived from XIN: XIN divided by 4.
1999 Sep 27
35
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
handbook, full pagewidth
tf 90% XIN 50% 10% 10% t su(i)(D)
tr 90%
t h(i)(D)
data input
t h(o)(D) 90% data output 10% 10% 90%
t d(o)(D)
FCE324
Fig.13 Data input/output timing.
1999 Sep 27
36
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
SAA8113HL
handbook, full pagewidth
t wFH1 FH1 50% t d1 t d2 FH2 50% t wFH2 FCDS 50% t wFCDS t d5 t wFS t d6_wide 50% 50% 50%
FS_wide t d6_narrow
FS_narrow t d3 t wFR t d4_wide 50% t d4_narrow FR_narrow 50% t d3_delayed FR_wide_delayed 50%
FR_wide
FR_narrow_delayed t d7 CLK1 50%
50% t d8 50% t wCLK1
FCE325
Fig.14 PPG high speed pulse timing diagram.
1999 Sep 27
37
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
13 APPLICATION INFORMATION
SAA8113HL
handbook, full pagewidth
analog preprocessing optics CCD sensor PAL/NTSC (medium resolution) CDS, AGC AND ADC
SAA8113HL
DIGITAL SIGNAL PROCESSING
VDAC
LPF
analog (CVBS)
DRIVERS
PREPROCESSING, TIMING AND CONTROL SENSOR, TIMING AND CONTROL MODE CONTROL AND CLOCK GENERATOR MICROCONTROLLER 80C51 CDAC
parallel interface
program PROM
serial interface
settings EEPROM I2C-bus interface
HUMAN INTERFACE
AUDIO AMPLIFIER
FCE326
Fig.15 Application block diagram.
1999 Sep 27
38
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
14 PACKAGE OUTLINE LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
SAA8113HL
SOT407-1
c
y X 75 76 51 50 ZE A
e E HE wM bp L pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X Lp A A2 (A 3)
A1
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.5 1.3 A3 0.25 bp 0.28 0.16 c 0.18 0.12 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7 0o
o
16.25 16.25 15.75 15.75
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-12-19 97-08-04
1999 Sep 27
39
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
15 SOLDERING 15.1 Introduction to soldering surface mount packages
SAA8113HL
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 15.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 15.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 Sep 27
40
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
15.5 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable suitable(2) recommended(3)(4) recommended(5) suitable not not suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not
SAA8113HL
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 Sep 27
41
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
16 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA8113HL
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 18 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1999 Sep 27
42
Philips Semiconductors
Preliminary specification
Digital PC-camera signal processor
NOTES
SAA8113HL
1999 Sep 27
43
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 68
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545006/25/01/pp44
Date of release: 1999
Sep 27
Document order number:
9397 750 04816

▲Up To Search▲

Price & Availability of SAA8113HL

	To Download SAA8113HL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .