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S3F49DAX
MultiMediaCard Controllers Datasheet
Revision 1.0
S3F49DAX
MULTIMEDIACARD CONTROLLER
PRODUCT OVERVIEW
S3F49DAX 16/32-bit RISC microprocessor would be designed to provide a cost-effective, low power, small die size and high performance micro-controller solution for Low voltage MMC (MultiMediaCard). To reduce total system cost, S3F49DAX also provides the followings: 16K Byte SRAM, 48K Byte Internal NOR Flash memory, NAND Flash controller, interrupt controller, 2-channel DMA (Direct Memory Access), 3-channel Timer and Analog block including IVC (Internal Voltage Converter), POR (Power-On Reset) and RCOSC (RC Oscillator). S3F49DAX microprocessor would be developed using an ARM7TDMI-S core, 0.18um CMOS standard cells housed in 64UELP package. And S3F49DAX adopts the new bus architecture, AMBA 2.0 (Advanced Micro-controller Bus Architecture). The integrated on-chip functions that are described in this document include: * * * * * * * * * Compliant with MMC (MultiMediaCard) system specification version 3.3 Built in internal memory: 48K Byte NOR Flash for program, 16K Byte SRAM for data buffer and stack Integrated NAND Flash memory controller Built in ECC (Error Correction Code) Engine. Two-channel DMA (Direct Memory Access) Three-channel Timer and one-channel UART with interrupt-based operation Interrupt controller: 21 interrupt sources Power control: Normal, Slow and Standby mode Built in analog function block: POR (Power-On Reset), RCOSC (RC Oscillator) and IVC (Internal Voltage Converter)
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FEATURES
Architecture * * * Integrated system for Low Voltage MMC (MultiMediaCard). 16/32-bit RISC architecture and powerful instruction set with ARM7TDMI-S CPU core. Internal AMBA (Advanced Micro-controller Bus Architecture, AMBA 2.0) NOR Flash Memory Controller * * * * Built in 48K Byte NOR Flash memory. Supports two type programming mode: User programming mode, Tool programming mode Supports three type data protection: Read Protection, LD Protection, Hardware Protection Supports Byte Programming/Option Sector Programming/Chip Erase/Sector Erase/Verify Sequence.
ARM7TDMI-S * * * * * Supports fixed little endian mode. 32/16-bit RISC architecture. (ARM V4T) 32-bit ARM instruction set for maximum performance and flexibility 16-bit Thumb instruction set for increased code density Coprocessor Interface / JTAG debug interface unit
SRAM Memory Controller * Built in 16K Byte SRAM memory for FTL map table, ECC, Global variables, Stack & Heap area.
Interrupt Controller * * * Supports normal or fast interrupt modes (IRQ, FIQ) Supports vectored interrupts (Hard-wired Interrupt) S/W programmable interrupt priority.
MMC Interface * * * * Fully compliant with MultiMediaCard specification version 3.3 Supports MMC (MultiMediaCard) mode and SPI mode. Supports command classes which are class 0, 2, 4, 5, 6, 7 CRC (Cyclic Redundancy Check) bits generation and check
DMA (Direct Memory Access) * Two dedicated DMA (Host I/F DMA, NAND Flash I/F DMA)
Timer * * * One-channel 16-bit timer & 32-bit timer. Watch-dog Timer Interrupt-based operation (Support interval mode)
NAND Flash Memory Controller * * Supports variable capacity NAND Flash memory. Supports low voltage NAND Flash memory (Operating voltage range of NAND Flash: 1.65 V to 1.95 V) Supports up to Two NAND flash memories extension.
*
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UART * * One-channel UART with interrupt-based operation Programmable baud rate.
Operating Frequency * 18 MHz 3 MHz (RCOSC Output Frequency)
Operating Voltage * * * * Internal Logic: 1.65 V to 1.95 V I/O: 1.65 V to 3.6 V NAND flash interface: 1.65 V to 3.6 V In case of high voltage MMC, You must use the interface power (2.7 V to 3.6 V).
DES / T-DES * * * Built-in hardware DES Four keys for encryption and decryption Start / Stop control
Random Number Generator * * One 16-bit random number generator in accordance with FIPS140-2 Start / Stop Control Package Type * 64-pin UELP Operating Temperature * Regular specification: -25 C to +85 C
Analog Function Block * * * Built-in RCOSC (RC Oscillator): 18 MHz @ 1.8 V Built-in POR (Power-on Reset) and LVD (Low Voltage Detector) Built-in IVC: 3.3 V to 1.8 V
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S3C49DAX
BLOCK DIAGRAM
ARM7TDMI-S
D M A
NAND Flash Controller
NAND Flash
JTAG Port
TAP Controller D M A A H B MMC Host Interface MMC Host
16K Byte SRAM
48K Byte NOR Flash
Interrupt Controller
XADDR XDATA
External ROM Interface
General IO
GPIO
Power Management
RNG
POR
Bridge
RCOSC
UART & Timer
APB
DES
Figure 1. S3C49DAX Block Diagram
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PIN ASSIGNMENTS
CLKOUT 35
XADDR0
EXTCLK
nTRST
FIO0
FIO1
FIO2
FIO3
FIO4
FIO5
FIO6
FIO7
VDD
TMS 33
VSS
TDI 34
36
37
38
39
40
41
42
43
44
45
46
47
48
TCK RTCK TDO MDATA VDD MCLK VSS MCMD MCS OM3 OM2 OM1 OM0 VDD1I HVMMC RSTOUT
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 nRESET 15 nFCE1 14 FRnB1 13 GPIO7 12 GPIO6 11 nFWP 10 nFWE 9 FALE 8 FCLE 7 VSS 6 VDD 5 nFCE0 4 3 2 1
49
XADDR1 XADDR2 XADDR3 XADDR4 XADDR5 XADDR6 VSS SCLK SDAT VDD GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5
S3F49DAX 64-UELP (Bottom View)
50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Figure 2. S3F49DAX Pin Assignments
nFRE
FRnB0
VPP
Margin
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S3C49DAX
Table 1. 64-Pin ELP Pin Assignment Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name Margin VPP FRnB0 nFRE nFCE0 VDD VSS FCLE FALE nFWE nFWP GPIO6/XDATA6 GPIO7/XDATA7 FRnB1 nFCE1 nRESET RSTOUT HVMMC IVCOUT OM0 OM1 OM2 OM3 MCS MCMD VSS MCLK VDD MDATA TDO RTCK TDI Function Internal NOR flash cell margin test Internal NOR flash program power NAND flash memory ready/busy signal 0 NAND flash memory read enable signal NAND flash memory chip enable signal 0 MMC power MMC ground NAND flash memory command latch enable signal NAND flash memory address latch enable signal NAND flash memory write enable signal NAND flash memory write protect signal General IO port 6/External ROM data 6 General IO port 7/External ROM data 7 NAND flash memory ready/busy signal 1 NAND flash memory chip enable signal 1 Global reset input for the S3F49DAX Internal POR monitoring output High voltage MMC select Internal VDD (1.8V) Operation mode select 0 Operation mode select 1 Operation mode select 2 Operation mode select 3 MMC card select signal for SPI mode MMC command signal MMC ground MMC clock signal MMC power MMC data signal TAP controller data output Returned TCK TAP controller data input I/O State I I I O O P G O O O O I/O I/O I O I O O P I I I I I I/O G I P I/O O O I I/O Type phia vpp12 phicu10 phmbct phmbct vdd3io vss3io phmbct phmbct phmbct phmbct phbcu60t phbcu60t phicu10 phmbct phicu60 phob4 phic vdd1i phic phic phic phic phmicu60 phmbcu10t vss3io phmic vdd3io phmbcu60t phob phob phicu60
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Table 1. 64-Pin ELP Pin Assignment (Continued) Pin No 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 TMS TDI CLKOUT EXTCLK nTRST FIO0 FIO1 FIO2 FIO3 VSS VDD FIO4 FIO5 FIO6 FIO7 XADDR0 XADDR1 XADDR2 XADDR3 XADDR4 XADDR5 XADDR6 VSS SCLK SDAT VDD GPIO0/XDATA0 GPIO1/XDATA1 GPIO2/XDATA2 GPIO3/XDATA3 GPIO4/XDATA4 GPIO5/XDATA5 Pin Name Function TAP controller mode select TAP controller data input Internal VCO clock monitoring output External clock input TAP controller reset NAND flash memory IO signal 0 NAND flash memory IO signal 1 NAND flash memory IO signal 2 NAND flash memory IO signal 3 MMC ground MMC power NAND flash memory IO signal 4 NAND flash memory IO signal 5 NAND flash memory IO signal 6 NAND flash memory IO signal 7 External ROM address 0 out for test External ROM address 1 out for test External ROM address 2 out for test External ROM address 3 out for test External ROM address 4 out for test External ROM address 5 out for test External ROM address 6 out for test MMC ground Serial clock input for NOR Flash programming Serial data signal for NOR Flash programming MMC power General IO port 0/External ROM data 0 General IO port 1/External ROM data 1 General IO port 2/External ROM data 2 General IO port 3/External ROM data 3 General IO port 4/External ROM data 4 General IO port 5/External ROM data 5 I/O State I I O I I I/O I/O I/O I/O G P I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O G I I/O P I/O I/O I/O I/O I/O I/O I/O Type phicu60 phicu60 phob phic phicu60 phmbct phmbct phmbct phmbct vss3io vdd3io phmbct phmbct phmbct phmbct phob phob phob phob phob phob phob vss3io phicu60 phbcu60t vdd3io phbcu60t phbcu60t phbcu60t phbcu60t phbcu60t phbcu60t
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Table 2. I/O Type Description I/O Type phia phic phicu60 phicu10 phmic phob phmbct phmbc60t phmbc10t vdd3io vss3io vdd1i High voltage analog input buffer High voltage CMOS input buffer High voltage CMOS input buffer with pull-up resistor (60 k) High voltage CMOS input buffer with pull-up resistor (10 k) High voltage CMOS MMC input buffer High voltage normal output buffer, Io = 4 mA High voltage CMOS MMC input buffer and tri-stat output buffer High voltage CMOS MMC input buffer with pull-up resistor (60 k) and tri-stat output buffer High voltage CMOS MMC input buffer with pull-up resistor (10 k) and tri-stat output buffer 3.3 V VDD Ground 1.8 V VDD (Internal Regulator Output) Description
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SIGNAL DESCRIPTIONS
Table 3. S3F49DAX Signal Description Signal I/O Description
NAND Flash Interface FIO [7:0] nFCE [1:0] FCLE FALE nFRE nFWE nFWP FRnB[1:0] MMC Interface MCS MCMD MCLK MDATA Clock & Reset nRESET RSTOUT EXTCLK CLKOUT Special Interface OM[3:0] I These pins determine status of product for manufacture test. 0000 = Normal operation mode HVMMC GPIO [7:0] XADDR[6:0] XDATA I IO O I/O This pin is used to select high voltage MMC General IO port External ROM Address: These pins are used to check manufacture test. External ROM data: These pins are used to check manufacture test. I O I O External System Reset: This signal suspends any operation in progress. Internal POR Output: This pin is used to check the Power-On Reset detect voltage. External Clock Source: External clock input for test mode VCO Output: This pin is used to check the Internal VCO Characteristics I I/O I I/O MMC Card Select: Host to card chip select signal MMC Command: Host to/from card Command/Response signal MMC Serial Clock: Host to Card clock signal MMC Data: Host to/from card data signal I/O O O O O O O I Data Input/Output: These pins are use to input data during read operations, and to output command, address and data. Chip Enable: The nFCE output is the device selection control. Command Latch Enable: The FCLE output controls the activating path for commands to the NAND Flash. Address Latch Enable: The FALE output controls the activating path for address to NAND Flash Read Enable: The nFRE output controls the serial data-out from NAND Flash, and when active fetches the data onto the I/O bus. Write Enable: The nFWE output controls writes to I/O port Write Protect: The nFWP signal provides inadvertent write/erase protection during power transitions. Ready/Busy: These pins indicate the status of the NAND Flash operation. When low, it indicates that a program, erase or random read operation is in process.
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Table 3. S3F49DAX Signal Description (Continuous) Signal I/O Description
NOR Flash Interface SCLK SDAT VPP Margin JTAG Interface nTRST I This pin (TAP Controller Reset) can reset the TAP controller at power-up. If the debugger is not used, this pin should be "Low" level or low active pulse should be applied before CPU running. For example, nRESET signal can be tied with this pin This pin (TAP Controller Mode Select) can control the sequence of the state diagram of TAP controller This pin (TAP Controller Clock) can provide the clock input for the JTAG logic This pin is the returned TCK This pin (TAP Controller Data Input) is the serial input for JTAG port. This Pin (TAP Controller Data Output) is the serial data output for JTAG port. I IO P I Serial CLOCK: This pin is used Tool program for internal Flash (Write speed: Max 250 kHz, Read speed: Max 3 MHz) Serial DATA: This pin is used Tool program for internal Flash (Output when reading, Input when writing.) Input & push-pull output port can be assigned. Flash cell writing power supply pin for tool program mode. The function of entering flash writing Mode. This pin can used the flash cell margin test
TMS TCK RTCK TDI TDO Power IVCOUT VDD VSS
I I O I O
P P P
IVC Out: This pin output the internal IVC Output voltage (1.8 V) Interface power supply Interface ground
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1.
MULTIMEDIACARD FUNCTION DESCTION
The MultiMediaCard system defines two communication protocols: MMC and SPI mode. All communication between host and card is controlled by the host. The card automatically selects the mode of the reset command and will operate all command to be in the same communication mode.
MMC MODE
The basic MultiMediaCard concept is based on transferring data via a minimal number of signals. The communication signals are: * * CLK: with each cycle of this signal an one bit transfer on the command and data lines is done. The frequency may vary between zero and the maximum clock frequency. CMD: is a bi-directional command channel used for card initialization and data transfer commands. The CMD signal has two operation modes: open-drain for initialization mode and push-pull for fast command transfer. Commands are sent from the MultiMediaCard bus master to the card and responses from the cards to the host. DAT: is a bi-directional data channel. The DAT signal operates in push-pull mode. Only one card or the host is driving this signal at a time.
*
Table 4. MMC/SPI Interface Pin Configuration Pin No 1 2 3 4 5 6 7
NOTE:
MultiMediaCard Mode Name RSV CMD VSS1 VDD CLK VSS2 DAT Type1 NC I/O/PP/OD S S I S I/O/PP Description Reserved Command/Response Supply voltage ground Supply voltage Clock Supply voltage ground Data Name CS DI VSS VDD SCLK VSS2 DO Type I I/PP S S I S O/PP
SPI Mode Description Chip select (Active Low) Data In Supply voltage ground Supply voltage Clock Supply voltage ground Data Out
S: Power supply; I: Input; O: Output; PP: Push-pull; OD: Open-drain; NC: Not connected (or Logical high)
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SPI MODE
The SPI mode consists of a secondary, optional communication protocol which is offered by Flash-based MultiMediaCards. This mode is a subset of the MultiMediaCard protocol, designed to communicate with a SPI channel, commonly found in Motorola's (and lately a few other vendors') microcontrollers. The interface is selected during the first reset command after power up (CMD0) and cannot be changed once the part is powered on. The SPI standard defines the physical link only, and not the complete data transfer protocol. The MultiMediaCard SPI implementation uses a subset of the MultiMediaCard protocol and command set. It is intended to be used by systems which require a small number of cards (typically one) and have lower data transfer rates (compared to MultiMediaCard protocol based systems). From the application point of view, the advantage of the SPI mode is the capability of using an off-the-shelf host, hence reducing the design-in effort to minimum. The MultiMediaCard SPI interface is compatible with SPI hosts available on the market. As in any other SPI device, the MultiMediaCard SPI channel consists of the following four signals: * * * * CS: CLK: DataIn: DataOut: Host to card Chip Select signal. Host to card clock signal Host to card data signal. Card to host data signal.
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MULTIMEDIACARD PROTOCOL
MMC MODE After a power-on reset, the card is initialized by MultiMediaCard bus protocol using the command channel. MultiMediaCard bus protocol is represented by one of the following tokens: * Command: A command is a token, which starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line. Response: A response is a token, which is sent from an addressed card, or (synchronously) from all connected cards, to the host as an answer to a previously received command. A response is transferred serially on the CMD line. Data: Data can be transferred from the card to the host or vice versa. Data is transferred via the data line.
*
*
Card addressing is implemented using a session address assigned during the initialization phase, by the bus controller to all currently connected cards. Individual cards are identified by their CID number. This method requires that every card will have an unique CID number. To ensure uniqueness of CIDs the CID register contains 24 bits (MID and OID fields - see Chapter 5), which are defined by the MMCA. Every card manufacturers is required to apply for an unique MID (and optionally OID) number. MultiMediaCard bus data transfers are composed of these tokens. One data transfer is a bus operation. There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token, the others transfer their information directly within the command or response structure. In this case no data token is present in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the host clock. Two types of data transfer commands are defined: * Sequential commands: These commands initiate a continuous data stream, they are terminated only when a stop command follows on the CMD line. This mode reduces the command overhead to an absolute minimum. Block-oriented commands: These commands send a data block succeeded by CRC bits. Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the sequential read.
*
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From Host to Card CMD Command Response
From Card to Host
Data From Card to Host
Stop Command Stops Data Transfer Command Response
DAT
Data Stream
Data Transfer Operation
Data Stop Operation
Figure 3. Sequential Read Operations
From Host to Card CMD Command Response
From Card to Host
Data From Card to Host
Stop Command Stops Data Transfer Command Response
DAT
Data Block
crc
Data Block
crc
Data Block
crc
Block Read Operation Multiple Block Read Operation
Data Stop Operation
Figure 4. (Multiple) Block Read Operations
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MULTIMEDIACARD CONTROLLER
From Host to Card(s) CMD Command Response
From Card to Host
Data From Host to Card
Stop Command Stops Data Transfer Command Response Busy From Card to Host
DAT
Data Stream
busy
Data Transfer Operation
Data Stop Operation
Figure 5. Sequential Write Operations The block write operation uses a simple busy signalling of the write operation duration on the data (DAT) line. (see Figure6).
From Host to Card CMD Command Response
From Card to Host
Data From Host to Card
Data From Card to Host
Stop Command Stops Data Transfer Command Response
DAT
Data Block
crc
busy
Data Block
crc
busy
Block Write Operation Multiple Block Write Operation
Data Stop Operation
Figure 6. (Multiple) Block Write Operations
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From Host to Card(s) CMD Command
From Host to Card Command Response
From Card to Host
DAT
Operation (no response)
Operation (no data)
Figure 7. "No Response" and "No Data" Operations Command tokens have the following coding scheme:
Transmitter Bit: '1' = Host Command Start Bit: always '0' 0 1 Command Content: Command and address information or parameter, protected by 7 bit CRC checksum End Bit: always '1'
Content Total Length = 48 Bits
CRC
1
Figure 8. Command Token Format
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MULTIMEDIACARD CONTROLLER
Each command token is preceded by a start bit (`0') and succeeded by an end bit (`1'). The total length is 48 bits. Each token is protected by CRC bits so that transmission errors can be detected and the operation may be repeated. Response tokens have five coding schemes depending on their content. The token length is either 48 or 136 bits. The detailed commands and response definition is given in next sections. The CRC protection algorithm for block data is a 16 bits CCITT polynomial.
Transmitter Bit: '0' = Card Response Start Bit: always '0' R1, R3, R4, R5 0 0
Response Content: Mirrord command and status information(R1 response), OCR register(R3 response) or RCA(R4 and R5), protected by a 7bit CRC checksum End Bit: always '1' Content Total Length = 48 Bits 0 0 Content = CID or CSD Total Length = 136 Bits CRC 1 CRC 1 End Bit: always '1'
R2
Figure 9. Response Token Format
1 Bit Bus (only DAT0 used): End bit, always '1' sent when transfer is interrupted by a CMD
Sequential Data
Start Bit: always '0' DAT0 Start Bit: always '0' DAT0 0 0
LSB
...
LSB MSB 0 1
1
Block Data
...
Block Length = S
4095
CRC
1
Figure 10. Data Token Format
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SPI MODE While the MultiMediaCard channel is based on command and data bit streams, which are initiated by a start bit and terminated by a stop bit, the SPI channel is byte oriented. Every command or data block is built of 8-bit bytes and is byte aligned to the CS signal (i.e. the length is a multiple of 8 clock cycles). Similar to the MultiMediaCard protocol, the SPI messages consist of command, response and data-block tokens (see Chapter 3 for a detailed description). All communication between host and cards is controlled by the host (master). The host starts every bus transaction by asserting the CS signal low. The response behavior in the SPI mode differs from the MultiMediaCard mode in the following three aspects: * * * The selected card always responds to the command. Additional (8, 16 & 40 bit) response structures are used When the card encounters a data retrieval problem, it will respond with an error response (which replaces the expected data block) rather than by a time-out, as in the MultiMediaCard mode.
Only single and multiple block read/write operations are supported in SPI mode (sequential mode is not supported). In addition to the command response, every data block sent to the card during write operations will be responded to with a special data response token. A data block may be as big as one card write block and as small as a single byte. Partial block read/write operations are enabled by card options specified in the CSD register.
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Data Read The SPI mode supports single and multiple block read operations. The main difference between SPI and MultiMediaCard modes is that the data and the response are both transmitted to the host on the DataOut signal (refer to Figure11 and Figure12). Therefore the card response to the STOP_COMMAND may cut-short and replace the last data block.
From Host to Card DataIn Command
From Card to Host
Data From Card to Host Command
Next Command
DataOut
Response
Data Block
CRC
Figure 11. Single Block Read Operation
From Host to Card DataIn Command
From Card to Host
Data From Card to Host Command
Stop Command
DataOut
Response
Data Block
CRC
Data Block
CRC
Data B.
Response
Figure 12. Multiple Block Read Operation In case of a data retrieval error (e.g. out of range, address misalignment, internal error, etc.), the card will not transmit any data. Instead (as opposed to MultiMediaCard mode where the card times out), a special data error token will be sent to the host. Figure13 shows a single block read operation, which terminates with an error token rather than a data block.
From Card to Host Command Data error token from card to host Command
From Host to Card DataIn
Next Command
DataOut
Response
Data Error
Figure 13. Read Operation - Data Error
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Multiple block read operation can be terminated the same way, the error token replacing a data block anywhere in the sequence. The host must than abort the operation by sending the stop transmission command. If the host sends a stop transmission command after the card transmitted the last block of a multiple block read with a pre-defined number of blocks, it will be responded to as an illegal command. If the host uses partial blocks whose accumulated length is not block aligned and block misalignment is not allowed, the card shall detect a block misalignment error condition at the beginning of the first misaligned block (ADDRESS_ERROR error bit will is set in the data error token). Data Write The SPI mode supports single block and Multiple block write commands. Upon reception of a valid write command (CMD24 or CMD25), the card will respond with a response token and will wait for a data block to be sent from the host. CRC suffix, block length and start address restrictions are (with the exception of the CSD parameter WRITE_BL_PARTIAL controlling the partial block write option) identical to the read operation (see Figure14). If a CRC error is detected it will be reported in the data-response token and the data block will not be programmed.
Data From Host to Card
From Host to Card DataIn Command
From Card to Host
Start Block Token
Data response and busy from card Command
New Command Form Host
Data Block
DataOut
Response
Data_Response
busy
Figure 14. Single Block Write Operation Every data block has a prefix of `Start Block' token (one byte). After a data block has been received, the card will respond with a data-response token. If the data block has been received without errors, it will be programmed. As long as the card is busy programming, a continuous stream of busy tokens will be sent to the host (effectively holding the DataOut line low). In Multiple Block write operation the stop transmission will be done by sending `Stop Tran' token instead of `Start Block' token at the beginning of the next block.
From Host to Card DataIn Command
From Card to Host
Start Block Token
Data From Host to Card
Data response and busy from card Data Block
Data From Stop Tran Host to Token Card
Data Block
DataOut
Response
Data_Response
busy
Data_Response
busy
busy
Figure 15. Multiple Block Write Operation
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COMMANDS
Command Types There are four kinds of commands defined to control the MultiMediaCard: * * * * Broadcast commands (bc), no response. Broadcast commands with response (bcr) response from all cards simultaneously. Addressed (point-to-point) commands (ac) no data transfer on DAT. Addressed (point-to-point) data transfer commands (adtc) data transfer on DAT
All commands and responses are sent over the CMD line of the MultiMediaCard bus. The command transmission always starts with the left bit of the bit-string corresponding to the command codeword. Command Format All commands have a fixed code length of 48 bits, needing a transmission time of 2.4usec @ 20 MHz Bit Position Width (bits) Value Description 47 1 "0" Start bit 46 1 "1" Transmission bit [45:40] 6 "x" Command index [39:8] 32 "x" Argument [7:1] 7 "x" CRC7 [0] 1 "1" End bit
A command always starts with a start bit (always `0'), followed by the bit indicating the direction of transmission (host = `1'). The next 6 bits indicate the index of the command, this value being interpreted as a binary coded number (between 0 and 63). Some commands need an argument (e.g. an address), which is coded by 32 bits. A value denoted by `x' in the table above indicates this variable is dependent on the command. All commands are protected by a CRC (see Chapter 8.2 for the definition of CRC7). Every command codeword is terminated by the end bit (always `1'). All commands and their arguments are listed in Table 5, Table 13. Detailed Command Description The following tables define in detail all MultiMediaCard bus commands. The responses R1-R5 are defined in Response section. The registers CID, CSD and DSR are described in Register section.
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Table 5. Basic Commands (class 0) and Read Stream Commands (class 1) CMD Index CMD0 CMD1 Type bc bcr Argument [31:0] stuff bits [31:0] OCR without busy [31:0] stuff bits [31:16] RCA [15:0] stuff bits CMD4 bc [31:16] DSR [15:0] stuff bits CMD5 CMD6 CMD7 Reserved Reserved ac [31:16] RCA [15:0] stuff bits R1b SELECT/DISELECT_ CARD Command toggles a card between the standby and transfer states or between the programming and disconnect states. In both cases the card is selected by its own relative address and gets deselected by any other address; address 0 deselects all. - Resp. - R3 Abbreviation GO_IDLE_STATE SEND_OP_COND Command Description Resets all cards to idle state Asks all cards in idle state to send their operation conditions register contents in the response on the CMD line. Asks all cards to send their CID numbers on the CMD line. Assigns relative address to the card
CMD2 CMD3
bcr ac
R2 R1
ALL_SEND_CID SET_RELATIVE_ ADDR SET_DSR
Programs the DSR of all cards
CMD8 CMD9
Reserved ac [31:16] RCA [15:0] stuff bits R2 SEND_CSD Addressed card sends its card-specific data (CSD) on the CMD line. Addressed card sends its cardidentification data (CID) on the CMD line. Reads data stream from the card, starting at the given address, until a STOP_TRANSMISSION follows. Terminates a read/write stream/multiple block operation. When CMD12 is used to terminate a read transaction the card will respond with R1. when it is used to stop a write transaction the card will respond with R1b. Addressed card sends its status register.
CMD10
ac
[31:16] RCA [15:0] stuff bits
R2
SEND_CID
CMD11
adtc
[31:0] data address [31:0] stuff bits
R1
READ_DATA_UNTIL _STOP
CMD12
ac
R1 or R1b
STOP_ TRANSMISSION
CMD13
ac
[31:16] RCA [15:0] stuff bits
R1
SEND_STATUS
CMD14 CMD15
Reserved ac [31:16] RCA [15:0] stuff bits - GO_INACTIVE_ STATE Set the card to inactive state in order to protect the card stack against communication breakdowns
22
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MULTIMEDIACARD CONTROLLER
Table 6. Block Oriented Read Commands (class 2) CMD Index CMD16 Type ac Argument [31:0] block address Resp. R1 Abbreviation SET_BLOCKLEN Command Description Sets the block length (in bytes) for all following block commands (read/write). Default block length is specified in the CSD Reads a block of the size selected by the SET_BLOCKLEN command. Continuously transfers data blocks from card to host until interrupted by a stop command or the requested number of data block transmitted.
CMD17
adtc
[31:0] block address [31:0] block address
R1
READ_SINGLE_ BLOCK
CMD18
adtc
R1
READ_MULTIPLE_ BLOCK
CMD19
Reserved
Table 7. Stream Write Commands (class 3) CMD Index CMD20 Type adtc Argument [31:0] block address Resp. R1 Abbreviation WRITE_DAT_ UNTIL_STOP Command Description Writes data stream from the host, starting at the given address. Until a STOP_SRANSMISSION follows.
CMD21 CMD22
Reserved Reserved
23
MULTIMEDIACARD CONTROLLER
S3C49DAX
Table 8. Block Oriented Write Commands (class 4) CMD Index CMD23 Type ac Argument [31:16] set to 0 [15:0] number of block CMD24 CMD25 adtc adtc [31:0] block address [31:0] block address [31:0] stuff bits R1 R1 Resp. R1 Abbreviation SET_BLOCK_ COUNT Command Description Defines the number of blocks which are going to be transfer in the immediately succeeding multiple block read or write commands. Writes a block of the size selected by the SET_BLOCKLEN command. Continuously writes blocks of data until a STOP_TRANSMISSION follows or the requested number of block received. Programming of the card identification register. This command shall be issued only once per card. The card contains hardware to prevent this operation after the first programming. Normally this command is reserved for the manufacturer Programming of the programmable bits of the CSD.
WRITE_BLOCK WRITE_MULTIPLE _BLOCK
CMD26
adtc
R1
PROGRAM_CID
CMD27
adtc
[31:0] stuff bits
R1
PROGRAM_CSD
Table 9. Block Oriented Write Protection Commands (class 6) CMD Index CMD28 Type ac Argument [31:0] block address Resp. R1 Abbreviation SET_WRITE_PROT Command Description If the card has write protection features, this command sets the write protection bit of the addressed group. The properties of write protection are coded in the card specific data (WP_GRP_SIZE). If the card provides write protection features, this command clears the write protection bit of the addressed group. If the card provides write protection features, this command asks the card to send the status of the write protection bits
CMD29
ac
[31:0] block address [31:0] write protect data address
R1b
CLR_WRITE_PROT
CMD30
adtc
R1
SEND_WRITE_ PROT
CMD31
Reserved
24
S3F49DAX
MULTIMEDIACARD CONTROLLER
Table 10. Erase Commands (class 5) CMD Index CMD32 CMD33 CMD34 CMD35 ac [31:0] block address [31:0] block address R1 ERASE_GROUP_ START R1 ERASE_GROUP_ END Sets the address of the first erase group within a range to be selected for erase. Sets the address of the last erase group within a continuous range to be selected for erase Type Argument Resp. Abbreviation Command Description
Reserved: These command indexes cannot be used in order to maintain backwards compatibility with older versions of the MultiMediaCards.
CMD36
ac
CMD37 CMD38
Reserved: These command indexes cannot be used in order to maintain backwards compatibility with older versions of the MultiMediaCards. ac [31:0] stuff bits R1b ERASE Erases all previously selected write blocks
Table 11. I/O Mode Commands (class 9, S3F49DAX cannot support the this command class) CMD Index CMD39 Type ac Argument [31:16] RCA [15] Register write flag [14:8] Register address [7:0] Register data CMD40 CMD41 bcr [31:0] stuff bits R5 GO_IRQ_STATE Resp. R4 Abbreviation FAST_IO Command Description Used to write and read 8 bit (register) data fields. The command addresses a card and a register and provides the data for writing if the write flag is set. The R4 response contains data read from the addressed register. This command accesses application dependent registers which are not defined in the MultiMediaCard standard. Sets the system into interrupt mode.
Reserved
Table 12. Lock Card (class 7) CMD Index CMD42 Type adtc Argument [31:0] stuff bits Resp. R1b Abbreviation LOCK_UNLOCK Command Description Used to set/reset the password or lock/ unlock the card. The size of the data block is set by the SET_BLOCK_LEN command.
CMD43 - CMD54
Reserved
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MULTIMEDIACARD CONTROLLER
S3C49DAX
Table 13. Application Specific Commands (class 8, S3F49DAX cannot support the this command class) CMD Index CMD55 Type ac Argument [31:16] RCA [15:0]stuff bits Resp. R1 Abbreviation APP_CMD Command Description Indicates to the card that the next command is an application specific command rather than a standard command Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. The size of the data block shall be set by the SEL_BLOCK_LEN command.
CMD56
adtc
[31:1] stuff bits [0] RD/WR
R1b
GEN_CMD
CMD57 CMD58 CMD59 CMD60 CMD61 CMD62 CMD63
Reserved
Reserved for manufacture
26
S3F49DAX
MULTIMEDIACARD CONTROLLER
RESPONSES All responses are sent via the command line CMD. The response transmission always starts with the left bit of the bit-string corresponding to the response codeword. The code length depends on the response type. A response always starts with a start bit (always `0'), followed by the bit indicating the direction of transmission (card = `0'). A value denoted by `x' in the tables below indicates a variable entry. All responses except for the type R3 (see below) are protected by a CRC. Every command codeword is terminated by the end bit (always `1'). There are five types of responses. Their formats are defined as follows: * R1 (normal response command): code length 48 bit. The bits 45:40 indicate the index of the command to be responded to, this value being interpreted as a binary coded number (between 0 and 63). The status of the card is coded in 32 bits. The card status is described in next section. Bit Position Width (bits) Value Description 47 1 "0" Start bit 46 1 "0" Transmission bit [45:40] 6 "x" Command index [39:8] 32 "x" Argument [7:1] 7 "x" CRC7 [0] 1 "1" End bit
* *
R1b is identical to R1 with an optional busy signal transmitted on the data line. The card may become busy after receiving these commands based on its state prior to the command reception. R2 (CID, CSD register): code length 136 bits. The contents of the CID register are sent as a response to the commands CMD2 and CMD10. The contents of the CSD register are sent as a response to CMD9. Only the bits [127...1] of the CID and CSD are transferred, the reserved bit [0] of these registers is replaced by the end bit of the response. Bit Position Width (bits) Value Description 135 1 "0" Start bit 134 1 "0" Transmission bit [133:128] 6 "111111" Reserved [127:1] 127 "x" CID or CSD register incl. Internal CRC7 [0] 1 "1" End bit
*
R3 (OCR register): code length 48 bits. The contents of the OCR register is sent as a response to CMD1. The level coding is as follows: restricted voltage windows = LOW, card busy = LOW. Bit Position Width (bits) Value Description 47 1 "0" Start bit 46 1 "0" Transmission bit [45:40] 6 "111111" Reserved [39:8] 32 "x" OCR Register [7:1] 7 "1111111" Reserved [0] 1 "1" End bit
27
MULTIMEDIACARD CONTROLLER
S3C49DAX
*
R4 (Fast I/O): code length 48 bits. The argument field contains the RCA of the addressed card, the register address to be read out or written to, and its contents. Bit Position Width (bits) Value Description 47 1 "0" Start bit 46 1 "1" Transmission bit [45:40] 6 "100111" CMD39 16 "x" RCA[31:16] [39:8] Argument field 8 "x" Register Address 8 "x" Read Register Contents [7:0] [7:1] 7 "x" CRC7 [0] 1 "1" End bit
*
R5 (Interrupt request): code length 48 bits. If the response is generated by the host, the RCA field in the argument shall be 0x0. Bit Position Width (bits) Value Description 47 1 "0" Start bit 46 1 "1" Transmission bit [45:40] 6 "100111" CMD39 [39:8] Argument field 16 "x" RCA [31:16] of winning card or of the host 16 "x" [15:0] Not defined. May be used for IRQ data [7:1] 7 "x" CRC7 [0] 1 "1" End bit
CARD STATUS The response format R1 contains a 32-bit field named card status. This field is intended to transmit the card's status information (which may be stored in a local status register) to the host. If not specified otherwise, the status entries are always related to the previous issued command. The semantics of this register is according to the CSD entry SPEC_VERS (see Chapter 5.3), indicating the version of the response formats (possibly used for later extensions). Table 16 defines the different entries of the status. The type and clear condition fields in the table are abbreviated as follows: Types: * * * * E: Error bit. S: Status bit. R: Detected and set for the actual command response. X: Detected and set during command execution. The host must poll the card by issuing the status command in order to read these bits.
Card Condition: * * * A: According to the card current state. B: Always related to the previous command. Reception of a valid command will clear it (with a delay of one command). C: Clear by read
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MULTIMEDIACARD CONTROLLER
Table 14. Card Status Bits 31 30 Identifier OUT_OF_RANGE ADDRESS_ERROR Type ER ERX Value 0 = No error 1 = Error 0 = No error 1 = Error 0 = No error 1 = Error Description The command's argument was out of the allowed range for this card A misaligned address, which did not match the block length, was used in the command. The transferred block length is not allowed for this card, or the number of transferred bytes does not match the block length. An error in the sequence of erase commands occurred. An invalid selection of erase groups for erase occurred. Attempt to program a write protected block. When set, signals that the card is locked by the host Set when a sequence or password error has been detected in lock/ unlock card command or if there was an attempt to access a locked card The CRC check of the previous command failed. Command not legal for the card state Card initial ECC was applied but failed to correct the data Internal card controller error A general or an unknown error occurred during the operation. The card could not sustain data transfer in stream read mode. The card could not sustain programming in stream write mode. Clear Condition C C
29
BLOCK_LEN_ERROR
ER
C
28 27 26 25 24
ERASE_SEQ_ERROR ERASE_PARA WP_VIOLATION CARD_IS_LOCKED LOCK_UNLOCK_ FAILED
ER EX ERX SX ERX
0 = No error 1 = Error 0 = No error 1 = Error 0 = Not protected 1 = Protected 0 = Card unlocked 1 = Card locked 0 = No error 1 = Error
C C C A C
23 22 21 20 19 18 17
COM_CRC_ERROR ILLEGAL_COMMAND CARD_ECC_FAILED CC_ERROR ERROR UNDERRUN OVERRUN
ER ER EX ERX ERX EX EX
0 = No error 1 = Error 0 = No error 1 = Error 0 = No error 1 = Error 0 = No error 1 = Error 0 = No error 1 = Error 0 = No error 1 = Error 0 = No error 1 = Error
B B C C C C C
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MULTIMEDIACARD CONTROLLER
S3C49DAX
Table 14. Card Status Bits Identifier Type Value Description Clear Condition 16 CID/CSD_ OVERWRITE ERX 0 = No error 1 = Error Card be either one of the following error: - The CID register has been already written and cannot be overwritten. - The read only section of the CSD does not match the card content. - An attempt to reverse the copy (set as original) or permanent WP (unprotected) bits was made. 15 14 WP_ERASE_SKIP CARD_ECC_ DISABLED 13 ERASE_RESET SR SX SX 0 = Not protected 1 = Protected 0 = Enabled 1 = Disabled 0 = Cleared 1 = Set 0 = idle 1 = ready 2 = ident 3 = standby 4 = tran 5 = data 6 = rcv 7 = prg 8 = dis 9-15 = reserved 0 = Not ready 1 = Ready Only partial address space was erased due to existing write protected blocks. The command has been executed without using the internal ECC. An erase sequence was cleared before executing because an out of erase sequence command was received. The state of the card when receiving the command. If the command execution causes a state change, it will be visible to the host in the response to the next command. The four bits are interpreted as a binary coded number between 0 and 15 C A C
C
12:9 CURRENT_STATE
SX
B
8 7:6 5
READY_FOR_DAT A Reserved APP_CMD
SX
Corresponds to buffer empty signaling on the bus
A
SR
0 = Disabled 1 = Enabled
The card will expect ACMD, or indication that the command has been interpreted as ACMD
C
4 3, 2 1, 0
Reserved Reserved for application specific commands Reserved for manufacture test mode
30
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MULTIMEDIACARD CONTROLLER
2. CARD REGISTERS
Within the card interface five registers are defined: OCR, CID, CSD, RCA and DSR. These can be accessed only by corresponding commands (above section). The OCR, CID and CSD registers carry the card/content specific information, while the RCA and DSR registers are configuration registers storing actual configuration parameters. OCR Register (Operation Condition Register) The 32-bit operation conditions register stores the VDD voltage profile of the card. In addition, this register includes a status information bit. This status bit is set if the card power up procedure has been finished. The register is optional and can be read only. The OCR register shall be implemented by the cards, which do not support the full operating voltage range of the MultiMediaCard bus. The operation voltage range of S3F49DAX is 2.7V to 3.6V, and the initial value of OCR is "0x00FF8000". The supported voltage range is coded as shown in Table 15. A voltage range is not supported if the corresponding bit value is set to LOW. As long as the card is busy, the corresponding bit (31) is set to LOW. Table 15. OCR Register Definitions OCR Bit Bit [6:0] Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15
NOTE:
Supply Voltage Range Window Reserved 1.65 - 1.95 2.0 - 2.1 2.1 - 2.2 2.2 - 2.3 2.3 - 2.4 2.4 - 2.5 2.5 - 2.6 2.6 - 2.7 2.7 - 2.8
OCR Bit Bit 16 Bit 17 Bit 18 Bit 19 Bit 20 Bit 21 Bit 22 Bit 23 Bit [30:24] Bit 31
Supply Voltage Range Window 2.8 - 2.9 2.9 - 3.0 3.0 - 3.1 3.1 - 3.2 3.2 - 3.3 3.3 - 3.4 3.4 - 3.5 3.5 - 3.6 Reserved Card power up status bit (busy)
(NOTE)
This bit is set to LOW if the card has not finished the power up routine.
31
MULTIMEDIACARD CONTROLLER
S3C49DAX
CID Register (Card Identification Register) The Card IDentification (CID) register is 128 bits wide. It contains the card identification information used during the card identification phase (MultiMediaCard protocol). Every individual flash or I/O card shall have an unique identification number. Every type of MultiMediaCard ROM cards (defined by content) shall have an unique identification number. The structure of the CID register is defined in the following paragraphs: * MID: An 8 bit binary number that identifies the card manufacturer. The MID number is controlled, defined and allocated to a MultiMediaCard manufacturer by the MMCA. This procedure is established to ensure uniqueness of the CID register. OID: A 16 bit binary number that identifies the card OEM and/or the card contents (when used as a distribution media either on ROM or FLASH cards). The OID number is controlled, defined and allocated to a MultiMediaCard manufacturer by the MMCA. This procedure is established to ensure uniqueness of the CID register. PNM: The product name is a string, 6 ASCII characters long. PRV: The product revision is composed of two Binary Coded Decimal (BCD) digits, four bits each, representing an "n.m" revision number. The "n" is the most significant nibble and "m" is the least significant nibble. As an example, the PRV binary value field for product revision "6.2" will be: 0110 0010 PSN: A 32 bits unsigned binary integer. MDT: The manufacturing date is composed of two hexadecimal digits, four bits each, representing a two digits date code m/y; The "m" field, most significant nibble, is the month code. 1 = January. The "y" field, least significant nibble, is the year code. 0 = 1997. As an example, the binary value of the MDT field for production date "April 2000" will be: 0100 0011 CRC: CRC7 checksum (7 bits). Table 16. CID Register Name Manufacturer ID OEM/Application ID Product Name Product Revision Product Serial Number Manufacturing Date CRC7 Not used, always "1" Field MID OID PNM PRV PSN MDT CRC - Width 8 16 48 8 32 8 7 1 CID-Slice [127:120] [119:104] [103:56] [55:48] [47:16] [15:8] [7:1] [0]
*
* *
* *
*
32
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MULTIMEDIACARD CONTROLLER
CSD Register (Card Specific Data Register) The Card-Specific Data register provides information on how to access the card contents. The CSD defines the data format, error correction type, maximum data access time, data transfer speed, whether the DSR register can be used etc. The programmable part of the register (entries marked by W or E, see below) can be changed by CMD27. The type of the entries in the table below is coded as follows: R = readable, W = writable once, E = erasable (multiple writable). Table 17. The CSD Field Name CSD Structure System Specification Version Reserved Data Read Access Time 1 Data Read Access Timer 2 in CLK cycles Max. Data Transfer Rate Card Command Classes Max. Read Data Block Length Partial Blocks For Read Allowed Write Block Misalignment Read Block Misalignment DSR implemented Reserved Device Size Max. Read Current @ VDD min Max. Read Current @ VDD max Max. Write Current @ VDD min Max. Write Current @ VDD max Device Size Multiplier Erase Sector Size Erase Group Size Write Protect Group Size Write Protect Group Enable Manufacturer Default ECC Write Speed Factor Max. Write Data Block Length Partial Blocks for Write Allowed Reserved C_SIZE VDD_R_CURR_MIN VDD_R_CURR_MAX VDD_W_CURR_MIN VDD_W_CURR_MAX C_SIZE_MULT SECTOR_SIZE ERASE_GRP_SIZE WP_GRP_SIZE WP_GRP_ENABLE DEFAULT_ECC R2W_FACTOR WRITE_BL_LEN WRITE_BL_PARTIAL - TAAC NSAC TRAN_SPEED CCC READ_BL_LEN READ_BL_PARTIAL WRITE_BLK_MISALIGN READ_BLK_MISALIGN DSR_IMP - Field CSD_STRUCTURE SPEC_VER - Width 2 4 2 8 8 8 12 4 1 1 1 1 2 12 3 3 3 3 3 5 5 5 1 2 3 4 1 5 Cell Type R R R R R R R R R R R R R R R R R R R R R R R R R R R R CSD-Slice [127:126] [125:122] [121:120] [119:112] [111:104] [103:96] [95:84] [83:80] [79] [78] [77] [76] [75:74] [73:62] [61:59] [58:56] [55:53] [52:50] [49:47] [46:42] [41:37] [36:32] [31] [30:29] [28:26] [25:22] [21] [20:16]
33
MULTIMEDIACARD CONTROLLER
S3C49DAX
Table 17. The CSD Field (Continuous) Name File Format Group Copy Flag (OTP) Permanent Write Protection Temporary Write Protection File Format ECC Code CRC Not used, always "1" Field FILE_FORMAT_GRP COPY PERM_WRITE_PROTECT TMP_WRITE_PROTECT FILE_FORMAT ECC CRC - Width 1 1 1 1 2 2 7 1 Cell Type R/W R/W R/W R/W R/W R/W/E R/W/E - CSD-Slice [15] [14] [13] [12] [11:10] [9:8] [7:1] [0]
The following sections describe the CSD fields and the relevant data types. If not explicitly defined otherwise, all bitstrings are interpreted as binary coded numbers starting with the left bit first. * CSD_STRUCTURE: Describes the version number of the CSD structure. CSD_STRUCTURE 0 1 2 3 CSD Structure Version CSD version No. 1.0 CSD version No. 1.1 CSD version No. 1.2 Reserved Valid for System Specification Version Version 1.0 - 1.2 Version 1.4 - 2.2 Version 3.1 Reserved
*
SPEC_VER: Defines the MultiMediaCard System Specification version supported by the card. SPEC_VER 0 1 2 3 4-15 Version 1.0 - 1.2 Version 1.4 Version 2.0 - 2.2 Version 3.1 Reserved System Specification Version Number
*
TAAC: Defines the asynchronous part of the data access time. TAAC 2:0 6:3 7 Description Time Unit: 000 = 1nsec 001 = 10nsec 010 = 100nsec 100 = 10usec 101 = 100usec 110 = 1msec 011 = 1usec, 111 = 10msec
Time Value: 0 = Reserved, 1 = 1.0, 2 = 1.2, 3 = 1.3, 4 = 1.5, 5 = 2.0, 6 = 2.5 7 = 3.0, 8 = 3.5, 9 = 4.0, A = 4.5, B = 5.0, C = 5.5, D = 6.0, E = 7.0, F = 8.0 Reserved
34
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MULTIMEDIACARD CONTROLLER
*
NSAC: Defines the typical case for the clock dependent factor of the data access time. The unit for NSAC is 100 clock cycles. Therefore, the maximal value for the clock dependent part of the data access time is 25.5k clock cycles. The total access time NAC is calculated based on TAAC and NSAC. It has to be computed by the host for the actual clock rate. The read access time should be interpreted as a typical delay for the first data bit of a data block or stream. TRAN_SPEED: The following table defines the maximum data transfer rate TRAN_SPEED TRAN_SPEED 2:0 Transfer Rate Unit: 000 = 100Kbit/s 011 = 10Mbit/s 6:3 Description 001 = 1Mbit/s 010 = 10Mbit/s
*
Other = Reserved
Time Value: 0 = Reserved, 1 = 1.0, 2 = 1.2, 3 = 1.3, 4 = 1.5, 5 = 2.0, 6 = 2.5 7 = 3.0, 8 = 3.5, 9 = 4.0, A = 4.5, B = 5.0, C = 5.5, D = 6.0, E = 7.0, F = 8.0
7
Reserved
*
CCC: The MultiMediaCard command set is divided into subsets (command classes). The card command class register CCC defines which command classes are supported by this card. A value of `1' in a CCC bit means that the corresponding command class is supported. Bit Position 0 1 2 3 Description Class 0 Class 1 Class 2 Class 3 Bit Position 4 5 6 7 Description Class 4 Class 5 Class 6 Class 7 Bit Position 8 9 10 11 Description Class 8 Class 9 Class 10 Class 11
*
READ_BL_LEN: The data block length is computed as 2READ_BL_LEN. The block length might therefore be in the range 1,2,4...2048 bytes. Bit Value 0 1 2 3 15:12 Description 20 = 1 byte 21 = 2 bytes 22 = 4 bytes 23 = 8 bytes Reserved Bit Value 4 5 6 7 Description 24 = 16 bytes 25 = 32 bytes 26 = 64 bytes 27 = 128 bytes Bit Value 8 9 10 11 Description 28 = 256 bytes 29 = 512 bytes 210 = 1024 bytes 211 = 2048 bytes
35
MULTIMEDIACARD CONTROLLER
S3C49DAX
*
READ_BL_PARTIAL: Defines whether partial block sizes can be used in block read commands. READ_BL_PARTIAL=0 means that only the READ_BL_LEN block size can be used for block oriented data transfers. READ_BL_PARTIAL=1 means that smaller blocks can be used as well. The minimum block size will be equal to minimum addressable unit (one byte)
*
WRITE_BLK_MISALIGN: Defines if the data block to be written by one command can be spread over more than one physical block of the memory device. The size of the memory block is defined in WRITE_BL_LEN. WRITE_BLK_MISALIGN=0 signals that crossing physical block boundaries is invalid. WRITE_BLK_MISALIGN=1 signals that crossing physical block boundaries is allowed.
*
READ_BLK_MISALIGN: Defines if the data block to be read by one command can be spread over more than one physical block of the memory device. The size of the memory block is defined in READ_BL_LEN. READ_BLK_MISALIGN=0 signals that crossing physical block boundaries is invalid. READ_BLK_MISALIGN=1 signals that crossing physical block boundaries is allowed.
*
DSR_IMP: Defines if the configurable driver stage is integrated on the card. If set, a driver stage register (DSR) must be implemented also. S3F49DAX have no DSR implementation. DSR_IMP=0 no DSR implementation DSR_IMP=1 DSR implementation
*
C-SIZE: This parameter is used to compute the card capacity. The memory capacity of the card is computed from the entries C_SIZE, C_SIZE_MULT and READ_BL_LEN as follows: memory capacity = BLOCKNR * BLOCK_LEN where BLOCKNR = (C_SIZE+1) * MULT MULT = 2C_SIZE_MULT+2 (C_SIZE_MULT < 8) BLOCK_LEN = 2READ_BL_LEN , (READ_BL_LEN < 12) Therefore, the maximal capacity which can be coded is 4096*512*2048 = 4 GBytes. Example: A 4 Mbyte card with BLOCK_LEN = 512 can be coded by C_SIZE_MULT = 0 and C_SIZE = 2047.
*
VDD_R_CURR_MIN, VDD_W_CURR_MIN: The maximum values for read and write currents at the minimal power supply VDD are coded as follows: VDD_R_CURR_MIN VDD_W_CURR_MIN 2:0 000 = 0.5mA, 100 = 25mA, Code for Current Consumption @ VDD 001 = 1mA, 010 = 5mA, 011 = 10mA, 101 = 35mA, 110 = 60mA, 111 = 100mA
36
S3F49DAX
MULTIMEDIACARD CONTROLLER
*
VDD_R_CURR_MAX, VDD_W_CURR_MAX: The maximum values for read and write currents at the maximal power supply VDD coded as follows: VDD_R_CURR_MAX VDD_W_CURR_MAX 2:0 000 = 0.5mA, 100 = 25mA, Code for Current Consumption @ VDD 001 = 1mA, 010 = 5mA, 011 = 10mA, 101 = 35mA, 110 = 60mA, 111 = 100mA
*
C_SIZE_MULT: This parameter is used for coding a factor MULT for computing the total device size (see `C_SIZE'). The fac tor MULT is defined as 2C_SIZE_MULT+2. Bit Value 0 1 2 3 24 = 4 23 = 8 24 = 16 25 = 32 Description Bit Value 4 5 6 7 26 = 64 27 = 128 28 = 256 29 = 512 Description
*
ERASE_GRP_SIZE: The contents of this register is a 5 bit binary coded value, used to calculate the size of the erasable unit of the card. The size of the erase unit (also referred to as erase group) is determined by the ERASE_GRP_SIZE and the ERASE_GRP_MULT entries of the CSD, using the following equation: size of erasable unit = (ERASE_GRP_SIZE + 1) x (ERASE_GRP_MULT + 1) This size is given as minimum number of write blocks that can be erased in a single erase command.
* *
RASE_GRP_MULT: A 5 bit binary coded value used for calculating the size of the erasable unit of the card. P_GRP_SIZE: The size of a write protected group. The contents of this register is a 5 bit binary coded value, defining the number of erase groups which can be write protected. The actual size is computed by increasing this number by one. A value of zero means 1 erase group, 31 means 32 erase groups. P_GRP_ENABLE: A value of `0' means no group write protection possible. EFAULT_ECC: Set by the card manufacturer. It defines the ECC code, which is recommended for use. The field definition is the same as for the ECC field described later.
* *
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MULTIMEDIACARD CONTROLLER
S3C49DAX
*
R2W_FACTOR: Defines the typical block program time as a multiple of the read access time. The following table defines the field format. R2W_FACTOR Value 0 1 2 3 4 5 6, 7 1 2 (write half as fast as read) 4 8 16 32 Reserved Multiple of Read Access Time
* *
WRITE_BL_LEN: Block length for write operations. See READ_BL_LEN for field coding. WRITE_BL_PARTIAL: Defines whether partial block sizes can be used in block write commands. WRITE_BL_PARTIAL='0' means that only the WRITE_BL_LEN block size can be used for block oriented data write. WRITE_BL_PARTIAL='1' means that smaller blocks can be used as well. The minimum block size is one byte.
*
FILE_FORMAT_GRP: Indicates the selected group of file formats. This field is read-only for ROM. The usage of this field is shown in FILE_FORMAT description. COPY: Defines if the contents is original (= `0') or has been copied (='1'). The COPY bit for OTP and MTP devices, sold to end consumers, is set to `1' which identifies the card contents as a copy. The COPY bit is an one time programmable bit. PERM_WRITE_PROTECT: Permanently protects the whole card content against overwriting or erasing (all write and erase commands for this card are permanently disabled). The default value is `0', i.e. not permanently write protected. TMP_WRITE_PROTECT: Temporarily protects the whole card content from being overwritten or erased (all write and erase commands for this card are temporarily disabled). This bit can be set and reset. The default value is `0', i.e. not write protected. CONTENTS_PROT_APP: This field in the CSD indicates whether the content protection application is supported. S3F49DAX cannot support the contents protection application.
*
*
*
*
38
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MULTIMEDIACARD CONTROLLER
*
FILE_FORMAT: Indicates the file format on the card. This field is read-only for ROM. The following formats are defined: FILE_FORMAT_GRP 0 0 0 0 1 FILE_FORMAT 0 1 2 3 0, 1, 2, 3 Type Hard disk-like file system with partition table DOS FAT (floppy-like) with boot sector only (no partition table) Universal File Format Others / Unknown Reserved
A more detailed description is given in MultiMediaCard File System Specification. * ECC: Defines the ECC code that was used for storing data on the card. This field is used by the host (or application) to decode the user data. The following table defines the field format: ECC 0 1 2, 3 ECC_TYPE None (default) BHC (542, 512) Reserved Maximum Number of Correctable Bits Per Block None 3 -
*
CRC: The CRC field carries the check sum for the CSD contents. The checksum has to be recalculated by the host for any CSD modification. The default corresponds to the initial CSD contents.
RCA Register (Relative Card Address Register) The writable 16-bit relative card address register carries the card address assigned by the host during the card identification. This address is used for the addressed host-card communication after the card identification procedure. The default value of the RCA register is 0x0001. The value 0x0000 is reserved to set all cards into the Stand-by State with CMD7. DSR Register (Driver Stage Register) S3F49DAX is not implement
39
MULTIMEDIACARD CONTROLLER
S3C49DAX
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS Symbol VDD VIN IIN TSTG Parameter Supply voltage Input voltage DC input current Storage temperature Ratings -0.3 to 3.8 -0.3 to VDD + 0.3 -10 -40 to 125 Unit V V UA
o
C
RECOMMANDED OPERATING CONDITIONS Symbol VDD TOPR Parameter Supply voltage Operating temperature Ratings 1.65 to 1.95 / 2.7 to 3.6 -25 to 85 Unit V
o
C
40
S3F49DAX
MULTIMEDIACARD CONTROLLER
DC ELECTRICAL CHARACTERISTICS Table 18. DC Electrical Characteristics (V DD = 1.65 V to 1.95 V, 2.7 V to 3.6 V, TA = -25 to 85 oC) Symbol VIH Parameters High level input voltage Conditions VDD = 2.7 V to 3.6 V VDD = 1.65 V to 1.95 V VIL Low level input voltage Min 0.625xVDD 0.7 x VDD VSS - 0.3 VSS - 0.3 IIH IIL High level input current Low level input current Pull-up Resistor: 10K Pull-up Resistor: 60K -10 -1000 -300 -10 VOH High level output voltage IOH = -100 uA VDD = 2.7 V to 3.6 V IOH = -100 uA VDD = 1.65 V to 1.95 V VOL Low level output voltage IOH = 100 uA VDD = 2.7 V to 3.6 V IOH = 100 uA VDD = 1.65 V to 1.95 V ICC ISTOP CIN COUT
NOTE:
Type
Max VDD + 0.3 VDD + 0.3 0.25 x VDD 0.30 x VDD 10 10 10 10
Unit V V V V uA uA uA uA V
0.75 x VDD
VDD - 0.2
V
0.125 x VDD
V
0.2
V
Operating Current Standby Current Input capacitance (NOTE) Output capacitance (NOTE)
Read/Write/Erase
20 100
mA uA pF pF
Any input and bi-directional buffers Any output buffer
4 4
This value excludes package parasitic
41
MULTIMEDIACARD CONTROLLER
S3C49DAX
AC CHARACTERISTICS
Table 19. System Clock Timing Symbol TC Tlpd Thpd Clock cycle time Clock low pulse duration Clock high pulse duration Parameter Min 54 0.4Tc 0.4Tc Typ 55 0.5Tc 0.5Tc Max 63 0.6Tc 0.6Tc Unit ns ns ns
Tlpd
Thpd
Tc
Table 20. POR (Power On Reset) Detection Level Symbol POR Parameter POR detection level Min 1.1 Typ 1.3 Max 1.55 Unit V
42
S3F49DAX
MULTIMEDIACARD CONTROLLER
MECHANICAL DATA
0.10
(4C0 .4 B 00)
9.0 8.75
BSC
A
0.53MAX 0~0.05
0.10 BSC
64-UELP
( (1.10)
0.70-Dp 0.03 MAX) 8
0) .40 C0 (4-
0.08 C 8.75
0.10
9.0
0.10
BSC C
BSC
(1.10) TOP VIEW
0.25REF
0.40
0.10
Pin #1 Index
0.75
0.50BSC BOTTOM VIEW
0.20
+ 0.10 - 0.02
0.10 M C A B
43

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