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| LTC2846 3.3V Software-Selectable Multiprotocol Transceiver with Termination FEATURES s s s DESCRIPTIO s s s s s Software-Selectable Transceiver Supports: RS232, RS449, EIA530, EIA530-A, V.35, V.36, X.21 Operates from Single 3.3V Supply TUV Rheinland of North America Inc. Certified NET1, NET2 and TBR2 Compliant, Report No.: TBR2/050101/02, TBR2/051501/02 1.2MHz Boost Switching Regulator for 3.3V to 5V Conversion On-Chip Cable Termination Complete DTE or DCE Port with LTC2844 or LTC2845 Small Footprint Available in 36-Lead SSOP (0.209 Wide) Package APPLICATIO S s s s The LTC(R)2846 is a 3-driver/3-receiver multiprotocol transceiver with on-chip cable termination. When combined with the LTC2844 or LTC2845, this chip set forms a complete software-selectable DTE or DCE interface port that supports the RS232, RS449, EIA530, EIA530-A, V.35, V.36 and X.21 protocols. All necessary cable termination is provided inside the LTC2846. The LTC2846 has a boost regulator that takes in a 3.3V input and switches at 1.2MHz, allowing the use of tiny, low cost capacitors and inductors 2mm or less in height. The 5V output drives an internal charge pump that requires only five space-saving surface mounted capacitors. The LTC2846 is available in a 36-lead SSOP surface mount package. , LTC and LT are registered trademarks of Linear Technology Corporation. Data Networking CSU and DSU Data Routers TYPICAL APPLICATIO LL CTS DSR Complete DTE or DCE Multiprotocol Serial Interface with DB-25 Connector DCD DTR RTS RXD RXC TXC SCTE TXD LTC2844 D4 R4 R3 R2 R1 D3 D2 D1 R3 R2 LTC2846 D3 R1 D2 D1 T T 18 13 5 22 6 10 8 23 20 19 4 1 7 16 3 9 17 DB-25 CONNECTOR 2846 TA01 U T T T 12 15 11 24 14 2 U U DSR B DSR A (107) LL A (141) CTS B CTS A (106) DTR B DTR A (108) RTS B RTS A (105) SHIELD (101) SG (102) DCD B DCD A (109) TXC B TXC A (114) SCTE B SCTE A (113) TXD B TXD A (103) RXD B RXD A (104) RXC B RXC A (115) sn2846 2846fs 1 LTC2846 ABSOLUTE (Note 1) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW NC PGND VIN SHDN C1- C1 + VCC Voltage.............................................. - 0.3V to 6.5V VIN Voltage .............................................. - 0.3V to 6.5V Input Voltage Transmitters ........................... - 0.3V to (VCC + 0.3V) Receivers ............................................... - 18V to 18V Logic Pins .............................. - 0.3V to (VCC + 0.3V) Output Voltage Transmitters ................. (VEE - 0.3V) to (VDD + 0.3V) Receivers ................................. - 0.3V to (VIN + 0.3V) VEE ........................................................ - 10V to 0.3V VDD ....................................................... - 0.3V to 10V Short-Circuit Duration Transmitter Output ..................................... Indefinite Receiver Output .......................................... Indefinite VEE .................................................................. 30 sec SW Voltage ............................................... - 0.4V to 36V FB Voltage ............................................... - 0.3V to 2.5V Current into FB Pin .............................................. 1mA SHDN Voltage ........................................... - 0.3V to 10V Operating Temperature Range LTC2846C ............................................... 0C to 70C LTC2846I ........................................... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C ORDER PART NUMBER 36 SW 35 FB 34 SGND 33 C2 + 32 C2 - 31 VEE 1 2 3 4 5 6 7 8 9 D1 T T T CHARGE PUMP BOOST SWITCHING REGULATOR LTC2846CG LTC2846IG VDD VCC D1 30 GND 29 D1 A 28 D1 B 27 D2 A 26 D2 B 25 D3/R1 A 24 D3/R1 B D2 10 D3 11 R1 12 R2 13 R3 14 M0 15 M1 16 VIN 17 M2 18 R2 R1 D2 D3 23 R2 A T 22 R2 B 21 R3 A T 20 R3 B 19 DCE/DTE R3 G PACKAGE 36-LEAD PLASTIC SSOP TJMAX = 125C, JA = 90C/W, JC = 35C/W *JA SOLDERED TO A CIRCUIT BOARD IS TYPICALLY 60C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS SYMBOL Supplies ICC VCC Supply Current (DCE Mode, All Digital Pins = GND or VIN) PARAMETER The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V, VIN = 3.3V, VSHDN = VIN, unless otherwise noted. (Notes 2, 3) CONDITIONS RS530, RS530-A, X.21 Modes, No Load RS530, RS530-A, X.21 Modes, Full Load V.35 Mode V.28 Mode, No Load V.28 Mode, Full Load No-Cable Mode RS530, RS530-A, X.21 Modes, Full Load V.35 Mode, Full Load V.28 Mode, Full Load V.11 or V.28 Mode, No Load V.35 Mode V.28 Mode, with Load V.28 Mode, with Load, IDD = 10mA q q q MIN TYP 14 100 126 20 35 300 550 775 200 MAX UNITS mA mA mA mA mA A mW mW mW V V V V sn2846 2846fs q q q q 130 170 75 900 PD Internal Power Dissipation (DCE Mode) V+ Positive Charge Pump Output Voltage 8 7 8 9.3 8.0 8.7 6.5 2 U W U U WW W LTC2846 ELECTRICAL CHARACTERISTICS SYMBOL V- PARAMETER Negative Charge Pump Output Voltage The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V, VIN = 3.3V, VSHDN = VIN, unless otherwise noted. (Notes 2, 3) CONDITIONS V.28 Mode, No Load V.28 Mode, Full Load V.35 Mode RS530, RS530-A, X.21 Modes, Full Load No-Cable Mode/Power-Off to Normal Operation D1, D2, D3, M0, M1, M2, DCE/DTE SHDN D1, D2, D3, M0, M1, M2, DCE/DTE SHDN D1, D2, D3 M0, M1, M2, DCE/DTE = GND M0, M1, M2, DCE/DTE = VIN SHDN = GND SHDN = 3V IO = - 3mA IO = 1.6mA 0V VO VIN M0 = M1 = M2 = VIN, VO = GND M0 = M1 = M2 = VIN, VO = VIN RL = 1.95k (Figure 1) RL = 50 (Figure 1) RL = 50 (Figure 1) RL = 50 (Figure 1) RL = 50 (Figure 1) RL = 50 (Figure 1) VOUT = GND VA and VB 0.25V, Power Off or q q q q q q q q q q q q q MIN - 7.5 - 5.5 - 4.5 TYP - 9.6 - 8.5 - 6.5 - 6.0 500 2 MAX UNITS V V V V kHz ms V V fOSC tr VIH VIL IIN Charge Pump Oscillator Frequency Charge Pump Rise Time Logic Input High Voltage Logic Input Low Voltage Logic Input Current Logic Inputs and Outputs 2.0 2.4 0.8 0.5 - 30 - 75 10 - 120 10 0.1 32 0.4 50 -30 -85 -160 10 5 0.5VODO 2 0.67VODO 0.2 3 0.2 150 1 2 15 15 0 15 40 40 3 3 100 25 65 65 12 V V A A A A A V V mA A A V V V V V V mA A ns ns ns ns ns 16 q q q q q VOH VOL IOSR IOZR V.11 Driver VODO VODL VOD VOC VOC ISS IOZ t r, t f t PLH t PHL t t SKEW Output High Voltage Output Low Voltage Output Short-Circuit Current Three-State Output Current 2.7 3 0.2 Open Circuit Differential Output Voltage Loaded Differential Output Voltage Change in Magnitude of Differential Output Voltage Common Mode Output Voltage Change in Magnitude of Common Mode Output Voltage Short-Circuit Current Output Leakage Current Rise or Fall Time Input to Output Rising Input to Output Falling Input to Output Difference, tPLH - tPHL Output to Output Skew q q q q q No-Cable Mode or Driver Disabled (Figures 2, 13) (Figures 2, 13) (Figures 2, 13) (Figures 2, 13) (Figures 2, 13) sn2846 2846fs 3 LTC2846 ELECTRICAL CHARACTERISTICS SYMBOL VTH VTH RIN t r, t f t PLH t PHL t V.35 Driver VOD VOA, VOB VOC IOH IOL IOZ ROD ROC t r , tf t PLH t PHL t t SKEW VTH VTH RID RIC t r, t f tPLH tPHL t V.28 Driver VO ISS ROZ SR t PLH t PHL Output Voltage Short-Circuit Current Power-Off Resistance Slew Rate Input to Output Input to Output Differential Output Voltage Single-Ended Output Voltage Transmitter Output Offset Transmitter Output High Current Transmitter Output Low Current Transmitter Output Leakage Current Transmitter Differential Mode Impedance Transmitter Common Mode Impedance Rise or Fall Time Input to Output Input to Output Input to Output Difference, tPLH - tPHL Output to Output Skew Differential Receiver Input Threshold Voltage Receiver Input Hysteresis Receiver Differential Mode Impedance Receiver Common Mode Impedance Rise or Fall Time Input to Output Input to Output Input to Output Difference, tPLH - tPHL PARAMETER Input Threshold Voltage Input Hysteresis Input Impedance Rise or Fall Time Input to Output Rising Input to Output Falling Input to Output Difference, tPLH - tPHL V.11 Receiver The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V, VIN = 3.3V, VSHDN = VIN, unless otherwise noted. (Notes 2, 3) CONDITIONS - 7V VCM 7V - 7V VCM 7V -7V VCM 7V (Figure 3) CL = 50pF (Figures 4, 14) CL = 50pF (Figures 4, 14) CL = 50pF (Figures 4, 14) CL = 50pF (Figures 4, 14) Open Circuit, RL = 1.95k (Figure 5) With Load, - 4V VCM 4V (Figure 6) Open Circuit, RL = 1.95k (Figure 5) RL = 50 (Figure 5) VA, VB = 0V VA, VB = 0V VA and VB 0.25V q q q q q q MIN - 0.2 TYP MAX 0.2 UNITS V mV ns 15 100 103 15 50 50 0 4 40 90 90 25 1.2 0.66 1.2 0.6 ns ns ns V V V V mA mA A ns ns ns ns ns q 0.44 q q q q q q 0.55 -9 9 50 135 - 11 11 1 100 150 5 35 35 0 4 - 13 13 100 150 165 65 65 16 - 2V VCM 2V (Figure 7) (Figures 8, 13) (Figures 8, 13) (Figures 8, 13) (Figures 8, 13) (Figures 8, 13) - 2V VCM 2V (Figure 9) - 2V VCM 2V (Figure 9) - 2V VCM 2V - 2V VCM 2V (Figure 10) CL = 50pF (Figures 4, 14) CL = 50pF (Figures 4, 14) CL = 50pF (Figures 4, 14) CL = 50pF (Figures 4, 14) Open Circuit RL = 3k (Figure 11) VOUT = GND - 2V < VO < 2V, Power Off or No-Cable Mode RL = 7k, CL = 0 (Figures 11, 15) RL = 3k, CL = 2500pF (Figures 11, 15) RL = 3k, CL = 2500pF (Figures 11, 15) q q q q q q q q q 15 15 V.35 Receiver - 0.2 15 90 135 103 150 15 50 50 0 4 90 90 25 10 150 300 4 1.5 1.5 30 2.5 2.5 0.2 40 110 165 V mV ns ns ns ns V V mA V/s s s sn2846 2846fs q q q q q q q 5 8.5 4 LTC2846 ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER V.28 Receiver VTHL Input Low Threshold Voltage VTLH Input High Threshold Voltage VTH Receiver Input Hysteresis RIN Receiver Input Impedance t r , tf Rise or Fall Time tPLH Input to Output tPHL Input to Output Boost Switching Regulator (Note 4) VIN Operating Voltage VFB Feedback Voltage IFB FB Pin Bias Current IQ Quiescent Current Quiescent Current in Shutdown VFB(LR) Reference Line Regulation f Switching Frequency DCMAX Maximum Duty Cycle ILIM Switch Current Limit VSAT Switch VCESAT ILEAK Switch Leakage Current The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V, VIN = 3.3V, VSHDN = VIN, unless otherwise noted. (Notes 2, 3) CONDITIONS (Figure 12) (Figure 12) (Figure 12) - 15V VA 15V CL = 50pF (Figures 12, 16) CL = 50pF (Figures 12, 16) CL = 50pF (Figures 12, 16) q q q q q q MIN TYP MAX 0.8 UNITS V V V k ns ns ns V V nA mA A %/V MHz % A mV A 2 0 3 0.05 5 15 60 160 3.3 1.255 120 4.2 0.01 0.01 1.2 90 1.2 350 0.01 0.3 7 300 300 3.6 1.280 360 6 1 0.05 1.6 2 1 q 3 1.230 VFB = 1.255V VSHDN = 2.4V, Not Switching VSHDN = 0V, VIN = 3V 3V VIN 3.6V q q q (Note 5) ISW = 900mA VSW = 5V 0.85 82 1 Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All currents into device pins are positive; all currents out of device are negative. All voltages are referenced to device ground unless otherwise specified. Note 3: All typicals are given for VCC = 5V, VIN = 3.3V, CVCC = CVIN = 10F, CVDD = 1F, CVEE = 3.3F and TA = 25C. Note 4: The Boost Regulator is specified for VIN = 3V unless otherwise noted. Note 5: Current limit guaranteed by design and/or correlation to static test. TYPICAL PERFOR A CE CHARACTERISTICS V.11 Mode ICC vs Data Rate 170 160 150 140 ICC (mA) ICC (mA) 140 ICC (mA) 135 130 125 120 50 45 40 35 30 TA = 25C 130 120 110 100 90 10 100 1000 10000 2846 G04 DATA RATE (kBd) UW V.35 Mode ICC vs Data Rate 150 145 60 V.28 Mode ICC vs Data Rate TA = 25C TA = 25C 55 10 100 1000 DATA RATE (kBd) 10000 2846 G05 10 20 40 DATA RATE (kBd) 60 80 100 2846 G06 sn2846 2846fs 5 LTC2846 TYPICAL PERFOR A CE CHARACTERISTICS V.11 Mode ICC vs Temperature 110 105 100 ICC (mA) ICC (mA) 95 90 85 80 -40 -20 125.5 125.0 124.5 124.0 123.5 ICC (mA) 40 20 0 60 TEMPERATURE (C) 80 100 40 20 60 0 TEMPERATURE (C) Boost Switching Regulator SHDN Pin Current vs Voltage 40 35 1.4 1.2 CURRENT LIMIT (A) SHDN PIN CURRENT (A) 30 25 TA = 25C 20 15 10 5 0 0 1 4 3 SHDN PIN VOLTAGE (V) 2 5 6 2846 G10 FREQUENCY (MHz) TA = 100C EFFICIENCY (%) 6 UW 80 2846 G07 V.35 Mode ICC vs Temperature 128.0 127.5 127.0 126.5 126.0 V.28 Mode ICC vs Temperature 37.5 37.0 36.5 36.0 35.5 35.0 34.5 34.0 33.5 -40 - 20 0 60 40 20 TEMPERATURE (C) 80 100 3846 G09 100 123.0 -40 -20 2846 G08 Boost Switching Regulator Current Limit vs Duty Cycle 1.30 TA = 25C 1.25 Boost Switching Regulator Oscillator Frequency vs Temperature 1.0 0.8 0.6 0.4 0.2 0 10 20 30 50 40 60 DUTY CYCLE (%) 70 80 1.20 1.15 1.10 1.05 -40 -20 40 20 0 60 TEMPERATURE (C) 80 100 2846 G11 2846 G12 Efficiency vs Load Current 90 85 80 75 70 65 60 55 50 0 50 100 150 200 250 300 350 400 450 500 LOAD CURRENT (mA) 2846 TA01b TA = 25C VIN = 3.3V sn2846 2846fs LTC2846 PI FU CTIO S NC (Pin 1): No Connect. PGND (Pin 2): Boost Switching Regulator Power Ground. Tie PGND to SGND. VIN (Pin 3): Input Supply Pin. Input supply to boost switching regulator. 3V VIN 3.6V. Bypass with a 10F capacitor to ground. SHDN (Pin 4): Boost Switching Regulator Shutdown Pin. Tie to 2.4V or more to enable regulator. Ground to shut down. C1 - (Pin 5): Capacitor C1 Negative Terminal. Connect a 1F capacitor between C1+ and C1-. C1 + (Pin 6): Capacitor C1 Positive Terminal. Connect a 1F capacitor between C1 + and C1 -. VDD (Pin 7): Generated Positive Supply Voltage for V.28. Connect a 1F capacitor to ground. VCC (Pin 8): Input Supply Pin. Input supply to transceiver. 4.75V VCC 5.25V. Connect to output of switching regulator. D1 (Pin 9): TTL Level Driver 1 Input. D2 (Pin 10): TTL Level Driver 2 Input. D3 (Pin 11): TTL Level Driver 3 Input. R1 (Pin 12): CMOS Level Receiver 1 Output with Pull-Up to VIN when Three-Stated. R2 (Pin 13): CMOS Level Receiver 2 Output with Pull-Up to VIN when Three-Stated. R3 (Pin 14): CMOS Level Receiver 3 Output with Pull-Up to VIN when Three-Stated. M0 (Pin 15): TTL Level Mode Select Input 0 with Pull-Up to VIN. See Table 1. M1 (Pin 16): TTL Level Mode Select Input 1 with Pull-Up to VIN. See Table 1. VIN (Pin 17): Input Supply Pin. Input supply to transceiver. 3V VIN 3.6V. Connect to Pin 3. M2 (Pin 18): TTL Level Mode Select Input 2 with Pull-Up to VIN. See Table 1. DCE/DTE (Pin 19): TTL Level Mode Select Input with Pull-Up to VIN. See Table 1. R3 B (Pin 20): Receiver 3 Noninverting Input. R3 A (Pin 21): Receiver 3 Inverting Input. R2 B (Pin 22): Receiver 2 Noninverting Input. R2 A (Pin 23): Receiver 2 Inverting Input. D3/R1 B (Pin 24): Receiver 1 Noninverting Input and Driver 3 Noninverting Output. D3/R1 A (Pin 25): Receiver 1 Inverting Input and Driver 3 Inverting Output. D2 B (Pin 26): Driver 2 Noninverting Output. D2 A (Pin 27): Driver 2 Inverting Output. D1 B (Pin 28): Driver 1 Noninverting Output. D1 A (Pin 29): Driver 1 Inverting Output. GND (Pin 30): Transceiver Ground. VEE (Pin 31): Generated Negative Supply Voltage. Connect a 3.3F capacitor to GND. C2 - (Pin 32): Capacitor C2 Negative Terminal. Connect a 1F capacitor between C2 + and C2 -. C2 + (Pin 33): Capacitor C2 Positive Terminal. Connect a 1F capacitor between C2 + and C2 - . SGND (Pin 34): Boost Switching Regulator Signal Ground. Tie PGND to SGND. FB (Pin 35): Boost Switching Regulator Feedback Pin. Reference voltage is 1.255V. Connect resistive divider tap here. Minimize trace area at FB. SW (Pin 36): Boost Switching Regulator Switch Pin. Connect inductor/diode here. Minimize trace area at this pin to reduce EMI. U U U sn2846 2846fs 7 LTC2846 BLOCK DIAGRA PGND VIN SHDN DCE/DTE 19 10k R1 12 R1 20k 8 W BOOST SWITCHING REGULATOR 2 3 4 GND VIN SW FB 36 SW 35 FB 34 SGND SHDN GND CHARGE PUMP C1- C1+ VDD 5 6 7 C1- C1+ VDD C2+ C2- VEE 33 C2+ 32 C2- 31 VEE VCC 8 50 S1 D1 9 D1 50 28 D1B 27 D2A 50 S1 D2 10 D2 50 26 D2B D3 11 D3 10k 20k 6k S3 S2 51.5 S1 125 51.5 24 D3/R1 B 23 R2A 20k 10k R2 13 R2 10k 20k 21 R3A 20k 10k R3 14 VIN 17 M0 15 M1 16 M2 18 MODE SELECTION LOGIC 20k R3 10k S3 S2 125 51.5 20 R3B 2846 BD VCC GND 30 GND 29 D1A S2 125 S2 125 25 D3/R1 A 6k 51.5 S3 S2 125 51.5 22 R2B 6k 51.5 sn2846 2846fs LTC2846 TEST CIRCUITS D B A VOD RL 2846 F01 RL D VOC B A RL 100 CL 100pF CL 100pF 2846 F02 Figure 1. V.11 Driver DC Test Circuit IB B R IA VCM = 7V Figure 2. V.11 Driver AC Test Circuit B A R CL 2846 F04 + - A 2(VB - VA) RIN = IB - IA 2846 F03 Figure 3. Input Impedance Test Circuit VOB VOB Figure 4. V.11, V.35 Receiver AC Test Circuit 125 50 VOD 50 RL 125 VOC 50 50 125 VCM 125 50 RL 50 50 50 + - 2846 F07 VCM = 2V 2846 F05 2846 F06 VOA VOA Figure 5. V.35 Driver Open-Circuit Test Figure 6. V.35 Driver Test Circuit Figure 7. V.35 Driver Common Mode Impedance Test Circuit 51.5 125 50 50 125 125 50 50 VTH VCM + - + - 2846 F09 VCM = 2V + - 51.5 2846 F08 2846 F10 Figure 8. V.35 Driver AC Test Circuit Figure 9. V.35 Receiver DC Test Circuit Figure 10. Receiver Common Mode Impedance Test Circuit R CL 2846 F12 D A CL 2846 F11 A RL VA Figure 11. V.28 Driver Test Circuit Figure 12. V.28 Receiver Test Circuit sn2846 2846fs 9 LTC2846 ODE SELECTIO Table 1 Mode Name (Note 1) (Note 1) M2 M1 M0 DCE/ D1,2 D3 DTE A Not Used (Default V.11) 0 RS530A RS530 X.21 V.35 RS449/V.36 V.28/RS232 No Cable 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TTL TTL TTL TTL TTL TTL TTL X Not Used (Default V.11) 0 RS530A RS530 X.21 V.35 RS449/V.36 V.28/RS232 No Cable 0 0 0 1 1 1 1 TTL TTL V.11 V.11 V.11 V.11 V.11 V.11 30k 30k V.11 V.11 V.11 V.11 TTL TTL V.11 V.11 V.11 V.11 V.11 V.11 30k 30k V.11 V.11 V.11 V.11 TTL TTL V.11 V.11 V.11 V.11 V.11 V.11 30k 30k V.11 V.11 V.11 V.11 TTL TTL V.11 V.11 V.11 V.11 V.11 V.11 30k 30k V.11 V.11 V.11 V.11 TTL TTL V.35 V.35 V.35 V.35 V.35 V.35 30k 30k V.35 V.35 V.35 V.35 TTL TTL V.11 V.11 V.11 V.11 V.11 V.11 30k 30k V.11 V.11 V.11 V.11 TTL TTL V.28 X X Z Z Z V.28 Z Z Z V.28 Z Z Z 30k 30k V.28 30k V.28 30k 30k 30k 30k 30k 30k 30k Note 1: Driver inputs are TTL level compatible. Note 2: Unused receiver inputs are terminated with 30k to ground. In addition, R2 and R3 are always terminated by a 103 differential impedence (see Block Diagram on page 8). Note 3: Receiver Outputs are CMOS level compatible and have a weak pull up to VIN when Z. SWITCHI G TI E WAVEFOR S 3V D 0V VO B-A -VO A VO B t SKEW t SKEW 2846 F13 1.5V t PLH 50% tr 90% 10% 1/2 VO Figure 13. V.11, V.35 Driver Propagation Delays VOD2 B-A -VOD2 VOH R VOL 0V t PLH 1.65V OUTPUT f = 1MHz : t r 10ns : t f 10ns INPUT 0V t PHL 1.65V 2846 F14 Figure 14. V.11, V.35 Receiver Propagation Delays sn2846 2846fs 10 W U D1 B A D2 B A Z Z Z Z Z Z Z Z D3 B Z Z Z Z Z Z Z Z A R1 (Note 2) W U W R2 (Note 2) R3 (Note 2) R1 (Note 3) R2,R3 (Note 3) VDD (Note 4) VEE (Note 5) B A B A B CMOS CMOS CMOS CMOS CMOS CMOS CMOS Z CMOS CMOS CMOS CMOS CMOS CMOS CMOS Z 9.3V 9.3V 9.3V 9.3V 8V 9.3V 8.7V 4.7V 9.3V 9.3V 9.3V 9.3V 8V 9.3V 8.7V 4.7V -6V -6V -6V -6V -6.5V -6V -8.5V 0.3V -6V -6V -6V -6V -6.5V -6V -8.5V 0.3V X X X X X X X X V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.35 V.35 V.35 V.35 V.11 V.11 V.11 V.11 V.28 Z Z Z V.28 Z Z Z V.11 V.11 V.11 V.11 V.11 V.11 CMOS V.11 V.11 V.11 V.11 V.11 V.11 CMOS V.11 V.11 V.11 V.11 V.11 V.11 CMOS V.11 V.11 V.11 V.11 V.11 V.11 CMOS V.35 V.35 V.35 V.35 V.35 V.35 CMOS V.11 V.11 V.11 V.11 V.11 V.11 CMOS V.28 30k V.28 30k V.28 30k CMOS 30k 30k 30k 30k 30k 30k Z Z Z Z Z Z Z Z Z Note 4: VDD values shown are typical values for VCC = 5V, VIN = 3.3V and TA = 25C with LTC2846 under full load for each mode. Note 5: VEE values shown are typical values for VCC = 5V, VIN = 3.3V and TA = 25C with LTC2846 under full load for each mode. f = 1MHz : t r 10ns : t f 10ns 1.5V t PHL 90% tf 50% 10% LTC2846 SWITCHI G TI E WAVEFOR S 3V D 0V VO A -VO tf 1.5V t PHL 3V 0V SR = 6V tf -3V 1.5V t PLH 0V -3V tr 3V SR = 6V tr 2846 F15 Figure 15. V.28 Driver Propagation Delays VIH A VIL VOH R VOL 1.5V t PHL 1.65V 1.5V t PLH 1.65V 2846 F16 Figure 16. V.28 Receiver Propagation Delays APPLICATIO S I FOR ATIO Overview The LTC2846 consists of a boost switching regulator, a charge pump and a 3-driver/3-receiver transceiver. The boost switching regulator generates a 5V VCC from the 3.3V input at VIN to power the charge pump and transceiver. The charge pump generates the VDD and VEE supplies. The LTC2846's VCC, VDD and VEE supplies can be used to power a companion chip like the LTC2844 or LTC2845. The receiver outputs are driven between 0V and VIN to interface with 3.3V logic. The LTC2846 and LTC2844 form a complete softwareselectable DTE or DCE interface port that supports the RS232, RS449, EIA530, EIA530-A, V.35, V.36 and X.21 protocols. Cable termination is provided on-chip, eliminating the need for discrete termination designs. A complete DCE-to-DTE interface operating in EIA530 mode is shown in Figure 17. The LTC2846 half of each port is used to generate and appropriately terminate the clock and data signals. The LTC2844 is used to generate the control signals along with LL (Local Loopback). W U W UU W U Mode Selection The interface protocol is selected using the mode select pins M0, M1 and M2 (see Table 1). For example, if the port is configured as a V.35 interface, the mode selection pins should be M2 = 1, M1 = 0, M0 = 0. For the control signals, the drivers and receivers will operate in V.28 (RS232) electrical mode. For the clock and data signals, the drivers and receivers will operate in V.35 electrical mode. The DCE/DTE pin will configure the port for DCE mode when high, and DTE when low. The interface protocol may be selected simply by plugging the appropriate interface cable into the connector. The mode pins are routed to the connector and are left unconnected (1) or wired to ground (0) in the cable as shown in Figure 18. The internal pull-up current sources will ensure a binary 1 when a pin is left unconnected. The mode selection may also be accomplished by using jumpers to connect the mode pins to ground or VIN. sn2846 2846fs 11 LTC2846 APPLICATIO S I FOR ATIO DTE SERIAL CONTROLLER TXD D1 LTC2846 SCTE D2 D3 TXC R1 103 RXC R2 103 RXD R3 103 LTC2844 RTS D1 RTS DTR D2 D3 DCD R1 DSR R2 CTS R3 LL D4 R4 Figure 17. Complete Multiprotocol Interface in EIA530 Mode When the cable is removed, leaving all mode pins unconnected, the LTC2846/LTC2844 will enter no-cable mode. In this mode the LTC2846/LTC2844 supply current drops to less than 900A and the LTC2846/LTC2844 driver outputs are forced into a high impedance state. At the same time, the R2 and R3 receivers of the LTC2846 are differentially terminated with 103 and the other receivers on 12 U DCE LTC2846 TXD 103 R3 SERIAL CONTROLLER TXD SCTE 103 R2 SCTE R1 TXC D3 TXC RXC D2 RXC RXD D1 RXD LTC2844 R3 RTS DTR R2 DTR R1 DCD D3 DCD DSR D2 DSR CTS LL R4 D4 2846 F17 W UU D1 CTS LL the LTC2846 and LTC2844 are terminated with 30k to ground. Cable Termination Traditional implementations used expensive relays to switch resistors or required the user to change termination modules every time a new interface standard was sn2846 2846fs LTC2846 APPLICATIO S I FOR ATIO (DATA) M0 LTC2846 M1 M2 DCE/DTE 15 16 18 19 DCE/DTE M2 LTC2844 M1 M0 (DATA) 14 13 12 11 2846 F18 Figure 18. Single Port DCE V.35 Mode Selection in the Cable selected. Switching the terminations with FETs is difficult because the FETs must remain off when the signal voltage is beyond the supply voltage. Alternatively, custom cables may contain termination in the cable head or route signals to various terminations on the board. The LTC2846/LTC2844 chip set solves the cable termination switching problem by automatically providing the appropriate termination and switching on-chip for the V.10 (RS423), V.11 (RS422), V.28 (RS232) and V.35 electrical protocols. V.10 (RS423) Interface All V.10 drivers and receivers necessary for the RS449, EIA530, EIA530-A, V.36 and X.21 protocols are implemented on the LTC2844 or LTC2845. A typical V.10 unbalanced interface is shown in Figure 19. A V.10 single-ended generator with output A and ground C is connected to a differential receiver with input A' connected to A, and ground C' connected via the signal return to ground C. Usually, no cable termination is required for V.10 interfaces, but the receiver inputs must be compliant with the impedance curve shown in Figure 20. The V.10 receiver configuration in the LTC2844 and LTC2845 is shown in Figure 21. In V.10 mode, switch S3 inside the LTC2844 and LTC2845 is turned off. The noninverting input is disconnected inside the LTC2844 U CONNECTOR NC NC CABLE GENERATOR BALANCED INTERCONNECTING CABLE LOAD CABLE TERMINATION A A' RECEIVER C C' 2846 F19 W UU Figure 19. Typical V.10 Interface IZ 3.25mA -10V -3V VZ 3V 10V -3.25mA 2846 F20 Figure 20. V.10 Receiver Input Impedance sn2846 2846fs 13 LTC2846 APPLICATIO S I FOR ATIO A' A R8 6k S3 R5 20k R6 10k RECEIVER LTC2844 B' C' B GND R4 20k R7 10k 2846 F21 Figure 21. V.10 Receiver Configuration BALANCED INTERCONNECTING CABLE GENERATOR LOAD CABLE TERMINATION RECEIVER A A' 100 MIN B C B' C' Figure 22. Typical V.11 Interface and LTC2845 receivers and connected to ground. The cable termination is then the 30k input impedance to ground of the LTC2844 and LTC2845 V.10 receiver. V.11 (RS422) Interface A typical V.11 balanced interface is shown in Figure 22. A V.11 differential generator with outputs A and B and ground C is connected to a differential receiver with input A' connected to A, input B' connected to B, and ground C' connected via the signal return to ground C. The V.11 interface has a differential termination at the receiver end that has a minimum value of 100. The termination resistor is optional in the V.11 specification, but for the high speed clock and data lines, the termination is essential to prevent reflections from corrupting the data. The receiver inputs must also be compliant with the impedance curve shown in Figure 20. In V.11 mode, all switches are off except S1 of the LTC2846's receivers which connects a 103 differential there is no switch S1 in receivers R2 and R3. However, for simplicity, all termination networks on the LTC2846 can be treated identically if it is assumed that an S1 switch exists and is always closed on the R2 and R3 receivers. 1Actually, 14 U A' R1 51.5 S1 S2 R2 51.5 R8 6k S3 R5 20k R6 10k R3 124 RECEIVER LTC2846 B' C' R4 20k R7 10k GND 2846 F23 W UU Figure 23. V.11 Receiver Configuration termination impedance to the cable as shown in Figure 231. The LTC2844 and LTC2845 only handle control signals, so no termination other than their V.11 receivers' 30k input impedance is necessary. V.28 (RS232) Interface A typical V.28 unbalanced interface is shown in Figure 24. A V.28 single-ended generator with output A and ground C is connected to a single-ended receiver with input A' connected to A and ground C' connected via the signal return to ground C. GENERATOR BALANCED INTERCONNECTING CABLE LOAD CABLE TERMINATION A A' RECEIVER 2846 F22 C C' 2846 F24 Figure 24. Typical V.28 Interface A' R1 51.5 S1 S2 R2 51.5 R8 6k S3 R5 20k R6 10k RECEIVER LTC2846 R3 124 B' R4 20k R7 10k C' GND 2846 F25 Figure 25. V.28 Receiver Configuration sn2846 2846fs LTC2846 APPLICATIO S I FOR ATIO In V.28 mode, S3 is closed inside the LTC2846/LTC2844 which connects a 6k (R8) impedance to ground in parallel with 20k (R5) plus 10k (R6) for a combined impedance of 5k as shown in Figure 25. Proper termination is only provided when the B input of the receivers is floating, since S1 of the LTC2846's R2 and R3 receivers remains on in V.28 mode1. The noninverting input is disconnected inside the LTC2846/LTC2844 receiver and connected to a TTL level reference voltage to give a 1.4V receiver trip point. V.35 Interface A typical V.35 balanced interface is shown in Figure 26. A V.35 differential generator with outputs A and B and ground C is connected to a differential receiver with input A' connected to A, input B' connected to B, and ground C' connected via the signal return to ground C. The V.35 interface requires a T or delta network termination at the receiver end and the generator end. The receiver differential impedance measured at the connector must be GENERATOR BALANCED INTERCONNECTING CABLE LOAD CABLE TERMINATION A 50 A' 50 RECEIVER 125 125 50 B C B' C' 50 Figure 26. Typical V.35 Interface A' R1 51.5 S1 S2 R2 51.5 R8 6k S3 R5 20k R6 10k R3 124 RECEIVER LTC2846 B' 5V 2846 F27 8 C5 10F VCC GND 30 C' GND Figure 27. V.35 Receiver Configuration Figure 28. Charge Pump sn2846 2846fs + R4 20k R7 10k U 100 10, and the impedance between shorted terminals (A' and B') and ground (C') must be 150 15. In V.35 mode, both switches S1 and S2 inside the LTC2846 are on, connecting a T network impedance as shown in Figure 27. The 30k input impedance of the receiver is placed in parallel with the T network termination, but does not affect the overall input impedance significantly. The generator differential impedance must be 50 to 150 and the impedance between shorted terminals (A and B) and ground (C) must be 150 15. No-Cable Mode The no-cable mode (M0 = M1 = M2 = 1) is intended for the case when the cable is disconnected from the connector. The charge pump, bias circuitry, drivers and receivers are turned off, the driver outputs are forced into a high impedance state, and the VCC supply current to the transceiver drops to less than 300A while its VIN supply current drops to less than 10A. Note that the LTC2846's R2 and R3 receivers continue to be terminated by a 103 differential impedance. Charge Pump The LTC2846 uses an internal capacitive charge pump to generate VDD and VEE as shown in Figure 28. A voltage doubler generates about 8V on VDD and a voltage inverter generates about - 7.5V on VEE. Three 1F surface mounted tantalum or ceramic capacitors are required for C1, C2 and C3. The VEE capacitor C4 should be a minimum of 3.3F. All capacitors are 16V and should be placed as close as possible to the LTC2846 to reduce EMI. 2846 F26 W UU 7 C3 1F 6 C1 1F 5 VDD C1+ LTC2846 C1- C2 + C2 - VEE 33 32 31 C4 3.3F C2 1F 2846 F28 15 LTC2846 APPLICATIO S I FOR ATIO Switching Regulator The circuit as shown in Figure 29 can provide up to 480mA at 5V to drive the LTC2846's transceiver as well as its companion chip in the DTE-DCE interface. In its shut down mode with the SHDN pin at 0V, the boost switching regulator draws less than 10A. Ferrite core inductors should be used to obtain the best efficiency, as core losses at 1.2MHz are much lower for ferrite cores than for cheaper powdered-iron types. Choose an inductor that can handle at least 1A without saturating, and ensure that the inductor has a low DCR (copper wire resistance) to minimize I2R power losses. Use low ESR capacitors for the output to minimize output ripple voltage. Multilayer ceramic capacitors are an excellent choice, as they have extremely low ESR and are available in very small packages. Ceramic capacitors also make a good choice for the input decoupling capacitor, and should be placed as close as possible to the switching regulator. Solid tantalum or OS-CON capacitors can be used but they will occupy more board area than a ceramic and will have a higher ESR. A Schottky diode is recommended for use with the switching regulator. The ON Semiconductor MBR0520 is a very good choice. To set the output voltage, select the values of R1 and R2 according to the following equation. R1 = R2[(5V/1.255V) - 1] A good value for R2 is 4.3k which sets the current in the resistor divider chain to 1.255V/4.3k = 292A. VIN 3.3V C6 10F L1 5.6H 3 VIN 36 SW R1 13k C5 10F R2 4.3k D1 VCC 5V 480mA + SHDN BOOST SWITCHING REGULATOR 35 4 SHDN FB GND 2, 34 C5,C6: TAIYO YUDEN X5R JMK316BJ106ML D1: ON SEMICONDUCTOR MBR0520 L1: SUMIDA CR43-5R6 Figure 29. Boost Switching Regulator 16 U The switching regulator has a switch current limit of 1A. This current limit protects the switch as well as the external components connected to the switching regulator. The high speed operation of the boost switching regulator demands careful attention to board layout. Figure 30 shows the recommended component placement. Receiver Fail-Safe All LTC2846/LTC2844 receivers feature fail-safe operation in all modes. If the receiver inputs are left floating or are shorted together by a termination resistor, the receiver output will always be forced to a logic high. DTE vs DCE Operation The DCE/DTE pin acts as an enable for Driver 3/Receiver 1 in the LTC2846, and Driver 3/Receiver 1 and Receiver 4/ Driver 4 in the LTC2844. The LTC2846/LTC2844 can be configured for either DTE or DCE operation in one of two ways: a dedicated DTE or DCE port with a connector of appropriate gender or a port with one connector that can be configured for DTE or DCE operation by rerouting the signals to the LTC2846/LTC2844 using a dedicated DTE cable or dedicated DCE cable. A dedicated DTE port using a DB-25 male connector is shown in Figure 31. The interface mode is selected by logic outputs from the controller or from jumpers to either VIN or GND on the mode select pins. A dedicated DCE port using a DB-25 female connector is shown in Figure 32. GND VCC W UU + VIN C5 L1 C6 R1 D1 R2 SHUTDOWN 2846 F30 2846 F29 Figure 30. Suggested Layout sn2846 2846fs LTC2846 TYPICAL APPLICATIO S A port with one DB-25 connector, that can be configured for either DTE or DCE operation is shown in Figure 33. The configuration requires separate cables for proper signal routing in DTE or DCE operation. For example, in DTE mode, the TXD signal is routed to Pins 2 and 14 via the LTC2846's Driver 1. In DCE mode, Driver 1 now routes the RXD signal to Pins 2 and 14. Multiprotocol Interface with RL, LL, TM and a DB-25 Connector If the RL, LL and TM signals are implemented, there are not enough drivers and receivers available in the LTC2846/ LTC2844. In Figure 34, the required control signals are handled by the LTC2845. The LTC2845 has an additional single-ended driver/receiver pair that can handle two more optional control signals such as TM and RL. Cable-Selectable Multiprotocol Interface A cable-selectable multiprotocol DTE/DCE interface is shown in Figure 35. The select lines M0, M1 and DCE/DTE are brought out to the connector. The mode is selected by the cable by wiring M0 (connector Pin 18) and M1 (connector Pin 21) and DCE/DTE (connector Pin 25) to ground (connector Pin 7) or letting them float. If M0, M1 or DCE/DTE is floating, internal pull-up current sources will pull the signals to VIN. The select bit M2 is floating, and therefore, internally pulled high. When the cable is pulled out, the interface will go into the no-cable mode. Power Dissipation Calculations The LTC2846 takes in a 3.3V supply and produces a 5V VCC with an internal switcher at approximately 80% efficiency. VDD and VEE are in turn produced from VCC with an internal charge pump at approximately 80% and 70% efficiency respectively. Current drawn internally from VDD or VEE translates directly into a higher ICC. The LTC2846 dissipates power according to the equation: PDISS(2846) = 125% * (VCC * ICC) - ND * PRT + NR * PRT (1) PRT refers to the power dissipated by each driver in a receiver termination on the far end of the cable while ND is the number of drivers. Conversely, current from the far end drivers dissipate power NR * PRT in the internal receiver termination where NR is the number of receivers. LTC2846 Power Dissipation Consider an LTC2846 in X.21, DCE mode (three V.11 drivers and two V.11 receivers). From the Electrical Characteristics Table, ICC at no load = 14mA, ICC at full load = 100mA. Each receiver termination is 100 (RRT) and current going into each receiver termination = (100mA - 14mA)/3 = 28.7mA (IRT). PRT = (IRT)2 * RRT (2) From Equation (2), PRT = 82.4mW and from Equation (1), DC power dissipation PDISS(2846) = 125% * (5V * 100mA) - 3 * 82.4mW + 2 * 82.4mW = 543mW. Consider the above example running at a baud rate of 10MBd. From the Typical Characteristic for "V.11 Mode ICC vs Data Rate," the ICC at 10MBd is 160mA. ICC increases with baud rate due to driver transient dissipation. From Equation (1), AC power dissipation PDISS(2846) = 125% * (5V * 160mA) -3 * 82.4mW + 2 * 82.4mW = 918mW. LTC2845 Power Dissipation If a LTC2845 is used to form a complete DCE port with the LTC2846, it will be running in the X.21 mode (three V.11 drivers and two V.10 drivers, two V.11 receivers and two V.10 receivers, all with internal 30k termination). In addition to VCC, it uses the VDD and VEE outputs from the LTC2846. Negligible power is dissipated in the large internal receiver termination of the LTC2845 so the NR * PRT term of Equation (1) can be omitted. Thus Equation (1) is modified as follows: PDISS(2845) = (VCC * ICC) + (VDD * IDD) U sn2846 2846fs 17 LTC2846 TYPICAL APPLICATIO S + (VEE * IEE) - ND * PRT (3) 79mW and V.10 PRT = 49.6mW. From Equation (3), PDISS(2845) = 5V * (110mA - 23mA) + (8V * 0.3mA) + 5.5V * 23mA - 3 * 79mW - 2 * 49.6mW = 228mW. Since the LTC2845 runs slow control signals, the AC power dissipation can be assumed to be equal to the DC power dissipation. The extra power dissipated in the LTC2846 due to LTC2845 is given by Equation(4), PDISS1(2846) = 25% * (5V * 87mA) + 56% * (8V * 0.3mA) + 79% * (5.5V * 23mA) = 210mW. So for an X.21 DCE port running at 10MBd, the LTC2846 dissipates approximately 918mW + 210mW = 1128mW while the LTC2845 dissipates 228mW. Compliance Testing The LTC2846/LTC2844 and LTC2846/LTC2845 chipsets have been tested by TUV Rheinland of North America Inc. and passed the NET1, NET2 and TBR2 requirements. Copies of the test reports are available from LTC or TUV Rheinland of North America Inc. The title of the reports are Test Report No.: TBR2/051501/02 and TBR2/050101/02 The address of TUV Rheinland of North America Inc. is: TUV Rheinland of North America Inc. 1775, Old Highway 8 NW, Suite 107 St. Paul, MN 55112 Tel. (651) 639-0775 Fax (651) 639-0873 Since power is drawn from the supplies of the LTC2846 (VCC, VDD and VEE) at less than 100% efficiency, the LTC2846 dissipates extra power to source PDISS(2845) and PRT : PDISS1(2846) = 125% * (VCC * ICC) + 125% * 125% * (VDD * IDD) + 125% * 143% * (VEE * IEE) - PDISS(2845) - ND * PRT = 25% * (VCC * ICC) + 56% * (VDD * IDD) + 79% * (VEE * IEE) (4) From the LTC2845 Electrical Characteristics Table, for VCC = 5V, VDD = 8V and VEE = - 5.5V: ICC at no load ICC at full load with all drivers high IEE at no load IEE at full load with both V.10 drivers low IDD at no load IDD at full load 2.7mA 110mA 2mA 23mA 0.3mA 0.3mA The V.11 drivers are driven between VCC and GND while the V.10 drivers are driven between VCC and VEE. Assume that the V.11 driver outputs are high and V.10 driver outputs low. Current going into each 100 V.11 receiver termination = (110mA - 2.7mA) - 23mA/3 = 28.1mA. Current going into each 450 V.10 receiver termination = 23mA - 2mA/2 = 10.5mA. From Equation (2), V.11 PRT = 18 U sn2846 2846fs LTC2846 TYPICAL APPLICATIO S L1 5.6H VIN 3.3V C6 10F SHDN 3 4 7 C3 1F VCC 5V 5 C1 1F 6 8 LTC2846 TXD 9 D1 T CHARGE PUMP BOOST SWITCHING REGULATOR 36 35 33 32 31 30 C4 3.3F C2 1F D1 MBR0520 R1 13k R2 4.3k C5 10F VCC 5V 29 28 27 SCTE 10 D2 T 26 11 D3 12 T 25 TXC R1 24 23 RXC 13 R2 T 22 21 RXD 14 15 16 18 19 M0 M1 M2 DCE/DTE 17 VIN 3.3V 7 1 R3 T 20 15 12 17 9 3 16 TXC A (114) TXC B RXC A (115) RXC B RXD A (104) RXD B SG SHIELD C7 1F C8 1F VCC 1 VCC 2 VDD 3 D1 VEE GND 28 27 26 C9 1F 4 19 20 23 RTS 25 24 DTR 4 D2 23 5 D3 LTC2844 22 21 20 R2 19 18 R3 17 16 8 10 6 22 5 13 18 DCD 6 7 R1 DSR CTS 8 10 9 LL R4 D4 M0 M1 M2 DCE/DTE VIN M0 M1 M2 11 12 13 14 15 C10 1F Figure 31. Controller-Selectable Multiprotocol DTE Port with DB-25 Connector sn2846 2846fs + U 2 14 24 11 TXD A (103) TXD B SCTE A (113) SCTE B DB-25 MALE CONNECTOR RTS A (105) RTS B DTR A (108) DTR B DCD A (109) DCD B DSR A (107) DSR B CTS A (106) CTS B LL A (141) VIN 3.3V 2846 F31 19 LTC2846 TYPICAL APPLICATIO S L1 5.6H VIN 3.3V C6 10F SHDN 3 4 7 C3 1F VCC 5V 5 C1 1F 6 8 LTC2846 RXD 9 D1 T CHARGE PUMP BOOST SWITCHING REGULATOR 36 35 33 32 31 30 C2 1F C4 3.3F D1 MBR0520 R1 13k R2 4.3k C5 10F VCC 5V 29 28 27 RXC 10 D2 T 26 11 D3 12 T 25 TXC R1 24 23 SCTE 13 R2 T 22 21 TXD 14 15 16 18 NC C7 1F C8 1F 19 M0 M1 M2 DCE/DTE 17 VIN 3.3V VEE GND D1 28 27 26 CTS 3 25 24 D2 23 C9 1F 5 13 6 22 7 1 R3 T 20 15 12 24 11 2 14 TXC A (114) TXC B SCTE A (113) SCTE B TXD A (103) TXD B SGND (102) SHIELD (101) DB-25 FEMALE CONNECTOR VCC 1 VCC 2 VDD DSR 4 5 D3 LTC2844 22 21 20 R2 19 18 R3 17 16 8 10 20 23 4 19 18 DCD 6 7 R1 DTR RTS 8 10 9 LL R4 D4 M0 M1 M2 DCE/DTE VIN M0 M1 M2 NC 11 12 13 14 15 C10 1F Figure 32. Controller-Selectable DCE Port with DB-25 Connector sn2846 2846fs 20 + U 3 16 17 9 RXD A (104) RXD B RXC A (115) RXC B CTS A (106) CTS B DSR A (107) DSR B DCD A (109) DCD B DTR A (108) DTR B RTS A (105) RTS B LL A (141) VIN 3.3V 2846 F32 LTC2846 TYPICAL APPLICATIO S L1 5.6H VIN 3.3V C6 10F SHDN 3 4 7 C3 1F VCC 5V 5 C1 1F 6 8 LTC2846 DTE_TXD/DCE_RXD 9 D1 T CHARGE PUMP BOOST SWITCHING REGULATOR 36 35 33 32 31 30 C2 1F C4 3.3F DTE TXD A TXD B SCTE A SCTE B DCE RXD A RXD B RXC A RXC B D1 MBR0520 VCC 5V C5 10F R1 13k R2 4.3k 29 28 27 DTE_SCTE/DCE_RXC 10 D2 T 26 11 D3 DTE_TXC/DCE_TXC 12 T 25 R1 24 23 DTE_RXC/DCE_SCTE 13 R2 T 22 21 DTE_RXD/DCE_TXD 14 15 16 18 19 C7 1F C8 1F M0 M1 M2 DCE/DTE 17 VIN 3.3V VEE GND D1 28 27 26 DTE_RTS/DCE_CTS 3 25 24 D2 23 C9 1F 4 19 20 23 7 1 R3 T 20 15 12 17 9 3 16 TXC A TXC B RXC A RXC B RXD A RXD B SG SHIELD DB-25 CONNECTOR TXC A TXC B SCTE A SCTE B TXD A TXD B VCC 1 VCC 2 VDD DTE_DTR/DCE_DSR 4 5 D3 LTC2844 22 21 20 R2 19 18 R3 17 16 8 10 6 22 5 13 18 DTE_DCD/DCE_DCD 6 7 R1 DTE_DSR/DCE_DTR DTE_CTS/DCE_RTS 8 10 9 DTE_LL/DCE_LL R4 D4 M0 M1 M2 DCE/DTE VIN M0 M1 M2 DCE/DTE 11 12 13 14 15 C10 1F Figure 33. Controller-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector sn2846 2846fs + U 2 14 24 11 RTS A RTS B DTR A DTR B CTS A CTS B DSR A DSR B DCD A DCD B DSR A DSR B CTS A CTS B LL A DCD A DCD B DTR A DTR B RTS A RTS B LL A VIN 3.3V 2846 F33 21 LTC2846 TYPICAL APPLICATIO S L1 5.6H VIN 3.3V C6 10F SHDN 3 4 7 C3 1F VCC 5V 5 C1 1F 6 8 LTC2846 DTE_TXD/DCE_RXD 9 D1 T CHARGE PUMP BOOST SWITCHING REGULATOR 36 35 33 32 31 30 C2 1F C4 3.3F D1 MBR0520 R1 13k R2 4.3k C5 10F VCC 5V 29 28 27 DTE_SCTE/DCE_RXC 10 D2 T 26 11 D3 12 T 25 DTE_TXC/DCE_TXC R1 24 23 DTE_RXC/DCE_SCTE 13 R2 T 22 21 DTE_RXD/DCE_TXD 14 15 16 18 19 C7 1F VCC 5V C8 1F M0 M1 M2 DCE/DTE 17 VIN 3.3V 36 35 34 DTE_RTS/DCE_CTS 3 D1 33 32 DTE_DTR/DCE_DSR 4 D2 31 C9 1F 4 19 20 23 1 R3 T 20 15 12 17 9 3 16 7 TXC A TXC B RXC A RXC B RXD A RXD B SG SHIELD TXC A TXC B SCTE A SCTE B TXD A TXD B 1, 19 VCC 2 VDD VEE GND 5 D3 LTC2845 30 29 28 R2 27 26 R3 D4 R4 R5 D5 M0 M1 M2 DCE/DTE R4EN 25 24 23 22 21 20 VIN 15 D4ENB 16 NC VIN 3.3V 8 10 6 22 5 13 DTE_DCD/DCE_DCD 6 7 R1 DTE_DSR/DCE_DTR DTE_CTS/DCE_RTS DTE_LL/DCE_RI DTE_RI/DCE_LL DTE_TM/DCE_RL DTE_RL/DCE_TM M0 M1 M2 DCE/DTE 8 9 10 17 18 11 12 13 14 Figure 34. Controller-Selectable Multiprotocol DTE/DCE Port with RL, LL, TM and DB-25 Connector sn2846 2846fs 22 + U 2 14 24 11 DTE TXD A TXD B SCTE A SCTE B DCE RXD A RXD B RXC A RXC B DB-25 CONNECTOR RTS A RTS B DTR A DTR B CTS A CTS B DSR A DSR B DCD A DCD B DSR A DSR B CTS A DCD A DCD B DTR A DTR B RTS A RTS B RI LL RL TM CTS B 18 LL * 25 21 RI TM RL C10 1F *OPTIONAL 2846 F34 LTC2846 TYPICAL APPLICATIO S L1 5.6H VIN 3.3V C6 10F SHDN 3 4 7 C3 1F VCC 5V 5 C1 1F 6 8 LTC2846 DTE_TXD/DCE_RXD 9 D1 T CHARGE PUMP BOOST SWITCHING REGULATOR 36 35 33 32 31 30 C2 1F C4 3.3F DTE TXD A TXD B SCTE A SCTE B DCE RXD A RXD B RXC A RXC B D1 MBR0520 R1 13k R2 4.3k C5 10F VCC 5V 29 28 27 DTE_SCTE/DCE_RXC 10 D2 T 26 11 D3 12 T 25 DTE_TXC/DCE_TXC R1 24 23 DTE_RXC/DCE_SCTE 13 R2 T 22 21 DTE_RXD/DCE_TXD 14 15 16 NC 18 19 M0 M1 M2 DCE/DTE 17 VIN 3.3V R3 T 20 15 12 17 9 3 RXD A 16 7 1 RXD B SG SHIELD DB-25 CONNECTOR C7 1F C8 1F VCC 1 VCC 2 VDD 3 D1 28 27 26 DTE_RTS/DCE_CTS 25 24 D2 23 C9 1F 25 DCE/DTE 21 M1 18 M0 4 RTS A 19 RTS B 20 DTR A 23 DTR B TXC A TXC B RXC A RXC B TXC A TXC B SCTE A SCTE B TXD A TXD B VEE GND DTE_DTR/DCE_DSR 4 5 D3 LTC2844 22 21 20 R2 19 18 R3 17 16 CABLE WIRING FOR MODE SELECTION MODE PIN 18 PIN 21 V.35 PIN 7 PIN 7 RS449, V.36 NC PIN 7 RS232 PIN 7 NC CABLE WIRING FOR DTE/DCE SELECTION MODE DTE DCE PIN 25 PIN 7 NC 2846 F35 DTE_DCD/DCE_DCD 6 7 R1 DTE_DSR/DCE_DTR DTE_CTS/DCE_RTS 8 10 9 11 12 NC 13 14 M0 M1 M2 R4 D4 VIN 15 C10 1F DCE/DTE Figure 35. Cable-Selectable Multiprotocol DTE/DCE Port with DB-25 Connector sn2846 2846fs Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. + U 2 14 24 11 CTS A CTS B DSR A DSR B 8 10 6 22 5 13 DCD A DCD B DSR A DSR B CTS A CTS B DCD A DCD B DTR A DTR B RTS A RTS B VIN 3.3V 23 LTC2846 PACKAGE DESCRIPTIO 7.8 - 8.2 0.42 0.03 RECOMMENDED SOLDER PAD LAYOUT 5.00 - 5.60** (.197 - .221) 0.09 - 0.25 (.0035 - .010) 0.55 - 0.95 (.022 - .037) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE RELATED PARTS PART NUMBER LTC1321 LTC1334 LTC1343 LTC1344A LTC1345 LTC1346A LTC1543 LTC1544 LTC1545 LTC1546 LTC2844 LTC2845 DESCRIPTION Dual RS232/RS485 Transceiver Single 5V RS232/RS485 Multiprotocol Transceiver Software-Selectable Multiprotocol Transceiver Software-Selectable Cable Terminator Single Supply V.35 Transceiver Dual Supply V.35 Transceiver Software-Selectable Multiprotocol Transceiver Software-Selectable Multiprotocol Transceiver Software-Selectable Multiprotocol Transceiver Software-Selectable Multiprotocol Transceiver 3.3V Software-Selectable Multiprotocol Transceiver 3.3V Software-Selectable Multiprotocol Transceiver 24 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 q FAX: (408) 434-0507 q U G Package 36-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 12.50 - 13.10* (.492 - .516) 1.25 0.12 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 5.3 - 5.7 7.40 - 8.20 (.291 - .323) 0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 2.0 (.079) 0 - 8 0.65 (.0256) BSC 0.22 - 0.38 (.009 - .015) 0.05 (.002) G36 SSOP 0802 COMMENTS Two RS232 Driver/Receiver Pairs or Two RS485 Driver/Receiver Pairs Two RS232 Driver/Receiver or Four RS232 Driver/Receiver Pairs 4-Driver/4-Receiver for Data and Clock Signals Perfect for Terminating the LTC1543 (Not Needed with LTC1546) 3-Driver/3-Receiver for Data and Clock Signals 3-Driver/3-Receiver for Data and Clock Signals Terminated with LTC1344A for Data and Clock Signals, Companion to LTC1544 or LTC1545 for Control Signals Companion to LTC1546 or LTC1543 for Control Signals Including LL 5-Driver/5-Receiver Companion to LTC1546 or LTC1543 for Control Signals Including LL, TM and RL 3-Driver/3-Receiver with Termination for Data and Clock Signals Companion to LTC2846 for Control Signals Including LL 5-Driver/5-Receiver Companion to LTC2846 for Control Signals Including LL, TM and RL sn2846 2846fs LT/TP 0503 1K * PRINTED IN USA www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2002 |
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