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| VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC7126 Features * ANSI X3T11 Fibre Channel Compatible 1.0625 Gbps Full-duplex Transceiver * GLM Compatible (FCSI-301-Rev 1.0) * 20 Bit TTL Interface For Transmit And Receive Data * Monolithic Clock Synthesis And Clock Recovery No External Components * 53.125 MHz TTL Reference Clock 1.0625 Gbits/sec Fibre Channel Transceiver * Automatic Lock-to-Reference Function * Suitable For Both Copper And Fiber Optical Link Applications * Low Power Operation - 850 mW * 80 Pin, 14x14 mm PQFP * Single +3.3V Power Supply General Description The VSC7126 is a full-speed Fibre Channel Transceiver optimized for Host Adapter and other space- constrained applications. It accepts two 10-bit 8B/10B encoded transmit characters, latches them on the rising edge of TBC and serializes the data onto the TX+/- PECL differential outputs at a baud rate which is twenty times the TBC frequency. It also samples serial receive data on the RX+/- PECL differential inputs, recovers the clock and data, deserializes it onto two 10-bit receive characters, outputs a recovered clocks at one twentieth of the incoming baud rate and detects Fibre Channel "Comma" characters. The VSC7126 contains on-chip PLL circuitry for synthesis of the baud-rate transmit clock, and extraction of the clock from the received serial stream. These circuits are fully monolithic and require no external components. VSC7126 Block Diagram EWRAP 20 R0:19 QD Serial to Parallel Retimed Data Recovered Clock QD Clock Recovery 2:1 RX+ RX- RBC(0) RBC(1) L_UNUSE COM_DET EN_CDET 53.125 MHz / 20 Comma Detect Frame Logic 20 T0:19 DQ Parallel to Serial Serial Data Synthesized Clock DQ TX+ TX- 53.125 MHz TBC TXEN# PLL Clock Multiply (x20) G52148-0, Rev. 4.3 3/4/99 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 1 VITESSE SEMICONDUCTOR CORPORATION 1.0625 Gbits/sec Fibre Channel Transceiver Datasheet VSC7126 Functional Description Clock Synthesizer: The VSC7126 clock synthesizer multiplies the 53.125 MHz reference frequency provided on the TBC pin by 20 to achieve a baud rate clock at nominally 1.0625 GHz. The clock synthesizer contains a fully monolithic PLL which does not require any external components. Serializer: The VSC7126 accepts TTL input data as two parallel 10 bit characters on the T0:19 bus which is latched into the input latch on the rising edge of TBC. This data will be serialized and transmitted on the TX PECL differential outputs at a baud rate of twenty times the frequency of the TBC input, with bit T0 transmitted first. User data should be encoded for transmission using the 8B/10B block code described in the Fibre Channel specification, or an equivalent, edge rich, DC-balanced code. If either EWRAP or TXEN# is HIGH the transmitter will be disabled with TX+ HIGH and TX- LOW. If both EWRAP and TXEN# are LOW, the transmitter outputs serialized data. Transmission Character Interface In Fibre Channel, an encoded byte is 10 bits and is referred to as a transmission character. The 20 bit interface on the VSC7126 corresponds to two transmission characters. This mapping is illustrated in Figure 1. Figure 1: Transmission Order and Mapping to Fibre Channel Character Parallel Data Bits 8B/10B Bit Position Valid Comma Position 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 j h g f i e d c b a j h g f 1 i 1 e 1 d 1 c 1 b 0 a 0 Last Data Bit Transmitted First Data Bit Transmitted Clock Recovery: The VSC7126 accepts differential high speed serial inputs on the RX+/RX- pins, (when EWRAP is LOW), extracts the clock and retimes the data. The serial bit stream should be encoded to provide DC balance and limited run length by a Fibre Channel compatible 8B/10B transmitter or equivalent. The VSC7126 clock recovery circuitry is completely monolithic and requires no external components. For proper operation, the baud rate of the data stream to be recovered should be within 200 ppm of twenty times the TBC frequency. This allows oscillators on either end of the link to be 53.125 MHz +/- 100ppm. Deserializer: The retimed serial bit stream is converted into two 10-bit parallel output characters. The VSC7126 provides a TTL recovered clock, RBC(0) and its complement RBC(1), at one-twentieth of the serial baud rate. The clocks are generated by dividing down the high-speed clock which is phase locked to the serial data. The serial data is retimed by the internal high-speed clock, and deserialized. The resulting parallel data will be captured Page 2 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52148-0, Rev. 4.3 3/4/99 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC7126 1.0625 Gbits/sec Fibre Channel Transceiver by the adjoining protocol logic on the falling edge of RBC(0). In order to maximize the setup and hold times available at this interface, the parallel data is loaded into the output register at a point nominally midway between the falling edges of RBC(0). If serial input data is not present, or does not meet the required baud rate, the VSC7126 will continue to produce a recovered clock so that downstream logic may continue to function. In the absence of a signal, the RBC(0)/RBC(1) output clocks will immediately lock to the TBC reference clock. Word Alignment: The VSC7126 provides 7-bit Fibre Channel comma character recognition and data word alignment. Word synchronization is enabled by asserting EN_CDET HIGH. When synchronization is enabled, the VSC7126 constantly examines the serial data for the presence of the Fibre Channel "comma" character. This pattern is "0011111XXX", where the leading zero corresponds to the first bit received. The comma sequence is not contained in any normal 8B/10B coded data character or pair of adjacent characters. It occurs only within special characters, known as K28.1, K28.5 and K28.7, which are defined specifically for synchronization in Fibre Channel systems. Improper alignment of the comma character is defined as any of the following conditions: 1) The comma is not aligned within the 10-bit transmission character such that T0...T6 = "0011111" 2) The comma straddles the boundary between two 10-bit transmission characters. When EN_CDET is HIGH and an improperly aligned comma is encountered, the internal data is shifted in such a manner that the comma character is aligned properly in R0:6 as shown in Figure 1. This results in proper character and word alignment. When the parallel data alignment changes in response to an improperly aligned comma pattern, some data which would have been presented on the parallel output port may be lost. However, the synchronization character and subsequent data will be output correctly and properly aligned. When EN_CDET is LOW, the current alignment of the serial data is maintained indefinitely, regardless of data pattern. On encountering a comma character, COM_DET is driven HIGH to inform the user that realignment of the parallel data field may have occurred. The COM_DET pulse is presented simultaneously with the comma character and has a duration equal to the data. The COM_DET signal is timed such that it can be captured by the adjoining protocol logic on the falling edge of RBC(0). Functional waveforms for synchronization are given in Figure 2 and Figure 3. Figure 2 shows the case when a comma character is detected and no phase adjustment is necessary. It illustrates the position of the COM_DET pulse in relation to the comma character on R0:6. Figure 3 shows the case where the K28.5 is detected, but it is out of phase and a change in the output data alignment is required. Note that up to three characters prior to the comma character may be corrupted by the realignment process. Signal Detection: An output, LUNUSE, is provided to signal when the link is open or down. This signal is asserted if R0:19 are all either LOW or HIGH and EWRAP is LOW. G52148-0, Rev. 4.3 3/4/99 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 3 VITESSE SEMICONDUCTOR CORPORATION 1.0625 Gbits/sec Fibre Channel Transceiver Figure 2: Detection of a Properly Aligned Comma Character Datasheet VSC7126 RBC(0) COM_DET R0:9 R10:19 K28.5 TChar TChar TChar TChar TChar TChar TChar TChar: 10 bit Transmission Character Figure 3: Detection and Resynchronization of an Improperly Aligned Comma Receiving Two Consecutive K28.5+TChar Transmission Words RBC(0) COM_DET R0:9 R10:19 PC PC PC K28.5 TChar TChar TChar TChar TChar TChar TChar K28.5 TChar TChar TChar PC = Potentially Corrupted Page 4 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52148-0, Rev. 4.3 3/4/99 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC7126 AC Characteristics Figure 4: Transmit Timing Waveforms 1.0625 Gbits/sec Fibre Channel Transceiver TBC T1 T2 T0:19 20 Bit Data Data Valid Data Valid Data Valid Table 1: Transmit AC Characteristics Parameters T1 T2 TSDR,TSDF TLAT Description T0:19 Setup time to the rising edge of TBC T0:19 hold time after the rising edge of TBC TX+/TX- rise and fall time Latency from rising edge of TBC to T0 appearing on TX+/TXSerial data output random jitter (RMS) Serial data output deterministic jitter (p-p) Min 1.5 2.5 -- 20 bc - 4 ns Max -- -- 300 Units ns. ns. ps. ns. Conditions Measured between the valid data level of T0:19 to the 1.4V point of TBC 20% to 80%, 75 Ohm load to Vdd-2V Tested on a sample basis bc = Bit Clock Periods Transmitter Output Jitter Allocation TRJ TDJ -- -- 20 120 ps. ps. RMS, tested on a sample basis (refer to Figure 8) Peak to peak, tested on a sample basis (refer to Figure 8) G52148-0, Rev. 4.3 3/4/99 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 5 VITESSE SEMICONDUCTOR CORPORATION 1.0625 Gbits/sec Fibre Channel Transceiver Figure 5: Receive Timing Waveforms Datasheet VSC7126 T3 RBC(0) TSKEW RBC(1) T1 T2 Data Valid R0:19 & COM_DET LUNUSE Data Valid Data Valid Table 2: Receive AC Characteristics Parameters T1 T2 Description Data or COM_DET Valid prior to RBC(0) fall Data or COM_DET Valid after RBC(0) fall Deviation of RBC(0) falling edge to falling edge delay from nominal. R0:19, COM_DET, RBC(0) rise and fall time Latency from RX to RBC(0) falling and RO valid. Skew between edges of RBC(0) and RBC(1) Data acquisition lock time @ 1.0625Gb/s Min. 4 6.0 Max. -- -- Units ns. ns. Conditions Measured between the 1.4V point of RBC(0) and a valid level of R0:19 or COM_DET. All outputs driving 10pF load. Nominal delay is 20 bit times. Tested on sample basis Between Vil(max) and Vih(min), into 10 pf. load. bc = bit clock periods T4 TR, TF Rlat TSKEW TLOCK -500 0.7 40 bc + 10 ns ----- 500 2.4 59 bc + 10 ns 1.5 2.4 ps. ns. Bit Clocks ns s. 8B/10B IDLE pattern. Tested on a sample basis NOTE: Probability of Recovery for data acquisition is 95% per section 5.3 of the FC-PH rev 4.3. Page 6 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52148-0, Rev. 4.3 3/4/99 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC7126 Figure 6: TBC Timing Waveforms 1.0625 Gbits/sec Fibre Channel Transceiver TH TBC Vih(min) Vil(max) TL Table 3: Reference Clock Requirements Parameters FR Description Frequency Range Min 50 Max 55 Units MHz Conditions Range over which both transmit and receive reference clocks on any link may be centered Mean frequency offset between transmit and receive reference clocks on one link Low is measured from Vil(max) to Vil(max), High is measured from Vih(min) to Vih(min) Measured at 1.5V Between Vil(max) and Vih(min) Peak-to-peak total jitter for frequencies between 50KHz and 7MHz FO TL,TH DC TRCR,TRCF JT Frequency Offset Pulse Width, Low / High TBC duty cycle TBC rise and fall time Total jitter tolerance on REFCLK -200 4.5 30 ------- 200 ---70 2.0 120 ppm. ns % ns. ps G52148-0, Rev. 4.3 3/4/99 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 7 VITESSE SEMICONDUCTOR CORPORATION 1.0625 Gbits/sec Fibre Channel Transceiver Datasheet VSC7126 DC Characteristics (Over recommended operating conditions). Parameters VOH VOL VOUT75 Description Output HIGH voltage (TTL) Output LOW voltage (TTL) Serial Output voltage differential peak-to-peak swing (TX+/TX-) Serial Output voltage differential peak-to-peak swing (TX+/TX-) Serial Input voltage differential peak-to-peak swing (RX+/RX-) Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) Supply voltage Power dissipation Supply Current Min 2.4 -- 1200 Typ 2.9 -- -- Max -- 0.5 2200 Units V V mV Conditions IOH = -1.0 mA IOL = +1.0 mA 75 to VDD - 2.0 V VOUT50 VIN VIH VIL IIH IIL VDD PD IDD 1000 400 2.0 0 -- -- 3.14 -- -- -- -- -- -- 50 -- -- 850 245 2200 3200 5.5 0.8 500 -500 3.47 1560 450 mV mV V V A A V mW mA 50 to VDD - 2.0 V -- VIN = 2.4 V VIN = 0.5 V 3.3V5% Outputs open, VDD = VDD max Outputs open, VDD = VDD max Absolute Maximum Ratings (1) Power Supply Voltage, (VDD) ............................................................................................................-0.5V to +4V DC Input Voltage (PECL inputs)............................................................................................ -0.5V to VDD +0.5V DC Input Voltage (TTL inputs) ......................................................................................................... -0.5V to 5.5V DC Output Voltage (TTL Outputs)........................................................................................ -0.5V to VDD + 0.5V Output Current (TTL Outputs) ................................................................................................................. +/-50mA Output Current (PECL Outputs)................................................................................................................+/-50mA Case Temperature Under Bias .........................................................................................................-55o to +125oC Storage Temperature..................................................................................................................... -65oC to +150oC Maximum Input ESD (Human Body Model)............................................................................................... 1500V Recommended Operating Conditions Power Supply Voltage, (VDD) ................................................................................................................+3.3V+5% Operating Temperature Range ................................................................0oC Ambient to 90oC Case Temperature Notes: (1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Page 8 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52148-0, Rev. 4.3 3/4/99 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC7126 Figure 7: Parametric Measurement Information 1.0625 Gbits/sec Fibre Channel Transceiver Serial Input Rise and Fall Time 80% 20% TTL Input and Output Rise and Fall Time Vih(min) Vil(max) Tr Tf Tr Tf Receiver Input Eye Diagram Jitter Tolerance Mask Bit Time Amplitude Total jitter tolerance is 0.7UI, according to Fibre Channel 4.3 Annex J Eye Width% Parametric Test Load Circuit Serial Output Load TTL A.C. Output Load Z0 = 75 75 10 pF VDD - 2.0V G52148-0, Rev. 4.3 3/4/99 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 9 VITESSE SEMICONDUCTOR CORPORATION 1.0625 Gbits/sec Fibre Channel Transceiver Figure 8: Transmitter Jitter Measurement Method Random Jitter Measurement Datasheet VSC7126 BERT Pattern Generator DATA DATA 53.125MHz Trigger CLK = 1.0625 GHz DATA = 00000 0000011111 11111 Digitizing Scope 53.125MHz RJ -K28.7 -K28.7 0011111000 0011111000 VSC7126 TX TBC T00:19 TX+ TX- 1.0625 Gbit/s Single-Ended Measurement Random jitter (RJ) measurements performed according to Fibre Channel 4.3 Annex A, Test Methods, Section A.4.4. Measure standard deviation of all 50% crossing points. Peak to peak RJ is + 7 sigma of distribution. Deterministic Jitter Measurement BERT DATA Pattern PAT SYNC Generator CLK = 1.0625 GHz DATA = 00000 0000011111 11111 53.125 Trigger Digitizing Scope 53.125MHz VSC7126 TX TBC DJ -K28.5 +K28.5 0011111010 1100000101 TX+ TX- 1.0625 Gbit/s Single-Ended Measurement T0:19 TRIGGER DATA 20 bit time 19 bit time 18 bit time 17 bit time Deterministic jitter (DJ) measurements performed according to Fibre Channel 4.3 Annex A, Test Methods, Section A.4.3. Measure time of all the 50% points of all ten transitions. DJ is the range of the timing variation from expected. 12 bit time 10 bit time 9 bit time 8 bit time 7 bit time 2 bit time Page 10 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52148-0, Rev. 4.3 3/4/99 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC7126 Input Structures Figure 9: Input Structures 1.0625 Gbits/sec Fibre Channel Transceiver VDD +3.3 V INPUT Current Limit R R GND TBC and TTL Inputs A VDD +3.3 V INPUT INPUT All Resistors 3.3K GND High Speed Differential Input (RX+/RX-) B G52148-0, Rev. 4.3 3/4/99 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 11 VITESSE SEMICONDUCTOR CORPORATION 1.0625 Gbits/sec Fibre Channel Transceiver Datasheet VSC7126 Figure 10: Pin Diagram Package Pin Descriptions Table 4: Pin Identification Pin # 2,4,6,9,11,14, 16,18,20,23,3, 5,8,10,12,15, 17,19,22,24 31 79 77 Name T0:19 Description Transmit Data Bus, Bits 0 thru 19. INPUTS - TTL 20-bit transmit character. Parallel data on this bus is clocked in on the rising edge of TBC. The data bit corresponding to T0 is transmitted first. Transmit Byte Clock. INPUT - TTL This rising edge of this clock latches T0:9 into the input register. It also provides the reference clock, at one twentieth of the baud rate to the PLL. Transmitter Serial Outputs. OUTPUTS - Differential PECL These pins output the serialized transmit data when EWRAP is LOW. When EWRAP is HIGH, TX+ is HIGH and TX- is LOW. (AC Coupling recommended) TBC TX+ TX- Page 12 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52148-0, Rev. 4.3 3/4/99 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC7126 Pin # 65,63,59,57, 55,52,50,48, 45,43,64,62, 58,56,54,51, 49,47,44,42 34 70 69 39 38 27 1.0625 Gbits/sec Fibre Channel Transceiver Name Description Receive Data Bus, Bits 0 thru 19 OUTPUTS - TTL 20-bit received character. Parallel data on this bus is clocked out on the rising edge of RBC(0). R0 is the first bit received on RX+/RX-. Enable Internal WRAP Mode. INPUT - TTL LOW for Normal Operation. When HIGH, an internal loopback path from the transmitter to the receiver is enabled, TX+ = HIGH and TX- is LOW. Receive Serial Inputs INPUTS - Differential PECL The receiver inputs when EWRAP is LOW. Internally biased to VDD/2, with 3.3K resistors to VDD and GND. (AC Coupling recommended) Recovered Byte Clock and Complement OUTPUT - TTL Recovered clock and complement derived from one twentieth of the RX+/- data stream. The rising edge of RBC(0) corresponds to a new word on R0:19. ENable Comma DETect. INPUT - TTL Enables comma detection and word resynchronization when HIGH. When LOW, keeps current word alignment and disables comma detection. COMma DETect OUTPUT - TTL This output goes HIGH to indicate that R0:6 contains a Comma Character (`0011111'). COMDET will go HIGH only during a cycle when RBC(0) is falling. COMDET is enabled by EN_CDET being HIGH. Transmitter ENable INPUT - TTL When LOW, the TX outputs transmit serial data. When HIGH, the TX+ is HIGH and the TX- is LOW. Link UNUSE OUTPUT - TTL Normally is LOW. If R0:19 is all LOW or all HIGH and EWRAP is LOW, this output will be asserted HIGH to indicate an open link on RX+/-. TEST Mode Pins Factory test pins. Tie to VDD for normal operation. Digital Ground Digital Ground for TTL Outputs Analog Ground Digital Power (3.3V) Digital Power for TTL outputs (3.3V) Digital Power for PECL outputs (3.3V) Analog Power (3.3V) Not Internally Connected. INPUT - TTL R0:19 EWRAP RX+ RXRBC(0) RBC(1) EN_CDET 37 COMDET 35 TXEN# 66 26 28 29 1,21,30,68,72 40,41,60,61 74 7,13,25,32,33, 67,71,75 36,46,53 76,80 73 78 LUNUSE TEST1 TEST2 TEST3 VSS VSST VSSA VDD VDDT VDDP VDDA N/C G52148-0, Rev. 4.3 3/4/99 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 13 VITESSE SEMICONDUCTOR CORPORATION 1.0625 Gbits/sec Fibre Channel Transceiver Datasheet VSC7126 80-pin PQFP Package Drawing Package Information F G 80 61 60 1 Item A D E F G 14 mm 2.35 2.00 0.30 17.20 14.00 17.20 14.00 0.88 0.65 Tolerance MAX +0.10/-0.05 .05 .25 .10 .25 .10 +.15/-.10 BASIC I H H I J K 20 21 40 41 10 TYP A D 10 TYP K 0.30 RAD. TYP. 0.20 RAD. TYP. A 0.25 STANDOFF 0.25 MAX. 0.102 MAX LEAD COPLANARITY 0.17 MAX. 0 - 8 J NOTES: Drawing not to scale. All units in mm unless otherwise noted. E Page 14 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52148-0, Rev. 4.3 3/4/99 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC7126 Package Thermal Characteristics 1.0625 Gbits/sec Fibre Channel Transceiver The VSC7126 is packaged in a 14 mm PQFP with an integrated heat spreader. These packages use industry-standard EIAJ footprints, but have been enhanced to improve thermal dissipation. The construction of the packages is as shown in Figure 11. Figure 11: Package Cross Section - 14 mm package Plastic Molding Compound Copper Heat Spreader Lead Table 5: Thermal Resistance Symbol Bond Wire Die Description Thermal resistance from junction to case Thermal resistance from case to ambient in still air including conduction through the leads. Thermal resistance from case to ambient with 100 LFM airflow Thermal resistance from case to ambient with200 LFM airflow Thermal resistance from case to ambient with 400 LFM airflow Thermal resistance from case to ambient with 600 LFM airflow 14mm Value 17 32 28 25 22 20 Units oC/W oC/W oC/W oC/W oC/W oC/W jc ca ca-100 ca-200 ca-400 ca-600 The VSC7126 is designed to operate with a case temperature up to 90oC. The user must guarantee that the temperature specification is not violated. With the Thermal Resistances shown above, the 14x14 PQFP can operate in still air ambient temperatures of 40oC (40C = 90C - 1.56W * 32C/W). If the ambient air temperature exceeds these limits, then some form of cooling through a heatsink or an increase in airflow will be needed. Moisture Sensitivity Level This device is rated with a moisture sensitivity level 3 rating. Refer to Application Note AN-20 for appropriate handling procedures. G52148-0, Rev. 4.3 3/4/99 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 15 VITESSE SEMICONDUCTOR CORPORATION 1.0625 Gbits/sec Fibre Channel Transceiver Datasheet VSC7126 Ordering Information The order number for this product is formed by a combination of the device number, and package type. VSC7126 Device Type VSC7126: 1.0625 Gbps Transceiver QX Package Style QX: 80-pin, 14 x 14 mm PQFP Notice Vitesse Semiconductor Corporation reserves the right to make changes in its products, specifications or other information at any time without prior notice. Therefore the reader is cautioned to confirmation that this datasheet is current prior to placing any orders. The company assumes no responsibility for any circuitry described other than circuitry entirely embodied in a Vitesse product. Warning Vitesse Semiconductor Corporation's product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited. Page 16 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52148-0, Rev. 4.3 3/4/99 |
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