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MPU Interface (GND = 0V, VCC = 2.7 to 5.5V, Ta = -30 to +75C)*
Item E cycle time E high level width E low level width E rise time E fall time Address setup time Address hold time Data setup time Data delay time Data hold time (write) Data hold time (read) Symbol t CYC PWEH PWEL tr tf t AS t AH t DSW t DDR t DHW t DHR Min 1000 450 450 -- -- 140 10 200 -- 10 20 Typ -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- 25 25 -- -- -- 320 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns
Code D/I 0 0 0 0 0 RESET 1: Reset 0: Normal Busy 0 ON/ Reset 0 OFF 0 0 0 Reads the status. 0 1 Y address (0-63) 1 0 1 1 1 Page (0-7) 1 1 Display start line (0-63) 0 0 1 1 1 1 1 1/0 Controls display on/off. RAM data and internal status are not affected. 1: on, 0: off. Specifies the RAM line displayed at the top of the screen. Sets the page (X address) of RAM at the page (X address) register. Sets the Y address in the Y address counter. DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Functions
Instructions
R/W
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0
Set page (X address)
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Set Y address
0
Status read
1
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1 Read data
ON/OFF 1: Display off 0: Display on 1: Internal operation 0: Ready
Write display data
0
Writes data DB0 (LSB) to DB7 (MSB) on the data bus into display RAM.
Reads data DB0 (LSB) to DB7 (MSB) from the display RAM to the data bus.
Read display data
1
Has access to the address of the display RAM specified in advance. After the access, Y address is increased by 1.
Note: Busy time varies with the frequency (fCLK) of o1, and o2. (1/fCLK TBUSY 3/fCLK)








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