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| S71JL128HC0/128HB0/064HB0/ 064HA0/064H80 Stacked Multi-Chip Product (MCP) Flash Memory and pSRAM CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and Static RAM/Pseudo-static RAM DISTINCTIVE CHARACTERISTICS MCP Features Operating Voltage Range of 2.7 to 3.3 V High Performance -- Access time as fast as 55 ns Packages -- 73-ball FBGA--8 x 11.6 mm -- 88-ball FBGA--8 x 11.6 mm Operating Temperatures -- Wireless: -25C to +85C -- Industrial: -40C to +85C PRELIMINARY GENERAL DESCRIPTION The S71JLxxxH Series is a product line of stacked Multi-Chip Products (MCP) and consists of One or more S29JL064H Flash devices SRAM or pSRAM options -- 8Mb x 8/x 16 SRAM -- 16Mb x 16-only SRAM -- pSRAM x 16 only: 8Mb pSRAM 16Mb pSRAM 32Mb pSRAM 64Mb pSRAM The products covered by this document are listed below. For details about their specifications, please refer to the individual constituent data sheets for further details. MCP S71JL064H80 S71JL064HA0 S71JL064HB0 S71JL128HB0 S71JL128HC0 Number of S29JL064H 1 1 1 2 2 Total Flash Density 64Mb 64Mb 64Mb 128Mb 128Mb SRAM/pSRAM Density 8Mb 16Mb 32Mb 32Mb 64Mb Notes: 1. This MCP is only guaranteed to operate @ 2.7 - 3.3 V regardless of component operating ranges. 2. BYTE# operation is only supported on the S71JL064H80xx0x. Publication Number S29JLxxxHxx_00 Revision A Amendment 2 Issue Date February 26, 2004 Preliminary Product Selector Guide Device-Model # S71JL064H80Bxx01 S71JL064H80Bxx02 S71JL064H80Bxx10 S71JL064H80Bxx11 S71JL064H80Bxx12 SRAM/pSRAM Density 8Mb 8Mb 8Mb 8Mb 8Mb SRAM/pSRAM Type SRAM - x8/x16 SRAM - x8/x16 pSRAM - x16 pSRAM - x16 pSRAM - x16 Supplier Supplier 1 Supplier 1 Supplier 2 Supplier 2 Supplier 2 Flash Access RAM Access Time (ns) Time (ns) 70 85 55 70 85 70 85 55 70 85 Packages FLB073 FLB073 FLJ073 FLJ073 FLJ073 S71JL064HA0Bxx01 S71JL064HA0Bxx02 S71JL064HA0Bxx10 S71JL064HA0Bxx11 S71JL064HA0Bxx12 S71JL064HA0Bxx62 16Mb 16Mb 16Mb 16Mb 16Mb 16Mb SRAM - x16 SRAM - x16 pSRAM - x16 pSRAM - x16 pSRAM - x16 pSRAM - x16 Supplier 1 Supplier 1 Supplier 2 Supplier 2 Supplier 2 Supplier 4 70 85 55 70 85 70 70 85 55 70 85 70 FLB073 FLB073 FLJ073 FLJ073 FLJ073 FLJ073 S71JL128HB0Bxx01 S71JL128HB0Bxx02 32Mb 32Mb pSRAM - x16 pSRAM - x16 Supplier 3 Supplier 3 70 85 70 85 FTA073 FTA073 S71JL128HC0Bxx01 S71JL128HC0Bxx02 64Mb 64Mb pSRAM - x16 pSRAM - x16 Supplier 3 Supplier 3 70 85 70 85 FTA088 FTA088 2 S71JL128HC0/128HB0/064HB0/064HA0/064H80 S29JLxxxHxx_00A2 February 26, 2004 Advance Information TABLE OF CONTENTS S71JL128HC0/128HB0/064HB0/064HA0/064H80 Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . 1 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 MCP Block Diagram of S71JL064H80, Model Numbers 01/02 ................6 MCP Block Diagram of S71JL064H80, Model Numbers 10/11/12 ..............6 MCP Block Diagram of S71JL064HA0, Model Numbers 01/02 ................7 MCP Block Diagram of S71JL064HA0, Model Numbers 10/11/12/61 ........7 MCP Block Diagram of S71JL064HB0, Model Numbers 00/01/02 ..........8 MCP Block Diagram of S71JL128HB0, Model Numbers 00/01/02 ...........9 MCP Block Diagram of S71JL128HC0, Model Numbers 00/01/02 ........ 10 Requirements for Reading Array Data ........................................................ 43 Writing Commands/Command Sequences ................................................ 43 Accelerated Program Operation ...............................................................44 Autoselect Functions .....................................................................................44 Simultaneous Read/Write Operations with Zero Latency ...................44 Standby Mode ......................................................................................................44 Automatic Sleep Mode .....................................................................................44 RESET#: Hardware Reset Pin ......................................................................... 45 Output Disable Mode ....................................................................................... 45 Table 2. S29JL064H Sector Architecture ............................... 46 Table 3. Bank Address ........................................................ 49 Table 4. SecSiTM Sector Addresses ...................................... 49 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 11 Connection Diagram of S71JL064H80, Model Numbers 01/02 .............. 11 Special Package Handling Instructions ...................................................... 12 Pin Description ................................................................................................ 12 Logic Symbol .....................................................................................................13 Connection Diagram of S71JL064H80, Model Numbers 10/11/12 ........... 14 Pin Description .................................................................................................15 Logic Symbol .....................................................................................................15 Connection Diagram of S71JL064HA0, Model Numbers 01/02 ............. 16 Pin Description .................................................................................................17 Logic Symbol .................................................................................................... 18 Connection Diagram of S71JL064HA0, Model Numbers 10/11/12/61 ..... 19 Pin Description ............................................................................................... 20 Logic Symbol ................................................................................................... 20 Connection Diagram of S71JL064HB0, Model Numbers 00/01/02 ....... 21 Pin Description ............................................................................................... 22 Logic Symbol ................................................................................................... 22 Connection Diagram of S71JL128HB0, Model Numbers 00/01/02 ........23 Pin Description ............................................................................................... 24 Logic Symbol ................................................................................................... 24 Connection Diagram of S71JL128HC0, Model Numbers 00/01/02 .......25 Special Package Handling Instructions ......................................................25 Pin Description ............................................................................................... 26 Logic Symbol ................................................................................................... 26 Look-ahead Connection Diagram ..................................................................27 Autoselect Mode ................................................................................................49 Sector/Sector Block Protection and Unprotection .................................50 Table 5. S71JLxxxHxx_00 Boot Sector/Sector Block Addresses for Protection/Unprotection ...................................................... 50 Write Protect (WP#) ........................................................................................ 51 Table 6. WP#/ACC Modes ................................................... 52 Temporary Sector Unprotect ........................................................................ 52 Figure 1. Temporary Sector Unprotect Operation ................... 52 Figure 2. In-System Sector Protect/Unprotect Algorithms ....... 53 SecSiTM (Secured Silicon) Sector Flash Memory Region .......................... 53 Factory Locked: SecSi Sector Programmed and Protected At the Factory ............................................................................................................... 54 Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory ....................................................................................................... 54 Figure 3. SecSi Sector Protect Verify .................................... 55 Hardware Data Protection ............................................................................. 55 Low VCC Write Inhibit ................................................................................ 55 Write Pulse "Glitch" Protection ............................................................... 55 Logical Inhibit ................................................................................................... 56 Power-Up Write Inhibit ............................................................................... 56 Common Flash Memory Interface (CFI) . . . . . . 56 Table 7. CFI Query Identification String ................................ 56 Table 8. System Interface String ......................................... 57 Table 9. Device Geometry Definition .................................... 57 Table 10. Primary Vendor-Specific Extended Query ................ 58 Command Definitions . . . . . . . . . . . . . . . . . . . . . . 59 Reading Array Data ........................................................................................... 59 Reset Command ................................................................................................. 59 Autoselect Command Sequence ....................................................................60 Enter SecSiTM Sector/Exit SecSi Sector Command Sequence ................60 Byte/Word Program Command Sequence .................................................60 Unlock Bypass Command Sequence ......................................................... 61 Figure 4. Program Operation ............................................... 62 Ordering Information . . . . . . . . . . . . . . . . . . . . . . .29 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 33 FLB073 ....................................................................................................................33 FLJ073 ......................................................................................................................34 FTA073 ...................................................................................................................35 FTA088 ..................................................................................................................36 S29JL064H Chip Erase Command Sequence ................................................................... 62 Sector Erase Command Sequence ................................................................ 63 Figure 5. Erase Operation ................................................... 64 General Description 38 Simultaneous Read/Write Operations with Zero Latency ....................38 S71JLxxxHxx_00 Features ................................................................................38 Erase Suspend/Erase Resume Commands ..................................................64 Table 11. S29JL064H Command Definitions .......................... 65 Write Operation Status . . . . . . . . . . . . . . . . . . . . 66 DQ7: Data# Polling ............................................................................................ 66 Figure 6. Data# Polling Algorithm ........................................ 68 Product Selector Guide . . . . . . . . . . . . . . . . . . . . .40 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .42 Table 1. S71JLxxxHxx_00 Device Bus Operations .................. 42 RY/BY#: Ready/Busy# .......................................................................................68 DQ6: Toggle Bit I ...............................................................................................69 Figure 7. Toggle Bit Algorithm ............................................. 70 Word/Byte Configuration ................................................................................ 43 DQ2: Toggle Bit II ..............................................................................................70 Reading Toggle Bits DQ6/DQ2 ...................................................................... 71 DQ5: Exceeded Timing Limits ......................................................................... 71 February 24, 2004 S71JLxxxHxx_00A0 3 Advance Information DQ3: Sector Erase Timer ..................................................................................71 Table 12. Write Operation Status ......................................... 72 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . 73 Figure 8. Maximum Negative Overshoot Waveform ................. 73 Figure 9. Maximum Positive Overshoot Waveform .................. 73 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .73 Wireless (W) Devices ...................................................................................73 Industrial (I) Devices ......................................................................................73 VCC Supply Voltages ......................................................................................73 Table 13. CMOS Compatible ................................................ 74 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 28. Timing Waveform of Read Cycle(1) (address controlled, CD#1=OE#=VIL, CS2=WE#=VIH, UB# and/or LB#=VIL) ........ 93 Figure 29. Timing Waveform of Read Cycle(2) (WE#=VIH, if BYTE# is low, ignore UB#/LB# timing) ........................................... 93 Figure 30. Timing Waveform of Write Cycle(1) (WE# controlled, if BYTE# is low, ignore UB#/LB# timing)................................. 93 Figure 31. Timing Waveform of Write Cycle(2) (CE1# controlled, if BYTE# is low, ignore UB#/LB# timing)................................. 94 Figure 32. Timing Waveform of Write Cycle(3) (UB#, LB# controlled, BYTE# must be high) ......................................... 94 Data Retention Waveforms ............................................................................ 95 Figure 33. CE1# Controlled................................................. 95 Figure 34. CS2 Controlled ................................................... 95 Zero-Power Flash ...............................................................................................75 Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents).................................................................. 75 Figure 11. Typical ICC1 vs. Frequency................................... 75 16 Mb SRAM (supplier 1) Functional Description . . . . . . . . . . . . . . . . . . . . . 96 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 96 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 97 Recommended DC Operating Conditions (Note 1) ............................... 97 Capacitance (f=1MHz, TA=25C) ................................................................... 97 DC Operating Characteristics ....................................................................... 97 Test Conditions ...................................................................................................76 Figure 12. Test Setup ........................................................ 76 Table 14. Test Specifications ............................................... 76 Switching Waveforms ........................................................................................76 Table 15. Key To Switching Waveforms ................................ 76 Figure 13. Input Waveforms and Measurement Levels............. 76 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 77 Read-Only Operations ......................................................................................77 Figure 14. Read Operation Timings ....................................... 77 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 98 Read/Write Charcteristics (VCC=2.7-3.3V) ................................................98 Data Retention Characteristics .....................................................................98 Timing Diagrams .................................................................................................99 Figure 35. Timing Waveform of Read Cycle(1) (address controlled, CD#1=OE#=VIL, CS2=WE#=VIH, UB# and/or LB#=VIL) ........ 99 Figure 36. Timing Waveform of Read Cycle(2) (WE#=VIH) ...... 99 Figure 37. Timing Waveform of Write Cycle(1) (WE# controlled)... 100 Figure 38. Timing Waveform of Write Cycle(2) (CS# controlled) ... 100 Figure 39. Timing Waveform of Write Cycle(3) (UB#, LB# controlled)...................................................................... 101 Figure 40. Data Retention Waveform.................................. 102 Hardware Reset (RESET#) .............................................................................. 78 Figure 15. Reset Timings..................................................... 78 Word/Byte Configuration (BYTE#) ............................................................. 78 Figure 16. BYTE# Timings for Read Operations ...................... 79 Figure 17. BYTE# Timings for Write Operations ...................... 79 Erase and Program Operations ..................................................................... 80 Figure 18. Program Operation Timings .................................. 81 Figure 19. Accelerated Program Timing Diagram .................... 81 Figure 20. Chip/Sector Erase Operation Timings ..................... 82 Figure 21. Back-to-back Read/Write Cycle Timings ................. 82 Figure 22. Data# Polling Timings (During Embedded Algorithms) . 83 Figure 23. Toggle Bit Timings (During Embedded Algorithms) .. 83 Figure 24. DQ2 vs. DQ6 ...................................................... 84 8 Mb pSRAM (supplier 2) Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 General Description . . . . . . . . . . . . . . . . . . . . . . . 103 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 41. Functional Block Diagram .................................. 104 Table 18. Functional Description ........................................ 104 Temporary Sector Unprotect ........................................................................ 84 Figure 25. Temporary Sector Unprotect Timing Diagram.......... 84 Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram............................................................................ 85 Alternate CE# Controlled Erase and Program Operations ................. 86 Figure 27. Alternate CE# Controlled Write (Erase/Program) Operation Timings .............................................................. 87 Erase And Programming Performance . . . . . . . .88 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 88 Absolute Maximum Ratings (See Note) . . . . . . 104 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 105 Operating Characteristics (Over Specified Temperature Range) ......105 8 Mb SRAM (supplier 1) Functional Description . . . . . . . . . . . . . . . . . . . . . 89 Table 16. Word Mode ......................................................... 89 Table 17. Byte Mode .......................................................... 89 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 105 Table 19. Timing Test Conditions ....................................... 105 Table 20. Timings ............................................................ 106 Timing Diagrams ................................................................................................107 Figure 42. Timing of Read Cycle (CE1# = OE# = VIL, WE# = CE2 = VIH)............................................................................ 107 Figure 43. Timing Waveform of Read Cycle (WE# = VIH) ...... 107 Figure 44. Timing Waveform of Write Cycle (WE# Control) ... 108 Figure 45. Timing Waveform of Write Cycle (CE1# Control)... 108 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 90 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 90 Recommended DC Operating Conditions ................................................ 90 Capacitance (f=1MHz, TA=25C) ................................................................... 90 DC and Operating Characteristics ................................................................ 91 16 Mb pSRAM (supplier 2) Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 General Description . . . . . . . . . . . . . . . . . . . . . . 109 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 46. Functional Block Diagram .................................. 110 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .92 Read/Write Charcteristics (VCC=2.7-3.3V) ................................................ 92 Data Retention Characteristics ..................................................................... 92 Timing Diagrams ..................................................................................................93 4 S71JLxxxHxx_00A0 February 24, 2004 Advance Information Table 21. Functional Description .........................................110 Absolute Maximum Ratings (See Note) . . . . . . . 111 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 111 Operating Characteristics (Over Specified Temperature Range) ....... 111 Absolute Maxumum Ratings . . . . . . . . . . . . . . . . 124 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 27. DC Recommended Operating Conditions (TA = -40C to 85C) ............................................................................. 124 Table 28. DC Characteristics (TA = -40C to 85C, VDD = 2.6 to 3.3V) ............................................................................. 125 Table 29. Capacitance (TA = 25C, f = 1 MHz) ..................... 125 Table 30. AC Characteristics and Operating Conditions (TA = -40C to 85C, VDD = 2.6 to 3.3V) .............................................. 125 Table 31. AC Test Conditions ............................................. 126 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 112 Timing Test Conditions .................................................................................... 112 Timings .................................................................................................................. 112 Timings .................................................................................................................. 113 Figure 47. Timing of Read Cycle (CE1# = OE# = VIL, WE# = CE2 = VIH) ............................................................................ 113 Figure 48. Timing Waveform of Read Cycle (WE# = VIH) ....... 113 Figure 49. Timing Waveform of Write Cycle (WE# Control) .... 114 Figure 50. Timing Waveform of Write Cycle (CE1# Control, CE2 = High).............................................................................. 114 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 125 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 127 Figure 61. Read Cycle ...................................................... Figure 62. Page Read Cycle (8 words access) ...................... Figure 63. Write Cycle 1 (WE# controlled) .......................... Figure 64. Write Cycle 2 (CE# controlled) ........................... Figure 65. Deep Power-down Timing .................................. Figure 66. Power-on Timing .............................................. Figure 67. Read Address Skew Provisions ........................... Figure 68. Write Address Skew Provisions ........................... 127 128 129 130 130 130 131 131 16 Mb pSRAM (supplier 4) Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maxumum Ratings (see Note) . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 115 115 115 116 116 116 64 Mb pSRAM (supplier 3) Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maxumum Ratings . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 132 132 132 133 133 133 Table 22. DC Recommended Operating Conditions ................116 Table 23. DC Characteristics (TA = -25C to 85C, VDD = 2.6 to 3.3V) ..............................................................................117 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 24. AC Characteristics and Operating Conditions (TA = -25C to 85C, VDD = 2.6 to 3.3V) ...............................................117 Table 25. AC Test Conditions .............................................118 Figure 51. AC Test Loads................................................... 118 Figure 52. State Diagram .................................................. 119 Table 26. Standby Mode Characteristics ..............................119 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 119 Figure 53. Read Cycle 1--Addressed Controlled .................... Figure 54. Read Cycle 2--CS1# Controlled .......................... Figure 55. Write Cycle 1--WE# Controlled ........................... Figure 56. Write Cycle 2--CS1# Controlled .......................... Figure 57. Write Cycle3--UB#, LB# Controlled ..................... Figure 58. Deep Power-down Mode..................................... Figure 59. Power-up Mode................................................. Figure 60. Abnormal Timing............................................... 119 120 120 121 121 122 122 122 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 32. DC Recommended Operating Conditions (TA = -25C to 85C) ............................................................................. 133 Table 33. DC Characteristics (TA = -25C to 85C, VDD = 2.6 to 3.3V) ............................................................................. 134 Table 34. Capacitance (TA = 25C, f = 1 MHz) ..................... 134 Table 35. AC Characteristics and Operating Conditions (TA = -25C to 85C, VDD = 2.6 to 3.3V) .............................................. 134 Table 36. AC Test Conditions ............................................. 135 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 136 Figure 69. Read Cycle ...................................................... Figure 70. Page Read Cycle (8 words access) ...................... Figure 71. Write Cycle 1 (WE# controlled) .......................... Figure 72. Write Cycle 2 (CE# controlled) ........................... Figure 73. Deep Power-down Timing .................................. Figure 74. Power-on Timing .............................................. Figure 75. Read Address Skew Provisions ........................... Figure 76. Write Address Skew Provisions ........................... 136 137 138 139 139 139 140 140 32 Mb pSRAM (Supplier 3) Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . 123 123 123 124 Revision Summary February 24, 2004 S71JLxxxHxx_00A0 5 Preliminary Block Diagrams MCP Block Diagram of S71JL064H80, Model Numbers 01/02 VCCf A21 to A0 A21 to A0 A-1 WP#/ACC RESET# CE#f CIOf VSS RY/BY# 64 MBit Flash Memory DQ15/A-1 to DQ0 DQ15/A-1 to DQ0 VCCs VSS A0 toto A0 A18 A19 SA LB# UB# WE# OE# CE1#s CE2s CIOs 8 MBit SRAM DQ15/A-1 to DQ0 MCP Block Diagram of S71JL064H80, Model Numbers 10/11/12 VCCf VSS RY/BY# A21 to A0 WP#/ACC RESET# CE#f A21 to A0 64 MBit Flash Memory DQ15 to DQ0 DQ15 to DQ0 VCCs VSS A0 toto A0 A18 A19 LB# UB# WE# OE# CE1#s CE2s 8 MBit PSRAM RY/BY# DQ15 to DQ0 6 S71JLxxxHxx_00A1 February 25, 2004 Preliminary MCP Block Diagram of S71JL064HA0, Model Numbers 01/02 VCCf A21 to A0 A21 to A0 WP#/ACC RESET# CE#f VSS RY/BY# 64 MBit Flash Memory DQ15 to DQ0 DQ15 to DQ0 VCCs VSS A0 toto A0 A19 A19 LB# UB# WE# OE# CE1#s CE2s 16 MBit SRAM DQ15 to DQ0 MCP Block Diagram of S71JL064HA0, Model Numbers 10/11/12/62 VCCf A21 to A0 A21 to A0 WP#/ACC RESET# CE#f VSS RY/BY# 64 MBit Flash Memory DQ15 to DQ0 DQ15 to DQ0 VCCs VSS A0 toto A0 A19 A19 LB# UB# WE# OE# CE1#s CE2s 16 MBit pSRAM DQ15 to DQ0 February 25, 2004 S71JLxxxHxx_00A1 7 Preliminary MCP Block Diagram of S71JL064HB0, Model Numbers 00/01/02 VCCf A21 to A0 A21 to A0 WP#/ACC RESET# CE#f VSS RY/BY# 64 MBit Flash Memory DQ15 to DQ0 DQ15 to DQ0 VCCs VSS A0 to A0 A20 to A19 LB# UB# WE# OE# CE1#s CE2s 16 MBit pSRAM DQ15 to DQ0 8 S71JLxxxHxx_00A1 February 25, 2004 Preliminary MCP Block Diagram of S71JL128HB0, Model Numbers 00/01/02 VCCf A21 to A0 VSS 64 MBit Flash Memory #1 CE#f1 DQ15 to DQ0 VCCf VSS A21 to A0 WP#/ACC RESET# CE#f2 A21 to A0 RY/BY# 64 MBit Flash Memory #2 DQ15 to DQ0 DQ15 to DQ0 VCCs VSS A20 to A0 LB# UB# WE# OE# CE1#s CE2s 32 MBit pSRAM DQ15 to DQ0 February 25, 2004 S71JLxxxHxx_00A1 9 Preliminary MCP Block Diagram of S71JL128HC0, Model Numbers 00/01/02 VCCf A21 to A0 VSS RY/BY#1 RESET#1 CE#f1 64 MBit Flash Memory #1 DQ15 to DQ0 VCCf VSS A21 to A0 WP#/ACC RESET#2 CE#f2 A21 to A0 RY/BY#2 64 MBit Flash Memory #2 DQ15 to DQ0 DQ15 to DQ0 VCCs VSS A21 to A0 LB# UB# WE# OE# CE1#ps CE2ps 64 MBit pSRAM DQ15 to DQ0 10 S71JLxxxHxx_00A1 February 25, 2004 Preliminary Connection Diagrams Connection Diagram of S71JL064H80, Model Numbers 01/02 73-Ball FBGA Top View A1 NC A10 NC Flash only B1 NC B5 NC B6 NC B10 NC SRAM only C1 NC C3 A7 C4 D4 UB# C5 D5 E5 RY/BY# C6 D6 E6 A20 C7 A8 C8 A11 Shared LB# WP#/ACC WE# D2 A3 D3 A6 D7 A19 D8 A12 D9 A15 RESET# CE2s E2 A2 E3 A5 E4 A18 E7 A9 E8 A13 E9 A21 F1 NC F2 A1 F3 A4 F4 A17 F7 A10 F8 A14 F9 NC F10 NC G1 NC G2 A0 G3 VSS G4 DQ1 G7 DQ6 G8 SA G9 A16 G10 NC H2 CE#f H3 OE# H4 DQ9 H5 DQ3 H6 DQ4 H7 J7 DQ12 H8 J8 DQ7 H9 J9 VSS DQ13 DQ15/A-1 CIOf J2 CE1#s J3 DQ0 J4 DQ10 J5 VCCf J6 VCCs K3 DQ8 K4 DQ2 K5 DQ11 K6 CIOs K7 DQ5 K8 DQ14 L1 NC L5 NC L6 NC L10 NC M1 NC M10 NC February 25, 2004 S71JLxxxHxx_00A1 11 Preliminary Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (FBGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. Pin Description A18-A0 A21-A19, A-1 SA DQ15-DQ0 CE#f CE#s OE# WE# RY/BY# UB# LB# CIOf = = = = = = = = = = = = 19 Address Inputs (Common) 4 Address Inputs (Flash) Highest Order Address Pin (SRAM) Byte mode 16 Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable (SRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Output Upper Byte Control (SRAM) Lower Byte Control (SRAM) I/O Configuration (Flash) CIOf = VIH = Word mode (x16), CIOf = VIL = Byte mode (x8) I/O Configuration (SRAM) CIOs = VIH = Word mode (x16), CIOs = VIL = Byte mode (x8) Hardware Reset Pin, Active Low Hardware Write Protect/Acceleration Pin (Flash) Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) SRAM Power Supply Device Ground (Common) Pin Not Connected Internally CIOs = RESET# WP#/ACC VCCf VCCs VSS NC = = = = = = 12 S71JLxxxHxx_00A1 February 25, 2004 Preliminary Logic Symbol 19 A18-A0 A21-A19, A-1 SA CE#f CE1#s CE2s OE# WE# WP#/ACC RESET# UB# LB# CIOf CIOs RY/BY# DQ15-DQ0 16 or 8 February 25, 2004 S71JLxxxHxx_00A1 13 Preliminary Connection Diagram of S71JL064H80, Model Numbers 10/11/12 73-Ball FBGA Top View A1 NC A10 NC Flash only B1 NC B5 NC B6 NC B10 NC SRAM only C1 NC C3 A7 C4 D4 UB# C5 D5 E5 RY/BY# C6 D6 E6 A20 C7 A8 C8 A11 Shared LB# WP#/ACC WE# D2 A3 D3 A6 D7 A19 D8 A12 D9 A15 RESET# CE2s E2 A2 E3 A5 E4 A18 E7 A9 E8 A13 E9 A21 F1 NC F2 A1 F3 A4 F4 A17 F7 A10 F8 A14 F9 NC F10 NC G1 NC G2 A0 G3 VSS G4 DQ1 G7 DQ6 G8 NC G9 A16 G10 NC H2 CE#f H3 OE# H4 DQ9 H5 DQ3 H6 DQ4 H7 DQ13 H8 DQ15 H9 NC J2 CE1#s J3 DQ0 J4 DQ10 J5 VCCf J6 VCCs J7 DQ12 J8 DQ7 J9 VSS K3 DQ8 K4 DQ2 K5 DQ11 K6 NC K7 DQ5 K8 DQ14 L1 NC L5 NC L6 NC L10 NC M1 NC M10 NC 14 S71JLxxxHxx_00A1 February 25, 2004 Preliminary Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP, BGA, PDIP, SSOP, PLCC). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. Pin Description A18-A0 A21-A19 DQ15-DQ0 CE#f CE1#s CE2s OE# WE# RY/BY# UB# LB# RESET# WP#/ACC VCCf VCCs VSS NC = = = = = = = = = = = = = = 19 Address Inputs (Common) 2 Address Inputs (Flash) 16 Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable 1 (pSRAM) Chip Enable 2 (pSRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Output Upper Byte Control (pSRAM) Lower Byte Control (pSRAM) Hardware Reset Pin, Active Low Hardware Write Protect/Acceleration Pin (Flash) Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) pSRAM Power Supply Device Ground (Common) Pin Not Connected Internally = = = Logic Symbol 19 A18-A0 A21, A19 SA CE#f CE1#s CE2s OE# WE# WP#/ACC RESET# UB# LB# RY/BY# DQ15-DQ0 16 February 25, 2004 S71JLxxxHxx_00A1 15 Preliminary Connection Diagram of S71JL064HA0, Model Numbers 01/02 73-Ball FBGA Top View A1 NC A10 NC Flash only B1 NC B5 NC B6 NC B10 NC SRAM only C1 NC C3 A7 C4 D4 UB# C5 D5 E5 RY/BY# C6 D6 E6 A20 C7 A8 C8 A11 Shared LB# WP#/ACC WE# D2 A3 D3 A6 D7 A19 D8 A12 D9 A15 RESET# CE2s E2 A2 E3 A5 E4 A18 E7 A9 E8 A13 E9 A21 F1 NC F2 A1 F3 A4 F4 A17 F7 A10 F8 A14 F9 NC F10 NC G1 NC G2 A0 G3 VSS G4 DQ1 G7 DQ6 G8 NC G9 A16 G10 NC H2 CE#f H3 OE# H4 DQ9 H5 DQ3 H6 DQ4 H7 DQ13 H8 DQ15 H9 NC J2 CE1#s J3 DQ0 J4 DQ10 J5 VCCf J6 VCCs J7 DQ12 J8 DQ7 J9 VSS K3 DQ8 K4 DQ2 K5 DQ11 K6 NC K7 DQ5 K8 DQ14 L1 NC L5 NC L6 NC L10 NC M1 NC M10 NC 16 S71JLxxxHxx_00A1 February 25, 2004 Preliminary Special Package Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. Pin Description A19-A0 A21-A20 DQ15-DQ0 CE#f CE#s OE# WE# RY/BY# UB# LB# RESET# WP#/ACC VCCf VCCs VSS NC = = = = = = = = = = = = = 20 Address Inputs (Common) 2 Address Inputs (Flash) 16 Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable (SRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Output Upper Byte Control (SRAM) Lower Byte Control (SRAM) Hardware Reset Pin, Active Low Hardware Write Protect/Acceleration Pin (Flash) Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) SRAM Power Supply Device Ground (Common) Pin Not Connected Internally = = = February 25, 2004 S71JLxxxHxx_00A1 17 Preliminary Logic Symbol 20 A19-A0 A21-A20 16 CE#f CE1#s CE2s OE# WE# WP#/ACC RESET# UB# LB# RY/BY# DQ15-DQ0 18 S71JLxxxHxx_00A1 February 25, 2004 Preliminary Connection Diagram of S71JL064HA0, Model Numbers 10/11/12/62 73-Ball FBGA Top View A1 NC A10 NC Flash only B1 NC B5 NC B6 NC B10 NC SRAM only C1 NC C3 A7 C4 D4 UB# C5 D5 E5 RY/BY# C6 D6 E6 A20 C7 A8 C8 A11 Shared LB# WP#/ACC WE# D2 A3 D3 A6 D7 A19 D8 A12 D9 A15 RESET# CE2s E2 A2 E3 A5 E4 A18 E7 A9 E8 A13 E9 A21 F1 NC F2 A1 F3 A4 F4 A17 F7 A10 F8 A14 F9 NC F10 NC G1 NC G2 A0 G3 VSS G4 DQ1 G7 DQ6 G8 NC G9 A16 G10 NC H2 CE#f H3 OE# H4 DQ9 H5 DQ3 H6 DQ4 H7 DQ13 H8 DQ15 H9 NC J2 CE1#s J3 DQ0 J4 DQ10 J5 VCCf J6 VCCs J7 DQ12 J8 DQ7 J9 VSS K3 DQ8 K4 DQ2 K5 DQ11 K6 NC K7 DQ5 K8 DQ14 L1 NC L5 NC L6 NC L10 NC M1 NC M10 NC February 25, 2004 S71JLxxxHxx_00A1 19 Preliminary Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP, BGA, PDIP, SSOP, PLCC). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. Pin Description A19-A0 A21-A20 DQ15-DQ0 CE#f CE1#s CE2s OE# WE# RY/BY# UB# LB# RESET# WP#/ACC VCCf VCCs VSS NC = = = = = = = = = = = = = = 20 Address Inputs (Common) 2 Address Inputs (Flash) 16 Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable 1 (pSRAM) Chip Enable 2 (pSRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Output Upper Byte Control (pSRAM) Lower Byte Control (pSRAM) Hardware Reset Pin, Active Low Hardware Write Protect/Acceleration Pin (Flash) Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) pSRAM Power Supply Device Ground (Common) Pin Not Connected Internally = = = Logic Symbol 20 A19-A0 SA CE#f CE1#s CE2s OE# WE# WP#/ACC RESET# UB# LB# RY/BY# DQ15-DQ0 16 20 S71JLxxxHxx_00A1 February 25, 2004 Preliminary Connection Diagram of S71JL064HB0, Model Numbers 00/01/02 73-Ball FBGA Top View A1 NC A10 NC Flash only B1 NC B5 NC B6 NC B10 NC SRAM only C1 NC C3 A7 C4 D4 UB# C5 D5 E5 RY/BY# C6 D6 E6 A20 C7 A8 C8 A11 Shared LB# WP#/ACC WE# D2 A3 D3 A6 D7 A19 D8 A12 D9 A15 RESET# CE2s E2 A2 E3 A5 E4 A18 E7 A9 E8 A13 E9 A21 F1 NC F2 A1 F3 A4 F4 A17 F7 A10 F8 A14 F9 NC F10 NC G1 NC G2 A0 G3 VSS G4 DQ1 G7 DQ6 G8 NC G9 A16 G10 NC H2 CE#f H3 OE# H4 DQ9 H5 DQ3 H6 DQ4 H7 DQ13 H8 DQ15 H9 NC J2 CE1#s J3 DQ0 J4 DQ10 J5 VCCf J6 VCCs J7 DQ12 J8 DQ7 J9 VSS K3 DQ8 K4 DQ2 K5 DQ11 K6 NC K7 DQ5 K8 DQ14 L1 NC L5 NC L6 NC L10 NC M1 NC M10 NC February 25, 2004 S71JLxxxHxx_00A1 21 Preliminary Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP, BGA, PDIP, SSOP, PLCC). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. Pin Description A20-A0 A21 DQ15-DQ0 CE#f CE1#s CE2s OE# WE# RY/BY# UB# LB# RESET# WP#/ACC VCCf VCCs VSS NC = = = = = = = = = = = = = = 20 Address Inputs (Common) 1 Address Input (Flash) 16 Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable 1 (pSRAM) Chip Enable 2 (pSRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Output Upper Byte Control (pSRAM) Lower Byte Control (pSRAM) Hardware Reset Pin, Active Low Hardware Write Protect/Acceleration Pin (Flash) Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) pSRAM Power Supply Device Ground (Common) Pin Not Connected Internally = = = Logic Symbol 21 A20-A0 A21 SA CE#f CE1#s CE2s OE# WE# WP#/ACC RESET# UB# LB# RY/BY# DQ15-DQ0 16 22 S71JLxxxHxx_00A1 February 25, 2004 Preliminary Connection Diagram of S71JL128HB0, Model Numbers 00/01/02 73-Ball FBGA Top View A1 NC A10 NC Flash 1 only B1 NC B5 NC B6 NC B10 NC Flash 2 only C1 NC C3 A7 C4 D4 UB# C5 D5 E5 RY/BY# C6 D6 E6 A20 C7 A8 C8 A11 LB# WP#/ACC WE# Pseudo SRAM only D2 A3 D3 A6 D7 A19 D8 A12 D9 A15 RESET# CE2s Flash 1 and 2 shared Flash 1, 2, and Pseudo SRAM shared E2 A2 E3 A5 E4 A18 E7 A9 E8 A13 E9 A21 F1 NC F2 A1 F3 A4 F4 A17 F7 A10 F8 A14 F9 CE#f2 F10 NC G1 NC G2 A0 G3 VSS G4 DQ1 G7 DQ6 G8 NC G9 A16 G10 NC H2 CE#f1 H3 OE# H4 DQ9 H5 DQ3 H6 DQ4 H7 DQ13 H8 DQ15 H9 NC J2 CE1#s J3 DQ0 J4 DQ10 J5 VCCf J6 VCCs J7 DQ12 J8 DQ7 J9 VSS K3 DQ8 K4 DQ2 K5 DQ11 K6 NC K7 DQ5 K8 DQ14 L1 NC L5 NC L6 NC L10 NC M1 NC M10 NC February 25, 2004 S71JLxxxHxx_00A1 23 Preliminary Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. Pin Description A20-A0 A21 DQ15-DQ0 CE#f1 CE#f2 CE1#ps CE2ps OE# WE# RY/BY# UB# LB# RESET# WP#/ACC VCCf VCCps VSS NC = = = = = = = = = = = = = = = 21 Address Inputs (Common) 1 Address Input (Flash) 16 Data Inputs/Outputs (Common) Chip Enable 1 (Flash 1) Chip Enable 2 (Flash 2) Chip Enable 1 (pSRAM) Chip Enable 2 (pSRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Output Upper Byte Control (pSRAM) Lower Byte Control (pSRAM) Hardware Reset Pin, Active Low Hardware Write Protect/Acceleration Pin (Flash) Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) pSRAM Power Supply Device Ground (Common) Pin Not Connected Internally = = = Logic Symbol 21 A20-A0 A21 16 CE#f1 CE#f2 CE1#ps CE2ps OE# WE# WP#/ACC RESET# UB# LB# RY/BY# DQ15-DQ0 24 S71JLxxxHxx_00A1 February 25, 2004 Preliminary Connection Diagram of S71JL128HC0, Model Numbers 00/01/02 88-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) A1 NC A2 NC B2 NC C2 NC D2 A3 E2 A2 F2 A1 G2 A0 H2 CE#f1 J2 CE1#fs K2 NC L2 NC B3 VSS C3 A7 D3 A6 E3 A5 F3 A4 G3 VSS H3 OE# J3 DQ0 K3 DQ8 L3 RESET#2 B4 Ry/BY#2 C4 LB# D4 UB# E4 A18 F4 A17 G4 DQ1 H4 DQ9 J4 DQ10 K4 DQ2 L4 VSS B5 CE#f2 C5 WP#/Acc D5 RESET#1 E5 RY/BY#1 F5 NC G5 NC H5 DQ3 J5 J4 VCCf K5 DQ11 L5 VCCf B6 NC C6 WE# D6 CE2s E6 A20 F6 NC G6 NC H6 DQ4 J4 VCCs K6 NC L6 NC B7 NC C7 A8 D7 A19 E7 A9 F7 A10 G7 DQ6 H7 DQ13 J7 DQ12 K7 DQ5 L7 NC B8 NC C8 A11 D8 A12 E8 A13 F8 A14 G8 NC H8 DQ15 J8 DQ7 K8 DQ14 L8 NC A9 NC B9 NC A10 NC Shared Flash 1 and 2 Shared Flash 1 Only Flash 2 Only C9 NC D9 A15 E9 A21 F9 NC G9 A16 H9 NC J9 VSS K9 NC L9 NC M9 NC M10 NC SRAM Only M1 NC M2 NC Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP, BGA, PLCC, PDIP, SSOP). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. February 25, 2004 S71JLxxxHxx_00A1 25 Preliminary Pin Description A21-A0 DQ15-DQ0 CE#f1 CE#f2 CE1#ps CE2ps OE# WE# RY/BY#1 RY/BY#2 UB# LB# RESET#1 RESET#2 WP#/ACC VCCf VCCps VSS NC = = = = = = = = = = = = = = = = 22 Address Inputs (Common) 16 Data Inputs/Outputs (Common) Chip Enable 1 (Flash 1) Chip Enable 2 (Flash 2) Chip Enable 1 (pSRAM) Chip Enable 2 (pSRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Output (Flash 1) Ready/Busy Output (Flash 2) Upper Byte Control (pSRAM) Lower Byte Control (pSRAM) Hardware Reset Pin, Active Low (Flash 1) Hardware Reset Pin, Active Low (Flash 2) Hardware Write Protect/Acceleration Pin (Flash) Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) pSRAM Power Supply Device Ground (Common) Pin Not Connected Internally = = = Logic Symbol 22 A21-A0 16 CE#f1 CE#f2 CE1#ps CE2ps OE# WE# WP#/ACC RESET#1 RESET#2 UB# LB# RY/BY#1 RY/BY#2 DQ15-DQ0 26 S71JLxxxHxx_00A1 February 25, 2004 Preliminary Look-ahead Connection Diagram 96-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down) Legend: A1 NC B1 NC A2 NC B2 NC C2 AVD# D2 WP# E2 A3 F2 A2 G2 A1 H2 A0 J2 CE#f1 K2 CE1#s1 L2 VCCds M2 A27 N1 NC P1 NC N2 NC P2 NC C3 VSSds D3 A7 E3 A6 F3 A5 G3 A4 H3 VSS J3 OE# K3 DQ0 L3 DQ8 M3 A26 C4 CLK D4 LB#s E4 UB#s F4 A18 G4 A17 H4 DQ1 J4 DQ9 K4 DQ10 L4 DQ2 M4 VSSnds C5 CE#f2 D5 WP#/ACC E5 RESET#f F5 RY/BY# G5 CE1#s2 H5 VCCs2 J5 DQ3 K5 VCCf L5 DQ11 M5 C6 C7 C8 A9 NC B9 NC C9 A10 NC B10 NC ds = Data storage only f = Flash shared only f1 = 1st Flash only f2 = 2nd Flash only NC = Outrigger balls s = RAM shared s1 = 1st RAM only s2 = 2nd RAM only VCCds RESET#ds CLKds RY/BY#ds D6 WE# E6 CE2s1 F6 A20 G6 A23 H6 CE2s2 J6 DQ4 K6 VCCs1 L6 A25 M6 D7 A8 E7 A19 F7 A9 G7 A10 H7 DQ6 J7 DQ13 K7 DQ12 L7 DQ5 M7 VCCQs1 D8 A11 E8 A12 F8 A13 G8 A14 H8 A24 J8 DQ15 K8 DQ7 L8 D9 CE1#ds E9 A15 F9 A21 G9 A22 H9 A16 J2 CREs K9 VSS L9 DQ14 LOCK or WP#/ACCds M8 VCCQds M9 TEST N9 NC P9 NC N10 NC P10 NC VCCf CE2#ds or VCCQf Note: To provide customers with a migration path to higher densities and an option to stack more die in a package, FASL has prepared a standard pinout that supports NOR Flash and SRAM densities up to 4 Gigabits NOR Flash and pSRAM densities up to 4 Gigabits February 25, 2004 S71JLxxxHxx_00A1 27 Preliminary NOR Flash and pSRAM and DATA STORAGE densities up to 4 Gigabits The signal locations of the resultant MCP device are shown above. Note that for different densities, the actual package outline may vary. Any pinout in any MCP, however, will be a subset of the pinout above. In some cases, there may be outrigger balls in locations outside the grid shown above. In such cases, the user is recommended to treat them as reserved and not connect them to any other signal. For any further inquiries about the above look-ahead pinout, please refer to the application note on this subject or contact your sales office. 28 S71JLxxxHxx_00A1 February 25, 2004 Preliminary Ordering Information The order number (Valid Combination) is formed by the following: S 71 J L 064 H A 0 B AW 00 0 PACKING TYPE 0 2 3 = Tray = 7" Tape & Reel = 13" Tape & Reel Additional ordering options See Product Selector Guide TEMPERATURE (and RELIABILITY) GRADE E W I A F B 0 8 A B C = Engineering Samples = Wireless (-25C to +85C) = Industrial (-40C to +85C) = Standard (Pb-free compliant) Package = Lead (Pb)-free Package = BGA Package = No second content = = = = 8 Mb 16 Mb 32 Mb 64 Mb PACKAGE MATERIAL SET (BGA Package Type) PACKAGE TYPE CHIP CONTENTS--2 CHIP CONTENTS--1 Spansion FLASH MEMORY PROCESS TECHNOLOGY (Highest-density Flash described in Characters 4-8) H 064 128 L = 130 nm Floating Gate Technology = one S29JL064H = two S29JL064H = 3-volt VCC BASE NOR FLASH DENSITY BASE NOR FLASH CORE VOLTAGE BASE NOR FLASH INTERFACE and SIMULTANEOUS READ/ WRITE J 71 S = Simultaneous Read/Write = Flash Base + xRAM. = Spansion PRODUCT FAMILY PREFIX Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Valid Combinations Order Number S71JL064H80BAI01 S71JL064H80BAI02 S71JL064H80BAI10 S71JL064H80BAI11 Package Marking 71JL064H80BAI01 71JL064H80BAI02 71JL064H80BAI10 71JL064H80BAI11 Flash Access Time (ns) 70 85 55 70 (p)SRAM Access Time (ns) 70 85 55 70 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Supplier Supplier 1 Supplier 1 Supplier 2 Supplier 2 February 25, 2004 S71JLxxxHxx_00A1 29 Preliminary Valid Combinations Order Number S71JL064H80BAI12 S71JL064H80BAW01 S71JL064H80BAW02 S71JL064H80BAW10 S71JL064H80BAW11 S71JL064H80BAW12 S71JL064H80BFI01 S71JL064H80BFI02 S71JL064H80BFI10 S71JL064H80BFI11 S71JL064H80BFI12 S71JL064H80BFW01 S71JL064H80BFW02 S71JL064H80BFW10 S71JL064H80BFW11 S71JL064H80BFW12 Package Marking 71JL064H80BAI12 71JL064H80BAW01 71JL064H80BAW02 71JL064H80BAW10 71JL064H80BAW11 71JL064H80BAW12 71JL064H80BFI01 71JL064H80BFI02 71JL064H80BFI10 71JL064H80BFI11 71JL064H80BFI12 71JL064H80BFW01 71JL064H80BFW02 71JL064H80BFW10 71JL064H80BFW11 71JL064H80BFW12 Flash Access Time (ns) 85 70 85 55 70 85 70 85 55 70 85 70 85 55 70 85 (p)SRAM Access Time (ns) 85 70 85 55 70 85 70 85 55 70 85 70 85 55 70 85 Temperature Range -40C to +85C -25C to +85C -25C to +85C -25C to +85C -25C to +85C -25C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -25C to +85C -25C to +85C -25C to +85C -25C to +85C -25C to +85C Supplier Supplier 2 Supplier 1 Supplier 1 Supplier 2 Supplier 2 Supplier 2 Supplier 1 Supplier 1 Supplier 2 Supplier 2 Supplier 2 Supplier 1 Supplier 1 Supplier 2 Supplier 2 Supplier 2 S71JL064HA0BAI01 S71JL064HA0BAI02 S71JL064HA0BAI10 S71JL064HA0BAI11 S71JL064HA0BAI12 S71JL064HA0BAI62 S71JL064HA0BAW01 S71JL064HA0BAW02 S71JL064HA0BAW10 S71JL064HA0BAW11 S71JL064HA0BAW12 S71JL064HA0BAW62 S71JL064HA0BFI01 S71JL064HA0BFI02 S71JL064HA0BFI10 S71JL064HA0BFI11 S71JL064HA0BFI12 S71JL064HA0BFI62 71JL064HA0BAI01 71JL064HA0BAI02 71JL064HA0BAI10 71JL064HA0BAI11 71JL064HA0BAI12 71JL064HA0BAI62 71JL064HA0BAW01 71JL064HA0BAW02 71JL064HA0BAW10 71JL064HA0BAW11 71JL064HA0BAW12 71JL064HA0BAW62 71JL064HA0BFI01 71JL064HA0BFI02 71JL064HA0BFI10 71JL064HA0BFI11 71JL064HA0BFI12 71JL064HA0BFI62 70 85 55 70 85 70 70 85 55 70 85 70 70 85 55 70 85 70 70 85 55 70 85 70 70 85 55 70 85 70 70 85 55 70 85 70 -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -25C to +85C -25C to +85C -25C to +85C -25C to +85C -25C to +85C -25C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Supplier 1 Supplier 1 Supplier 2 Supplier 2 Supplier 2 Supplier 4 Supplier 1 Supplier 1 Supplier 2 Supplier 2 Supplier 2 Supplier 4 Supplier 1 Supplier 1 Supplier 2 Supplier 2 Supplier 2 Supplier 4 30 S71JLxxxHxx_00A1 February 25, 2004 Preliminary Valid Combinations Order Number S71JL064HA0BFW01 S71JL064HA0BFW02 S71JL064HA0BFW10 S71JL064HA0BFW11 S71JL064HA0BFW12 S71JL064HA0BFW62 Package Marking 71JL064HA0BFW01 71JL064HA0BFW02 71JL064HA0BFW10 71JL064HA0BFW11 71JL064HA0BFW12 71JL064HA0BFW62 Flash Access Time (ns) 70 85 55 70 85 70 (p)SRAM Access Time (ns) 70 85 55 70 85 70 Temperature Range -25C to +85C -25C to +85C -25C to +85C -25C to +85C -25C to +85C -25C to +85C Supplier Supplier 1 Supplier 1 Supplier 2 Supplier 2 Supplier 2 Supplier 4 S71JL064HB0BAI00 S71JL064HB0BAI01 S71JL064HB0BAI02 S71JL064HB0BAW00 S71JL064HB0BAW01 S71JL064HB0BAW02 S71JL064HB0BFI00 S71JL064HB0BFI01 S71JL064HB0BFI02 S71JL064HB0BFW00 S71JL064HB0BFW01 S71JL064HB0BFW02 71JL064HB0BAI00 71JL064HB0BAI01 71JL064HB0BAI02 71JL064HB0BAW00 71JL064HB0BAW01 71JL064HB0BAW02 71JL064HB0BFI00 71JL064HB0BFI01 71JL064HB0BFI02 71JL064HB0BFW00 71JL064HB0BFW01 71JL064HB0BFW02 55 70 85 55 70 85 55 70 85 55 70 85 55 70 85 55 70 85 55 70 85 55 70 85 -40C to +85C -40C to +85C -40C to +85C -25C to +85C -25C to +85C -25C to +85C -40C to +85C -40C to +85C -40C to +85C -25C to +85C -25C to +85C -25C to +85C Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 S71JL128HB0BAI00 S71JL128HB0BAI01 S71JL128HB0BAI02 S71JL128HB0BAW00 S71JL128HB0BAW01 S71JL128HB0BAW02 S71JL128HB0BFI00 S71JL128HB0BFI01 S71JL128HB0BFI02 S71JL128HB0BFW00 S71JL128HB0BFW01 S71JL128HB0BFW02 71JL128HB0BAI00 71JL128HB0BAI01 71JL128HB0BAI02 71JL128HB0BAW00 71JL128HB0BAW01 71JL128HB0BAW02 71JL128HB0BFI00 71JL128HB0BFI01 71JL128HB0BFI02 71JL128HB0BFW00 71JL128HB0BFW01 71JL128HB0BFW02 55 70 85 55 70 85 55 70 85 55 70 85 55 70 85 55 70 85 55 70 85 55 70 85 -40C to +85C -40C to +85C -40C to +85C -25C to +85C -25C to +85C -25C to +85C -40C to +85C -40C to +85C -40C to +85C -25C to +85C -25C to +85C -25C to +85C Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 S71JL128HC0BAI00 S71JL128HC0BAI01 71JL128HC0BAI00 71JL128HC0BAI01 55 70 55 70 -40C to +85C -40C to +85C Supplier 3 Supplier 3 February 25, 2004 S71JLxxxHxx_00A1 31 Preliminary Valid Combinations Order Number S71JL128HC0BAI02 S71JL128HC0BAW00 S71JL128HC0BAW01 S71JL128HC0BAW02 S71JL128HC0BFI00 S71JL128HC0BFI01 S71JL128HC0BFI02 S71JL128HC0BFW00 S71JL128HC0BFW01 S71JL128HC0BFW02 Package Marking 71JL128HC0BAI02 71JL128HC0BAW00 71JL128HC0BAW01 71JL128HC0BAW02 71JL128HC0BFI00 71JL128HC0BFI01 71JL128HC0BFI02 71JL128HC0BFW00 71JL128HC0BFW01 71JL128HC0BFW02 Flash Access Time (ns) 85 55 70 85 55 70 85 55 70 85 (p)SRAM Access Time (ns) 85 55 70 85 55 70 85 55 70 85 Temperature Range -40C to +85C -25C to +85C -25C to +85C -25C to +85C -40C to +85C -40C to +85C -40C to +85C -25C to +85C -25C to +85C -25C to +85C Supplier Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 Supplier 3 32 S71JLxxxHxx_00A1 February 25, 2004 Preliminary Physical Dimensions FLB073 D 0.15 C (2X) 10 9 8 7 6 5 4 3 2 1 ML KJ HGFEDCB A B 7 SD PIN A1 CORNER A eD D1 SE 7 E1 E eE INDEX MARK PIN A1 CORNER 10 TOP VIEW A A2 0.15 C (2X) 0.20 C BOTTOM VIEW A1 6 73X b 0.15 M C A B 0.08 M C C 0.08 C SIDE VIEW NOTES: PACKAGE JEDEC FLB 073 N/A 11.60 mm x 8.00 mm PACKAGE MIN. NOM. --0.20 0.95 ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 73 0.25 0.30 0.80 BSC 0.80 BSC 0.40 BSC 0.35 1. NOTE 2. MAX. 1.40 --1.13 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 8. 9. 6 7 3. 4. 5. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD/SE A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALL B2,B3,B4,B7,B8,B9 C2,C9,C10,D1,D10,E1,E10 F5,F6,G5,G6,H1,H10 J1,J10,K1,K2, K9,K10,L2,L3,L4,L7,L8,L9 M2,M3,M4,M5,M6,M7,M8,M9 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTION OR OTHER MEANS. 3188\38.14b February 25, 2004 S71JLxxxHxx_00A1 33 Preliminary FLJ073 D 0.15 C (2X) 10 9 8 7 A D1 eD SE 7 E eE 6 5 4 3 2 1 L J H G F E DCB A E1 INDEX MARK PIN A1 CORNER 10 M K B 7 TOP VIEW 0.15 C (2X) SD PIN A1 CORNER BOTTOM VIEW A A2 A1 6 0.20 C C 0.08 C SIDE VIEW b M C AB MC 73X 0.15 0.08 NOTES: PACKAGE JEDEC FLJ 073 N/A 11.60 mm x 8.00 mm PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME n b eE eD SD / SE 0.30 MIN --0.25 0.95 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 73 0.35 0.80 BSC. 0.80 BSC. 0.40 BSC. 0.40 MAX 1.40 --1.13 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 8. 9. 7 6 NOTE 1. 2. 3. 4. 5. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. NOT USED. A2,A3,A4,A5,A6,A7,A8,A9,B2,B3,B4,B7,B8,B9 C2,C9,C10,D1,D10,E1,E10,F5,F6,G5,G6,H1,H10 DEPOPULATED SOLDER BALLS J1,J10,K1,K2,K9,K10,L2,L3,L4,L7,L8,L9 M2,M3,M4,M5,M6,M7,M8,M9 10. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3232 \ 16-038.14b 34 S71JLxxxHxx_00A1 February 25, 2004 Preliminary FTA073 D 0.15 C (2X) 10 9 8 7 A D1 eD SE 7 E eE 6 5 4 3 2 1 E1 INDEX MARK PIN A1 CORNER 10 M L K J H G F E D CB A B 7 TOP VIEW 0.15 C (2X) SD PIN A1 CORNER BOTTOM VIEW 0.20 C A A2 A1 6 C 0.08 C SIDE VIEW b CAB C 73X 0.15 M 0.08 M NOTES: PACKAGE JEDEC FTA 073 N/A 11.60 mm x 8.00 mm PACKAGE MIN. NOM. MAX. --0.25 1.00 ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 73 0.30 0.35 0.80 BSC 0.80 BSC 0.40 BSC A2,A3,A4,A5,A6,A7,A8,A9 B2,B3,B4,B7,B8,B9,C2,C9,C10 D1,D10,E1,E10,F5,F6,G5,G6 H1,H10,J1,J10,K1,K2,K9,K10 L2,L3,L4,L7,L8,L9 M2,M3,M4,M5,M6,M7,M8,M9 0.40 1.40 --1.11 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALL 9. 8. 6 7 NOTE 1. 2. 3. 4. 5. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD/SE 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTION OR OTHER MEANS. 3159\38.14b February 25, 2004 S71JLxxxHxx_00A1 35 Preliminary FTA088 D 0.15 C (2X) 10 9 8 7 A D1 eD SE 7 E eE 6 5 4 3 2 1 E1 INDEX MARK PIN A1 CORNER 10 M L K J H G F E D CB A B 7 TOP VIEW 0.15 C (2X) SD PIN A1 CORNER BOTTOM VIEW A A2 A1 6 0.20 C C 0.08 C SIDE VIEW b M CAB MC 88X 0.15 0.08 NOTES: PACKAGE JEDEC FTA 088 N/A 11.60 mm x 8.00 mm PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME n b eE eD SD / SE 0.30 MIN --0.25 1.00 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 88 0.35 0.80 BSC. 0.80 BSC 0.40 BSC. 0.40 MAX 1.40 --1.11 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A A3,A4,A5,A6,A7,A8,B1,B10,C1,C10,D1,D10 DEPOPULATED SOLDER BALLS E1,E10,F1,F10,G1,G10,H1,H10 J1,J10,K1,K10,L1,L10,M3,M4,M5,M6,M7,M8 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3237 \ 16-038.14b 36 S71JLxxxHxx_00A1 February 25, 2004 Preliminary S29JL064H For Multi-Chip Products (MCP) 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory Distinctive Characteristics Architectural Advantages Simultaneous Read/Write operations -- Data can be continuously read from one bank while executing erase/program functions in another bank. -- Zero latency between read and write operations Flexible Bank architecture -- Read may occur in any of the three banks not being written or erased. -- Four banks may be grouped by customer to achieve desired bank divisions. Boot Sectors -- Top and bottom boot sectors in the same device -- Any combination of sectors can be erased Manufactured on 130 nm process technology SecSiTM (Secured Silicon) Sector: Extra 256 Byte sector -- Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. -- Customer lockable: One-time programmable only. Once locked, data cannot be changed Zero Power Operation -- Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero. Compatible with JEDEC standards -- Pinout and software compatible with single-powersupply flash standard -- 10 mA active read current at 5 MHz -- 200 nA in standby or automatic sleep mode Cycling Endurance: 1 million cycles per sector typical Data Retention: 20 years typical Software Features Supports Common Flash Memory Interface (CFI) Erase Suspend/Erase Resume -- Suspends erase operations to read data from, or program data to, a sector that is not being erased, then resumes the erase operation. Data# Polling and Toggle Bits -- Provides a software method of detecting the status of program or erase cycles Unlock Bypass Program command -- Reduces overall programming time when issuing multiple program command sequences Hardware Features Ready/Busy# output (RY/BY#) -- Hardware method for detecting program or erase cycle completion Hardware reset pin (RESET#) -- Hardware method of resetting the internal state machine to the read mode WP#/ACC input pin -- Write protect (WP#) function protects sectors 0, 1, 140, and 141, regardless of sector protect status -- Acceleration (ACC) function accelerates program timing Sector protection -- Hardware method to prevent any program or erase operation within a sector -- Temporary Sector Unprotect allows changing data in protected sectors in-system Performance Characteristics High performance -- Access time as fast as 55 ns -- Program time: 4 s/word typical using accelerated programming function Ultra low power consumption (typical values) -- 2 mA active read current at 1 MHz February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 37 Preliminary General Description The S71JLxxxHxx_00 is a 64 megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. Word mode Data appears on DQ15-DQ0; byte mode data appears on DQ7-DQ0. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers. Standard control pins--chip enable (CE#), write enable (WE#), and output enable (OE#)--control normal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks, two 8 Mb banks with small and large sectors, and two 24 Mb banks of large sectors. Sector addresses are fixed, system software can be used to form user-defined bank groups. During an Erase/Program operation, any of the three non-busy banks may be read from. Note that only two banks can operate simultaneously. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The S71JLxxxHxx_00 can be organized as both a top and bottom boot sector configuration. Bank Bank 1 Bank 2 Bank 3 Bank 4 Megabits 8 Mb 24 Mb 24 Mb 8 Mb Sector Sizes Eight 8 Kbyte/4 Kword, Fifteen 64 Kbyte/32 Kword Forty-eight 64 Kbyte/32 Kword Forty-eight 64 Kbyte/32 Kword Eight 8 Kbyte/4 Kword, Fifteen 64 Kbyte/32 Kword S71JLxxxHxx_00 Features The SecSiTM (Secured Silicon) Sector is an extra 256 byte sector capable of being permanently locked by FASL or customers. The SecSi Customer Indicator Bit (DQ6) is permanently set to 1 if the part has been customer locked, permanently set to 0 if the part has been factory locked, and is 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory locked part. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (programmed through Spansion programming services), or both. Customer Lockable parts may utilize the SecSi Sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. 38 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where userwritten software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory devices), and more. Using DMS, user-written software does not need to interface with the Flash memory directly. Instead, the user's software accesses the Flash memory by calling one of only six functions. The device offers complete compatibility with the JEDEC 42.4 single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device status bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes. February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 39 Preliminary Product Selector Guide Part Number Speed Option Standard Voltage Range: VCC = 2.7-3.6 V 55 55 55 25 S71JLxxxHxx_00 70 70 70 30 85 85 85 40 Max Access Time (ns), tACC CE# Access (ns), tCE OE# Access (ns), tOE BLOCK DIAGRAM VCC VSS OE# BYTE# Mux A21-A0 Bank 1 Address Bank 1 Y-gate X-Decoder A21-A0 RY/BY# Bank 2 Address Bank 2 X-Decoder A21-A0 RESET# WE# CE# BYTE# WP#/ACC DQ0-DQ15 STATE CONTROL & COMMAND REGISTER Status DQ15-DQ0 DQ15-DQ0 DQ15-DQ0 Control Mux A21-A0 X-Decoder Bank 3 Address Bank 3 DQ15-DQ0 DQ15-DQ0 Y-gate X-Decoder A21-A0 Mux Bank 4 Address Bank 4 40 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary Pin Description A21-A0 DQ14-DQ0 DQ15/A-1 CE# OE# WE# WP#/ACC = = = = = = = 22 Addresses 15 Data Inputs/Outputs (x16-only devices) DQ15 (Data Input/Output, word mode), A-1 (LSB Address Input, byte mode) Chip Enable Output Enable Write Enable Hardware Write Protect/ Acceleration Pin RESET#=Hardware Reset Pin, Active Low Selects 8-bit or 16-bit mode Ready/Busy Output 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) Device Ground Pin Not Connected Internally BYTE# RY/BY# VCC VSS NC = = = = = LOGIC SYMBOL 22 A21-A0 DQ15-DQ0 (A-1) CE# OE# WE# WP#/ACC RESET# BYTE# RY/BY# 16 or 8 February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 41 Preliminary Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. S71JLxxxHxx_00 Device Bus Operations DQ15-DQ8 Operation Read Write Standby Output Disable Reset Sector Protect (Note 2) Sector Unprotect (Note 2) Temporary Sector Unprotect CE# L L VCC 0.3 V L X L L X OE# L H X H X H H X WE# H L X H X L L X RESET# H H VCC 0.3 V H L VID VID VID WP#/ACC L/H (Note 3) L/H L/H L/H L/H (Note 3) (Note 3) Addresses (Note 2) AIN AIN X X X SA, A6 = L, A1 = H, A0 = L SA, A6 = H, A1 = H, A0 = L AIN BYTE# = VIH DOUT DIN High-Z High-Z High-Z X X DIN BYTE# = VIL DQ14-DQ8 = HighZ, DQ15 = A-1 High-Z High-Z High-Z X X High-Z DQ7- DQ0 DOUT DIN High-Z High-Z High-Z DIN DIN DIN Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5 V, VHH = 9.0 0.5 V, X = Don't Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A21:A0 in word mode (BYTE# = VIH), A21:A-1 in byte mode (BYTE# = VIL). 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the "Sector/Sector Block Protection and Unprotection" section. 3. If WP#/ACC = VIL, sectors 0, 1, 140, and 141 remain protected. If WP#/ACC = VIH, protection on sectors 0, 1, 140, and 141 depends on whether they were last protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection". If WP#/ACC = VHH, all sectors will be unprotected. 42 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary Word/Byte Configuration The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic `1', the device is in word configuration, DQ15-DQ0 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic `0', the device is in byte configuration, and only data I/O pins DQ7-DQ0 are active and controlled by CE# and OE#. The data I/ O pins DQ14-DQ8 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to the AC "Read-Only Operations" section table for timing specifications and to 14 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to "Word/Byte Configuration" for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The "Byte/Word Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 3 indicates the address space that each sector occupies. Similarly, a "sector address" is the address bits required to uniquely select a sector. The "Command Definitions" section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. The device address space is divided into four banks. A "bank address" is the address bits required to uniquely select a bank. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The "AC Characteristics" section contains timing specification tables and timing diagrams for write operations. February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 43 Preliminary Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. See "Write Protect (WP#)" on page 51. for related information. Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15-DQ0. Standard read cycle timings apply in this mode. Refer to the "Autoselect Mode" section and "Autoselect Command Sequence" section sections for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 21 shows how read and write cycles may be initiated for simultaneous operation with zero latency. ICC6 and ICC7 in the "DC Characteristics" section table represent the current specifications for read-whileprogram and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the "DC Characteristics" section table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con- 44 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary trol signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I CC5 in the "DC Characteristics" section table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/ BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the "AC Characteristics" section tables for RESET# parameters and to 15 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 45 Preliminary Table 2. Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 Bank 1 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 Sector Address A21-A12 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001xxx 0000010xxx 0000011xxx 0000100xxx 0000101xxx 0000110xxx 0000111xxx 0001000xxx 0001001xxx 0001010xxx 0001011xxx 0001100xxx 0001101xxx 0001110xxx 0001111xxx S29JL064H Sector Architecture Sector Size (Kbytes/ Kwords) 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address Range 000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-009FFFh 00A000h-00BFFFh 00C000h-00DFFFh 00E000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh (x16) Address Range 00000h-00FFFh 01000h-01FFFh 02000h-02FFFh 03000h-03FFFh 04000h-04FFFh 05000h-05FFFh 06000h-06FFFh 07000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh 40000h-47FFFh 48000h-4FFFFh 50000h-57FFFh 58000h-5FFFFh 60000h-67FFFh 68000h-6FFFFh 70000h-77FFFh 78000h-7FFFFh 46 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary Table 2. Bank Sector SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 Bank 2 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 S29JL064H Sector Architecture (Continued) Sector Size (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address Range 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh (x16) Address Range 80000h-87FFFh 88000h-8FFFFh 90000h-97FFFh 98000h-9FFFFh A0000h-A7FFFh A8000h-AFFFFh B0000h-B7FFFh B8000h-BFFFFh C0000h-C7FFFh C8000h-CFFFFh D0000h-D7FFFh D8000h-DFFFFh E0000h-E7FFFh E8000h-EFFFFh F0000h-F7FFFh F8000h-FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh Sector Address A21-A12 0010000xxx 0010001xxx 0010010xxx 0010011xxx 0010100xxx 0010101xxx 0010110xxx 0010111xxx 0011000xxx 0011001xxx 0011010xxx 0011011xxx 0011000xxx 0011101xxx 0011110xxx 0011111xxx 0100000xxx 0100001xxx 0100010xxx 0101011xxx 0100100xxx 0100101xxx 0100110xxx 0100111xxx 0101000xxx 0101001xxx 0101010xxx 0101011xxx 0101100xxx 0101101xxx 0101110xxx 0101111xxx 0110000xxx 0110001xxx 0110010xxx 0110011xxx 0110100xxx 0110101xxx 0110110xxx 0110111xxx 0111000xxx 0111001xxx 0111010xxx 0111011xxx 0111100xxx 0111101xxx 0111110xxx 0111111xxx February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 47 Preliminary Table 2. Bank Sector SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 Bank 3 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 S29JL064H Sector Architecture (Continued) Sector Size (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 (x8) Address Range 400000h-40FFFFh 410000h-41FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh 500000h-50FFFFh 510000h-51FFFFh 520000h-52FFFFh 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 5A0000h-5AFFFFh 5B0000h-5BFFFFh 5C0000h-5CFFFFh 5D0000h-5DFFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh 600000h-60FFFFh 610000h-61FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh (x16) Address Range 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-28FFFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2FFFFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh Sector Address A21-A12 1000000xxx 1000001xxx 1000010xxx 1000011xxx 1000100xxx 1000101xxx 1000110xxx 1000111xxx 1001000xxx 1001001xxx 1001010xxx 1001011xxx 1001100xxx 1001101xxx 1001110xxx 1001111xxx 1010000xxx 1010001xxx 1010010xxx 1010011xxx 1010100xxx 1010101xxx 1010110xxx 1010111xxx 1011000xxx 1011001xxx 1011010xxx 1011011xxx 1011100xxx 1011101xxx 1011110xxx 1011111xxx 1100000xxx 1100001xxx 1100010xxx 1100011xxx 1100100xxx 1100101xxx 1100110xxx 1100111xxx 1101000xxx 1101001xxx 1101010xxx 1101011xxx 1101100xxx 1101101xxx 1101110xxx 1101111xxx 48 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary Table 2. Bank Sector SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 Bank 4 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 S29JL064H Sector Architecture (Continued) Sector Size (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 (x8) Address Range 700000h-70FFFFh 710000h-71FFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh 7A0000h-7AFFFFh 7B0000h-7BFFFFh 7C0000h-7CFFFFh 7D0000h-7DFFFFh 7E0000h-7EFFFFh 7F0000h-7F1FFFh 7F2000h-7F3FFFh 7F4000h-7F5FFFh 7F6000h-7F7FFFh 7F8000h-7F9FFFh 7FA000h-7FBFFFh 7FC000h-7FDFFFh 7FE000h-7FFFFFh (x16) Address Range 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3F8FFFh 3F9000h-3F9FFFh 3FA000h-3FAFFFh 3FB000h-3FBFFFh 3FC000h-3FCFFFh 3FD000h-3FDFFFh 3FE000h-3FEFFFh 3FF000h-3FFFFFh Sector Address A21-A12 1110000xxx 1110001xxx 1110010xxx 1110011xxx 1110100xxx 1110101xxx 1110110xxx 1110111xxx 1111000xxx 1111001xxx 1111010xxx 1111011xxx 1111100xxx 1111101xxx 1111110xxx 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111 Note: The address range is A21:A-1 in byte mode (BYTE#=VIL) or A21:A0 in word mode (BYTE#=VIH). Table 3. Bank 1 2 3 4 Bank Address A21-A19 000 001, 010, 011 100, 101, 110 111 Table 4. Device S29JL064H SecSiTM Sector Addresses Sector Size 256 bytes (x8) Address Range 000000h-0000FFh (x16) Address Range 000000h-00007Fh Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 49 Preliminary Sector/Sector Block Protection and Unprotection (Note: For the following discussion, the term "sector" applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table 5). The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/ unprotection can be implemented via two methods. Table 5. S71JLxxxHxx_00 Boot Sector/Sector Block Addresses for Protection/Unprotection Sector/ Sector Block Size 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 192 (3x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8-SA10 SA11-SA14 SA15-SA18 SA19-SA22 SA23-SA26 SA27-SA30 SA31-SA34 SA35-SA38 SA39-SA42 SA43-SA46 SA47-SA50 SA51-SA54 SA55-SA58 SA59-SA62 SA63-SA66 SA67-SA70 SA71-SA74 SA75-SA78 SA79-SA82 SA83-SA86 SA87-SA90 SA91-SA94 SA95-SA98 SA99-SA102 SA103-SA106 A21-A12 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001XXX, 0000010XXX, 0000011XXX, 00001XXXXX 00010XXXXX 00011XXXXX 00100XXXXX 00101XXXXX 00110XXXXX 00111XXXXX 01000XXXXX 01001XXXXX 01010XXXXX 01011XXXXX 01100XXXXX 01101XXXXX 01110XXXXX 01111XXXXX 10000XXXXX 10001XXXXX 10010XXXXX 10011XXXXX 10100XXXXX 10101XXXXX 10110XXXXX 10111XXXXX 11000XXXXX 50 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary Table 5. S71JLxxxHxx_00 Boot Sector/Sector Block Addresses for Protection/Unprotection (Continued) Sector/ Sector Block Size 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 256 (4x64) Kbytes 192 (3x64) Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes 8 Kbytes Sector SA107-SA110 SA111-SA114 SA115-SA118 SA119-SA122 SA123-SA126 SA127-SA130 SA131-SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 A21-A12 11001XXXXX 11010XXXXX 11011XXXXX 11100XXXXX 11101XXXXX 11110XXXXX 1111100XXX, 1111101XXX, 1111110XXX 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111 Sector protect/Sector Unprotect requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 26 shows the timing diagram. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. Note that the sector unprotect algorithm unprotects all sectors in parallel. All previously protected sectors must be individually re-protected. To change data in protected sectors efficiently, the temporary sector unprotect function is available. See "Temporary Sector Unprotect" . The device is shipped with all sectors unprotected. Optional Spansion programming service enable programming and protecting sectors at the factory prior to shipping the device. Contact your local sales office for details. It is possible to determine whether a sector is protected or unprotected. See the "Autoselect Mode" section section for details. Write Protect (WP#) The Write Protect function provides a hardware method of protecting without using VID. This function is one of two provided by the WP#/ACC pin. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in sectors 0, 1, 140, and 141, independently of whether those sectors were protected or unprotected using the method described in "Sector/ Sector Block Protection and Unprotection". If the system asserts VIH on the WP#/ACC pin, the device reverts to whether sectors 0, 1, 140, and 141 were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in "Sector/Sector Block Protection and Unprotection". Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 51 Preliminary Table 6. WP# Input Voltage WP#/ACC Modes Device Mode VIL VIH VHH Disables programming and erasing in SA0, SA1, SA140, and SA141 Enables programming and erasing in SA0, SA1, SA140, and SA141, dependent on whether they were last protected or unprotected. Enables accelerated progamming (ACC). See "Accelerated Program Operation" on page 44.. Temporary Sector Unprotect (Note: For the following discussion, the term "sector" applies to both sectors and sector blocks. A sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see Table 5). This feature allows temporary unprotection of previously protected sectors to change data in-system. The Temporary Sector Unprotect mode is activated by setting the RESET# pin to "VID" section. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 2 shows the algorithm, and Figure 25 shows the timing diagrams, for this feature. If the WP#/ACC pin is at VIL, sectors 0, 1, 140, and 141 will remain protected during the Temporary sector Unprotect mode. START RESET# = VID (Note 1) Perform Erase or Program Operations RESET# = VIH Temporary Sector Unprotect Completed (Note 2) Notes: 1. All protected sectors unprotected (If WP#/ACC = VIL, sectors 0, 1, 140, and 141 will remain protected). 2. All previously protected sectors are protected once again. Figure 1. Temporary Sector Unprotect Operation 52 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary START PLSCNT = 1 RESET# = VID Wait 1 ms Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address START PLSCNT = 1 RESET# = VID Wait 1 ms Temporary Sector Unprotect Mode No First Write Cycle = 60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Wait 150 s Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Read from sector address with A6 = 0, A1 = 1, A0 = 0 No No First Write Cycle = 60h? Yes All sectors protected? Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0 Temporary Sector Unprotect Mode Increment PLSCNT Reset PLSCNT = 1 Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0 No No PLSCNT = 25? Yes Data = 01h? Increment PLSCNT Yes No Yes No Read from sector address with A6 = 1, A1 = 1, A0 = 0 Set up next sector address Device failed Protect another sector? No Remove VID from RESET# PLSCNT = 1000? Yes Data = 00h? Yes Device failed Write reset command Last sector verified? Yes No Sector Protect Algorithm Sector Protect complete Sector Unprotect Algorithm Remove VID from RESET# Write reset command Sector Unprotect complete Figure 2. In-System Sector Protect/Unprotect Algorithms SecSiTM (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 256 bytes in length, and uses a SecSi Sector Indicator February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 53 Preliminary Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. The product is available with the SecSi Sector either factory locked or customer lockable. The factory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a "1." The customer-lockable version is shipped with the SecSi Sector unprotected, allowing customers to utilize the that sector in any manner they choose. The customer-lockable version has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a "0." Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The SecSi Customer Indicator Bit (DQ6) is permanently set to 1 if the part has been customer locked, permanently set to 0 if the part has been factory locked, and is 0 if customer lockable. The system accesses the SecSi Sector Secure through a command sequence (see "Enter SecSiTM Sector/Exit SecSi Sector Command Sequence"). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the first 256 bytes of Sector 0. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. Factory Locked: SecSi Sector Programmed and Protected At the Factory In a factory locked device, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is preprogrammed with both a random number and a secure ESN. The 8word random number is at addresses 000000h-000007h in word mode (or 000000h-00000Fh in byte mode). The secure ESN is programmed in the next 8 words at addresses 000008h-00000Fh (or 000010h-00001Fh in byte mode). The device is available preprogrammed with one of the following: A random, secure ESN only Customer code through Spansion programming services Both a random, secure ESN and customer code through Spansion programming services Contact an your local sales office for details on using Spansion programming services. Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space. The SecSi Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The SecSi Sector area can be protected using one of the following procedures: Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, except that RESET# may be at either VIH or VID. This allows in-system protec- 54 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary tion of the SecSi Sector Region without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 3. Once the SecSi Sector is locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. START RESET# = VIH or VID Wait 1 ms Write 60h to any address If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected. Remove VIH or VID from RESET# Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Write reset command SecSi Sector Protect Verify complete Figure 3. SecSi Sector Protect Verify Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 11 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 55 Preliminary Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 7-10. To terminate reading CFI data, the system must write the reset command.The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 7-10. The system must write the reset command to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100. Contact your local sales office for copies of these documents. Table 7. CFI Query Identification String Addresses (Word Mode) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Addresses (Byte Mode) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Description Query Unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) 56 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary Table 8. Addresses (Word Mode) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Addresses (Byte Mode) 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch Data 0027h 0036h 0000h 0000h 0003h 0000h 0009h 0000h 0005h 0000h 0004h 0000h System Interface String Description VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported) Table 9. Addresses (Word Mode) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Addresses (Byte Mode) 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h Data 0017h 0002h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 007Dh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h Device Geometry Definition Description Device Size = 2N byte Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100) Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100) February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 57 Preliminary Table 10. Addresses (Word Mode) 40h 41h 42h 43h 44h 45h Addresses (Byte Mode) 80h 82h 84h 86h 88h 8Ah Primary Vendor-Specific Extended Query Data Description Query-unique ASCII string "PRI" Major version number, ASCII (reflects modifications to the silicon) Minor version number, ASCII (reflects modifications to the CFI table) Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode Simultaneous Operation 00 = Not Supported, X = Number of Sectors (excluding Bank 1) Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 00h = Uniform device, 01h = 8 x 8 Kbyte Sectors, Top And Bottom Boot with Write Protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h= Both Top and Bottom Program Suspend 0 = Not supported, 1 = Supported Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks Bank 1 Region Information X = Number of Sectors in Bank 1 Bank 2 Region Information X = Number of Sectors in Bank 2 Bank 3 Region Information X = Number of Sectors in Bank 3 Bank 4 Region Information X = Number of Sectors in Bank 4 0050h 0052h 0049h 0031h 0033h 000Ch 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 8Ch 8Eh 90h 92h 94h 96h 98h 9Ah 9Ch 0002h 0001h 0001h 0004h 0077h 0000h 0000h 0085h 0095h 4Fh 9Eh 0001h 50h 57h 58h 59h 5Ah 5Bh A0h AEh B0h B2h B4h B6h 0001h 0004h 0017h 0030h 0030h 0017h 58 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. Table 11 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the "AC Characteristics" section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the "Erase Suspend/Erase Resume Commands" section section for more information. The system must issue the reset command to return a bank to the read (or erasesuspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the next section, "Reset Command" section, for more information. See also "Requirements for Reading Array Data" section in the "Device Bus Operations" section section for more information. The "Read-Only Operations" section table provides the read parameters, and 14 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don't cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 59 Preliminary If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in another bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read any number of autoselect codes without reinitiating the command sequence. Table 11 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SA). Table 3 shows the address range and bank number associated with each sector. The system must write the reset command to return to the read mode (or erasesuspend-read mode if the bank was previously in Erase Suspend). Enter SecSiTM Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 11 shows the address and data requirements for both command sequences. See also "SecSiTM (Secured Silicon) Sector Flash Memory Region" for further information. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. Byte/Word Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 11 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the "Write Operation Status" section section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program 60 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a program operation is in progress. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from "0" back to a "1." Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1." Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 11 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (See Table 12). The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH for any operation other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. 4 illustrates the algorithm for the program operation. Refer to the "Erase and Program Operations" section table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams. February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 61 Preliminary START Write Program Command Sequence Embedded Program algorithm in progress Data Poll from System Verify Data? No Yes No Increment Address Last Address? Yes Programming Completed Note: See Table 11 for program command sequence. Figure 4. Program Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 11 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the "Write Operation Status" section section for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when an erase operation is in progress. 62 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary 5 illustrates the algorithm for the erase operation. Refer to the "Erase and Program Operations" section tables in the AC Characteristics section for parameters, and Figure 20 section for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 11 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 80 s occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 80 s, otherwise erasure may begin. Any sector erase address and command following the exceeded timeout may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# or CE# pulse (first rising edge) in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the "Write Operation Status" section section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when an erase operation is in progress. 5 illustrates the algorithm for the erase operation. Refer to the "Erase and Program Operations" section tables in the AC Characteristics section for parameters, and Figure 20 section for timing diagrams. February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 63 Preliminary START Write Erase Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed Notes: 1. See Table 11 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Figure 5. Erase Operation Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the 80 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. The bank address must contain one of the sectors currently selected for erase. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the "Write Operation Status" section section for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program 64 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary operation using the DQ7 or DQ6 status bits, just as in the standard Byte Program operation. Refer to the "Write Operation Status" section section for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. Refer to the "Autoselect Mode" section and "Autoselect Command Sequence" section sections for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Table 11. Command Sequence (Note 1) Read (Note 6) Reset (Note 7) Autoselect (Note 8) Manufacturer ID Device ID (Note 9) SecSi Sector Factory Protect (Note 10) Sector/Sector Block Protect Verify (Note 11) Word Byte Word Byte Word Byte Word Cycles First Addr RA XXX 555 AAA 555 AAA 555 AAA 555 Data RD F0 AA AA AA AA AA AA AA AA A0 90 AA AA B0 30 98 S29JL064H Command Definitions Second Addr Data Bus Cycles (Notes 2-5) Third Fourth Addr Data Addr Data Fifth Addr Data Sixth Addr Data 1 1 4 6 4 4 3 4 4 3 2 2 6 6 1 1 1 2AA 555 2AA 555 2AA 555 2AA 55 55 55 55 55 55 55 55 PD 00 55 55 (BA)555 (BA)AAA (BA)555 (BA)AAA (BA)555 (BA)AAA (BA)555 90 90 90 90 88 90 A0 20 (BA)X00 (BA)X01 (BA)X02 (BA)X03 (BA)X06 (SA)X02 (SA)X04 01 7E 80/ 00 00/ 01 (BA)X0E (BA)X1C 02 (BA)X0F (BA)X1E 01 Byte AAA 555 AAA 555 AAA 555 AAA 555 AAA XXX XXX 555 AAA 555 AAA BA BA 55 AA 555 2AA 555 2AA 555 2AA 555 2AA 555 PA XXX 2AA 555 2AA 555 (BA)AAA 555 AAA 555 AAA 555 AAA 555 AAA Word Byte Word Exit SecSi Sector Region Byte Word Program Byte Word Unlock Bypass Byte Unlock Bypass Program (Note 12) Unlock Bypass Reset (Note 13) Word Chip Erase Byte Word Sector Erase Byte Erase Suspend (Note 14) Erase Resume (Note 15) Word CFI Query (Note 16) Byte Enter SecSi Sector Region Legend: XXX PA 00 PD 555 AAA 555 AAA 80 80 555 AAA 555 AAA AA AA 2AA 555 2AA 555 55 55 555 AAA SA 10 30 X = Don't care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A21-A12 uniquely select any sector. Refer to Table 3 for information on sector addresses. BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. A21-A19 uniquely select a bank. February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 65 Preliminary Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the read cycle and the fourth, fifth, and sixth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits DQ15-DQ8 are don't care in command sequences, except for RD and PD. 5. Unless otherwise noted, address bits A21-A11 are don't cares for unlock and command cycles, unless SA or PA is required. 6. No unlock or command cycles required when bank is reading array data. 7. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information). 8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address to obtain the manufacturer ID, device ID, or SecSi Sector factory protect information. Data bits DQ15-DQ8 are don't care. While reading the autoselect addresses, the bank address must be the same until a reset command is given. See the "Autoselect Command Sequence" section section for more information. 9. The device ID must be read across the fourth, fifth, and sixth cycles. 10.The data is 80h for factory locked, 40h for customer locked, and 00h for not factory/customer locked. 11.The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 12.The Unlock Bypass command is required prior to the Unlock Bypass Program command. 13.The Unlock Bypass Reset command is required to return to the read mode when the bank is in the unlock bypass mode. 14.The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 15.The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16.Command is valid when device is ready to read array data or when device is in autoselect mode. Write Operation Status The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 12 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then that bank returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. The system must provide 66 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ15-DQ0 (or DQ7-DQ0 for x8-only device) on the following read cycles. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ15-DQ8 (DQ7-DQ0 for x8only device) while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ15-DQ0 may be still invalid. Valid data on DQ15-DQ0 (or DQ7-DQ0 for x8-only device) will appear on successive read cycles. Table 12 shows the outputs for Data# Polling on DQ7. 6 shows the Data# Polling algorithm. 22 in the "AC Characteristics" section shows the Data# Polling timing diagram. February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 67 Preliminary START Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5. Figure 6. Data# Polling Algorithm RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read mode. Table 12 shows the outputs for RY/BY#. 68 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on "DQ7: Data# Polling" section). If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 69 Preliminary START Read Byte (DQ7-DQ0) Address =VA Read Byte (DQ7-DQ0) Address =VA Toggle Bit = Toggle? Yes No No DQ5 = 1? Yes Read Byte Twice (DQ7-DQ0) Address = VA Toggle Bit = Toggle? Yes Program/Erase Operation Not Complete, Write Reset Command No Program/Erase Operation Complete Note: The system should recheck the toggle bit even if DQ5 = "1" because the toggle bit may stop toggling as DQ5 changes to "1." See the subsections on DQ6 and DQ2 for more information. Figure 7. Toggle Bit Algorithm DQ2: Toggle Bit II The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 12 to compare outputs for DQ2 and DQ6. 7 shows the toggle bit algorithm in flowchart form, and the section "DQ2: Toggle Bit II" explains the algorithm. See also the "DQ6: Toggle Bit I" section subsection. 70 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary 23 shows the toggle bit timing diagram. 24 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to 7 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ15-DQ0 (or DQ7-DQ0 for x8-only device) at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ15-DQ0 (or DQ7-DQ0 for x8-only device) on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of 7). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1," indicating that the program or erase cycle was not successfully completed. The device may output a "1" on DQ5 if the system tries to program a "1" to a location that was previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a "1." Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a "0" to a "1." If the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor DQ3. See also the "Sector Erase Command Sequence" section section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is "1," the Embedded Erase February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 71 Preliminary algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0," the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 12 shows the status of DQ3 relative to the other status bits. Table 12. Write Operation Status Status Standard Mode Embedded Program Algorithm Embedded Erase Algorithm Erase Erase-Suspend- Suspended Sector Read Non-Erase Suspended Sector Erase-Suspend-Program DQ7 (Note 2) DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 2) No toggle Toggle Toggle Data N/A RY/BY# 0 0 1 1 0 Erase Suspend Mode Notes: 1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank. 72 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary Absolute Maximum Ratings Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +125C Voltage with Respect to Ground VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V OE# and RESET# (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +12.5 V WP#/ACC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +10.5 V All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to - 2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 8. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 9. 2. Minimum DC input voltage on pins OE#, RESET#, and WP#/ACC is -0.5 V. During voltage transitions, OE#, WP#/ACC, and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC input voltage on WP#/ ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 20 ns +0.8 V -0.5 V -2.0 V 20 ns 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns 20 ns Figure 8. Maximum Negative Overshoot Waveform Figure 9. Maximum Positive Overshoot Waveform OPERATING RANGES Wireless (W) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C VCC Supply Voltages VCC for standard voltage range . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 73 Preliminary DC Characteristics Table 13. Parameter Symbol ILI ILIT ILO ILR Parameter Description Input Load Current OE# and RESET# Input Load Current Output Leakage Current Reset Leakage Current CMOS Compatible Test Conditions Min Typ Max 1.0 35 1.0 35 10 2 10 2 15 0.2 0.2 0.2 Byte Word Byte Word 21 21 21 21 17 -0.5 0.7 x VCC 16 4 16 4 30 5 5 5 45 45 45 45 35 0.8 VCC + 0.3 9.5 12.5 0.45 0.85 VCC VCC-0.4 2.3 2.5 V mA A A A mA mA mA V V V V V V mA Unit A A A A VIN = VSS to VCC, VCC = VCC max VCC = VCC max, OE# = VIH; OE# or RESET# = 12.5 V VOUT = VSS to VCC, VCC = VCC max, OE# = VIH VCC = VCC max; RESET# = 12.5 V CE# = VIL, OE# = VIH, Byte Mode CE# = VIL, OE# = VIH, Word Mode 5 MHz 1 MHz 5 MHz 1 MHz ICC1 VCC Active Read Current (Notes 1, 2) VCC Active Write Current (Notes 2, 3) VCC Standby Current (Note 2) VCC Reset Current (Note 2) Automatic Sleep Mode (Notes 2, 4) VCC Active Read-While-Program Current (Notes 1, 2) VCC Active Read-While-Erase Current (Notes 1, 2) VCC Active Program-While-EraseSuspended Current (Notes 2, 5) Input Low Voltage Input High Voltage Voltage for WP#/ACC Sector Protect/Unprotect and Program Acceleration Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage (Note 5) ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICC8 VIL VIH VHH VID VOL VOH1 VOH2 VLKO CE# = VIL, OE# = VIH, WE# = VIL CE#, RESET# = VCC 0.3 V RESET# = VSS 0.3 V VIH = VCC 0.3 V; VIL = VSS 0.3 V CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH VCC = 3.0 V 10% VCC = 3.0 V 10% IOL = 2.0 mA, VCC = VCC min IOH = -2.0 mA, VCC = VCC min IOH = -100 A, VCC = VCC min 8.5 11.5 Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. 74 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary Zero-Power Flash 25 Supply Current in mA 20 15 10 5 0 0 500 1000 1500 2000 Time in ns 2500 3000 3500 4000 Note: Addresses are switching at 1 MHz Figure 10. 12 ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) 3.6 V 10 2.7 V Supply Current in mA 8 6 4 2 0 1 2 3 Frequency in MHz 4 5 Note: T = 25 xC Figure 11. Typical ICC1 vs. Frequency February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 75 Preliminary Test Conditions 3.3 V Device Under Test CL 6.2 k 2.7 k Note: Diodes are IN3064 or equivalent Figure 12. Table 14. Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels Test Setup Test Specifications All Speeds 1 TTL gate 30 5 0.0-3.0 1.5 1.5 pF ns V V V Unit Switching Waveforms Table 15. Key To Switching Waveforms WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS 3.0 V 0.0 V Input 1.5 V Measurement Level 1.5 V Output Figure 13. 76 Input Waveforms and Measurement Levels T bl 1 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary AC Characteristics Read-Only Operations Parameter JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Std. tRC tACC tCE tOE tDF tDF tOH Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High Z (Notes 1, 3) Output Enable to Output High Z (Notes 1, 3) Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Output Enable Hold Time (Note 1) Read Toggle and Data# Polling CE#, OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Min Min Min 5 Speed Options 55 55 55 55 25 70 70 70 70 30 16 16 0 0 10 85 85 85 85 40 Unit ns ns ns ns ns ns ns ns ns tOEH Notes: 1. Not 100% tested. 2. See 12 and Table 14 for test specifications 3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF tRC Addresses CE# tRH tRH OE# tOEH WE# HIGH Z Data RESET# RY/BY# Valid Data tCE tOH HIGH Z tOE tDF Addresses Stable tACC 0V Figure 14. Read Operation Timings February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 77 Preliminary Hardware Reset (RESET#) Parameter JEDEC Std tReady tReady tRP tRH tRPD tRB Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Max Max Min Min Min Min All Speed Options 20 500 500 50 20 0 Unit s ns ns ns s ns Note: Not 100% tested. RY/BY# CE#f, OE# tRH RESET# tRP tReady Reset T imings NOT during E mbedded Algorithms Reset T imings during E mbedded Algorithms tReady RY/BY# tRB CE#f, OE# RESET# tRP Figure 15. Reset Timings Word/Byte Configuration (BYTE#) Parameter JEDEC Std. tELFL/tELFH tFLQZ tFHQV Description CE# to BYTE# Switching Low or High BYTE# Switching Low to Output HIGH Z BYTE# Switching High to Output Active Max Max Min 55 55 Speed Options 70 5 16 70 85 85 Unit ns ns ns 78 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary CE# OE# BYTE# tELFL BYTE# Switching from word to byte mode DQ14-DQ0 Data Output (DQ14-DQ0) DQ15 Output tFLQZ Data Output Address Input DQ15/A-1 tELFH BYTE# BYTE# Switching from byte to word mode DQ14-DQ0 Data Output Address Input tFHQ Data Output (DQ14-DQ0) DQ15 Output DQ15/A-1 Figure 16. BYTE# Timings for Read Operations CE# The falling edge of the last WE# signal WE# BYTE# tSET (tAS) tHOLD (tAH) Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. Figure 17. BYTE# Timings for Write Operations February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 79 Preliminary Erase and Program Operations Parameter JEDEC tAVAV tAVWL Std tWC tAS tASO tWLAX tAH tAHT tDVWH tWHDX tDS tDH tOEPH tGHWL tELWL tWHEH tWLWH tWHDL tGHWL tCS tCH tWP tWPH tSR/W tWHWH1 tWHWH1 tWHWH2 tWHWH1 tWHWH1 tWHWH2 tVCS tRB tBUSY Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information. Speed Options Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE# or OE# high during toggle bit polling Data Setup Time Data Hold Time Output Enable High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations Programming Operation (Note 2) Accelerated Programming Operation, Word or Byte (Note 2) Sector Erase Operation (Note 2) VCC Setup Time (Note 1) Write Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay Byte Word Min Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ Min Min Max 25 25 30 30 55 55 70 70 0 15 40 0 40 0 20 0 0 0 30 30 0 5 7 4 0.4 50 0 90 35 30 45 45 85 85 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s sec s ns ns 80 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# tWPH Read Status Data (last two cycles) PA PA tCH tWHWH1 A0h Status DOUT tRB VCC tVCS Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode Figure 18. Program Operation Timings VHH WP#/ACC VIL or VIH tVHH tVHH VIL or VIH Figure 19. Accelerated Program Timing Diagram February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 81 Preliminary Erase Command Sequence (last two cycles) tAS Addresses 2AAh SA 555h for chip erase Read Status Data VA tAH VA CE# OE# tWP WE# tCS tDS tCH tWPH tWHWH2 t Data 55h 30h 10 for Chip Erase Status DOUT tBUSY RY/BY# tVCS VCC tRB Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status". 2. These waveforms are for the word mode. Figure 20. Chip/Sector Erase Operation Timings tWC Addresses Valid PA tRC Valid RA tWC Valid PA tWC Valid PA tAH tACC CE# tCE tOE OE# tOEH tWP WE# tWPH tDS tDH Data Valid In tCPH tCP tGHWL tDF tOH Valid Out Valid In Valid In tSR/W WE# Controlled Write Cycle Read Cycle CE# or CE2# Controlled Write Cycles Figure 21. 82 Back-to-back Read/Write Cycle Timings S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary Addresses VA tACC tCE VA VA CE# tCH OE# tOEH WE# tOH DQ7 High Z tOE Complement Complement Tru Valid Data High Z DQ0-DQ6 tBUSY RY/BY# Status Data Status Data True Valid Data Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycl Figure 22. Data# Polling Timings (During Embedded Algorithms) tAHT Addresses tAS tAHT tASO CE# tOEH WE# tOEPH OE# tDH DQ6/DQ2 Valid Data Valid Status tCEPH tOE Valid Status Valid Status Valid Data (first read) RY/BY# (second read) (stops toggling) Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle Figure 23. Toggle Bit Timings (During Embedded Algorithms) February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 83 Preliminary Enter Embedded Erasing WE# Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete Erase Suspend Read DQ6 DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6. Figure 24. DQ2 vs. DQ6 Temporary Sector Unprotect Parameter JEDEC Std tVIDR tVHH tRSP tRRB Description VID Rise and Fall Time (see Note) VHH Rise and Fall Time (see Note) RESET# Setup Time for Temporary Sector Unprotect RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect Min Min Min Min All Speed Options 500 250 4 4 Unit ns ns s s Note: Not 100% tested. VID RESET# VSS, VIL, or VIH tVIDR Program or Erase Command Sequence CE# tVIDR VID VSS, VIL, or VIH WE# tRSP RY/BY# tRRB Figure 25. Temporary Sector Unprotect Timing Diagram 84 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary VID VIH RESET# SA, A6, A1, A0 Valid* Sector Group Protect/Unprotect Valid* Verify 40h Valid* Data 1 s CE# 60h 60h Status Sector Group Protect: 150 s Sector Group Unprotect: 15 ms WE# OE# Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 85 Preliminary Alternate CE# Controlled Erase and Program Operations Parameter JEDEC tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH1 tWHWH2 Std. tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH1 tWHWH2 Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Programming Operation (Note 2) Accelerated Programming Operation, Word or Byte (Note 2) Sector Erase Operation (Note 2) Byte Word Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ 25 25 5 7 4 0.4 30 30 55 55 Speed Options 70 70 0 40 40 0 0 0 0 40 30 45 45 45 85 85 Unit ns ns ns ns ns ns ns ns ns ns s s sec Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information. 86 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling PA Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase tAS tAH tWHWH1 or 2 tBUSY DQ7# DOUT RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode. Figure 27. Alternate CE# Controlled Write (Erase/Program) Operation Timings February 25, 2004 S71JLxxxHxx_00A1 S29JL064H 87 Preliminary Erase And Programming Performance Parameter Sector Erase Time Chip Erase Time Word Program Time Accelerated Byte/Word Program Time Accelerated Chip Programming Time Byte Program Time Chip Program Time (Note 3) Notes: Byte Mode Word Mode Typ (Note 1) 0.4 56 7 4 10 5 42 28 210 120 30 150 126 84 Max (Note 2) 5 Unit sec sec s s sec s sec Excludes system level overhead (Note 5) Comments Excludes 00h programming prior to erasure (Note 4) 1. Typical program and erase times assume the following conditions: 25C, 3.0 V VCC, 100,000 cycles; checkerboard data pattern. 2. Under worst case conditions of 90C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 11 for further information on command definitions. 6. The device has a minimum cycling endurance of 100,000 cycles per sector. 7. Contact the local sales office for minimum cycling endurance values in specific applications and operating conditions. Latchup Characteristics Description Input voltage with respect to VSS on all pins except I/O pins (including OE# and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Min -1.0 V -1.0 V -100 mA Max 12.5 V VCC + 1.0 V +100 mA Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. 88 S29JL064H S71JLxxxHxx_00A1 February 25, 2004 Preliminary 16 Mb SRAM (supplier 1) 16 Megabit (1Mb x 16 bit) CMOS SRAM Functional Description CE1# H X X L L L L L L L L CS2 X L X H H H H H H H H OE# X X X H H L L L X X X WE# X X X H H H H H L L L LB# X X H L X L H L L H L UB# X X H X L H L L H L L IO0~7 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din IO8~15 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Standby Standby Standby Active Active Active Active Active Active Active Active Note: X means don't care (must be low or high state). Absolute Maximum Ratings Item Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Power Dissipation Storage Temperature Operating Temperature Symbol VIN,VOUT VCC PD TSTG TA Ratings -0.2 to VCC+0.3V (Max. 3.6V) -0.2 to 3.6V 1.0 -85 to 150 -40 to 85 Unit V V W C C Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. February 25, 2004 S71JLxxxHxx_00A1 16 Mb SRAM (supplier 1) 89 Preliminary DC Characteristics Recommended DC Operating Conditions (Note 1) Item Supply voltage Ground Input high voltage Input low voltage Symbol VCC VSS VIH VIL Min 2.7 0 2.2 -0.2 (Note 3) Typ 3.0 0 Max 3.3 0 VCC+0.2 (Note 2) 0.6 Unit V V V V Notes: 1. TA = -40 to 85C, otherwise specified. 2. Overshoot: Vcc+2.0V in case of pulse width 20ns. 3. Undershoot: -2.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested. Capacitance (f=1MHz, TA=25C) Item Input capacitance Input/Output capacitance Symbol CIN CIO Test Condition VIN=0V VIO=0V Min Max 8 10 Unit pF pF Note: Capacitance is sampled, not 100% tested DC Operating Characteristics Item Input leakage current Output leakage current Symbol ILI ILO ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current (CMOS) VOL VOH ISB1 Test Conditions VIN=VSS to VCC CE1#=VIH, CS2=VIL or OE#=VIH or WE#=VIL or LB#=UB#=VIH, VIO=VSS to VCC Cycle time=1s, 100% duty, IIO=0mA, CE1#0.2V, LB#0.2V and/or UB#0.2V, CS2VCC-0.2V, VIN0.2V or VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CE1#=VIL, CS2=VIH, LB#=VIL and/or UB#=VIL, VIN=VIL or VIH IOL = 2.1mA IOH = -1.0mA Other input = 0-VCC 1. CE1#VCC-0.2V, CS2VCC-0.2V (CE1# controlled) or 2. 0VCS20.2V (CS2 controlled) 70ns Min -1 -1 Typ (Note) Max 1 1 Unit A A - - 5 A 2.4 - -5.0 30 0.4 25 mA V V A Note: Typical values are measured at VCC=2.0V, TA=25C and not 100% tested. 90 16 Mb SRAM (supplier 1) S71JLxxxHxx_00A1 February 25, 2004 Preliminary AC Characteristics Read/Write Charcteristics (VCC=2.7-3.3V) Parameter List Read cycle time Address access time Chip select to output Output enable to valid output LB#, UB# valid to data output Read Chip select to low-Z output Output enable to low-Z output LB#, UB# enable to low-Z output Output hold from address change Chip disable to high-Z output OE# disable to high-Z output UB#, LB# disable to high-Z output Write cycle time Chip select to end of write Address set-up time Address valid to end of write Write pulse width Write Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z LB#, UB# valid to end of write Symbol tRC tAA tCO1, tCO2 tOE tBA tLZ1, tLZ2 tOLZ tBLZ tOH tHZ1, tHZ2 tOHZ tBHZ tWC tCW1, tCW2 tAS tAW tWP tWR tWHZ tDW tDH tOW tBW Min 70 10 5 10 10 0 0 0 70 60 0 60 50 0 0 30 0 5 60 Max 70 70 35 70 25 25 25 20 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data Retention Characteristics Item VCC for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR Test Condition CE1#VCC-0.2V (Note 1), VIN0V VCC=1.5V, CE1#V-0.2V (Note 1), VIN0V See data retention waveform Min 1.5 0 tRC Typ 1.0 (Note 2) Max 3.3 15 Unit V A ns Notes: 1. CE1#VCC-0.2, CS2VCC-0.2V (CE1# controlled) or 0CS2-0.2V (CS2 controlled) 2. Typical values are measured at TA=26C and not 100% tested. February 25, 2004 S71JLxxxHxx_00A1 16 Mb SRAM (supplier 1) 91 Preliminary Timing Diagrams tRC Address tOH Data Out Previous Data Valid tAA Data Valid Figure 28. Timing Waveform of Read Cycle(1) (address controlled, CD#1=OE#=VIL, CS2=WE#=VIH, UB# and/or LB#=VIL) tRC Address tAA tCO1 tOH CS1# CS2 tCO2 tBA tHZ UB#, LB# OE# tOLZ tBLZ tLZ tOE tBHZ tOHZ Data Valid Data out High-Z Notes: 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. Figure 29. Timing Waveform of Read Cycle(2) (WE#=VIH) 92 16 Mb SRAM (supplier 1) S71JLxxxHxx_00A1 February 25, 2004 Preliminary tWC Address tCW(2) CS1# tWR(4) CS2 tAW tBW tWP(1) tAS(3) Data in High-Z tWHZ Data out Data Undefined UB#, LB# WE# tDW tDH High-Z tOW Data Valid Figure 30. Timing Waveform of Write Cycle(1) (WE# controlled) tWC Address tAS(3) CS1# tAW CS 2 tBW tWP(1) WE# tDW Data in tDH tCW(2) tWR(4) UB#, LB# Data Valid Data out High-Z High-Z Figure 31. Timing Waveform of Write Cycle(2) (CS# controlled) February 25, 2004 S71JLxxxHxx_00A1 16 Mb SRAM (supplier 1) 93 Preliminary tWC Address tCW(2) CS1# tAW CS2 UB#, LB# tBW tAS(3) tWP(1) tWR(4) WE# tDW Data in tDH Data Valid High-Z Data out High-Z Notes: 1. A write occurs during the overlap(tWP) of low CS1# and low WE#. A write begins when CS1# goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write ends at the earliest transition when CS1# goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1# going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS1# or WE# going high. Figure 32. Timing Waveform of Write Cycle(3) (UB#, LB# controlled) 94 16 Mb SRAM (supplier 1) S71JLxxxHxx_00A1 February 25, 2004 Preliminary CS1# Controlled VCC 2.7V tSDR Data Retention Mode tRDR 2.2V VDR CS1# GND CS2 Controlled VCC 2.7V CS2 CS1# VCC - 0.2V, CS2 VCC-0.2V Data Retention Mode tSDR tRDR VDR 0.4V GND CS2 0.2V Figure 33. Data Retention Waveform February 25, 2004 S71JLxxxHxx_00A1 16 Mb SRAM (supplier 1) 95 Preliminary 8 Mb pSRAM (supplier 2) 8 Megabit (512 K x 16 bit) Ultra-low Power Asynchronous CMOS Pseudo SRAM Features Single Wide Power Supply Range -- 2.7 to 3.6 Volts Very low standby current -- 65A at 3.0V (Max) Simple memory control -- Dual Chip Enables (CE1# and CE2) -- Byte control for independent byte operation -- Output Enable (OE#) for memory expansion Very fast output enable access time -- 35ns OE# access time Automatic power down to standby mode TTL compatible three-state output driver Operating Temperature -- -40C to +85C Power Supply -- 2.3V - 3.6V Speed -- 70ns @ 2.7V General Description The S71JL064H80--10/11/12 contains an integrated memory device containing a low power 8 Mbit SRAM built using a self-refresh DRAM array organized as 512,288 words by 16 bits. It is designed to be identical in operation and interface to standard 6T SRAMS. The device is designed for low standby and operating current and includes a power-down feature to automatically enter standby mode. The device operates with two chip enable (CE1# and CE2) controls and output enable (OE#) to allow for easy memory expansion. Byte controls (UB# and LB#) allow the upper and lower bytes to be accessed independently and can also be used to deselect the device. The S71JL064H80 is optimal for various applications where low-power is critical such as battery backup and hand-held devices. The device can operate over a very wide temperature range of -40C to +85C and is available in tested wafer format. February 25, 2004 S71JLxxxHxx_00A1 8 Mb pSRAM (supplier 2) 103 Preliminary Block Diagram Address Inputs A0 - A18 Address Decode Logic 512K x 16 bit RAM Array Input/ Output Mux and Buffers I/O0 - I/O7 I/O8 - I/O15 CE1# CE2 WE# OE# UB# LB# Control Logic Figure 41. Table 18. CE1# H X L L L L CE2 X L H H H H WE# X X X L H H OE# X X X UB# X X H Functional Block Diagram Functional Description LB# X X H I/O0 - I/O15 (Note 1) High Z High Z High Z Data In Data Out High Z MODE Standby (Note 2) Standby (Note 2) Standby Write Read Active POWER Standby Standby Standby Active Active Active X (Note 3) L (Note 1) L (Note 1) L H L (Note 1) L (Note 1) L (Note 1) L (Note 1) Notes: 1. When UB# and LB# are in select mode (low), I/O0 - I/O15 are affected as shown. When LB# only is in the select mode only I/O0 - I/O7 are affected as shown. When UB# is in the select mode only I/O8 - I/O15 are affected as shown. 2. When the device is in standby mode, control inputs (WE#, OE#, UB#, and LB#), address inputs and data input/ outputs are internally isolated from any external influence and disabled from exerting any influence externally. 3. When WE# is invoked, the OE# input is internally disabled and has no effect on the circuit. Absolute Maximum Ratings (See Note) Item Voltage on any pin relative to VSS Voltage on VCC Supply Relative to VSS Operating Temperature Symbol VIN,OUT VCC TA Rating -0.3 to VCC+0.3 -0.3 to 4.5 -40 to +85 Unit V V C Note: Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operating section of 104 8 Mb pSRAM (supplier 2) S71JLxxxHxx_00A1 February 25, 2004 Preliminary this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Characteristics Operating Characteristics (Over Specified Temperature Range) Item Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Symbol VCC VIH VIL VOH VOL ILI ILO ICC1 ICC2 ICC3 ICC4 IOH = -1.0mA IOL = 2.0mA VIN = 0 to VCC OE# = VIH or Chip Disabled VCC=3.6 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 VCC=3.3 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 VCC=3.6 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 VCC=3.3 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 VIN = VCC or 0V Chip Disabled tA= 85oC, VCC = 3.0 V VIN = VCC or 0V ISB1 Chip Disabled tA= 85 C, VCC = 3.0 V o Test Conditions Min 2.7 2.2 -0.3 VCC-0.4 Typ. (Note 1) 3.0 Max. 3.6 VCC+0.3 0.6 Unit V V V V 0.4 0.5 0.5 5.0 3.0 5.0 25.0 12.0 23.0 V A A Read/Write Operating Supply Current @ 1 s Cycle Time (Note 2) mA Read/Write Operating Supply Current @ 70ns Cycle Time (Note 2) mA Maximum Standby Current (Standard Part) Maximum Standby Current (Ultra Low Power Part) ISB1 70.0 A 60.0 A Notes: 1. Typical values are measured at VCC=VCC Typ., TA=25C, and not 100% tested. 2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. AC Characteristics Table 19. Item Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Operating Temperature 0.1VCC to 0.9 VCC 5ns 0.5 VCC -40 C to +85 C Timing Test Conditions February 25, 2004 S71JLxxxHxx_00A1 8 Mb pSRAM (supplier 2) 105 Preliminary Table 20. Timings Speed Bins 55 70 Max. Min. 70 55 55 30 55 5 5 5 0 0 0 10 55 45 45 45 45 0 0 25 40 0 5 40 0 5 20 20 20 5 5 5 0 0 0 10 70 55 55 55 55 0 0 25 25 25 25 70 70 35 70 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter List Read Cycle Time Address Access Time Chip Enable to Valid Output Output Enable to Valid Output Read Cycle Byte Select to Valid Output Chip Enable to Low-Z output Output Enable to Low-Z Output Byte Select to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Byte Select Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Enable to End of Write Address Valid to End of Write Byte Select to End of Write Write Cycle Write Pulse Width Address Setup Time Write Recovery Time Write to High-Z Output Data to Write Time Overlap Data Hold from Write Time End Write to Low-Z Output Symbol tRC tAA tCO tOE tLB, tUB tLZ tOLZ tLBZ, tUBZ tHZ tOHZ tLBHZ, tUBHZ tOH tWC tCW tAW tLBW, tUBW tWP tAS tWR tWHZ tDW tDH tOW Min. 55 106 8 Mb pSRAM (supplier 2) S71JLxxxHxx_00A1 February 25, 2004 Preliminary Timing Diagrams tRC Address tAA tOH Data Out Previous Data Valid Data Valid Figure 42. Timing of Read Cycle (CE1# = OE# = VIL, WE# = CE2 = VIH) tRC Address tAA tHZ CE1# tCO CE2 tLZ tOE OE# tOLZ tLB, tUB LB#, UB tOHZ tLBLZ, tUBLZ Data Out High-Z tLBHZ, tUBHZ Data Valid Figure 43. Timing Waveform of Read Cycle (WE# = VIH) February 25, 2004 S71JLxxxHxx_00A1 8 Mb pSRAM (supplier 2) 107 Preliminary tWC Address tAW tWR CE1# tCW CE2 tLBW, tUBW LB#, UB tAS WE# tDW Data In High-Z tDH tWP Data Valid tWHZ tOW High-Z Data Out Figure 44. Timing Waveform of Write Cycle (WE# Control) tWC Address tAW CE1# (for CE2 Control, use inverted signal tCW tAS tLBW, tUBW LB#, UB tWP WE# tDW Data In tLZ Data Out Data Valid tDH tWR tWHZ High-Z Figure 45. Timing Waveform of Write Cycle (CE1# Control) 108 8 Mb pSRAM (supplier 2) S71JLxxxHxx_00A1 February 25, 2004 Preliminary 16 Mb pSRAM (supplier 2) 16 Megabit (1Mb x 16bit) Ultra-low Power Asynchronous CMOS Pseudo SRAM Features Single Wide Power Supply Range -- 2.7 to 3.6 Volts Very low standby current -- 100A at 3.0V (Max) Simple memory control -- Dual Chip Enables (CE1# and CE2) -- Byte control for independent byte operation -- Output Enable (OE#) for memory expansion Very fast access time -- 55ns address access option -- 35ns OE# access time Automatic power down to standby mode TTL compatible three-state output driver Operating Temperature -- -40C to +85C Speed -- 70ns -- 55 ns General Description The S71JL064HA0-10/11/12 contains an integrated memory device containing a low-power, 16 Mbit SRAM built using a self-refresh DRAM array organized as 1,024,576 words by 16 bits. It is designed to be identical in operation and interface to standard 6T SRAMS. The device is designed for low standby and operating current and includes a power-down feature to automatically enter standby mode. The device operates with two chip enable (CE1# and CE2) controls and output enable (OE#) to allow for easy memory expansion. Byte controls (UB# and LB#) allow the upper and lower bytes to be accessed independently and can also be used to deselect the device. The S71JL064HA0 is optimal for various applications where low-power is critical, such as battery backup and hand-held devices. The device can operate over a very wide temperature range of -40C to +85C and is available in tested wafer format. February 25, 2004 S71JLxxxHxx_00A1 16 Mb pSRAM (supplier 2) 109 Preliminary Block Diagram Address Inputs A0 - A19 Address Decode Logic 1024K x 16 bit RAM Array Input/ Output Mux and Buffers I/O0 - I/O7 I/O8 - I/O15 CE1# CE2 WE# OE# UB# LB# Control Logic Figure 46. Table 21. CE1# H X L L L L CE2 X L H H H H WE# X X X L H H OE# X X X X L H UB#/LB# X X H L (Note 3) L (Note 3) L (Note 3) Functional Block Diagram Functional Description I/O (Note 1) High Z High Z High Z Data In Data Out High Z MODE Standby (Note 2) Standby (Note 4) Standby (Note 4) Write (Note 3) Read Active POWER Standby Standby Standby Active -> Standby (Note 4) Active -> Standby (Note 4) Standby (Note 4) Notes: 1. When UB# and LB# are in select mode (low), I/O0 - I/O15 are affected as shown. When LB# only is in the select mode only I/O0 - IO7 are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown. If both UB# and LB# are in the deselect mode (high), the chip is in a standby mode regardless of the state of CE1# or CE2.# 2. When the device is in standby mode, control inputs (WE#, OE#, UB#, and LB), address inputs and data input/ outputs are internally isolated from any external influence and disabled from exerting any influence externally. 3. When WE# is invoked, the OE# input is internally disabled and has no effect on the circuit. 4. The device will consume active power in this mode whenever addresses are changed. Data inputs are internally isolated from any external influence. 110 16 Mb pSRAM (supplier 2) S71JLxxxHxx_00A1 February 25, 2004 Preliminary Absolute Maximum Ratings (See Note) Item Voltage on any pin relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Symbol VIN,OUT VCC PD TSTG TA Rating -0.3 to VCC+0.3 -0.3 to 4.0 500 -40 to 125 -40 to +85 Unit V V mW C C Note: Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Characteristics Operating Characteristics (Over Specified Temperature Range) Item Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Read/Write Operating Supply Current @ 1 s Cycle Time (Note 2) Read/Write Operating Supply Current @ Min Cycle Time (Note 2) Standby Current Symbol VCC VIH VIL VOH VOL ILI ILO ICC1 ICC2 ISB IOH = -0.2 mA IOL = 0.2 mA VIN = 0 to VCC OE# = VIH or Chip Disabled VCC=VCCMAX, VIN=VIH/VIL Chip Enabled, IOUT = 0 VCC=VCCMAX, VIN=VIH/VIL Chip Enabled, IOUT = 0 VIN = VCC or 0V Chip Disabled tA = 85C, VCC= 3.0V Comments Min 2.7 2.2 -0.3 VCC-0.2 0.2 0.5 0.5 5 25 Typ. (Note 1) 3.0 Max. 3.6 VCC+0.3 0.6 Unit V V V V V A A mA mA 100.0 A Notes: 1. Typical values are measured at VCC=VCC Typ., TA=25C, and not 100% tested. 2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. February 25, 2004 S71JLxxxHxx_00A1 16 Mb pSRAM (supplier 2) 111 Preliminary AC Characteristics Timing Test Conditions Item Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Operating Temperature 0.1 VCC to 0.9 VCC 5ns 0.5 VCC -40 C to +85 C Timings 55 Item Read Cycle Time Address Access Time Chip Enable to Valid Output Output Enable to Valid Output Byte Select to Valid Output Chip Enable to Low-Z output Output Enable to Low-Z Output Byte Select to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Byte Select Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Enable to End of Write Address Valid to End of Write Byte Select to End of Write Write Pulse Width Write Recovery Time Write to High-Z Output Address Setup Time Data to Write Time Overlap Data Hold from Write Time End Write to Low-Z Output Symbol tRC tAA tCO tOE tLB, tUB tLZ tOLZ tLBZ, tUBZ tHZ tOHZ tLBHZ, tUBHZ tOH tWC tCW tAW tLBW, tUBW tWP tWR tWHZ tAS tDW tDH tOW 0 25 0 5 5 5 5 0 0 0 10 55 50 50 50 50 0 25 0 25 0 5 25 25 25 Min. 55 55 55 30 55 5 5 5 0 0 0 10 70 55 55 55 55 0 25 25 25 25 Max. Min. 70 70 70 35 70 70 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 112 16 Mb pSRAM (supplier 2) S71JLxxxHxx_00A1 February 25, 2004 Preliminary Timings tRC Address tAA tOH Data Out Previous Data Valid Data Valid Figure 47. Timing of Read Cycle (CE1# = OE# = VIL, WE# = CE2 = VIH) tRC Address tAA CE1# tCO CE2 tLZ tOE OE# tOLZ tLB, tUB LB#, UB# tLBLZ, tUBLZ High-Z Data Out tLBHZ, tUBHZ Data Valid tOHZ tHZ Figure 48. Timing Waveform of Read Cycle (WE# = VIH) February 25, 2004 S71JLxxxHxx_00A1 16 Mb pSRAM (supplier 2) 113 Preliminary tWC Address tAW CE1# tCW CE2 tLBW, tUBW LB#, UB# tAS WE# tDW Data In Hi gh-Z tWHZ Data Out High- Z D ata Valid tOW tDH tWP tWR Figure 49. Timing Waveform of Write Cycle (WE# Control) tWC Address tAW CE1# tAS tLBW, tUBW LB#, UB# tWP WE# tDW Data In tWHZ Data Out High- Z Data Valid tDH tCW tWR Figure 50. 114 Timing Waveform of Write Cycle (CE1# Control, CE2 = High) 16 Mb pSRAM (supplier 2) S71JLxxxHxx_00A1 February 25, 2004 Preliminary 16 Mb pSRAM (supplier 4) 16 Megabit (1M x 16) CMOS Pseudo SRAM Features Organized as 1M words by 16 bits Fast Cycle Time : 70 ns Standby Current : 100 A Deep power-down Current : 10 A (Memory cell data invalid) Byte data control: LB# (DQ0 - 7), UB# (DQ8 - 15) Compatible with low-power SRAM Single Power Supply Voltage : 3.0V0.3V Description The S71JL064HA0 Model #62 contains a 16M-bit Pseudo SRAM organized as 1M words by 16 bits. It is designed with advanced CMOS technology specified RAM featuring low-power static RAM-compatible function and pin configuration. This device operates from a single power supply. Advanced circuit technology provides both high speed and low power. It is automatically placed in low-power mode when CS1# or both UB# and LB# are asserted high or CS2 is asserted low. There are three control inputs. CS1# and CS2 are used to select the device, and output enable (OE#) provides fast memory access. Data byte control pins (LB#,UB#) provide lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. Pin Description A0 - A19 DQ0 - DQ15 CE1# CE2 OE# WE# LB# UB# VCC VSS = = = = = = = = = = Address Inputs Data Inputs/Outputs Chip Enable Deep Power Down Output Enable Write Control Lower Byte Control Upper Byte Control Power Supply Ground 96 16 Mb pSRAM (supplier 4) S71JLxxxHxx_00A1 February 25, 2004 Preliminary Operation Mode MODE Deselect Deselect Deselect Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write CE1# H X L L L L L L L L L CE2 H L H H H H H H H H H OE# X X X H H L L L X X X WE# X X X H H H H H L L L LB# X X H L X L H L L H L UB# X X H X L H L L H L L DQ0 to DQ7 High-Z High-Z High-Z High-Z High-Z D-out High-Z D-out D-in High-Z D-in DQ8 to DQ15 High-Z High-Z High-Z High-Z High-Z High-Z D-out D-out High-Z D-in D-in POWER Standby Deep Power Down Standby Active Active Active Active Active Active Active Active Note: X=don't care. H=logic high. L=logic low. Absolute Maxumum Ratings (see Note) SYMBOL VCC VIN VIN, VOUT ISH PD RATING Supply Voltage Input Voltages Output and output Voltages Output short circuit current Power Dissipation VALUE -0.2 to +3.6 -0.2 to VCC + 0.3 -2.0 to +3.6 100 1 UNIT V V V mA W Note: Absolute maximum DC requirements contains stress ratings only. Functional operation at the absolute maximum limits is not implied or guaranteed. Extended exposure to maximum ratings may affect device reliability. DC Characteristics Table 16. SYMBOL VDD VSS VIH VIL PARAMETER Power Supply Voltage Ground Input High Voltage Input Low Voltage DC Recommended Operating Conditions MIN 2.7 0 2.2 -0.2 (Note 2) TYP. 3.0 MAX 3.3 0 VCC + 0.2 (Note 1) +0.6 V UNIT Notes: 1. Overshoot: VCC + 2.0V in case of pulse width 20ns 2. Undershoot: -2.0V in case of pulse width 20ns 3. Overshoot and undershoot are sampled, not 100% tested. February 25, 2004 S71JLxxxHxx_00A1 16 Mb pSRAM (supplier 4) 97 Preliminary Table 17. SYMBOL IIL ILO DC Characteristics (TA = -25C to 85C, VDD = 2.6 to 3.3V) TEST CONDITION VIN = VSS to VDD VIO = VSS to VDD CE1# = VIH, CE2 = VIL or OE# = VIH or WE# = VIL Cycle time = Min., 100% duty, IIO = 0mA, CE1# = VIL, CE2 = VIH, VIN = VIH or VIL Cycle time = 1s, 100% duty IIO = 0mA, CE1# 0.2V, CE2 VDD -0.2V, VIN 0.2V or VIN VDD -0.2V CE1# = VDD - 0.2V and CE2 = VDD - 0.2V, Other inputs = VSS ~ VCC CE2 0.2V, Other inputs = VSS ~ VCC IOL = 2.1mA IOH = -1.0mA 2.4 MIN -1 -1 MAX UNIT 1 1 A A PARAMETER Input Leakage Current Output Leakage Current ICC1 Operating Current @ Min Cycle Time - 35 mA ICC2 Operating Current @ Max Cycle Time - 5 mA ISB1 ISBD VOL VOH Standby Current (CMOS) Deep Power-down Output Low Voltage Output High Voltage - 100 10 0.4 - A A V V AC Characteristics Table 18. AC Characteristics and Operating Conditions (TA = -25C to 85C, VDD = 2.6 to 3.3V) 70 Cycle Symbol tRC tAA tCO1 tCO2 tOE tBA Read tLZ tOLZ tBLZ tHZ tOHZ tBHZ tOH Parameter Read Cycle Time Address Access Time Chip Enable (CE#1) Access Time Chip Enable (CE2) Access Time Output Enable Access Time Data Byte Control Access Time Chip Enable Low to Output in Low-Z Output Enable Low to Output in Low-Z Data Byte Control Low to Output in Low-Z Chip Enable High to Output in High-Z Output Enable High to Output in High-Z Data Byte Control High to Output in High-Z Output Data Hold Time Min 70 10 5 10 10 Max 70 70 70 35 70 25 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 98 16 Mb pSRAM (supplier 4) S71JLxxxHxx_00A1 February 25, 2004 Preliminary Table 18. AC Characteristics and Operating Conditions (TA = -25C to 85C, VDD = 2.6 to 3.3V) (Continued) 70 Cycle Symbol tWC tWP tAW tCW tBW Parameter Write Cycle Time Write Pulse Width Address Valid to End of Write Chip Enable to End of Write Data Byte Control to End of Write Address Set-up Time Write Recovery Time WE# Low to Output High-Z WE# High to Output in High-Z Data to Write Overlap Data Hold Time WE# High Time Min 70 50 60 60 60 0 0 5 35 0 5 Max 20 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns Write tAS tWR tWZH tOW tDW tDH tWEH Table 19. Parameter Output load Input pulse level Timing measurements tR, tF AC Test Conditions Condition 50 pF + 1 TTL Gate 0.4 V, 2.4 0.5 x VCC 5 ns R L = 50 D OUT Z0 = 50 V L = 1.5 V C L = 50 pF (see Note) Note: Including scope and jig capacitance Figure 34. AC Test Loads February 25, 2004 S71JLxxxHxx_00A1 16 Mb pSRAM (supplier 4) 99 Preliminary Deep Pow er Down Exit Sequence Deep Powe r Down Mode CE2=VIH Powe r on Initial State (Wait 200 s) Activee CE2=VIL CE2=VIH, CE1# =VIH or UB#, LB# =VIH CE2=VIL Powe r Up Sequence CE1# =VIL, CE2=VIH, UB# & LB# or/and LB# = VIL Standby Mode Figure 35. State Diagram Table 20. Standby Mode Characteristics Power Mode Standby Deep Power Down Memory Cell Data Valid Invalid Standby Current (A) 100 10 Wait Time (s) 0 200 Timing Diagrams tRC Address tA A tOH Data Out Previous Data Valid tOH Data Valid Note: CE1# = OE# = VIL, CE2 = WE# = VIH, UB# and/or LB# = VIL Figure 36. Read Cycle 1--Addressed Controlled 100 16 Mb pSRAM (supplier 4) S71JLxxxHxx_00A1 February 25, 2004 Deep Power Down Entry Sequence CE1# = VIH or VIL, CE2=VIH Preliminary tRC Address tA A tLZ tCO tOH CE1# UB#, LB# tBLZ tBA tHZ tOE OE# tBHZ Data Out High-Z tOLZ tOHZ Data Valid High-Z Note: CE2 = WE# = VIH Figure 37. Read Cycle 2--CS1# Controlled tWC Address tAW tCW tWR CE1# UB#, LB# tBW WE# tAS High-Z tWHZ Data Out Data Undefined tWP tDW Data Valid tDH High-Z Data In tOW Notes: 1. CE2 = VIH 2. CE2 = WE# = VIH Figure 38. Write Cycle 1--WE# Controlled February 25, 2004 S71JLxxxHxx_00A1 16 Mb pSRAM (supplier 4) 101 Preliminary tWC Address tAW tCW tWR tAS CE1# UB#, LB# tBW WE# tWP tDW tDH Data In Data Valid Notes: 1. CE2 = VIH Data Out High-Z 2. CE2 = WE# = VIH Figure 39. Write Cycle 2--CS1# Controlled tWC Address tAW tCW tWR CE1# UB#, LB# tAS tBW WE# tWP tDW tDH Data In Data Valid Notes: 1. CE2 = VIH Data Out High-Z 2. CE2 = WE# = VIH Figure 40. Write Cycle3--UB#, LB# Controlled 102 16 Mb pSRAM (supplier 4) S71JLxxxHxx_00A1 February 25, 2004 Preliminary 200 s ~ ~ CE2 1 s Normal Operation Mode Suspend Deep Power Down Mode Wake Up Normal Operation ~ ~ CE1# Figure 41. Deep Power-down Mode 200 s ~ ~ VCC CE2 CE1# Figure 42. Power-up Mode > 15s CE1# WE# < tRC Address Note: The S71JL064HA0 Model 61 has a timing that is not supported at read operation. Data will be lost if your system has multiple invalid address signal shorter than tRC during over 15s at the read operation shown above. Figure 43. Abnormal Timing February 25, 2004 S71JLxxxHxx_00A1 16 Mb pSRAM (supplier 4) 103 Preliminary 32 Mb pSRAM (Supplier 3) 32 Megabit CMOS Pseudo Static RAM Features Organized as 2,097,152 words by 16 bits Single power supply voltage of 2.6 to 3.3 V Direct TTL compatibility for all inputs and outputs Deep power-down mode: Memory cell data invalid Page operation mode: -- Page read operation by 8 words Logic compatible with SRAM R/W (WE#) pin Standby current -- Standby -- Deep power-down standby Access Times: -- -- -- -- Access Time CE1# Access Time OE# Access Time Page Access Time 70 A 5 A 70 70 25 30 ns ns ns ns Description The S71JL128HB0 contains a 33,554,432-bit, pseudo static random access memory (PSRAM) organized as 2,097,152 words by 16 bits. It provides high density, high speed, and low power. The device operates single power supply. The device also features SRAM-like W/R timing whereby the device is controlled by DE1#, OE#, and WE# on asynchronous. The device has the page access operation. Page size is 8 words. The device also supports deep power-down mode, realizing lowpower standby. Pin Description A0 to A20 A0 to A2 I/O1 to I/O16 CE1# CE2 WE# OE# LB#, UB# VDD GND NC = = = = = = = = = = = Address Inputs Page Address Inputs Data Inputs/Outputs Chip Enable Input Chip select Input Write Enable Input Output Enable Input Data Byte Control Inputs Power Ground No Connection 104 32 Mb pSRAM (Supplier 3) S71JLxxxHxx_00A1 February 25, 2004 Preliminary Operation Mode MODE Read (Word) Read (Lower Byte) Read (Upper Byte) Write (Word) Write (Lower Byte) Write (Upper Byte) Outputs Disabled Standby Deep Power-down Standby CE1# L L L L L L L H H CE2 H H H H H H H H L OE# L L L X X X H X X WE# H H H L L L H X X LB# L L H L L H X X X UB# L H L L H L X X X Add X X X X X X X X X I/O1 to I/O8 DOUT DOUT High-Z DIN DIN Invalid High-Z High-Z High-Z I/O9 to I/O16 DOUT High-Z DOUT DIN Invalid DIN High-Z High-Z High-Z POWER IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDS IDDSD Note: L = Low-level Input (VIL), H = High-level Input (VIH), X = VIH or VIL, High-Z = High impedance Absolute Maxumum Ratings SYMBOL VDD VIN VOUT Topr. Tstrg. PD IOUT RATING Power Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Output Current VALUE -1.0 to 3.6 -1.0 to 3.6 -1.0 to 3.6 -40 to 85 -55 to 150 0.6 50 UNIT V V V C C W mA Note: (Stresses greater than listed under "Absolute Maximum Ratings" may cause permanent damage to the device DC Characteristics Table 21. SYMBOL VDD VIH VIL DC Recommended Operating Conditions (TA = -40C to 85C) PARAMETER MIN 2.6 2.0 -0.3 (Note TYP. 2.75 MAX 3.3 VDD + 0.3 (Note) 0.4 V UNIT Power Supply Voltage Input High Voltage Input Low Voltage Note: VIL(Min) -1.0 V with 10 ns pulse width; VIH(Max) VDD+1.0 V with 10 ns pulse width February 25, 2004 S71JLxxxHxx_00A1 32 Mb pSRAM (Supplier 3) 105 Preliminary Table 22. SYMBOL IIL ILO VOH VOL IDDO1 IDDO2 IDDS IDDSD DC Characteristics (TA = -40C to 85C, VDD = 2.6 to 3.3V) TEST CONDITION VIN = 0 V to VDD Output disable, VOUT = 0 V to VDD IOH = - 0.5 mA IOL = 1.0 mA CE1# = VIL CE2 = VIH, IOUT = 0 mA CE1# = VIL, CE2 = VIH, Page add. cycling, IOUT = 0 mA tRC = min tPC = min MIN -1.0 -1.0 2.4 TYP. MAX UNIT +1.0 +1.0 0.4 40 25 70 5 A A V V mA mA A A PARAMETER Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Operating Current Page Access Operating Current Standby Current (MOS) Deep Power-down Standby Current CE1# = VDD - 0.2 V, CE2 = VDD - 0.2 V CE2 = 0.2 V Notes: 1. IDDO depends on the cycle time. 2. IDDO depends on output loading. Specified values are defined with the output open condition. Table 23. Symbol CIN COUT Parameter Input Capacitance Output Capacitance Capacitance (TA = 25C, f = 1 MHz) Test Condition VIN = GND VOUT = GND Max 10 10 Unit pF pF AC Characteristics Table 24. Symbol tRC tACC tCO tOE tBA tCOE tOEE tBE tOD tODO tBD tOH tPM tPC AC Characteristics and Operating Conditions (TA = -40C to 85C, VDD = 2.6 to 3.3V) Parameter Read Cycle Time Address Access Time Chip Enable (CE#) Access Time Output Enable Access Time Data Byte Control Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Data Byte Control Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Data Byte Control High to Output High-Z Output Data Hold Time Page Mode Time Page Mode Cycle Time Min 70 - - - - 10 0 0 - - - 10 70 30 Max 10000 70 70 25 25 - - - 20 20 20 - 10000 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 106 32 Mb pSRAM (Supplier 3) S71JLxxxHxx_00A1 February 25, 2004 Preliminary Table 24. Symbol tAA tAOH tWC tWP tCW tBW tAW tAS tWR tCEH tWEH tODW tOEW tDS tDH tCS tCH tDPD tCHC tCHP AC Characteristics and Operating Conditions (TA = -40C to 85C, VDD = 2.6 to 3.3V) (Continued) Parameter Page Mode Address Access Time Page Mode Output Data Hold Time Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Byte Control to End of Write Address Valid to End of Write Address Set-up Time Write Recovery Time Chip Enable High Pulse Width Write Enable High Pulse Width WE# Low to Output High-Z WE# High to Output Active Data Set-up Time Data Hold Time CE2 Set-up Time CE2 Hold Time CE2 Pulse Width CE2 Hold from CE1# CE2 Hold from Power On Min - 10 70 50 70 60 60 0 0 10 6 - 0 30 0 0 300 10 0 30 Max 30 - 10000 - - - - - - - - 20 - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ms ns s Notes: 1. AC measurements are assumed tR, tF = 5 ns. 2. Parameters tOD, tODO, tBD and tODW define the time at which the output goes the open condition and are not output voltage reference levels. 3. Data cannot be retained at deep power-down stand-by mode. 4. If OE# is high during the write cycle, the outputs will remain at high impedance. 5. During the output state of I/O signals, input signals of reverse polarity must not be applied. 6. If CE1# or LB#/UB# goes LOW coincident with or after WE# goes LOW, the outputs will remain at high impedance. 7. If CE1# or LB#/UB# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high impedance. Table 25. AC Test Conditions Parameter Output load Input pulse level Timing measurements Reference level tR, tF Condition 30 pF + 1 TTL Gate VDD - 0.2 V, 0.2 V VDD x 0.5 VDDx 0.5 5 ns February 25, 2004 S71JLxxxHxx_00A1 32 Mb pSRAM (Supplier 3) 107 Preliminary Timing Diagrams tRC Addresses A0 to A20 tACC tCO tOH CE#1 CE2 tOD tOE Fixed High OE# tODO WE# LB#, UB# tBE tOEE tCOE tBA tBD High-Z Indeterminate Valid Data Out DOUT I/O1 to I/O16 High-Z Indeterminate Figure 44. Read Cycle 108 32 Mb pSRAM (Supplier 3) S71JLxxxHxx_00A1 February 25, 2004 Preliminary tPM Address A0 to A2 Address A3 to A20 CE1# tRC tPC tPC tPC CE2 OE# Fix-H WE# UB# LB# , tBA tOEE DOUT I/O1 to I/O1 tBE Hi-Z tCOE tCO tACC DOUT tAA DOUT tAA DOUT DOUT Hi-Z tOE tAOH tAOH tAOH tBD tOH tOD tAA tODO * Maximum 8 words Figure 45. Page Read Cycle (8 words access) February 25, 2004 S71JLxxxHxx_00A1 32 Mb pSRAM (Supplier 3) 109 Preliminary tWC Address A0 to A20 tAS WE# tAW tWP tWR tWEH tCW CE#1 tWR tCH CE2 tBW UB# , LB# tODW DOUT I/O1 to I/O16 DIN (See Note 2) Hi-Z tDS tDH (See Note 3) tOEW (See Note 4) tWR (See Note 3) VALID DATA IN I/O1 to I/O16 Notes: 1. If OE# is high during the write cycle, the outputs will remain at high impedance 2. If CE1# or LB#/UB# goes LOW coincident with or after WE# goes LOW, the outputs will remain at high impedance 3. During the output state of I/O signals, input signals of reverse polarity must not be applied 4. If CE1# or LB#/UB# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high impedance Figure 46. Write Cycle 1 (WE# controlled) 110 32 Mb pSRAM (Supplier 3) S71JLxxxHxx_00A1 February 25, 2004 Preliminary tWC Address A0 to A20 tAS WE# tAW tWP tWR tCEH tCW CE1# tWR tCH CE2 tBW UB#, LB# tBE DOUT I/O1 to I/O16 Hi-Z tCOE tDS DIN tDH tODW Hi-Z tWR (See Note 2) VALID DATA IN I/O1 to I/O16 Notes: 1. If OE# is high during the write cycle, the outputs will remain at high impedance 2. During the output state of I/O signals, input signals of reverse polarity must not be applied Figure 47. Write Cycle 2 (CE# controlled) CE1# tDPD CE2 tCS tCH Figure 48. Deep Power-down Timing VDD VDD min CE1# tCHC CE2 tCHP tCH Figure 49. Power-on Timing February 25, 2004 S71JLxxxHxx_00A1 32 Mb pSRAM (Supplier 3) 111 Preliminary over 10 s CE1# WE# Address t RC min Note: If multiple invalid address cycles shorter than tRC min occur for a period greater than 10 s, at least one valid address cycle over tRC min is required during that period. Figure 50. Read Address Skew Provisions over 10 s CE1# t WP min WE# Address t WC min Note: If multiple invalid address cycles shorter than tWC min occur for a period greater than 10 s, at least one valid address cycle over tWC min, in addition to tWP min, is required during that period. Figure 51. Write Address Skew Provisions 112 32 Mb pSRAM (Supplier 3) S71JLxxxHxx_00A1 February 25, 2004 Preliminary 64 Mb pSRAM (supplier 3) 64 Megabit CMOS Pseudo Static SRAM Features Organized as 4,194,304 words by 16 bits Single power supply voltage of 2.6 to 3.3 V Direct TTL compatibility for all inputs and outputs Deep power-down mode: Memory cell data invalid Page operation mode: -- Page read operation by 8 words Logic compatible with SRAM R/W (WE#) pin Standby current -- Standby -- Deep power-down standby Access Times: -- -- -- -- Access Time CE1# Access Time OE# Access Time Page Access Time 100 A 5 A 70 70 25 30 ns ns ns ns Description The S71JL128HC0 contains a 67,108,864-bit, pseudo static random access memory (PSRAM) organized as 4,194,304 words by 16 bits. It provides high density, high speed, and low power. The device operates on a single power supply. The device also features SRAM-like W/R timing whereby the device is controlled by DE1#, OE#, and WE# on asynchronous. The device has the page access operation. Page size is 8 words. The device also supports deep power-down mode, realizing low-power standby. Pin Description A0 to A21 A0 to A2 I/O1 to I/O16 CE1# CE2 WE# OE# LB#, UB# VDD GND NC = = = = = = = = = = = Address Inputs Page Address Inputs Data Inputs/Outputs Chip Enable Input Chip select Input Write Enable Input Output Enable Input Data Byte Control Inputs Power Ground No Connection February 25, 2004 S71JLxxxHxx_00A1 64 Mb pSRAM (supplier 3) 113 Preliminary Operation Mode MODE Read (Word) Read (Lower Byte) Read (Upper Byte) Write (Word) Write (Lower Byte) Write (Upper Byte) Outputs Disabled Standby Deep Power-down Standby CE1# L L L L L L L H H CE2 H H H H H H H H L OE# L L L X X X H X X WE# H H H L L L H X X LB# L L H L L H X X X UB# L H L L H L X X X Add X X X X X X X X X I/O1 to I/O8 DOUT DOUT High-Z DIN DIN Invalid High-Z High-Z High-Z I/O9 to I/O16 DOUT High-Z DOUT DIN Invalid DIN High-Z High-Z High-Z POWER IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDS IDDSD Note: L = Low-level Input (VIL), H = High-level Input (VIH), X = VIH or VIL, High-Z = High impedance Absolute Maxumum Ratings SYMBOL VDD VIN VOUT Topr. Tstrg. PD IOUT RATING Power Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Output Current VALUE -1.0 to 3.6 -1.0 to 3.6 -1.0 to 3.6 -25 to 85 -55 to 150 0.6 50 UNIT V V V C C W mA Note: (Stresses greater than listed under "Absolute Maximum Ratings" may cause permanent damage to the device DC Characteristics Table 26. SYMBOL VDD VIH VIL DC Recommended Operating Conditions (TA = -25C to 85C) PARAMETER MIN 2.6 2.0 -0.3 (Note TYP. 2.75 MAX 3.3 VDD + 0.3 (Note) 0.4 V UNIT Power Supply Voltage Input High Voltage Input Low Voltage Note: VIL(Min) -1.0 V with 10 ns pulse width; VIH(Max) VDD+1.0 V with 10 ns pulse width 114 64 Mb pSRAM (supplier 3) S71JLxxxHxx_00A1 February 25, 2004 Preliminary Table 27. SYMBOL IIL ILO VOH VOL IDDO1 IDDO2 IDDS IDDSD DC Characteristics (TA = -25C to 85C, VDD = 2.6 to 3.3V) TEST CONDITION VIN = 0 V to VDD Output disable, VOUT = 0 V to VDD IOH = - 0.5 mA IOL = 1.0 mA CE1# = VIL CE2 = VIH, IOUT = 0 mA CE1# = VIL, CE2 = VIH, Page add. cycling, IOUT = 0 mA tRC = min tPC = min MIN -1.0 -1.0 2.4 TYP. MAX UNIT +1.0 +1.0 0.4 50 25 100 5 A mA V V mA mA A A PARAMETER Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Operating Current Page Access Operating Current Standby Current (MOS) Deep Power-down Standby Current CE1# = VDD - 0.2 V, CE2 = VDD - 0.2 V CE2 = 0.2 V Notes: 1. IDDO depends on the cycle time. 2. IDDO depends on output loading. Specified values are defined with the output open condition. Table 28. SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance Capacitance (TA = 25C, f = 1 MHz) TEST CONDITION VIN = GND VOUT = GND MAX 10 10 UNIT pF pF AC Characteristics Table 29. Symbol tRC tACC tCO tOE tBA tCOE tOEE tBE tOD tODO tBD tOH tPM tPC AC Characteristics and Operating Conditions (TA = -25C to 85C, VDD = 2.6 to 3.3V) Parameter Read Cycle Time Address Access Time Chip Enable (CE#) Access Time Output Enable Access Time Data Byte Control Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Data Byte Control Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Data Byte Control High to Output High-Z Output Data Hold Time Page Mode Time Page Mode Cycle Time Min 70 - - - - 10 0 0 - - - 10 70 30 Max 10000 70 70 25 25 - - - 20 20 20 - 10000 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns February 25, 2004 S71JLxxxHxx_00A1 64 Mb pSRAM (supplier 3) 115 Preliminary Table 29. Symbol tAA tAOH tWC tWP tCW tBW tAW tAS tWR tCEH tWEH tODW tOEW tDS tDH tCS tCH tDPD tCHC tCHP AC Characteristics and Operating Conditions (TA = -25C to 85C, VDD = 2.6 to 3.3V) (Continued) Parameter Page Mode Address Access Time Page Mode Output Data Hold Time Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Byte Control to End of Write Address Valid to End of Write Address Set-up Time Write Recovery Time Chip Enable High Pulse Width Write Enable High Pulse Width WE# Low to Output High-Z WE# High to Output Active Data Set-up Time Data Hold Time CE2 Set-up Time CE2 Hold Time CE2 Pulse Width CE2 Hold from CE1# CE2 Hold from Power On Min - 10 70 50 70 60 60 0 0 10 15 - 0 30 0 0 300 10 0 30 Max 30 - 10000 - - - - - - - - 20 - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ms ns s Notes: 1. AC measurements are assumed tR, tF = 5 ns. 2. Parameters tOD, tODO, tBD and tODW define the time at which the output goes the open condition and are not output voltage reference levels. 3. Data cannot be retained at deep power-down stand-by mode. 4. If OE# is high during the write cycle, the outputs will remain at high impedance. 5. During the output state of I/O signals, input signals of reverse polarity must not be applied. 6. If CE1# or LB#/UB# goes LOW coincident with or after WE# goes LOW, the outputs will remain at high impedance. 7. If CE1# or LB#/UB# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high impedance. Table 30. Parameter Output load Input pulse level Timing measurements Reference level tR, tF AC Test Conditions Condition 30 pF + 1 TTL Gate VDD - 0.2 V, 0.2 V VDD x 0.5 VDDx 0.5 5 ns 116 64 Mb pSRAM (supplier 3) S71JLxxxHxx_00A1 February 25, 2004 Preliminary Timing Diagrams tRC Addresses A0 to A21 tACC tCO tOH CE#1 CE2 tOD tOE Fixed High OE# tODO WE# LB#, UB# tBE tOEE tCOE tBA tBD High-Z Indeterminate Valid Data Out DOUT I/O1 to I/O16 High-Z Indeterminate Figure 52. Read Cycle February 25, 2004 S71JLxxxHxx_00A1 64 Mb pSRAM (supplier 3) 117 Preliminary tPM Address A0 to A2 Address A3 to A21 CE1# tRC tPC tPC tPC CE2 OE# Fix-H WE# UB# LB# , tBA tOEE DOUT I/O1 to I/O1 tBE Hi-Z tCOE tCO tACC DOUT tAA DOUT tAA DOUT DOUT Hi-Z tOE tAOH tAOH tAOH tBD tOH tOD tAA tODO * Maximum 8 words Figure 53. Page Read Cycle (8 words access) 118 64 Mb pSRAM (supplier 3) S71JLxxxHxx_00A1 February 25, 2004 Preliminary tWC Address A0 to A21 tAS WE# tAW tWP tWR tWEH tCW CE#1 tWR tCH CE2 tBW UB# , LB# tODW DOUT I/O1 to I/O16 DIN (See Note 2) Hi-Z tDS tDH (See Note 3) tOEW (See Note 4) tWR (See Note 3) VALID DATA IN I/O1 to I/O16 Notes: 1. If OE# is high during the write cycle, the outputs will remain at high impedance 2. If CE1# or LB#/UB# goes LOW coincident with or after WE# goes LOW, the outputs will remain at high impedance 3. During the output state of I/O signals, input signals of reverse polarity must not be applied 4. If CE1# or LB#/UB# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high impedance Figure 54. Write Cycle 1 (WE# controlled) February 25, 2004 S71JLxxxHxx_00A1 64 Mb pSRAM (supplier 3) 119 Preliminary tWC Address A0 to A21 tAS WE# tAW tWP tWR tCEH tCW CE1# tWR tCH CE2 tBW UB#, LB# tBE DOUT I/O1 to I/O16 Hi-Z tCOE tDS DIN tDH tODW Hi-Z tWR (See Note 2) VALID DATA IN I/O1 to I/O16 Notes: 1. If OE# is high during the write cycle, the outputs will remain at high impedance 2. During the output state of I/O signals, input signals of reverse polarity must not be applied Figure 55. Write Cycle 2 (CE# controlled) CE1# tDPD CE2 tCS tCH Figure 56. Deep Power-down Timing VDD VDD min CE1# tCHC CE2 tCHP tCH Figure 57. Power-on Timing 120 64 Mb pSRAM (supplier 3) S71JLxxxHxx_00A1 February 25, 2004 Preliminary over10 s CE1# WE# Address t RC min Note: If multiple invalid address cycles shorter than tRC min occur for a period greater than 10 s, at least one valid address cycle over tRC min is required during that period. Figure 58. Read Address Skew Provisions over 10 s CE1# t WP min WE# Address t WC min Note: If multiple invalid address cycles shorter than tWC min occur for a period greater than 10 s, at least one valid address cycle over tWC min, in addition to tWP min, is required during that period. Figure 59. Write Address Skew Provisions February 25, 2004 S71JLxxxHxx_00A1 64 Mb pSRAM (supplier 3) 121 Preliminary 8 Mb SRAM (supplier 1) 8 Megabit (x8/x16) CMOS SRAM Functional Description Table 31. CS1# H X X L L L L L L L L CS#2 X L X H H H H H H H H OE# X X X H H L L L X X X WE# X X X H H H H H L L L BYTE# X X X VCC VCC VCC VCC VCC VCC VCC VCC SA X X X X X X X X X X X LB# X X H L X L H L L H L Word Mode UB# X X H X L H L L H L L DQ0~7 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din DQ8~15 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Standby Standby Standby Active Active Active Active Active Active Active Active Note: X = VIL or VIH Table 32. Byte Mode CS1# H X L L L CS#2 X L H H H OE# X X H L X WE# X X H H L BYTE# X X VSS VSS VSS SA X X SA (Note 2) SA (Note 2) SA (Note 2) LB# X X DNU DNU DNU UB# X X DNU DNU DNU DQ0~7 High-Z High-Z High-Z Dout Din DQ8~15 High-Z High-Z DNU DNU DNU Mode Deselected Deselected Output Disabled Lower Byte Read Lower Byte Write Power Standby Standby Active Active Active Notes: 1. X = VIL or VIH 2. Address input for byte operation. 122 8 Mb SRAM (supplier 1) S71JLxxxHxx_00A1 February 25, 2004 Preliminary Absolute Maximum Ratings Item Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Power Dissipation Operating Temperature Symbol VIN,VOUT VCC PD TA Ratings -0.2 to VCC+0.3V (Max. 3.6V) -0.2 to 3.6V 1.0 -40 to 85 Unit V V W C Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Characteristics Recommended DC Operating Conditions Item Supply voltage Ground Input high voltage Input low voltage Symbol VCC VSS VIH VIL Min 2.7 0 2.2 -0.2 (Note 2) Typ 3.0 0 Max 3.3 0 VCC+0.2 (Note 1) 0.6 Unit V V V V Notes: 1. Overshoot: Vcc+1.0V in case of pulse width 20ns. 2. Undershoot: -1.0V in case of pulse width 20ns. 3. Overshoot and undershoot are sampled, not 100% tested. Capacitance (f=1MHz, TA=25C) Item Input capacitance Input/Output capacitance Symbol CIN CIO Test Condition VIN=0V VIO=0V Min Max 8 10 Unit pF pF Note: Capacitance is sampled, not 100% tested February 25, 2004 S71JLxxxHxx_00A1 8 Mb SRAM (supplier 1) 123 Preliminary DC and Operating Characteristics Item Input leakage current Output leakage current Symbol ILI ILO ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current (CMOS) VOL VOH ISB1 Test Conditions VIN=VSS to VCC CE1#=VIH, CS2=VIL or OE#=VIH or WE#=VIL, VIO=VSS to VCC Cycle time=1s, 100% duty, IIO=0mA, CE1#0.2V, CS2VCC-0.2V, BYTE#=VSS or VCC, VIN0.2V or VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CE1#=VIL, CS2=VIH, BYTE#=VSS or VCC, VIN=VIL or VIH IOL = 2.1mA IOH = -1.0mA CE1#VCC-0.2V, CS2VCC-0.2V (CE1# controlled) or CS20.2V(CS2 controlled), BYTE3=VSS or VCC, Other input =0~VCC 70ns Min -1 -1 Typ Max 1 1 Unit mA mA - - 3 mA 2.4 - - 22 0.4 mA V V 15 mA 124 8 Mb SRAM (supplier 1) S71JLxxxHxx_00A1 February 25, 2004 Preliminary AC Characteristics Read/Write Charcteristics (VCC=2.7-3.3V) Parameter List Read cycle time Address access time Chip select to output Output enable to valid output UB#, LB# Access Time Read Chip select to low-Z output UB#, LB# enable to low-Z output Output enable to low-Z output Chip disable to high-Z output UB#, LB# disable to high-Z output Output disable to high-Z output Output hold from address change Write cycle time Chip select to end of write Address set-up time Address valid to end of write UB#, LB# Valid to End of Write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z Symbol tRC tAA tCO1, tCO2 tOE tBA tLZ1, tLZ2 tBLZ tOLZ tHZ1, tHZ2 tBHZ tOHZ tOH tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW Min 70 10 10 5 0 0 0 10 70 60 0 60 60 50 0 0 30 0 5 Max 70 70 35 70 25 25 25 20 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data Retention Characteristics Item VCC for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR Test Condition CS1#VCC-0.2V VCC=3.0V, CS1#VCC-0.2V See data retention waveform Min 1.5 0 tRC Typ Max 3.3 15 Unit V A ns Note: CE1#VCC-0.2V. CS2VCC-0.2V (CE1# controlled) or CS20.2V (CS2 controlled), BYTE#=VSS or VCC February 25, 2004 S71JLxxxHxx_00A1 8 Mb SRAM (supplier 1) 125 Preliminary Timing Diagrams tRC Address tOH Data Out Previous Data Valid tAA Data Valid Figure 60. Timing Waveform of Read Cycle(1) (address controlled, CD#1=OE#=VIL, CS2=WE#=VIH, UB# and/or LB#=VIL) tRC Address tAA tCO1 tOH CS1# CS2 tCO2 tBA tHZ UB#, LB# OE# tOLZ tBLZ tLZ tOE tBHZ tOHZ Data Valid Data out High-Z Notes: 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. Figure 61. Timing Waveform of Read Cycle(2) (WE#=VIH, if BYTE# is low, ignore UB#/LB# timing) tWC Address tCW(2) CS1# tWR(4) CS2 tAW tBW tWP(1) tAS(3) Data in High-Z tWHZ Data out Data Undefined UB#, LB# WE# tDW tDH High-Z tOW Data Valid Figure 62. Timing Waveform of Write Cycle(1) (WE# controlled, if BYTE# is low, ignore UB#/LB# timing) 126 8 Mb SRAM (supplier 1) S71JLxxxHxx_00A1 February 25, 2004 Preliminary tWC Address tAS(3) CS# tAW CS2 UB#, LB# tBW tWP(1) WE# tDW Data in tDH tCW(2) tWR(4) Data Valid Data out High-Z High-Z Figure 63. Timing Waveform of Write Cycle(2) (CE1# controlled, if BYTE# is low, ignore UB#/LB# timing) tWC Address tCW(2) CS1# tAW CS2 tCW(2) tBW tAS(3) tWP(1) tWR(4) UB#, LB# WE# tDW Data in tDH Data Valid High-Z Data out High-Z Notes: 1. A write occurs during the overlap(tWP) of low CS1# and low WE#. A write begins when CS1# goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write ends at the earliest transition when CS1# goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1# going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS1# or WE# going high. Figure 64. Timing Waveform of Write Cycle(3) (UB#, LB# controlled, BYTE# must be high) February 25, 2004 S71JLxxxHxx_00A1 8 Mb SRAM (supplier 1) 127 Preliminary Data Retention Waveforms VCC 2.7V tSDR Data Retention Mode tRDR 2.2V VDR CS1# GND CS1# VCC - 0.2V Figure 65. CE1# Controlled Data Retention Mode VCC 2.7V CS2 tSDR tRDR VDR 0.4V GND CS2 0.2V Figure 66. CS2 Controlled 128 8 Mb SRAM (supplier 1) S71JLxxxHxx_00A1 February 25, 2004 Preliminary Revision Summary Revision A (February 23, 2004) Initial release. Revision A+1 (February 25, 2004) Global Corrected Supplier 4 Model Number to 62. Revision A+2 (February 26, 2004) Global Corrected missed Supplier 4 Model Number to 62. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by FASL LLC. FASL LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided ias isi without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. FASL LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2003 FASL LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of FASL LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies. February 25, 2004 S71JLxxxHxx_00A1 Revision Summary 129 |
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