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MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1
FEATURES
Y High-quality zoom and shrink scaling engine (Compatible with VGA thru XGA) Y Integrated 8-bit triple-ADC/PLL Y On-screen display controller (OSD) Y Supports single-RGB inputs Y Supports composite sync and SOG separator Y Programmable 10-bit gamma correction Y Integrated Brightness & Contrast control adjustment Y Supports PWM backlit intensity control Y Supports sRGB Y Green PC and low EMI features Y Built-in LVDS transmitter Y Low standby power mode (< 15mA) n High-Performance Scaling Engine Y Programmable shrink/zoom capabilities Y High-quality scaling for all VESA and IBM mode to fit screen Y Variable sharpness control n Analog RGB Compliant Input Port Y Supports up to XGA at 85Hz Y Supports Composite Sync and SOG (Sync-on-Green) separator n Auto-Detection/Tune Y Auto input signal format (SOG, Composite, Separated HSYNC, VSYNC, and DE), and input mode (all VESA & IBM modes w/ resolution and polarity) detection Y Auto-tuning function including phasing, positioning, offset, gain, and jitter detection Y Smart screen-fitting n On-Screen OSD Controller Y Built-in OSD generator with 256 character font programmable RAM Y Supports for 4/8 multi-color fonts Y Gradient color function Y Supports button function Y Pattern generator for production test Y Support OSD MUX and alpha blending capability n LVDS Display Interface Y Supports Single Link up to 85MHz dot clock for XGA Y Supports 2 data output formats: Thine & TI data mappings Y Compatible with TIA/EIA Y With 6/8 bits options Y Reduced swing for LVDS for low EMI n External Connection/Component Y Built-in DDC circuit Y Supports serial (up to 400Kbit/sec) bus type
BLOCK DIAGRAM
Analog RGB Analog HSYNC
ADC
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LVDS
To Panel
OSD
SSC
interface XTAL/EXT CLK
GENERAL DESCRIPTION
The MST8011A is a high performance, and fully integrated graphics processing IC solution for LCD monitors with resolutions up to XGA. It is configured with an integrated triple-ADC/PLL, a high quality scaling engine, To further an on-screen display controller, a built-in output clock generator, and LVDS display interface. green-mode requirements and spread-spectrum support for EMI management.
reduce system costs, the MST8011A also integrates intelligent power management control capability for
Version 0.1
-1Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
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MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1
PIN DIAGRAM (MST8011A)
NC GNDP VDDP NC NC NC NC NC NC NC NC VDDC GNDC GNDP VDDP LVA0M LVA0P LVA1M LVA1P LVA2M LVA2P LVACKM LVACKP GNDP VDDP LVA3M
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104
NC AVSS_MPLL BYPASS NC NC NC NC NC NC GNDP VDDP NC NC NC NC NC NC VDDC GNDC GNDP VDDP NC NC NC NC NC NC DDC1_DAT DDC1_CLK DDCROM_CLK DDCROM_DAT HWRESET XIN XOUT AVDD_MPLL AVSS_MPLL HSYNC0 VSYNC0
103
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Pin 1
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
LVA3P NC 100 NC 99 NC 98 NC 97 VDDC 96 GNDC 95 GNDP 94 VDDP 93 NC 92 NC 91 NC 90 NC 89 NC 88 NC 87 VDDC 86 GNDC 85 GNDP 84 VDDP 83 NC 82 NC 81 NC 80 NC 79 NC 78 NC 77 NC 76 NC 75 NC 74 PWM1 73 PWM0 72 INT 71 SCL 70 SDA 69 CS 68 AVSS 67 REFM 66 REFP 65 AVDD
102 101 53 54 55 56 57 58 59 60 61 62 63 64
51
Version 0.1
AVSS NC NC AVSS NC NC AVDD NC NC AVSS NC NC AVDD REXT AVDD_PLL AVSS_PLL AVDD AVSS BIN0M BIN0 GIN0M GIN0 SOGIN0 RIN0M RIN0 AVSS
-2Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
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MST8011A
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MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1
PIN DESCRIPTION
CPU Interface
Pin Name HWRESET CS SDA SCL INT Pin Type Schmitt Trigger Input w/ 5V-tolerant Input w/ 5V-tolerant I/O w/ 5V-tolerant Input w/ 5V-tolerant Output Function Hardware reset; active high 3 Wire Serial Bus Chip Select; active high 3 Wire Serial Bus Data; 4mA driving strength 3 Wire Serial Bus Clock CPU interrupt; 4mA driving strength Pin 32 69 70 71 72
Analog Interface
Pin Name HSYNC0 VSYNC0 REFP REFM RIN0 RIN0M SOGIN0 GIN0 GIN0M BIN0 BIN0M REXT Pin Type Schmitt Trigger Input w/ 5V-tolerant Schmitt Trigger Input w/ 5V-tolerant Function Analog HSYNC input Analog VSYNC input Internal ADC top de-coupling pin Internal ADC bottom de-coupling pin Analog red input Reference ground for analog red input Sync-on-green input Analog green input Reference ground for analog green input Analog blue input Reference ground for analog blue input External resistor 390 ohm to AVDD Pin 37 38 66 67 63 62 61 60 59 58 57 52
Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input
LVDS Interface
Pin Name LVA0M LVA0P LVA1M LVA1P LVA2M LVA2P LVA3M LVA3P LVACKM LVACKP Pin Type Output Output Output Output Output Output Output Output Output Output Function Negative LVDS Differential Data Output Positive LVDS Differential Data Output Negative LVDS Differential Data Output Positive LVDS Differential Data Output Negative LVDS Differential Data Output Positive LVDS Differential Data Output Negative LVDS Differential Data Output Positive LVDS Differential Data Output Negative LVDS Differential Clock Output Positive LVDS Differential Clock Output Pin 113 112 111 110 109 108 103 102 107 106
GPIO Interface
Pin Name GOUT1/PWM1 GOUT0/PWM0 Pin Type Output Output Function GOUT1/PWM1; 4mA driving strength GOUT0/PWM0; 4mA driving strength Pin 74 73
Version 0.1
-3Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1
Misc. Interface
Pin Name BYPASS DDC1_DAT DDC1_CLK DDCROM_CLK DDCROM_DAT XIN XOUT Function For External Bypass Capacitor I/O w/ 5V-tolerant DDC Data for analog interface; 4mA driving strength Input w/ 5V-Tolerant DDC Clock for analog interface Input w/ 5V-Tolerant DDC ROM Clock I/O w/ 5V-tolerant DDC ROM Data; 4mA driving strength Crystal Oscillator Input Xin Crystal Oscillator Output Xout Pin Type Pin 3 28 29 30 31 33 34
Power Pins
Pin Name AVDD AVSS AVDD_PLL AVSS_PLL AVDD_MPLL AVSS_MPLL VDDP GNDP VDDC GNDC Pin Type 3.3V Power Ground 3.3V Power Ground 3.3V Power Ground 3.3V Power Ground 2.5V Power Ground Function ADC Power ADC Ground PLL Power PLL Ground MPLL Power MPLL Ground Digital Output Power Digital Output Ground Digital Core Power Digital Core Ground Pin 45, 51, 55, 65 39, 42, 48, 56, 64, 68 53 54 35 2, 36 11, 21, 84, 94, 104, 114, 126 10, 20, 85, 95, 105, 115, 127 18, 87, 97, 117 19, 86, 96, 116
No Connects
Pin Name Pin Type Function Pin 1, 4-9, 12-17, 22-27, 40, 41, 43, 44, 46, 47, 49, 50, 75-83, 88-93, 98-101, 118-125, 128
NC
No Connect.
Leave These Pins Floating.
Version 0.1
-4Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1
ELECTRICAL SPECIFICATIONS Analog Interface Characteristics
Parameter Resolution DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes ANALOG INPUT Input Voltage Range Minimum Maximum Input Bias Current Input Full-Scale Matching Brightness Level Adjustment SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate HSYNC Input Frequency PLL Clock Rate PLL Jitter Sampling Phase Tempco DIGITAL INPUTS Input Voltage, High (VIH) Input Voltage, Low (VIL) Input Current, High (IIH) Input Current, Low (IIL) Input Capacitance DIGITAL OUTPUTS Output Voltage, High (VOH) Output Voltage, Low (V OL) DYNAMIC PERFORMANCE Analog Bandwidth, Full Power Channel to Channel Matching
Specifications subject to change without notice.
Min
Typ 8 0.5 1 Guaranteed
Max
Unit Bits LSB LSB
+1.25/-1.0
0.5 1.0 1.5 62 165 15 20 1
V p-p V p-p uA %FS %FS MSPS MSPS kHz MHz ps p-p ps/C V V uA uA pF V V MHz Full-Scale
500 TBD
20 200 162.5
2.5
0.8 -1.0 1.0 5
VDDP-0.1 0.1 250 0.5%
Version 0.1
-5Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1
Absolute Maximum Ratings
Parameter 3.3V Supply Voltages 2.5V Supply Voltages Input Voltage (5V tolerant inputs) Input Voltage (non 5V tolerant inputs) Ambient Operating Temperature Storage Temperature Operating Junction Temp. Thermal Resistance (Junction to Air) Natural Conversion Thermal Resistance (Junction to Case) Natural Conversion Symbol V VDD_33 V VDD_25 V IN5Vtol VIN TA T STG TJ JA JC Min -0.3 -0.3 -0.3 -0.3 0 -40 0 Typ Max 3.6 2.75 5.0 VVDD_33 70 125 125 Units V V V V C C C C/W C/W
34 6.0
Note: Stress above those listed under Absolute Maximum Rating may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
ORDERING GUIDE
Model MST8011A Temperature Package Package Range Description Option 128 0C to +70C PQFP
DISCLAIMER
MSTAR SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. NO RESPONSIBILITY IS ASSUMED BY MSTAR SEMICONDUCTOR ARISING OUT OF THE APPLICATION OR USER OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
MARKING INFORMATION
MST8011A
Part Number Lot Number Operation Code A Operation Code B Date Code (YYWW)
Electrostatic charges accumulate on both test equipment and human body and can discharge without detection. MST8011A comes with ESD protection circuitry, however, the device may be permanently damaged when subjected to high energy discharges. The device should be handled with proper ESD precautions to prevent malfunction and performance degradation.
REVISION HISTORY
Document MST8011A_data_sheet_v01 Description Y Initial release Date May 2003
Version 0.1
-6Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1
MECHANICAL DIMENSIONS
Version 0.1
-7Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1
REGISTER DESCRIPTION General Control Register
Register Bank Select Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 00h REGBK PORR AINC n PORR Power On Reset Ready (read only) Y0 Not ready Y1 Ready n AINC Serial bus address auto increase Y0 Enable Y1 Disable n BUST BUS type (read only) Y0 Direct bus Y1 Serial bus n REGBK[1:0] Register Bank Select Y 00 Register of Scalar Y 01 Register of Internal ADC/DVI Receiver Y 10 Register of Timing Controller Y 11 Reserved Bit 2 BUST Bit 1 Bit 0 REGBK[1:0] Access R/W
ADC Register (Bank=01)
Double Buffer Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 01h DBFC n DBVB Double buffer load at vertical blanking Y0 Disable Y1 Enable PLL Divider Control Index Mnemonic Bit 7 Bit 6 Bit 5 02h PLLDIVM PLLDIV[11:4] 03h PLLDIVL PLLDIV[3:0] n PLLDIV[11:0] PLL Divider Ratio Y 1685 Default value (1688 - 3) Input Gain Index Mnemonic Bit 7 Bit 6 Bit 5 04h REDGAIN REDGAIN[7:0] 05h GRNGAIN GRNGAIN[7:0] 06h BLUGAIN BLUGAIN[7:0] n REDGAIN[7:0] Red channel gain adjust Y 80h Default value n GRNGAIN[7:0] Green channel gain adjust Y 80h Default value n BLUGAIN[7:0] Blue channel gain adjust Y 80h Default value Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W DB Bit 3 Bit 2 Bit 1 Bit 0 DBVB Access R/W
Version 0.1
-8Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Input Offset Index Mnemonic Bit 7 Bit 6 Bit 5 07h REDOFST REDOFST[7:0] 08h GRNOFST GRNOFST[7:0] 09h BLUOFST BLUOFST[7:0] n REDOFST[7:0] Red channel offset adjust Y 80h Default value n GRNOFST[7:0] Green channel offset adjust Y 80h Default value n BLUOFST[7:0] Blue channel offset adjust Y 80h Default value Clamp Timing Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 0Ah CLPLACE CLPLACE[7:0] 0Bh CLDUR CLDUR[7:0] n CLPLACE[7:0] Clamp Placement based on ADC clock Y 05h Default value n CLDUR[7:0] Clamp Duration based on ADC clock Y 05h Default value General Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0Ch GCTRL HSP ECLK HSLE CLPE CCDIS n HSP Input HSYNC polarity Y0 Active low Y1 Active high n ECLK External Clock Y0 ADC clock from internal ADC PLL Y1 ADC clock from external clock n HSLE HS Lock Edge Y0 Leading edge Y1 Tailing edge n CLPE Clamp reference Edge Y0 Tailing edge Y1 Leading edge n CCDIS Disable Clamp during active coast Y0 Always enable clamp Y1 Disable clamp during active coast n WDIS Disable PLL watchdog timer Y0 Enable PLL watchdog timer Y1 Disable PLL watchdog timer n CSTP Coast polarity Y0 Active low Y1 Active high, default value n DRBS DVI input Red/Blue swap (DVI feature only) Y0 Normal Y1 Swap Bit 2 WDIS Bit 1 CSTP Bit 0 DRBS Access R/W Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W
Version 0.1
-9Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 PLL Coefficient Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 0Dh BWCOEF BWCOEF[5:0] 0Eh FCOEF FREQCOEF[4:0] 0Fh DCOEF DAMPCOEF[3:0] n BWCOEF[5:0] PLL Loop filter control Y2 Default value n FREQCOEF[4:0] PLL Loop filter control Y9 Default value n DAMPCOEF[3:0] PLL Loop filter control Y5 Default value Clock Phase Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 10h CLKCTRL1 STAT2 PHASE[5:0] 11h CLKCTRL2 STAT[1:0] PHASECC[5:0] n PHASE[5:0] Clock phase adjust (should be always set to PHASECC + 8) Y 08h Default value n PHASECC[5:0] Clock phase adjust Y 00h Default value n STAT[2:0] Status select Y 00h Default value VCO Control Index 12h 13h Mnemonic VCOCTRL RT_CTL Bit 7 PDGT SFTF Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W Bit 0 Access R/W DB Bit 1 Bit 0 Access R/W R/W R/W
DPL_S[2:0] DEFE WDF enable
SETCNT[3:0] RT_CTL[4:0]
Note: The default value is 0x15h n PDGT Phase digitize
n n n
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Y0 Y1 DPL_S[2:0] SETCNT[3:0] SFTF Y0 Y1 Y DEFE Y0 Y1 WDF Y0 Y1 RT_CTL[4:0]
VCO range Settling time DVI error correction enable (DVI feature only) Error correction disable Error correction enable DVI R/G/B alignment edge on DE (DVI feature only) DE rising edge DE falling edge DVI word alignment frozen (DVI feature only) Disable Enable Resister termination control for DVI (DVI feature only)
SOG/HSYNC Programming Level Index Mnemonic Bit 7 Bit 6 Bit 5 14h SOG_LVL RMID BMID OFIR 15h HS_LVL ADCBW[2:0] n RMID Middle clamp of Red Channel Y0 Disable Bit 4 Bit 3 SOG_LVL[4:0] CLPF XSEL Bit 2 Bit 1 Bit 0 Access R/W R/W
HS_LVL[2:0]
Version 0.1
- 10 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Y1 BMID Y0 Y1 OFIR Y0 Y1 SOG_LVL[4:0] ADCBW[2:0] Y 000 Y 001 Y 010 Y 011 Y 111 CLPF Y0 Y1 XSEL Y0 Y1 HS_LVL[2:0] Enable (used when YPbPr input) Middle clamp of Blue Channel Disable Enable (used when YPbPr input) Output FIR Disable Enable (used when YPbPr input) SOG trigger level ADC bandwidth 300MHz 150MHz 75MHz 33MHz 15MHz Clamp Filter Normal Clamp Lower current clamp XTAL Select Default XTAL Backup XTAL HSYNC trigger level
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Status Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 16h STATUS1 LOCK D7 D6 D5 D4 D3 D2 D1 RO 18h STATUS5 RCMP[7:0] RO 19h STATUS4 PH_STAT[7:0] RO 1Ah STATUS5 PH_STAT[15:8] RO n LOCK PLL Lock Status n D7:D1 Status n RCMP[7:0] DVI termination resistor status in 2's complement (DVI feature only) Y Positive value represents resistance value on low side, RT_CTL needs to adjust higher for compensation Y Negative value represents resistance value on high side, RT_CTL needs to adjust lower for compensation n PH_STAT[15:0] DVI phase status indicator in 2's complement (DVI feature only) DVI Override (DVI feature only) Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1Bh DVI_PHR OVPR OVPHR[6:0] 1Ch DVI_PHG OVPG OVPHG[6:0] 1Dh DVI_PHB OVPB OVPHB[6:0] 1Eh DVI_ERST ERR_ST[7:0] 1Fh DVI_ERTH ERR_TH [7:0] n {OVPR,OVPHR} Freeze & override DVI red channel PLL phase selection with OVPHR[6:0] n {OVPG,OVPHG} Freeze & override DVI green channel PLL phase selection with OVPHG[6:0] n {OVPB,OVPHB} Freeze & override DVI blue channel PLL phase selection with OVPHB[6:0] n ERR_ST DVI bit error status indicator n ERR_TH DVI bit error tolerance threshold Access R/W R/W R/W R/W R/W
Version 0.1
- 11 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Test Mode Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 20h TESTEN TSTEN ERRCHSEL[1:0] ERRD RDST PHSEL[1:0] R/W 26h TESTA5 OVRD_ON AMUX DPLBG DMIBEX PHD DMUX DVIDET R/W 27h TESTA6 ADCR ADCG ADCB DPL AREF VREF R/W 2Dh TESTMOD TESTMOD[7:0] R/W n TSTEN Enable test mode Y0 Disable Y1 Enable n ERRCHSEL[1:0] Channel select for DVI error status indicator (DVI feature only) Y 00 Red channel Y 01 Green channel Y 10 Blue channel Y 11 Reserved n ERRD DVI bit error status indicator (ERR_ST) enable (DVI feature only) Y0 Normal Y1 Read status n RDST Terminator resistance status (RCMP) & DVI phase status enable (DVI feature only) Y0 Normal Y1 Read status n PHSEL[1:0] Channel select for DVI phase status (DVI feature only) Y 00 Red channel Y 01 Green channel Y 10 Blue channel Y 11 Reserved n OVRD_ON Enable for power down overrides Y0 Auto select in operation mode Y1 Overriding enable n AMUX Analog mux override select Y0 Select ADC0 Y1 Select ADC1 n DPLBG Override value for DPL bandgap Y0 Bandgap on Y1 Bandgap off n DMIBEX Override value for output current bias Y0 Bias on Y1 Bias off n PHD Override value for phase digitizer Y0 Phase digitizer on Y1 Phase digitizer off n DMUX Override value for DVI de-multiplexer (DVI feature only) Y0 De-multiplexer on Y1 De-multiplexer off n DVIDET Override value for DVI clock detection (DVI feature only) Y0 Detection on Y1 Detection off n ADCR Power down ADC red channel Y0 ADC red channel on Y1 ADC red channel off n ADCG Power down ADC green channel Y0 ADC green channel on Y1 ADC green channel off n ADCB Power down ADC blue channel Y0 ADC blue channel on Y1 ADC blue channel off
Version 0.1 - 12 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved. 5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1
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DPL Y0 Y1 AREF Y0 Y1 VREF Y0 Y1 TESTMOD[7] Y0 Y1 TESTMOD[4:0] Y 5'b01000 Y 5'b00111 Y 5'b00110
Power down DPL regulator DPL on DPL off Power down ADC voltage reference ADC voltage reference on ADC voltage reference off Power down HSYNC voltage reference HSYNC voltage reference on HSYNC voltage reference off LVDS/RSDS test mode Default Stop LVDS internal and output clock/stop RSDS-clock-side internal and output clock LVDS/RSDS differential output swing control 5.0mA for LVDS/ 2.5mA for RSDS 4.6mA for LVDS/ 2.3mA for RSDS 4.2mA for LVDS/ 2.1mA for RSDS
PLL Control for Video input Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 30h PLLCTRLV PLLCTRLV[7:0] n PLLCTRLV[7:0] PLL Control for composite sync input Y 0x95 Recommended value (power on default value is 0) Bit 1 Bit 0 Access R/W
Scalar Register (Bank=00)
Double Buffer Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 01h DBFC DBL[1:0] n DBL[1:0] Double buffer load Y 00 Keep old register value Y 01 Load new data (auto reset to 00 when load finish) Y 10 Automatically load data at VSYNC blanking Y 11 Reserved n DBC Double buffer Control Y0 Double buffer disable Y1 Double buffer enable Bit 0 DBC Access R/W
Graphic Port Register (11, 02h - 0Ch)
Input Source Select/Control Index 02h Mnemonic ISELECT Bit 7 NIS Bit 6 Bit 5 Bit 4 COMP Bit 3 CSC Bit 2 IHSU ESLS Bit 1 VWRP Bit 0 HWRP Access R/W R/W STYPE[1:0] ISEL[1:0]
04h IPCTRL2 n NIS Y0 Y1 n STYPE[1:0] Y 00 Y 01 Y 10 Y 11 n COMP Y0
Version 0.1
DHSR DEON IVSD HSE VSE Output Lock mode Lock input (input signal exits) Free Run (no input signal) Input Sync Type Auto detected Input is separated HSYNC, VSYNC. Input is Composite sync Input is sync on green (SOG) CSYNC/SOG select (only useful when STYPE=00) CSYNC
- 13 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Y1 SOG CSC CSC function Y0 Disable (RGB -> RGB) Y1 Enable (YCbCr -> RGB) IHSU Input HSYNC Usage When ISEL=00 or 01 Y0 Use HSYNC to do mode detection, HSOUT from ADC to sample pixel Y1 Use HSYNC only When ISEL=10 Y0 Normal Y1 Enable DE Ahead/Delay adjust When ISEL=11 Y0 Normal Y1 Output Black at blanking ISEL[1:0] Input Select Y 00 Analog 1 Y 01 Analog 2 Y 10 DVI Y 11 Video DHSR Digital Input Horizontal Sample Range Y0 Use DE as sample range, only V position can be adjusted Y1 Use SPRHST and SPRHDC as sample range, both H and V position can be adjusted DEON DE Only, HSYNC and VSYNC is ignored Y0 Disable Y1 Enable IVSD Input VSYNC Delay select Y0 Delay 1/4 input HSYNC (recommended) Y1 No delay HSE Input HSYNC reference edge select Y0 From HSYNC leading edge, default value Y1 From HSYNC tailing edge VSE Input VSYNC reference edge select Y0 From VSYNC leading edge, default value Y1 From VSYNC tailing edge ESLS Early Sample Line Select Y0 8 lines Y1 16 lines VWRP Input image Vertical wrap Y0 Disable Y1 Enable HWRP Input image Horizontal wrap Y0 Disable Y1 Enable
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Input Image Sample Range Index 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch Mnemonic SPRVST-L SPRVST-H SPRHST-L SPRHST-H SPRVDC-L SPRVDC-H SPRHDC-L SPRHDC-H Bit 7 Bit 6 SPRVST[7:0] SPRHST[7:0] SPRVDC[7:0] SPRHDC[7:0] Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W DB R/W DB R/W R/W SPRHDC[10:8]
SPRVST[10:8] SPRHST[10:8] SPRVDC[10:8]
Version 0.1
- 14 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 SPRVST[10:0] SPRHST[10:0] SPRVDC[10:0] n SPRHDC[10:0]
n n n
Image vertical sample start point, count by input HSYNC Image horizontal sample start point, count by input dot clock Image vertical resolution (vertical display enable area count by line) Image horizontal resolution (horizontal display enable area count by pixel)
Input Lock Point Index Mnemonic Bit 7 Bit 6 0Fh LYL n LYL[3:0] Lock Y Line Bit 5 Bit 4 Bit 3 Bit 2 LYL[3:0] Bit 1 Bit 0 Access R/W
Display Timing Register (24, 10h - 27h)
Output DE Size Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 10h DEVST-L DEVST[7:0] 11h DEVST-H DEVST[10:8] 12h DEHST-L DEHST[7:0] 13h DEHST-H DEHST[10:8] 14h DEVEND-L DEVEND[7:0] 15h DEVEND-H DEVEND[10:8] 16h DEHEND-L DEHEND[7:0] 17h DEHEND-H DEHEND[10:8] n DEVST[10:0] Output DE Vertical Start Y 00h Default value n DEHST[10:0] Output DE horizontal Start Y 48h Recommended value (power on default value is 3) n DEVEND[10:0] Output DE Vertical END Y 2FFh Recommended value for XGA output (power on default value is 6) Y 3FFh Recommended value for SXGA output n DEHEND[10:0] Output DE Horizontal END Y 447h Recommended value for XGA output (power on default value is 0) Y 547h Recommended value for SXGA output Scaling Image Window Size Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 18h SIHST-L SIHST[7:0] 19h SIHST-H SIHST[10:8] 1Ah SIVEND-L SIVEND[7:0] 1Bh SIVEND-H SIVEND[10:8] 1Ch SIHEND-L SIHEND[7:0] 1Dh SIHEND-H SIHEND[10:8] n SIHST[10:0] Scaling Image window horizontal start Y 48h Recommended value (power on default value is 0) n SIVEND[10:0] Scaling Image window vertical END Y 2FFh Recommended value for XGA output (power on default value is 6) Y 3FFh Recommended value for SXGA output n SIHEND[10:0] Scaling Image window horizontal END Y 447h Recommended value for XGA output (power on default value is 0) Y 547h Recommended value for SXGA output Access R/W R/W R/W Access R/W R/W R/W R/W
Version 0.1
- 15 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Output SYNC Timing Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 1Eh VDTOT-L VDTOT[7:0] 1Fh VDTOT-H VDTOT[10:8] 20h VSST-L VSST[7:0] 21h VSST-H VSRU VSST[10:8] 22h VSEND-L VSEND[7:0] 23h VSEND-H VSEND[10:8] 24h HDTOT-L HDTOT[7:0] 25h HDTOT-H HDTOT[10:8] 26h HSEND HSEND[7:0] n VDTOT[10:0] Output Vertical total Y 326h Recommended value for XGA output (power on default value is Y 42Ah Recommended value for SXGA output n VSST[10:0] Output VSYNC start (only useful when AOVS=1) Y 302h Recommended value for XGA output (power on default value is Y 402h Recommended value for SXGA output n VSEND[10:0] Output VSYNC end (only useful when AOVS=1) Y 304h Recommended value for XGA output (power on default value is Y 404h Recommended value for SXGA output n VSRU VSYNC Register Usage Y0 Register 20h - 23h is used to define output VSYNC Y1 Register 20h and 21h is used to define No signal VSYNC Y Register 22h and 23h is used to define minimum H total n HDTOT[10:0] Output Horizontal total Y 53fh Recommended value for XGA output (power on default value is Y 697h Recommended value for SXGA output n HSEND[7:0] Output HSYNC pulse width Y 20h Recommended value (power on default value is 0) Output Sync Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 27h OSCTRL1 AOVS LCM HSRM VSGP EHTT MOD2 AHRT CTRL 28h OSCTRL2 ATEN2 SLE CRM n AOVS Auto Output VSYNC Y0 OVSYNC is defined automatically Y1 OVSYNC is defined manually (register 0x20 - 0x23) n LOCK Lock mode Y0 Mode 0 Y1 Mode 1 n HSRM HSYNC Remove mode Y0 Normal Y1 Remove HSYNC when GPOA (Bank 2 register 0x62 - 0x6A) is low n VSGP VSYNC use GPO9 Y0 Disable Y1 Enable (Using Bank 2 register 0x59 - 0x61 to define OVSYNC) n EHTT Even H TOTAL Y0 Enable, Output HTOTAL always be even pixels Y1 Disable, Output HTOTAL may be odd pixels n MOD2 Mode 2 Y0 Disable Y1 Enable n AHRT Auto H total and Read Start Tuning Enable Access R/W R/W Bit 0 Access R/W R/W R/W R/W DB R/W 3) 3) 6)
3)
Version 0.1
- 16 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Y0 Y1 CTRL Y0 Y1 ATEN2 Y0 Y1 SLE Y0 Y1 CRM Y0 Y1 Disable Enable ATCTRL function Enable Disable Enable Lock Coarse Tune Type 2 Enable Disable Enable Short Line Even Clock Mode Even Odd Clock Reset Mode Old (near DE) New (move away from DE)
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Display Port Register (26, 2Ah - 43h)
Brightness Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 2Ah BRC 2Bh BCR BCR[7:0] 2Ch BCG BCG[7:0] 2Dh BCB BCB[7:0] n BRC Brightness function, reference to register 2Bh, 2Ch, 2Eh Y0 OFF Y1 ON n BCR[7:0] Brightness Coefficient - Red Color Y 00h -128 Y 80h 0, default value Y FFh +127 n BCG[7:0] Brightness Coefficient - Green Color Y 00h -128 Y 80h 0, default value Y FFh +127 n BCB[7:0] Brightness Coefficient - Blue Color Y 00h -128 Y 80h 0, default value Y FFh +127 Contrast Control Index 2Eh 2Fh 30h 31h n CCLR n CCLG n CCLB n CNTT Y0 Y1 n CNTR Y0 Y1
Version 0.1
Bit 1
Bit 0 BRC
Access R/W R/W R/W R/W
Mnemonic CNTR CCR CCG CCB
Bit 7 Bit 6 Bit 5 Bit 4 CCLR CCR[7:0] CCG[7:0] CCB[7:0] Contrast Coefficient LSB- Red Color Contrast Coefficient LSB- Green Color Contrast Coefficient LSB- Blue Color Contrast Type select Use 0 as center point Use 128 as center point Contrast function OFF ON
Bit 3 CCLG
Bit 2 CCLB
Bit 1 CNTT
Bit 0 CNTR
Access R/W R/W R/W R/W
- 17 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 CCR[7:0] Y 00h Y 80h Y FFh n CCG[7:0] Y 00h Y 80h Y FFh n CCB[7:0] Y 00h Y 80h Y FFh
n
Contrast Coefficient - Red Color 0.0000000 1.0000000, default value 1.1111111 Contrast Coefficient - Green Color 0.0000000 1.0000000, default value 1.1111111 Contrast Coefficient - Blue Color 0.0000000 1.0000000, default value 1.1111111
Border Color Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 32h FWC 33h FCR FCR[7:0] 34h FCG FCG[7:0] 35h FCB FCB[7:0] n FWC Border color (will be used when output is free run mode) Y0 OFF Y1 ON n FCR[7:0] Border Color - Red channel n FCG[7:0] Border Color - Green channel n FCB[7:0] Border Color - Blue channel Dither Control Index 36h 37h 38h Mnemonic DITHCTRL DITHCOEF TRFN Bit 7 Bit 6 DITHG[1:0] TL[1:0] Bit 5 Bit 4 DITHB[1:0] TR[1:0] DATP DRT Bit 3 Bit 2 SROT TROT BL[1:0] DT3 DT2 Bit 1 Bit 0 OBN DITH BR[1:0] DT1 TDFNC Access R/W R/W R/W Bit 1 Bit 0 FWC Access R/W R/W R/W R/W
Note: The default value of register 37h is 2Dh n SROT Spatial Coefficient Rotate
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n n n n n n n
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Y0 Y1 TROT Y0 Y1 OBN Y0 Y1 DITH Y0 Y1 DITHG[1:0] DITHB[1:0] TL[1:0] TR[1:0] BL[1:0] BR[1:0] DATP Y0 Y1 DRT
Disable Enable Temporal Coefficient Rotate Disable Enable Output Bits Number (used for 10bits/8 bits gamma) 8 bits output 6 bits output (power on default value) Dither Function OFF ON Dither Coefficient for G Channel Dither Coefficient for B Channel Top - Left Dither Coefficient Top - Right Dither Coefficient Bottom - Left Dither Coefficient Bottom - Right Dither Coefficient Dither based on Auto Phase threshold Disable Enable Dither Rotate Type
- 18 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved. 5/6/2003
Version 0.1
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Y0 Y1 DT3 Y0 Y1 DT2 Y0 Y1 DT1 Y0 Y1 TDFNC Y0 Y1 EOR Rotate Dither Type 2 control Disable dither type 2 Enable dither type 2 Dither Type 2 Output data bit 1 and 0 according to input pixel value Output data bit 2, 1, and 0 according to input pixel value Dither Type 1 Normal Output data bit 1 and 0 are always 00 Tempo-Dither Frame Number Control Tempo-dither every frame Tempo-dither every 2 frames
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Gamma Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 40h GAMMAC 41h GAMMAP GAMMAP[7:0] n GTCS Gamma Table Channel Select Y 00 Write Red Channel Y 01 Write Green Channel Y 10 Write Blue Channel Y 11 Write Red/Green/Blue Channel n GTIO Gamma Table I/O Access Y0 Disable Y1 Enable n GCFE Gamma correction function enable Y0 OFF Y1 ON n GAMMAP[7:0] Gamma Data Port Output Control Index 42h 43h 44h n LCPS Y0 Y1 n LCS Y0 Y1 n MLXT Y0 Y1 n LTIM Y0 Y1 n OMLX Y0 Y1 n EMLX Mnemonic OCTRL1 OCTRL2 OCTRL3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 LCPS LCS MLXT LTIM OMLX TCOP DOT WHTS BLKS REV CKSEL[4:0] LVDS Channel Polarity Swap (P/N swap) Disable Enable LVDS Channel Swap (0/1 swap, 2/5 swap) Disable Enable MSB/LSB Exchange Type Always reverse bit [7:0] Reverse bit [7:2] when 6 bits panel LVDS TI Mode Normal TI Mode Odd channel MSB/LSB Exchange Normal Exchange Even channel MSB/LSB Exchange Bit 2 EMLX STO Bit 1 ORBX DPX Bit 0 ERBX DPO Access R/W R/W R/W Bit 3 Bit 2 GTCS[1:0] Bit 1 GTIO Bit 0 GCFE Access R/W R/W
Version 0.1
- 19 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Y0 Y1 ORBX Y0 Y1 ERBX Y0 Y1 TCOP Y0 Y1 DOT Y0 Y1 WHTS Y0 Y1 BLKS Y0 Y1 REV Y0 Y1 STO Y0 Y1 DPX Y0 Y1 DPO Y0 Y1 CKSEL[4:0] Y Y CKSEL[4] Y CKSEL[3] Y CKSEL[2] Y CKSEL[1] Y CKSEL[0] Y Y 01h Y 1Dh Y 0Fh Y 15h Y 07h Y 00h Normal Exchange Odd channel Red/Blue bus Exchange Normal Exchange Even channel Red/Blue bus Exchange Normal Exchange TCON control pin port select (only used when OBN=1, 6 bits output) Use output data port Use video in port Differential Output Type LVDS/RSDS Reduced-swing LVDS/increased-swing RSDS White Screen (screen Off) Disable Enable Black Screen (screen Off) Disable Enable Reverse luminosity OFF ON Stagger output (only used when DPO=1) Disable Enable Dual pixel exchange (only used when DPO=1) Disable Enable Dual pixel output Single pixel Dual pixel Enable clock of internal control Supposes input interface (ADC/DVI) as the left-side Enable clock of down-side GPO Enable clock of up-side channel Enable clock of down-side channel Enable clock of right-side GPO Enable clock and output current of right-side channel Please use ADC bank register 0x2D bit 7 to control LVDS internal clock LVDS output Dual-Link RSDS output with down-side GPO Dual-Link RSDS output with right-side GPO Single-Link RSDS output with down-side GPO Single-Link RSDS output with right-side GPO TTL output
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OSD Overlay Registers (7, 46h - 4Ch)
OSD Alpha Blending Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 4Bh BLENDC CKIND[3:0] 4Ch BLENDL NBM Y When OSD register 0x10[7]=1, OSD is not backward compatible n CKIND[3:0] Color Index of Color Key Bit 2 Bit 1 ABM[2:0] BLENDL[2:0] Bit 0 Access R/W R/W
Version 0.1
- 20 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Y 0000 Color Index 0 Y 0001 Color Index 1 Y... ... Y 1111 Color Index 15 When OSD register 0x10[7]=0, OSD is backward compatible CKIND[3] Reserved ABM[2:0] Alpha Blending Mode Y 000 No alpha blending Y 001 Background alpha blending Y 010 Foreground alpha blending Y 011 Color key alpha blending Y 100 Not Color key alpha blending Y 101 Entire OSD alpha blending Y 11x Reserved NBM New Blending Level Y0 Original blending Level (BLENDL=000 means 0% transparency) Y1 New Blending Level (BLENDL=000 means 12.5% transparency) BLENDL[2:0] OSD alpha blending level Y 000 12.5% transparency. Y 001 25.0% transparency. Y 010 37.5% transparency. Y 011 50.0% transparency. Y 100 62.5% transparency. Y 101 75.0% transparency. Y 110 87.5% transparency. Y 111 100% transparency.
Y
n n
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Scaling Function Registers (28, 50h - 6Bh)
Scaling Ratio Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 50h SRH-L SRH[7:0] R/W 51h SRH-M SRH[15:8] R/W 52h SRH-H SENH HFMD SRH[21:16] R/W 53h SRV-L SRV[7:0] R/W 54h SRVH-M SRV[15:8] R/W 55h SRV-H SENV VFMD SRV[21:16] R/W n SENH Horizontal Scaling Enable Y0 Disable Y1 Enable n HFMD Horizontal Scaling Factor Mode Y0 N-1/M-1 for Horizontal Scaling Factor Y1 N/M for Horizontal Scaling Factor n SRH[21:0] Horizontal Scaling Ratio (2 bits integer, 20 bits fraction) for scaling down to 1/3.9999 Y xx.xxxxxxxxxxxxxxxxxxxx n SENV Vertical Scaling Enable Y0 Disable Y1 Enable n VFMD Vertical Scaling Factor Mode Y0 N-1 / M-1 for Vertical Scaling Factor Y1 N / M for Vertical Scaling Factor n SRV[21:0] Vertical Scaling Ratio (2 bits integer, 20 bits fraction) for scaling down to 1/2.9999 Y xx.xxxxxxxxxxxxxxxxxxxx
Version 0.1
- 21 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Scaling Filter Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 56h SFH SFH[7:0] 57h SFV SFV[7:0] 58h HDSUSG HDSUSG[7:0] 59h HDSUSL GSR TSR TXTJL[3:0] 5Ah VDSUSG VDSUSG[7:0] 5Bh VDSUSL MCKS IOCK GSE TSE DSUSL[3:0] n SFH[7:0] Horizontal Scaling filter n SFV[7:0] Vertical Scaling filter n HDSUSG[7:0] Horizontal DSUS Scaling Parameter n GSR Gray Scale Sensitive Register IO Y0 Disable Y1 Enable n TSR Text Sensitive Register IO Y0 Disable Y1 Enable n TXTJL[3:0] Text Judge Level n VDSUSG[7:0] Vertical DSUS Scaling Parameter n DSUSL[3:0] DSUS Scaling Parameter Level n MCKS Manual clock select Y0 Auto Select Y1 Manual select n IOCK Input/ FIX clock select (when MCKS=1) Y0 FIXCLK faster, FIXCLK defined by Reg D1h bit7 Y1 IDCLK faster n GSE Gray Scale Sensitive Function Enable Y0 Disable Y1 Enable n TSE Text Sensitive Function Enable Y0 Disable Y1 Enable Post Filter Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 5Ch PFEN 5Dh PFCOEF PFCOEF-H PFCOEF-L n PFEN Post Filter Enable Y0 Disable Y1 Enable n PFCOEF-H[3:0] Post Filter H Coefficient for edge part Y 0000 Blur Y... ... Y 1000 No action Y... ... Y 1111 Sharp n PFCOEF-L[3:0] Post Filter L Coefficient for no edge part Y 0000 Blur Y... ... Y 1000 No action Y... ... Y 1111 Sharp Bit 1 Bit 0 PFEN Access R/W R/W Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W
Version 0.1
- 22 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Filter Coefficient Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 65h FTAPEN sRGBP 66h SRGB12 SRGB12 [7:0] 67h SRGB13 SRGB13 [7:0] 68h SRGB21 SRGB21 [7:0] 69h SRGB23 SRGB23 [7:0] 6Ah SRGB31 SRGB31 [7:0] 6Bh SRGB32 SRGB32 [7:0] n sRGBP sRGB Precision Y0 Normal Y1 Shift 2 bits n sRGBG sRGB go through Gamma Y0 Bypass Gamma Y1 Go to Gamma n TPP Test Pattern Position Y0 After sRGB Y1 Before sRGB n FFSEL[1:0] Filter Function Select Y 00 Disable Y 01 Enable 3 tap function Y 1x Enable sRGB Function n SRGB12[7:0] Coefficient 12, 1 sign bit, 7 bits n... ... n SRGB32[7:0] Coefficient 32, 1 sign bit, 7 bits Interlaced Mode Line Shift Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 6Fh INTMDS ILIM ODDF n ILIM Insert line when interlace mode Y0 Don't insert Y1 Insert n ODDF Shift Odd Field Y0 Shift Even Field Y1 Shift Odd Field n SLN[2:0] Shift Line Numbers Y 000 Shift 0 line between odd and even field Y 001 Shift 1 line between odd and even field Y 010 Shift 2 line between odd and even field Y 011 Shift 3 line between odd and even field Y 1xx Shift 4 line between odd and even field Bit 2 Bit 1 SLN[2:0] Bit 0 Access R/W Bit 3 sRGBG Bit 2 TPP Bit 1 Bit 0 FFSEL[1:0] Access R/W R/W R/W R/W R/W R/W R/W
Auto Adjustment Registers (36, 70h - 93h)
Auto Gain Function Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 ATGM Bit 1 ATGR Bit 0 ATGE Access R/W 78h ATGCTRL n MAXR Y0 Y1 Y n MAXG MAXR MAXG MAXB ACE AGR Max value flag for red channel (read only) Normal Have max value (255) when AGR=0 Output over max value (255) when AGR=1 Max value flag for green channel (read only)
Version 0.1
- 23 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Y0 Y1 Y MAXB Y0 Y1 Y ACE Y0 Y1 AGR Y0 Y1 ATGM Y0 Y1 ATGR Y0 Y1 ATGE Y0 Y1 Normal Have max value(255) when AGR=0 Output over max value (255) when AGR=1 Max value flag for blue channel (read only) Normal Have max value(255) when AGR=0 Output over max value (255) when AGR=1 ADC Calibration Enable Disable Enable Auto Gain Result Selection Output has Max/Min Value Output is Overflow/Underflow Auto Gain Mode Normal Mode (result will be cleared every frame) History Mode (don't clear result until ATGE=0) Auto Gain result ready (read only) Result Not Ready Result Ready Auto Gain Function Enable Disable Enable
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Auto Gain Status Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 79h ATGST VCLP CALR CALG CALB MINR MING n VCLP Video auto gain Mode Y0 RGB mode Y1 YPbPr Mode n CALR Calibration value flag for red channel Y0 Normal Y1 Calibration result (need to increase offset) when ACE=1 n CALG Calibration value flag for green channel Y0 Normal Y1 Calibration result (need to increase offset) when ACE=1 n CALB Calibration value flag for blue channel Y0 Normal Y1 Calibration result (need to increase offset) when ACE=1 n MINR Min value flag for red channel Y0 Normal Y1 Have min value (0) when AGR=0, ACE=0 Y Output under min value (0) when AGR=1, ACE=0 Y Calibration result (need to decrease offset) when ACE=1 n MING Min value flag for green channel Y0 Normal Y1 Have min value (0) when AGR=0, ACE=0 Y Output under min value (0) when AGR=1, ACE=0 Y Calibration result (need to decrease offset) when ACE=1 n MINB Min value flag for blue channel Y0 Normal Y1 Have min value (0) when AGR=0, ACE=0 Y Output under min value (0) when AGR=1, ACE=0 Y Calibration result (need to decrease offset) when ACE=1 Bit 0 MINB Access RO
Version 0.1
- 24 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Auto Position Function and Jitter Function Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 7Bh ATOCTRL JITLR JITS JITM JITR ATOM ATOR ATOE 7Ch AOVDV AOVDV[3:0] n JITLR Jitter Function Left/Right Result for 86h and 87h Y0 Left Result Y1 Right Result n JITS Jitter Software Clear Y0 No clear Y1 Clear n JITM Jitter function mode Y0 Update every frame Y1 Keep the history value n JITR Jitter Function Result (read only) Y0 No Jitter Y1 Have Jitter n ATOM Auto Position function mode Y0 Update every frame Y1 Keep the history value n ATOR Auto Position result ready (read only) Y0 Result Not Ready Y1 Result Ready n ATOE Auto Position Function Enable Y0 Disable Y1 Enable Y Disable-to-enable needs at least 2 frames apart for ready bit to settle n AOVDV[3:0] Auto Position Valid Data Value Y 0000 Valid if data >= 0000 0000 Y 0001 Valid if data >= 0001 0000 Y 0010 Valid if data >= 0010 0000 Y... ... Y 1111 Valid if data >= 1111 0000 Auto Position Function Result Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 7Eh AOVST-L AOVST[7:0] 7Fh AOVST-H AOVST[10:8] 80h AOHST-L AOHST[7:0] 81h AOHST-H AOHST[11:8] 82h AOVEND-L AOVEND[7:0] 83h AOVEND-H AOVEND[10:8] 84h AOHEND-L AOHEND[7:0] 85h AOHEND-H AOHEND[11:8] n AOVST[10:0] Auto Position Detected Result Vertical Starting Point n AOHST[11:0] Auto Position Detected Result Horizontal Starting Point n AOVEND[10:0] Auto Position Detected Result Vertical End Point n AOHEND[11:0] Auto Position Detected Result Horizontal End Point Jitter Function Detecting Result Index 86h 87h Mnemonic JLR-L JLR-H Bit 7 Bit 6 JLR[7:0] Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access RO RO Bit 0 Access RO RO RO RO RO RO RO RO Access R/W R/W
JLR[10:8]
Version 0.1
- 25 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1
n
JLR[10:0] 7
Jitter function detected left/right most point state (previous frame) depend on Reg 7Bh bit
Auto Noise Reduction Function Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 88h ANRF HNEN BGEN n HNEN High Level Noise Reduction Enable Y0 Disable Y1 Enable n BGEN Background Noise Reduction Enable Y0 Disable Y1 Enable n ANLV[2:0] Auto Noise Level Y 111 Noise Level = 16 Auto Phase Control and Detecting Result
Bit 3
Bit 2 Bit 1 ANLV[2:0]
Bit 0
Access RO
Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 89h ATPGTH ATPGTH[7:0] 8Ah ATPTTH ATPTTH[7:0] 8Bh ATPCTRL GRY TXT APMASK[2:0] ATPR 8Ch ATPV1 ATPVALUE[7:0] 8Dh ATPV2 ATPVALUE[15:8] 8Eh ATPV3 ATPVALUE[23:16] 8Fh ATPV4 ATPVALUE[31:24] n ATPGTH[7:0] Auto Phase Gray Scale Threshold for ATPV3 when ATPN4=0 n ATPTTH[7:0] Auto Phase Text Threshold for ATPV4 n GRY Gray Scale Detect (read only) n TXT Text Detect (read only) n ATPTH[4:0] Auto Phase threshold n ATPMASK[2:0] Noise Mask Y 000 Mask 0 bit, default value Y 001 Mask 1 bit Y 010 Mask 2 bit Y 011 Mask 3 bit Y 100 Mask 4 bit Y 101 Mask 5 bit Y 110 Mask 6 bit Y 111 Mask 7 bit n ATPR Auto Phase result ready Y0 Result Not Ready Y1 Result Ready n ATPE Auto Phase Function Enable Y0 Disable Y1 Enable n ATPVALUE[31:0] Auto Phase Value VSYNC Status Index 90h 91h 92h 93h Mnemonic ASCTRL LSLVP-L LSLVP-H LSLW-L Bit 7 Bit 6 IVB LSLVP[7:0] LSLW[7:0] Bit 5 Bit 4 DLINE[1:0] Bit 3 Bit 2 Bit 1 UNDER
Bit 0
ATPE
Access R/W R/W R/W RO RO RO RO
Bit 0 OVER
LSLVP[10:8]
Access R/W RO RO RO
Version 0.1
- 26 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 VSYNC Status Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 94h LSLW-H 95h LVSST-L LVSSTATE[7:0] 96h LVSST-H 97h LHTST-L LHTSTAT[7:0] 98h LHTST-H 99h LFRST-L LFRSTAT[7:0] 9Ah LFRST-H 9Bh LMARGIN LHTTMGN[7:0] 9Ch LRSV-L LRSVALUE[7:0] 9Dh LRSV-H 9Eh LMARGIN LSSCMGN[7:0] n IVB Input VSYNC Blanking Status Y0 In display Y1 In blanking n DLINE[1:0] Delay Line n UNDER Under run status n OVER Over run status n LSLVP[10:0] Locking Short Line Vertical Position n LSLW[10:0] Locking Short Line Width n LVSSTAT[10:0] Locking Vertical Total Line Number n LHTSTAT[10:0] Locking H total Status n LFRSTAT[10:0] Locking Fraction Status n LHTTMGN[7:0] Locking H total Margin n LRSVALUE[10:0] Locking Read Start Value n LSSCMGN[7:0] Locking SSC Margin OSD I/O Access Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 A0h OSDIOA OSBM CLR RF DC n OSBM OSD SRAM I/O Access Burst Mode Y0 Disable Y1 Enable n CLR OSD Clear Bit (write only) Y0 Normal Y1 Clear code with 00h, attribute with 00h n RF OSD RAM Font I/O Access Y0 Disable Y1 Enable n DC OSD Display Code I/O Access Y0 Disable Y1 Enable n DA OSD Display Attribute I/O Access Y0 Disable Y1 Enable n ORBW OSD Register Burst Write Mode Y0 Disable Y1 Enable Bit 2 DA Bit 1 ORBW Bit 0 Access R/W Bit 3 Bit 2 Bit 1 LSLW[10:8] LVSSTATE[10:8] LHTSTAT[10:8] LFRSTAT[10:8] Bit 0 Access RO RO RO RO RO R/W R/W R/W R/W R/W R/W
LRSVALUE[10:8]
Version 0.1
- 27 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 OSD Register Address/Data Port Index Mnemonic Bit 7 Bit 6 Bit 5 A1h OSDRA OSDRA[6:0] A2h OSDRD OSDRD[7:0] n OSDRA[6:0] OSD Register Address Port n OSDRD[7:0] OSD Register Data Port OSD RAM Font Address/Data Port Index Mnemonic Bit 7 Bit 6 Bit 5 A3h RAMFA RAMFA[7:0] A4h RAMFD RAMFD[7:0] n RAMFA[7:0] OSD RAM Font Address Port n RAMFD[7:0] OSD RAM Font Data Port OSD Display Code Address/Data Port Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 A5h DISPCA-L DISPCA[7:0] A6h DISPCA-H A7h DISPCD DISPCD[7:0] n DISPCA[8:0] OSD Display Code Address Port n DISPCD[7:0] OSD Display Code Data Port OSD Display Attribute Address/Data Port Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 A8h DISPAA-L DISPAA[7:0] A9h DISPAA-H AAh DISPAD DISPAD[7:0] n DISPAA[8:0] OSD Display Attribute Address Port n DISPAD[7:0] OSD Display Attribute Data Port Bit 3 Bit 2 Bit 1 Bit 0 Access R/W DISPAA[8] R/W R/W Bit 3 Bit 2 Bit 1 Bit 0 Access R/W DISPCA[8] R/W R/W Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W
Frame Rate Convert for Fail-Safe Mode / LVDS/RSDS Test Mode Data Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Scaler bank register 0xD0[0] = 0 ABh FSM FSMEN FSMRATIO[3:0] Scaler bank register 0xD0[0] = 1 ABh TSTDATA TSTDATA[7:0] Y Scalar bank register 0xD0[0] = 0 n FSMEN Frame rate control enable Y0 Disable Y1 Enable n FSMRATIO[3:0] Output frame rate / input frame rate Y Bit[3] 1/2 Y Bit[2] 1/4 Y Bit[1] 1/8 Y Bit[0] 1 / 16 Y Scalar bank register 0xD0[0] = 1 n TSTDATA[7:0] LVDS/RSDS test mode data Y When LVDS output, use TSTDATA[7:1] Y When RSDS output, use TSTDATA[7:0] Bit 2 Bit 1 Bit 0 Access R/W R/W
Version 0.1
- 28 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1
I/O and PWM Control (16, B8h - C8h)
Watchdog Timer Function Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access B0h WDTEN WDTC WDTE R/W B1h WDTKEY WDTKEY[7:0] R/W B2h WDTCNT WDTCNT[7:0] R/W n WDTC Watchdog Timer Clear (protected by WDTKEY) Y0 Normal Y1 Clear n WDTE Watchdog Timer Enable (protected by WDTKEY) Y0 Disable Y1 Enable n WDTKEY[7:0] Watchdog Timer Enable Key Y To disable/clear Watchdog Timer, you must first write the WDTKEY with 55h, Aah to unlock. n WDTCNT[7:0] Watchdog Timer Counter Y The clock of Watchdog timer is frequency of XTAL/(256*1024) DDC Function Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 B3h DDCEN GPOU[1:0] DMEN CSOK DMST DMF GPO1 B4h DDCEN D_EN1 DFLT DIWP ISPT CSOK1 D_BSY1 D_RW1 B5h DDC_LAST DDC_LAST1[6:0] B6h DDCADDR S_RW1 DDC_ADDRP1[6:0] B7h DDCDATA DDC_DATAP1[7:0] B8h DDCEN D_EN2 D_BSY2 D_RW2 B9h DDC_LAST DDC_LAST2[6:0] Bah DDCADDR S_RW2 DDC_ADDRP2[6:0] BBh DDCDATA DDC_DATAP2[7:0] n GPOU[1:0] GPO Usage Y 00 GPO Y 01 MPU bypass Y 10 DDC bypass Y 11 ISP bypass (use I2C protocol) n DMEN DDC Master Function Enable Y0 Disable Y1 Enable n CSOK DDC Check sum (read only) Y0 Check sum not ok Y1 Check sum ok n DMST DDC Master Function Status (read only) Y0 Busy Y1 Not busy n DMF DDC Master Finish, already access 128 or 256 byte data (read only) Y0 Not finish Y1 Finish n GPO[1:0] GPO n D_EN DDC Function Enable Y0 Disable Y1 Enable n DFLT DDC Filter Y0 Enable Bit 0 Access GPO0 R/W D_DTY1 R/W RO R/W R/W D_DTY2 R/W RO R/W R/W
Version 0.1
- 29 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Y1 DIWP Y0 Y1 ISPT Y0 Y1 CSOK1 Y0 Y1 D_BSY Y0 Y1 D_RW Y0 Y1 D_DTY Y0 Y1 DDC_LAST[6:0] S_RW Y0 Y1 DDC_ADDRP[6:0] DDC_DATAP[7:0] Disable DDC I2C bus Write Protect Enable Disable ISP Using RS-232 Type Disable Enable DDC Check sum for input 1 (read only) Check sum not ok Check sum ok DDC Busy (read only) Not busy Busy DDC Last Read/Write Status (read Only) Write Read DDC SRAM Dirty status (read/clear) Not Dirty Dirty DDC Last R/W Address DDC SRAM Read/Write Write Read DDC Address Port DDC Data Port
n
n
n
n
n
n
n n
n n
MISC Function Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 BCh MISCFC AFT IDHTT VSGR VSP LBCG DEGP n AFT ATP filter for Text (4 frame) Y0 Disable Y1 Enable n IDHTT DE Only Mode HTT count by IDCLK Y0 Disable Y1 Enable n VSGR VSYNC glitch removal with line less than 2 (DE only) Y0 Disable Y1 Enable n VSP VSYNC protect with V total (DE only) Y0 Disable Y1 Enable n LBGC LB Clock no gating mode Y0 Disable Y1 Enable n DEGP DE Only Mode Glitch Protect for Position Y0 Disable Y1 Enable when F3 Bit7 = 1 and in DE Only Mode PWM Control Index C2h C3h C4h n PCLK
Version 0.1
Bit 1 -
Bit 0
Access R/W
Mnemonic PWMCLK PWM0C PWM1C
Bit 7 Bit 6 Bit 5 PWM0C[7:0] PWM1C[7:0] PWM base clock select
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 PCLK
Access R/W R/W R/W
- 30 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Y0 Y1 n PWM0C[7:0] n PWM1C[7:0] 14.318MHz 14.318MHz / 4 PWM0 Coarse adjustment PWM1 Coarse adjustment
Interrupt Control (9, Cah - D2h)
Interrupt Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Cah INTCTRL HCHGM DCMD HSPM HSST IVSI OVSI TRG INTT R/W CBh INTPULSE INTPULSE[7:0] R/W n HCHM HSYNC changing Detect method Y0 Interrupt only occurred at start and end of transition Y1 Interrupt occurred at every line n DCMD DVI Clock Missing Detected (read only; DVI feature only, independent of Scaler bank register 0x02h, ISEL[1:0]) Y0 DVI clock is OK Y1 DVI clock is missing n HSPM ADC mode: HSYNC pin monitor (read only), DVI mode: SCDT value Y When input is analog Y0 HSYNC pin is low Y1 HSYNC pin is high Y When input is DVI Y0 SCDT is missing Y1 SCDT is OK n HSST HS status (read only) Y0 Stable Y1 In change n IVSI Input V-SYNC interrupt generate by Y0 Leading edge Y1 Tailing edge n OVSI Output V-SYNC interrupt generate by Y0 Leading edge Y1 Tailing edge n TRGC Trigger condition Y0 Active low for level trigger/falling edge for edge trigger Y1 Active high for level trigger/rising edge for edge trigger n INTT Interrupt trigger Y0 Generate a edge trigger interrupt Y1 Generate a level trigger interrupt n INTPULSE[7:0] Interrupt Pulse Width by reference clock Interrupt Status Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 CCh INTSTA INTSTA[7:0] CDh INTSTB INTSTB[7:0] Ceh INTENA INTENA[7:0] CFh INTENB INTENB[7:0] n INTSTA[7:0] Interrupt Status Byte A Y Bit 7 Input VSYNC Changed (co-work with register E7h) Y Bit 6 Input HSYNC Changed (co-work with register E6h) Y Bit 5 Input VSYNC disappear Y Bit 4 Input HSYNC disappear Y Bit 3 Input VSYNC edge Bit 1 Bit 0 Access R/C R/C R/W R/W
Version 0.1
- 31 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Y Bit 2 Y Bit 1 Y Bit 0 n INTSTB[7:0] Y Bit 7 Y Bit 6 Y Bit 5 Y Bit 4 Y Bit 3 Y Bit 2 Y Bit 1 Y Bit 0 n INTENA[7:0] Y0 Y1 n INTENB[7:0] Y0 Y1 Output VSYNC edge ADC0 HSYNC0 pin toggling (independent with Reg 02h ISEL[1:0]) Composite sync/SOG status change Interrupt Status Control Byte B Auto Phase Ready Auto Position Ready Auto Gain Ready Jitter Detected ADC1 HSYNC1 pin toggling DVI clock status change; no clock <-> with clock Watchdog Timer Under / over run occurred Interrupt Enable Control Byte A Disable Interrupt Enable Interrupt Interrupt Enable Control Byte B Disable Interrupt Enable Interrupt
Clock generator (16, D0h-Dfh)
Clock Generator Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 D0h PLLCRTL1 XOUT EOCK XDIV[1:0] BPM D1h PLLCTRL2 MPPDIV LP_POR LP_RST LP_PD MP_K n XOUT Enable PWM1 as XTAL clock output Y0 Disable Y1 Enable, default value n EOCK Use External Clock (pin #) as Output Dot Clock Y0 Disable (use internal dot clock) Y1 Enable (use external dot clock), default value n XDIV XTAL clock divide by Y 00 16 Y 01 08 Y 10 04 Y 11 01 n BPM Bypass Clock Mode (IDCLK as ODCLK) Y0 Disable Y1 Enable n TSTM Test Mode Y0 Disable Y1 Enable n PTEN PLL Test Register Protect Bit Y0 Disable Y1 Enable n LRTM LVDS/RSDS Test Mode Enable Y0 Disable Y1 Enable n MPPDIV MPLL Post Divider Y0 div 3 (143 MHz) Y1 div 2.5 (172 MHz), for output dot clock higher n LP_POR Output PLL Power On Reset n LP_RST Output PLL Reset n LP_PD Output PLL Power Down n MP_K Master PLL output frequency divided by 2 Bit 2 Bit 1 Bit 0 TSTM PTEN LRTM MP_POR MP_RST MP_PD Access R/W R/W
than 143Mhz (Vertical=85Hz)
Version 0.1
- 32 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1
n n n
MP_POR MP_RST MP_PD
Master PLL Power On Reset Master PLL Reset Master PLL Power Down
Master & Output PLL Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 D2h MPLL_M MP_ICTRL[2:0] MPLL_M4:0] D3h LPLL_M SDEN SDMD LPLL_M4:0] D4h LPLL_CTL2 SCTRL[1:0] LP_TP LP_K[1:0] n MPLL_M[4:0] Master PLL divider n MP_K Master PLL Post Divider n MP_ICTRL[2:0] Master PLL Current Control Y 000 2.5 uA Y 001 5.0 uA Y 010 7.5 uA Y 011 10.0 uA, recommended Y 100 12.5 uA Y 101 15.0 uA Y 110 20.0 uA Y 111 40.0 uA n LPLL_M[4:0] Output PLL divider n LP_PD Output PLL Power Down n LP_RST Output PLL Reset n LP_POR Output PLL Power On Reset n LP_TP Output PLL Type Y0 LVDS Y1 RSDS/TTL n SCTRL[1:0] SSC Control Y 0x Normal Y 10 Disable SSC 2 lines Y 11 Disable SSC More lines n SDEN Output PLL Spread Spectrum Enable n SDMD Output PLL Spread Spectrum Mode Y0 Normal Y1 Reverse for Mode 1 n LP_K[1:0] Output PLL Post Divider Y 00 8 Y 01 4 Y 10 2 Y 11 1 n LP_ICTRL[2:0] Output PLL Current Control Y 000 1.25 uA Y 001 2.50 uA Y 010 3.75 uA Y 011 5.00 uA, recommended Y 100 6.25 uA Y 101 7.50 uA Y 110 10.0 uA Y 111 20.0 uA Frequency Synthesizer & SSC Control Index D5h Mnemonic LPLL_SET Bit 7 Bit 6 LP_SET[7:0] Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W, DB Bit 2 Bit 1 Bit 0 Access R/W R/W R/W
LP_ICTRL[2:0]
Version 0.1
- 33 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Frequency Synthesizer & SSC Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 D6h LPLL_SET LP_SET[15:8] D7h LPLL_SET LP_SET[23:16] D8h LPLL_STEP LP_STEP[7:0] D9h LPLL_STEP Dah LPLL_SPAN LP_SPAN[7:0] DBh LPLL_SPAN LP_SPAN[14:8] n LP_SET[23:0] Output PLL SET n LP_STEP[10:0] Output PLL Spread Spectrum Step n LP_SPAN[14:0] Output PLL Spread Spectrum Span PLL Test Control Index DCh DDh Deh DFh Mnemonic MPLL_TST LPLL_TSTD LPLL_TSTA SSC_TST Bit 7 Bit 6 MP_TEST[7:0] LP_TESTD[7:0] LP_TESTA[7:0] LP_TESTD[15:8] Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W Bit 3 Bit 2 Bit 1 Bit 0 Access R/W, DB R/W, DB R/W, DB R/W, DB R/W, DB R/W, DB
LP_STEP[10:8]
Mode Detect Status (10, E0h-E9h)
Input Sync Monitor Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 E0h STATUS1 IHSM IVSM OHSM n IHSM Input normalized horizontal SYNC pin monitor Y Show input horizontal SYNC pin directly n IVSM Input normalized vertical SYNC pin monitor Y Show input vertical SYNC pin directly n OHSM Output normalized horizontal SYNC pin monitor (pin OHSYNC) Y Show output horizontal SYNC directly n OVSM Output normalized vertical SYNC monitor (pin OVSYNC) Y Show output vertical SYNC directly Mode Detect Status Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 E1h STATUS2 CSD SOGD INTM INTF IHSP E2h VTOTAL-L VTOTAL[7:0] E3h VTOTAL-H VTOTAL[10:8] E4h HSPRD-L HSPRD[7:0] E5h HSPRD-H IHDM HSPRD[12:8] n CSD Composite Sync Detected Status Y0 Input is not Composite sync. Y1 Input is detected as Composite sync n SOGD Sync On Green Detected Status Y0 Input is not SOG. Y1 Input is detected as SOG n INTM Interlace/Non-interlace detecting result by this chip Y0 Non-interlace Y1 Interlace n INTF Input ODD/EVEN field detecting result by this chip Y0 EVEN Bit 0 IVSP Access RO RO RO RO RO Bit 0 OVSM Access RO
Version 0.1
- 34 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Y1 IHSP Y0 Y1 IVSP Y0 Y1 VTOTAL[10:0] IHDM Y0 Y1 HSPRD[12:0] ODD Incoming input horizontal SYNC polarity detecting result by this chip Active low Active high Incoming input vertical SYNC polarity detecting result by this chip Active low Active high Input Vertical Total, count by HSYNC Input HSYNC period Detect Mode One Line 16 Line Input Horizontal Period, count by reference clock
n
n
n n
n
Sync Change Tolerance Index Mnemonic Bit 7 Bit 6 Bit 5 E6h HSTOL HSTOL[7:0] E7h VSTOL ANGF n HSTOL[7:0] HSYNC Tolerance Y5 Default value n VSTOL[3:0] VSYNC Tolerance Y1 Default value n ANGF Auto No Signal Filter Mode n ANG Auto No Signal Status Override/Interlace Detect Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 E8h ISOVRD VERR CSHS UVSP IVSJ UHSP IHSJ UINT E9h MDCTRL VFIV VEXF INTF n VERR Video CCIR656 Error correct Y0 Disable Y1 Enable n CSHS HSYNC in coast Y0 HSOUT (recommended) Y1 Re-shaped HSYNC n UVSP User defined input vertical SYNC Polarity, active when IVSJ=1. Y0 Active LOW Y1 Active High n IVSJ Input vertical SYNC Polarity judgment Y0 Use result of internal circuit detection Y1 Defined by user (UVSP) n UHSP User defined input horizontal SYNC Polarity active when IHSJ=1. Y0 Active LOW Y1 Active High n IHSJ input horizontal SYNC Polarity judgment Y0 Use result of internal circuit detection Y1 Defined by user (UHSP) n UINT User defined non-interlace/Interlace active when INTJ=1. Y0 Non-interlace Y1 Interlace n INTJ Interlace judgment Y0 Use result of internal circuit detection Y1 Defined by user (UINT) n VFIV Video Field Inversion Y0 Normal
Version 0.1 - 35 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
Bit 4 ANG
Bit 3
Bit 2
Bit 1
Bit 0
VSTOL[3:0]
Access R/W R/W
Bit 0 INTJ IFI
Access R/W R/W
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Y1 VEXF Y0 Y1 n INTF Y0 Y1 n IFI Y0 Y1
n
Invert Video External Field Use result of internal circuit detection Use external field Interlace Field detect method select Use the HSYNC numbers of a field to judge Use the relationship of VSYNC and HSYNC to judge Interlace Field Invert Normal Invert
SOG HSYNC Pulse Width Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Eah SOGHSPW SOGHSPW[7:0] n SOGHSPW[7:0] SOG HSYNC Pulse width (OSC clock base unit) Bit 2 Bit 1 Bit 0 Access RO
Misc. Control (13, Edh - F6h)
Coast Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Edh COCTRL1 AVIS DLYV CSCM EXVS COVS Eeh COCTRL2 COST[7:0] Efh COCTRL3 COEND[7:0] n AVIS Analog Video Input Select Y0 PC Y1 Component analog video n DLYV Analog Delay Line for component analog video input Y0 Delay 1 line Y1 Don't delay n CSCM Composite SYNC Cut Mode Y0 Disable Y1 Enable n EXVS External VSYNC polarity (only used when COVS is 1) Y0 Normal Y1 Invert n COVS Coast VSYNC Select Y0 Internal VSEP Y1 External VSYNC n CTA Coast To ADC Y0 Disable Y1 Enable n Define the Coast signal coverage range n COEND[7:0] End tuning Y 00 COAST end at 1 HSYNC leading edge Y 01 COAST end at 2 HSYNC leading edge, default value Y... ... Y 254 COAST end at 255 HSYNC leading edge Y 255 COAST end at 256 HSYNC leading edge n COST[7:0] Front tuning Y 00 COAST start from 1 HSYNC leading edge Y 01 COAST start from 2 HSYNC leading edge, default value Y... ... Y 254 COAST start from 255 HSYNC leading edge Y 255 COAST start from 256 HSYNC leading edge Bit 0 CTA Access R/W R/W R/W
Version 0.1
- 36 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1
Power Down Control/Software Reset Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F0h PDMD APDLD APDLA PDDS GCLK[1:0] PDMD[1:0] F1h SWRST ADCR GPR DPR BIUR OSDR SWR n APDLD Automatically Power Down when Low Power using Digital pin Y0 Disable Y1 Enable n APDLA Automatically Power Down when Low Power using Analog Pin Y0 Disable Y1 Enable n PDDS Power Down DDC SRAM Y0 Normal Y1 Power Down while not used n GCLK[1:0] Gated Clock for SRAM (excluding DDC SRAM) Y 00 Normal Y 01 V Blank Y 10 H Blank and V Blank Y 11 Reserved n PDMD[1:0] Power Down Mode Y 00 Normal (no power saving) Y 01 Output (OSD) Only (used when no input signal) Y 10 BIU, Mode detection, GOUT are functional Y 11 All chip power down n ADCR ADC Reset Y0 Normal operation Y1 Reset ADC n GPR Graphic Port Reset Y0 Normal operation Y1 Reset n DPR Display Port Reset Y0 Normal operation Y1 Reset n BIUR BIU Reset Y0 Normal operation Y1 Reset BIU n OSDR Internal OSD Reset Y0 Normal operation Y1 Reset Internal OSD n SWR Software reset (reset GP, DP, BIU and OSD) Y0 Normal operation Y1 Reset Output Signal Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 F2h OSCTRL OCLKDLY[3:0]/RSCK_SKE[3:0] OCLK n OCKDLY[3:0] OCLK delay adjustment (TCON feature only) Y 16 steps to adjust Y Typical 0.8ns delay/step n RSCK_SKE[3:0] RSDS clock adjust Y RSCK_SKE[3] RSDS clock inverted Y0 Normal clock output Y1 RSDS clock output inverted Bit 2 ODE Bit 1 OVS Bit 0 OHS Access R/W Access R/W R/W
Version 0.1
- 37 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Y RSCK_SKE[2:0] Y 000 Y 001 Y 011 Y 111 n OCLK Y0 Y1 n ODE Y0 Y1 n OVS Y0 Y1 n OHS Y0 Y1 RSDS clock skew adjust Max. setup time/min. hold time to RSDS data output ... ... Min. setup time/max. hold time tot RSDS data output Output CLK Control Normal Invert Output DE Control Active High Active Low Output VSYNC Control Active High Active Low Output HSYNC Control Active High Active Low
Input Signal Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 F3h ISCTRL DEGE DEGR[2:0] n DEGE DE Glitch Removal Function Enable Y0 Disable Y1 Enable n DEGR[2:0] DE Glitch Removal Range n HSFL Input HSYNC filter Y When input source is Analog Y0 Filter OFF Y1 Filter ON Y When input source is DVI Y0 Normal Y1 More tolerance for unstable DE n ISSM Input sync sample mode Y0 Normal Y1 Glitch-removal n SCKI Input Sample CLK Invert Y0 Normal Y1 Invert Output Tri-State Control Index F4h Y0 Y1 n OEDB Y0 Y1 n OODB Y0 Y1 n OVS Y0 Mnemonic TRISTATE Bit 7 Bit 6 TCS Bit 5 OEDB Bit 4 OODB Bit 3 OVS Bit 2 OHS Bit 1 ODE Bit 0 OCLK Access R/W Bit 3 HSFL Bit 2 ISSM Bit 1 Bit 0 SCKI Access R/W
Note: The default value is 7Fh n TCS HSYNC/VSYNC
Control Signal pin tri-state control (TCON feature only) Normal Tri-state Output Even Data Bus pin control Normal TRI-state Output Odd Data Bus pin control Normal TRI-state OVSYNC pin control Normal
Version 0.1
- 38 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Y1 OHS Y0 Y1 n ODE Y0 Y1 n OCLK Y0 Y1
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TRI-state OHSYNC pin control Normal TRI-state ODE pin control Normal TRI-state OCLK pin control Normal TRI-state
Output Driving Current Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 F5h ODRV DEDRV[1:0] CLKDRV[1:0] ODDDRV[1:0] n DEDRV[1:0] Output DE Driving Current Select Y 00 4 mA Y 01 6 mA Y 10 8 mA Y 11 12 mA n CLKDRV[1:0] Output Clock Driving Current Select Y 00 4 mA Y 01 6 mA Y 10 8 mA Y 11 12 mA n ODDDRV[1:0] Output Data Odd Channel Driving Current Select Y 00 4 mA Y 01 6 mA Y 10 8 mA Y 11 12 mA n EVENDR[1:0] Output Data Even Channel Driving Current Select Y 00 4 mA Y 01 6 mA Y 10 8 mA Y 11 12 mA Even Clock Delay Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F6h ECLKDLY SKEW[1:0] ECLKDLY[3:0]/TESTMOD[15:12] n SKEW[1:0] Output data skew n ECKDLY[3:0] ECLK delay adjustment (TCON feature only) Y 16 steps to adjust Y Typical 0.8ns delay/step n TESTMOD[15:14] Reserved n TESTMOD[13] RSDS differential output clock test mode Y0 Normal operation Y1 Set RSDS differential output clock low n TESTMOD[12] RSDS differential output clock test mode Y0 Normal operation Y1 Set RSDS differential output clock high RSDS SRAM Test Status Index F7h Mnemonic RSDSTEST Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RSRP Bit 0 RSRF Access RO Access R/W Bit 1 Bit 0 EVENDR[1:0] Access R/W
Version 0.1
- 39 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 RSRP Y0 Y1 n RSRF Y0 Y1
n
RSDS SRAM Test Result Not Pass Pass RSDS SRAM Test Finish Not Finish Finish
Test Mode Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 F8h TEST TEST_CLK_MODE PLL_DIV2[1:0] n TEST_CLK_MODE Y0 Disable Y1 Enable, test clock tree n PLL_DIV2[1:0] Y 00 Normal Y 01 ODCLK and LBCLK divided by 2 Y 10 Reserved Y 11 Reserved n TESTMD[3:0] Test Mode Y 0011 BIST SRAM Test Status Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 F9h SRAMTEST DSRP DSRF GSRP GSRF n DSRP DDC SRAM Test Result Y0 Not Pass Y1 Pass n DSRF DDC SRAM Test Finish Y0 Not Finish Y1 Finish n GSRP Gamma SRAM Test Result Y0 Not Pass Y1 Pass n GSRF Gamma SRAM Test Finish Y0 Not Finish Y1 Finish n OSRP Internal OSD SRAM Test Result Y0 Not Pass Y1 Pass n OSRF Internal OSD SRAM Test Finish Y0 Not Finish Y1 Finish n LSRP Line buffer SRAM Test Result Y0 Not Pass Y1 Pass n LSRF Line buffer SRAM Test Finish Y0 Not Finish Y1 Finish Bit 3 OSRP Bit 2 OSRF Bit 1 LSRP Bit 0 LSRF Access RO Bit 3 Bit 2 TESTMD[3:0] Bit 1 Bit 0 Access R/W
Version 0.1
- 40 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1
OSD Register
OSD Double Buffer Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DBE Access R/W
01h OSDDBC n DBL[1:0] Y 00 Y 01 Y 10 Y 11 n DBE Y0 Y1 OSD Start Position
DBL[1:0] Double buffer load Keep old register value Load new data (auto reset to 00 when load finish) Automatically load data at VSYNC blanking Reserved Double Buffer Enable Disable Enable
Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 02h OHSTA-L OHSTA[7:0] 03h OHSTA-H 04h OVSTA-L OVSTA[7:0] 05h OVSTA-H n OHSTA[8:0] OSD window horizontal start position = 4 * OHSTA + 48 (pixel) n OVSTA[8:0] OSD window vertical start position = 4 * OVSTA (line) OSD Size Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 06h OSDW OSDW[5:0] 07h OSDH OSDH[4:0] n OSDW[5:0] OSD window width = OSDW + 1 (column), maximum 64 columns n OSDH[4:0] OSD window height = OSDH + 1 (row), maximum 32 rows OSD Space Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 08h OHSPA OHSPA[5:0] 09h OVSPA OVSPA[4:0] 0Ah OSPW OSPW[7:0] 0Bh OSPH OSPH[7:0] n OHSPA[5:0] OSD window horizontal space start position = OHSPA + 1 (row) n OVSPA[4:0] OSD window vertical space start position = OVSPA + 1 (column) n OSPW[7:0] OSD space width = 8 * OSPW (pixel) n OSPH[7:0] OSD space height = 8 * OSPH (line) Internal OSD Control 1 Index 0Ch
n
Bit 0
Access R/W OHSTA[8] DB R/W OVSTA[8] DB
Bit 0
Access R/W, DB R/W, DB
Bit 0
Access R/W R/W R/W R/W
Mnemonic IOSDC1
Bit 7 OVS[1:0]
Bit 6
Bit 5 OHS[1:0]
Bit 4
Bit 3 MWB
Bit 2 -
Bit 1
Bit 0 MWIN
Access R/W DB
OVS[1:0] Y 00 Y 01 Y 10
OSD vertical scaling Vertical normal size Vertical enlarged x2 by repeated pixels Vertical enlarged x3 by repeated pixels
Version 0.1
- 41 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Y 11 OHS[1:0] Y 00 Y 01 Y 10 Y 11 n MWBT Y0 Y1 n MWIN Y0 Y1
n
Vertical enlarged x4 by repeated pixels OSD horizontal scaling Horizontal normal size Horizontal enlarged x2 by repeated pixels Horizontal enlarged x3 by repeated pixels Horizontal enlarged x4 by repeated pixels OSD Main Window Border Type Bottom-right direction boundary (shadow border) All direction boundary (border) OSD Main Window Display Main window OFF Main window ON
Internal OSD Control 2 Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 0Dh IOSDC2 CF8E BCLR[2:0] BDC BDW n CF8E 8 color font enable Y0 Disable Y1 Enable n BCLR[3:0] OSD Border Color Index; BCLR[3] is located at 0E Bit5 Y 0000 Color Index 0 Y 0001 Color Index 1 Y 1111 Color Index 15 n BDC OSD Character Border Type Select Y0 All direction font boundary (border) Y1 Bottom - right direction font boundary (shadow) n BDW OSD Character Border Width Control Y0 One pixel width for all scale Y1 Scale with OVS[1:0] and OHS[1:0] n CPAL_SEL Y0 8 color palette Y1 16 color palette n CF4E 4 Color Font Enable Y0 Disable Y1 Enable Internal OSD Control 3 Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0Eh IOSDC3 CKIND[3] BCLR[3] SCLR[3] SDC SCLR[2:0] Y When OSD register 0x10[7]=0, OSD is backward compatible n CKIND[3] Color Index Bit 3 of Color Key Y When OSD register 0x10[7]=1, OSD is not backward compatible n CKIND[3] Resevred n BCLR[3] Border Color Bit 3; this bit should work with OSD 0D Bit[6:4] n SDC OSD Window Shadow Control Y0 OFF Y1 ON n SCLR[3:0] OSD Window Shadow Color Index Y 0000 Color Index 0 Y 0001 Color Index 1 Y... ... Y 1111 Color Index 15 Bit 0 Access R/W, DB Bit 1 Bit 0 C16_PAL CF4E Access R/W
Version 0.1
- 42 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 OSD Window Shadow Control Index Mnemonic Bit 7 Bit 6 0Fh OSHC OSDSH[3:0] n OSDSH[3:0] OSD Shadow Height n OSDSW[3:0] OSD Shadow Width OSD Color Font Format Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 10h OCFF OCFF n OCFF OSD backward compatibility Y0 Back compatible Y1 Not backward compatible n CFCTOSD Color Font Code Address Type Y0 RAM base Y1 Code base OSD Color Font Starting Address Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 11h OSDCFA OSD4CFA[7:0] n OSDCFA[7:0] OSD 4 Color RAM Font Starting Address OSD Code Buffer Offset/Base Address Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 12h OCBUFO COS OOFFSET[5:0] 13h OSDBA-L OSDBA[7:0] 14h OSDBA-H n COS OSD Code Buffer Offset Select Y0 Use OSDW[5:0] as offset Y1 Use OOFFSET[5:0] as offset n OOFFSET[5:0] OSD code buffer offset value n OSDBA[8:0] OSD Code Base Address OSD Gradually Color Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 15h GCCTRL GVS[1:0] GHS[1:0] GRAD n GVS[1:0] Gradually Color vertical scaling Y 00 Vertical normal size Y 01 Vertical enlarged x2 by repeated pixels Y 10 Vertical enlarged x3 by repeated pixels Y 11 Vertical enlarged x4 by repeated pixels n GHS[1:0] Gradually Color horizontal scaling Y 00 Horizontal normal size Y 01 Horizontal enlarged x2 by repeated pixels Y 10 Horizontal enlarged x3 by repeated pixels Y 11 Horizontal enlarged x4 by repeated pixels n GRAD Enable OSD Gradually Color Function Y0 Disable Y1 Enable n GCRNG[2:0] Gradually Color Applied Range Y 000 Sub Window 0 Bit 2 Bit 1 GCRNG[2:0] Bit 0 Access R/W Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W DB Bit 2 Bit 1 Bit 0 Access R/W Bit 3 CFCT Bit 2 Bit 1 Bit 0 Access R/W Bit 5 Bit 4 Bit 3 Bit 2 OSDSW[3:0] Bit 1 Bit 0 Access R/W
OSDBA[9:8]
Version 0.1
- 43 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Y Y Y Y 001 010 011 1xx Sub Window 1 Sub Window 2 Sub Window 3 Full Screen
OSD Starting Gradually Color Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 16h GRADCLR F/B RCLR[1:0] n F/B Gradually Applied Color Y0 Background Color Y1 Foreground Color n RCLR[1:0] Red Starting Gradually Color Y 00 Red color is 00h Y 01 Red color is 55h Y 10 Red color is Aah Y 11 Red color is FFh n GCLR[1:0] Green Starting Gradually Color Y 00 Green color is 00h Y 01 Green color is 55h Y 10 Green color is Aah Y 11 Green color is FFh n BCLR[1:0] Blue Starting Gradually Color Y 00 Blue color is 00h Y 01 Blue color is 55h Y 10 Blue color is Aah Y 11 Blue color is FFh OSD Horizontal Gradually Color Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 17h HGRADCR SR IRH R_GRADH[5:0] 18h HGRADCG SG IGH G_GRADH[5:0] 19h HGRADCB SB IBH B_GRADH[5:0] 1Ah HGRADSR HGRADSR[7:0] 1Bh HGRADSG HGRADSG[7:0] 1Ch HGRADSB HGRADSB[7:0] n SR Sign Bit of Red Color Y0 Increase Y1 Decrease n IRH Inverse Bit of Red Color Y0 Normal Y1 Invert n R_GRADH[6:0] Increase/Decrease value of Red Color n SG Sign Bit of Green Color Y0 Increase Y1 Decrease n IGH Inverse Bit of Green Color n G_GRADH[6:0] Increase/Decrease value of Green Color n SB Sign Bit of Blue Color Y0 Increase Y1 Decrease n IBH Inverse Bit of Blue Color n B_GRADH[6:0] Increase/Decrease value of Blue Color n HGRADSR[7:0] Horizontal Gradually Step of Red Color Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W Bit 3 Bit 2 GCLR[1:0] Bit 1 Bit 0 BCLR[1:0] Access R/W
Version 0.1
- 44 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1
n
HGRADSG[7:0]
Horizontal Gradually Step of Green Color
n HGRADSB[7:0] Horizontal Gradually Step of Blue Color For example, if RCLR=0, R_GRADH=16h, and HGRADSR=20h, then Pixel 0 - 19 : 0 Pixel 20 - 39 : 16 Pixel 40 - 59 : 32 Etc.
OSD Vertical Gradually Color Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 1Dh VGRADCR SR IRV R_GRADV[5:0] 1Eh VGRADCG SG IGV G_GRADV[5:0] 1Fh VGRADCB SB IBV B_GRADV[5:0] 20h VGRADSR VGRADSR[7:0] 21h VGRADSG VGRADSG[7:0] 22h VGRADSB VGRADSB[7:0] n SR Sign Bit of Red Color Y0 Increase Y1 Decrease n IRV Inverse Bit of Red Color Y0 Normal Y1 Invert n R_GRADV[6:0] Increase/Decrease value of Red Color n SG Sign Bit of Green Color Y0 Increase Y1 Decrease n IGV Inverse Bit of Green Color n G_GRADV[6:0] Increase/Decrease value of Green Color n SB Sign Bit of Blue Color Y0 Increase Y1 Decrease n IBV Inverse Bit of Blue Color n B_GRADV[6:0] Increase/Decrease value of Blue Color n VGRADSR[7:0] Horizontal Gradually Step of Red Color n VGRADSG[7:0] Horizontal Gradually Step of Green Color n VGRADSB[7:0] Horizontal Gradually Step of Blue Color OSD Sub Window 0 Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 23h SUBW0C BTN0 BD0 S0C S0E R/W, DB n BTN0 Enable Button Function for sub window 0 Y0 OFF Y1 ON n BD0 Enable OSD Sub Window 0 Border Y0 Disable Y1 Enable n S0C Sub Window 0 color select Y If Button function is disabled Y0 From Sub Window 0 attribute Y1 From attribute RAM Y If Button function is enabled Y0 Set this bit with 0. Use Sub Window 0 attribute to select FG/BG color and use attribute RAM to select button type n S0E Enable OSD Sub Window 0 Bit 2 Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W
Version 0.1
- 45 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Y0 Y1 Disable Enable
OSD Sub Window 0 Horizontal/Vertical Position Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 24h SW0HST SW0HST[5:0] 25h SW0HEND SW0HEND[5:0] 26h SW0VST SW0VST[4:0] 27h SW0VEND SW0VEND[4:0] n SW0HST[5:0] Sub Window 0 Horizontal Start Position n SW0HEND[5:0] Sub Window 0 Horizontal End Position n SW0VST[4:0] Sub Window 0 Vertical Start Position n SW0VEND[4:0] Sub Window 0 Vertical End Position OSD Sub Window 0 Attribute Index 28h Mnemonic SUBW0A2 Bit 7 BLNK Bit 6 Bit 5 FGCLR[2:0] Bit 4 Bit 3 TRAN Bit 2 Bit 1 BGCLR[2:0] Bit 0 Access R/W Bit 2 Bit 1 Bit 0 Access R/W, DB R/W, DB R/W, DB R/W, DB
Note: When Button function is enabled, the FG/BG color is defined by window attribute, character attribute is used to define button border type and S0C (sub window color select) is disabled. n BLNK OSD Sub Window 0 Blink Control Y0 Disable Y1 Enable n TRAN OSD Sub Window 0 Transparency Control Y0 Disable Y1 Enable n FGCLR[2:0] OSD Sub Window 0 Foreground Color Select Y 000 Color Index 0 Y 001 Color Index 1 Y... ... Y 111 Color Index 7 n BGCLR[2:0] OSD Sub Window 0 Background Color Select Y 000 Color Index 0 Y 001 Color Index 1 Y... ... Y 111 Color Index 7 Attribute SRAM Index Mnemonic Bit 7 Bit 6 28h SUBW0A2 n BTNU Button Up Control Y0 Button Up Y1 Button Down n BTNTYPE[3:0] Button border type Y0 No button Y1 1 2 3 4 5 6 Bit 5 Bit 4 BTNU Bit 3 Bit 2 BTNTYPE[3:0] Bit 1 Bit 0 Access R/W
7
8
9
a |
b |
c -
d -
e ||
f -
Note: The register of sub window 1, 2, and 3 are very similar with sub window 0
Version 0.1
- 46 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 OSD Sub Window 1 Register Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 29h SUBW1C BTN1 2Ah SW1HST SW1HST[5:0] 2Bh SW1HEND SW1HEND[5:0] 2Ch SW1VST SW1VST[4:0] 2Dh SW1VEND SW1VEND[4:0] 2Eh SUBW1A BLNK FGCLR[2:0] TRAN n BTN1 Enable Button Function for sub window 1 n BD1 Enable OSD Sub Window 1 Border n S1E Enable OSD Sub Window 1 n S1C Sub Window 1 color select n SW1HST[5:0] Sub Window 1 Horizontal Start Position n SW1HEND[5:0] Sub Window 1 Horizontal End Position n SW1VST[4:0] Sub Window 1 Vertical Start Position n SW1VEND[4:0] Sub Window 1 Vertical End Position n BLNK OSD Sub Window 1 Blink Control n FGCLR[2:0] OSD Sub Window 1 Foreground Color Select n TRAN OSD Sub Window 1 Transparency Control n BGCLR[2:0] OSD Sub Window 1 Background Color Select OSD Sub Window 2 Register Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 2Fh SUBW2C BTN2 30h SW2HST SW2HST[5:0] 31h SW2HEND SW2HEND[5:0] 32h SW2VST SW2VST[4:0] 33h SW2VEND SW2VEND[4:0] 34h SUBW2A BLNK FGCLR[2:0] TRAN n BTN2 Enable Button Function for sub window 2 n BD2 Enable OSD Sub Window 2 Border n S2E Enable OSD Sub Window 2 n S2C Sub Window 2 color select n SW2HST[5:0] Sub Window 2 Horizontal Start Position n SW2HEND[5:0] Sub Window 2 Horizontal End Position n SW2VST[4:0] Sub Window 2 Vertical Start Position n SW2VEND[4:0] Sub Window 2 Vertical End Position n BLNK OSD Sub Window 2 Blink Control n FGCLR[2:0] OSD Sub Window 2 Foreground Color Select n TRAN OSD Sub Window 2 Transparency Control n BGCLR[2:0] OSD Sub Window 2 Background Color Select OSD Sub Window 3 Register Index 35h 36h 37h 38h 39h 3Ah n BTN3 n BD3 Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 SUBW3C BTN3 SW3HST SW3HST[5:0] SW3HEND SW3HEND[5:0] SW3VST SW3VST[4:0] SW3VEND SW3VEND[4:0] SUBW3A BLNK FGCLR[2:0] TRAN Enable Button Function for sub window 3 Enable OSD Sub Window 3 Border Bit 2 BD3 Bit 1 S3C Bit 0 S3E Access R/W, DB R/W, DB R/W, DB R/W, DB R/W, DB R/W Bit 2 BD2 Bit 1 S2C Bit 0 S2E Access R/W, DB R/W, DB R/W, DB R/W, DB R/W, DB R/W Bit 2 BD1 Bit 1 S1C Bit 0 S1E Access R/W, DB R/W, DB R/W, DB R/W, DB R/W, DB R/W
BGCLR[2:0]
BGCLR[2:0]
BGCLR[2:0]
Version 0.1
- 47 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1
n n n n n n n n n n
S3E S3C SW3HST[5:0] SW3HEND[5:0] SW3VST[4:0] SW3VEND[4:0] BLNK FGCLR[2:0] TRAN BGCLR[2:0]
Enable OSD Sub Window 3 Sub Window 3 color select Sub Window 3 Horizontal Start Position Sub Window 3 Horizontal End Position Sub Window 3 Vertical Start Position Sub Window 3 Vertical End Position OSD Sub Window 3 Blink Control OSD Sub Window 3 Foreground Color Select OSD Sub Window 3 Transparency Control OSD Sub Window 3 Background Color Select
OSD 8 color Font Start Address Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 3Bh OSD8CFFA OSD8CFFA[7:0] 3Ch OSD8CFCA OSD8CFCA[7:0] n OSD8CFFA[7:0] OSD 8 color font RAM address n OSD8CFCA[7:0] OSD 8 color font code address OSD Color Palette (when C16_PAL=0) Index Mnemonic Bit 7 Bit 6 Bit 5 58h CLR0R CLR0R[7:0] 59h CLR0G CLR0G[7:0] 5Ah CLR0B CLR0B[7:0] 5Bh CLR1R CLR1R[7:0] 5Ch CLR1G CLR1G[7:0] 5Dh CLR1B CLR1B[7:0] 5Eh CLR2R CLR2R[7:0] 5Fh CLR2G CLR2G[7:0] 60h CLR2B CLR2B[7:0] 61h CLR3R CLR3R[7:0] 62h CLR3G CLR3G[7:0] 63h CLR3B CLR3B[7:0] 64h CLR4R CLR4R[7:0] 65H CLR4G CLR4G[7:0] 66h CLR4B CLR4B[7:0] 67h CLR5R CLR5R[7:0] 68h CLR5G CLR5G[7:0] 69h CLR5B CLR5B[7:0] 6Ah CLR6R CLR6R[7:0] 6Bh CLR6G CLR6G[7:0] 6Ch CLR6B CLR6B[7:0] 6Dh CLR7R CLR7R[7:0] 6Eh CLR7G CLR7G[7:0] 6Fh CLR7B CLR7B[7:0] OSD Color Palette (when C16_PAL=1) 16 color format: col[7:4],4'h0 Index 58h 59h 5Ah Mnemonic CLR0R CLR0G CLR0B Bit 7 Bit 6 CLR0R[7:4] CLR0G[7:4] CLR0B[7:4] Bit 5 Bit 4 Bit 3 Bit 2 CLR8R[7:4] CLR8G[7:4] CLR8B[7:4] Bit 1 Bit 0 Access R/W R/W R/W Bit 3 Bit 2 Bit 1 Bit 0 Access R/W R/W
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Version 0.1
- 48 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 OSD Color Palette (when C16_PAL=1) 16 color format: col[7:4],4'h0 Index 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65H 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh Mnemonic CLR1R CLR1G CLR1B CLR2R CLR2G CLR2B CLR3R CLR3G CLR3B CLR4R CLR4G CLR4B CLR5R CLR5G CLR5B CLR6R CLR6G CLR6B CLR7R CLR7G CLR7B Bit 7 Bit 6 CLR1R[7:4] CLR1G[7:4] CLR1B[7:4] CLR2R[7:4] CLR2G[7:4] CLR2B[7:4] CLR3R[7:4] CLR3G[7:4] CLR3B[7:4] CLR4R[7:4] CLR4G[7:4] CLR4B[7:4] CLR5R[7:4] CLR5G[7:4] CLR5B[7:4] CLR6R[7:4] CLR6G[7:4] CLR6B[7:4] CLR7R[7:4] CLR7G[7:4] CLR7B[7:4] Bit 5 Bit 4 Bit 3 Bit 2 CLR9R[7:4] CLR9G[7:4] CLR9B[7:4] CLR10R[7:4] CLR10G[7:4] CLR10B[7:0] CLR11R[7:0] CLR11G[7:4] CLR11B[7:4] CLR12R[7:4] CLR12G[7:4] CLR12B[7:4] CLR13R[7:4] CLR13G[7:4] CLR13B[7:4] CLR14R[7:4] CLR14G[7:4] CLR14B[7:4] CLR15R[7:4] CLR15G[7:4] CLR15B[7:4] Bit 1 Bit 0 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
OSD Random Test Pattern Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 71h OSDRTP n RTPT OSD Random Test Pattern Type Y0 RGB is same Y1 RGB is different n OSDRTP[1:0] OSD Random Test Pattern Y 00 Disable Y 01 1 random bit Y 10 2 random bit Y 11 Reserved
Bit 3
Bit 2 RTPT
Bit 1 Bit 0 OSDRTP[1:0]
Access R/W
TCON Register (Bank=10)
Output Format Control 1 (TCON feature only) Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 02h OFC1 IFC IFS IFE DPFS DPFC DPFE EEF TCEN R/W n IFC Inversion Function Combined Y0 Odd data inversion determined by OINV, even data inversion determined by EINV Y1 Odd/Even data inversion both determined by OINV n IFS Inversion Function Swap Y0 OINV/EINV=0 when data is inverted Y1 OINV/EINV=1 when data is inverted n IFE Inversion Function Enable Y0 Disable Y1 Enable. When enabled, an indication is output for each data bus. If the number of
Version 0.1
- 49 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 transitions from pixel to pixel exceed 24 bits from 48 bits (or 18 bits from 36 bits for 6 bits panel), the data is inverted and an indication corresponding to that bus is set active. Data Polarity Function Swap (useful when DPFE=1) Odd data inversion determined by OPOL, even data inversion determined by EPOL Odd data inversion determined by OPOL, even data opposite of ODD data Data Polarity Function Control Data Inversion when OPOL/EPOL is 0 Data Inversion when OPOL/EPOL is 1 Data Polarity Function Enable Disable Enable (line inversion, use OPOL/EPOL to determine the polarity of the output data) Early End Function Disable Enable Timing Controller Enable Disable Enable
n
n
n
n
n
DPFS Y0 Y1 DPFC Y0 Y1 DPFE Y0 Y1 EEF Y0 Y1 TCEN Y0 Y1
Output Format Control 2 (TCON feature only) Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 03h OFC2 ESPP ESPO[3:0] OSPP n ESPP Even Start Pulse Position Y0 Start pulse before data Y1 Start pulse after data n ESPO[2:0] Even Start Pulse Offset Y 000 Start pulse 0 clocks before/after data Y 001 Start pulse 1 clocks before/after data Y 010 Start pulse 2 clocks before/after data Y... ... Y 111 Start pulse 7 clocks before/after data n OSPP Odd Start Pulse Position Y0 Start pulse before data Y1 Start pulse after data n OSPO[2:0] Odd Start Pulse Offset Y 000 Start pulse 0 clocks before/after data Y 001 Start pulse 1 clocks before/after data Y 010 Start pulse 2 clocks before/after data Y... ... Y 111 Start pulse 7 clocks before/after data Output Drive/Polarity Control (TCON feature only) Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 04h ODPC OESPDC[1:0] GODC[1:0] n OESPDC[1:0] OSP/ESP Drive Control Y 00 4 mA Y 01 6 mA Y 10 8 mA Y 11 12 mA n GODC[1:0] OPOL/EPOL/GPO Drive Control Y 00 4 mA Y 01 6 mA Y 10 8 mA Y 11 12 mA
Bit 2 Bit 1 OSPO[3:0]
Bit 0
Access R/W
Bit 3 ECP
Bit 2 -
Bit 1 OCP
Bit 0 -
Access R/W
Version 0.1
- 50 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 ECP Y0 Y1 n OCP Y0 Y1
n
ECLK Polarity Normal Inverted OCLK Polarity Normal Inverted
Output Drive Control (TCON feature only) Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 05h ODC EDDC[1:0] ODDC[1:0] n EIDC[1:0] EINV Drive Control Y 00 4 mA Y 01 6 mA Y 10 8 mA Y 11 12 mA n OIDC[1:0] OINV Drive Control n RSBMLSW RSDS B-port MSB/LSB Swap Y Scaler Bank 0x42[5]=0 & 0x42[2]=1 Y0 Default Y1 B-port MSB/LSB swap for 8-bit RSDS output Y Scaler Bank 0x42[5]=1 & 0x42[2]=1 Y0 Default Y1 B-port MSB/LSB swap for 6-bit RSDS output n RSAMLSW RSDS A-port MSB/LSB Swap Y Scaler Bank 0x42[5]=0 & 0x42[3]=1 Y0 Default Y1 A-port MSB/LSB swap for 8-bit RSDS output Y Scaler Bank 0x42[5]=1 & 0x42[3]=1 Y0 Default Y1 A-port MSB/LSB swap for 6-bit RSDS output GPO4 (OE) Active Delay Frame (TCON feature only) Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 06h GPO4ADF n GPO4ADF[2:0] GPO4 (OE) Active Delay Frame Y 000 No delay Y 001 Delay 1 frame Y... ... Y 111 Delay 7 frame
Bit 1 Bit 0 Access RSBMLSW RSAMLSW R/W
Bit 3
Bit 2 Bit 1 GPO4ADF[2:0]
Bit 0
Access R/W
Input Format Control Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 07h IFCTRL WDG PUA G0AT DATI POLB SPB n WDG White Data Generation (TCON feature only) Y0 Black data generation during vertical blanking (GPOA) Y1 Enable white data generation during vertical blanking (GPOA) n PUA Power-up Active (TCON feature only) Y0 Outputs in-active Y1 Outputs active n G0AT GPO0 Auto Toggle Control (TCON feature only) Y0 Disable Y1 Enable n DATI Data Invert (TCON feature only)
Bit 0 CLKB
Access R/W
Version 0.1
- 51 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 Y0 Y1 n POLB Y0 Y1 n SPB Y0 Y1 n CLKB Y0 Y1 OFF ON Polarity Blanked Enable (TCON feature only) Disable Enable (EPOL/OPOL will be forced to blanked when GPOA is low) Start Pulse Blanked Enable (TCON feature only) Disable Enable (ESP/OSP will be forced to blanked when GPOA is low) Clock Blanked Enable Disable Enable (ECLK/OCLK will be forced to blanked when GPOA is low)
GPO0 (OPOL) (TCON feature only) Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 08h G0VST-L G0VST[7:0] R/W 09h G0VST-H G0VST[10:8] R/W 0Ah G0VEND-L G0VEND[7:0] R/W 0Bh G0VEND-H G0VEND[10:8] R/W 0Ch G0HST-L G0HST[7:0] R/W 0Dh G0HST-H G0HST[10:8] R/W 0Eh G0HEND-L G0HEND[7:0] R/W 0Fh G0HEND-H G0HEND[10:8] R/W 10h G0CTRL G0CS[2:0] G0TS[1:0] G0ES G0TC G0OP R/W n G0VST[10:0] Line number that GPO0 start n G0VEND[10:0] Line number that GPO0 end n G0HST[10:0] Pixel number that GPO0 start n G0HEND[10:0] Pixel number that GPO0 end n G0TS[1:0] GPO0 Type Select Y When Toggle Mode=0 Y 00 Normal Y 01 Duration is greater than a line time Y 10 Every two lines has one GPO0 pulse Y 11 Every three lines has one GPO0 pulse Y When Toggle Mode=1 Y 00 One Line Toggle Y 01 Reserved Y 10 Two Lines Toggle Y 11 Three Lines Toggle n G0CS[2:0] GPO0 Combination Select Y 000 No combination Y 001 AND Y 010 OR Y 011 Select GPO# and GPO#-1 on alternating frames Y 1xx Auto select 1 or 2 line toggle according to ATP value n G0ES GPO0 Early Start Function Y0 Normal Y1 Early Start capability Y The value in the Vertical Start Register (G0VST) is subtracted from the total number of lines/frame to determine the Vertical Start position. n G0TC GPO0 Toggle circuit enable Y0 Normal Y1 Toggle Y Toggle mode is useful in POL generation when alternating polarity is required from line to line. Frame to frame polarity changes are made by programming an odd # in
Version 0.1
- 52 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 G0OP Y0 Y1 the vertical duration when in toggle mode. GPO0 Output Polarity Active High Active Low
n
GPO1 (EPOL) (TCON feature only) Index Mnemonic Bit 7 Bit 6 Bit 5 11h G1VST-L G1VST[7:0] 12h G1VST-H 13h G1VEND-L G1VEND[7:0] 14h G1VEND-H 15h G1HST-L G1HST[7:0] 16h G1HST-H 17h G1HEND-L G1HEND[7:0] 18h G1HEND-H 19h G1CTRL G1CS[2:0] n G1VST[10:0] Line number that GPO1 start n G1VEND[10:0] Line number that GPO1 end n G1HST[10:0] Pixel number that GPO1 start n G1HEND[10:0] Pixel number that GPO1 end n G1TS[1:0] GPO1 Type Select n G1CS[2:0] GPO1 Combination Select n G1ES GPO1 Early Start Function n G1TC GPO1 Toggle circuit enable n G1OP GPO1 Output Polarity GPO2 (RSP2) (TCON feature only) Index Mnemonic Bit 7 Bit 6 Bit 5 1Ah G2VST-L G2VST[7:0] 1Bh G2VST-H 1Ch G2VEND-L G2VEND[7:0] 1Dh G2VEND-H 1Eh G2HST-L G2HST[7:0] 1Fh G2HST-H 20h G2HEND-L G2HEND[7:0] 21h G2HEND-H 22h G2CTRL G2CS[2:0] n G2VST[10:0] Line number that GPO2 start n G2VEND[10:0] Line number that GPO2 end n G2HST[10:0] Pixel number that GPO2 start n G2HEND[10:0] Pixel number that GPO2 end n G2TS[1:0] GPO2 Type Select n G2CS[2:0] GPO2 Combination Select n G2ES GPO2 Early Start Function n G2TC GPO2 Toggle circuit enable n G2OP GPO2 Output Polarity GPO3 (RSP3) (TCON feature only) Index Mnemonic Bit 7 Bit 6 23h G3VST-L G3VST[7:0] 24h G3VST-H 25h G3VEND-L G3VEND[7:0]
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
G1VST[10:8] G1VEND[10:8] G1HST[10:8] G1HEND[10:8] G1ES G1TC
G1TS[1:0]
G1OP
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
G2VST[10:8] G2VEND[10:8] G2HST[10:8] G2HEND[10:8] G2ES G2TC
G2TS[1:0]
G2OP
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
G3VST[10:8]
Access R/W R/W R/W
Version 0.1
- 53 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 GPO3 (RSP3) (TCON feature only) Index Mnemonic Bit 7 Bit 6 Bit 5 26h G3VEND-H 27h G3HST-L G3HST[7:0] 28h G3HST-H 29h G3HEND-L G3HEND[7:0] 2Ah G3HEND-H 2Bh G3CTRL G3CS[2:0] n G3VST[10:0] Line number that GPO3 start n G3VEND[10:0] Line number that GPO3 end n G3HST[10:0] Pixel number that GPO3 start n G3HEND[10:0] Pixel number that GPO3 end n G3TS[1:0] GPO3 Type Select n G3CS[2:0] GPO3 Combination Select n G3ES GPO3 Early Start Function n G3TC GPO3 Toggle circuit enable n G3OP GPO3 Output Polarity GPO4 (RCLK) (TCON feature only) Index Mnemonic Bit 7 Bit 6 Bit 5 2Ch G4VST-L G4VST[7:0] 2Dh G4VST-H 2Eh G4VEND-L G4VEND[7:0] 2Fh G4VEND-H 30h G4HST-L G4HST[7:0] 31h G4HST-H 32h G4HEND-L G4HEND[7:0] 33h G4HEND-H 34h G4CTRL G4CS[2:0] n G4VST[10:0] Line number that GPO4 start n G4VEND[10:0] Line number that GPO4 end n G4HST[10:0] Pixel number that GPO4 start n G4HEND[10:0] Pixel number that GPO4 end n G4TS[1:0] GPO4 Type Select n G4CS[2:0] GPO4 Combination Select n G4ES GPO4 Early Start Function n G4TC GPO4 Toggle circuit enable n G4OP GPO4 Output Polarity GPO5 (ROE) (TCON feature only) Index Mnemonic Bit 7 Bit 6 Bit 5 35h G5VST-L G5VST[7:0] 36h G5VST-H 37h G5VEND-L G5VEND[7:0] 38h G5VEND-H 39h G5HST-L G5HST[7:0] 3Ah G5HST-H 3Bh G5HEND-L G5HEND[7:0] 3Ch G5HEND-H 3Dh G5CTRL G5CS[2:0] n G5VST[10:0] Line number that GPO5 start n G5VEND[10:0] Line number that GPO5 end
Bit 4
Bit 3
Bit 2 Bit 1 G3VEND[10:8] G3HST[10:8] G3HEND[10:8] G3ES G3TC
Bit 0
G3TS[1:0]
G3OP
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Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
G4VST[10:8] G4VEND[10:8] G4HST[10:8] G4HEND[10:8] G4ES G4TC
G4TS[1:0]
G4OP
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Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
G5VST[10:8] G5VEND[10:8] G5HST[10:8] G5HEND[10:8] G5ES G5TC
G5TS[1:0]
G5OP
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Version 0.1
- 54 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1
n n n n n n n
G5HST[10:0] G5HEND[10:0] G5TS[1:0] G5CS[2:0] G5ES G5TC G5OP
Pixel number that GPO5 start Pixel number that GPO5 end GPO5 Type Select GPO5 Combination Select GPO5 Early Start Function GPO5 Toggle circuit enable GPO5 Output Polarity
GPO6 (ROE2) (TCON feature only) Index Mnemonic Bit 7 Bit 6 Bit 5 3Eh G6VST-L G6VST[7:0] 3Fh G6VST-H 40h G6VEND-L G6VEND[7:0] 41h G6VEND-H 42h G6HST-L G6HST[7:0] 43h G6HST-H 44h G6HEND-L G6HEND[7:0] 45h G6HEND-H 46h G6CTRL G6CS[2:0] n G6VST[10:0] Line number that GPO6 start n G6VEND[10:0] Line number that GPO6 end n G6HST[10:0] Pixel number that GPO6 start n G6HEND[10:0] Pixel number that GPO6 end n G6TS[1:0] GPO6 Type Select n G6CS[2:0] GPO6 Combination Select n G6ES GPO6 Early Start Function n G6TC GPO6 Toggle circuit enable n G6OP GPO6 Output Polarity GPO7 (ROE3) (TCON feature only) Index Mnemonic Bit 7 Bit 6 Bit 5 47h G7VST-L G7VST[7:0] 48h G7VST-H 49h G7VEND-L G7VEND[7:0] 4Ah G7VEND-H 4Bh G7HST-L G7HST[7:0] 4Ch G7HST-H 4Dh G7HEND-L G7HEND[7:0] 4Eh G7HEND-H 4Fh G7CTRL G7CS[2:0] n G7VST[10:0] Line number that GPO7 start n G7VEND[10:0] Line number that GPO7 end n G7HST[10:0] Pixel number that GPO7 start n G7HEND[10:0] Pixel number that GPO7 end n G7TS[1:0] GPO7 Type Select n G7CS[2:0] GPO7 Combination Select n G7ES GPO7 Early Start Function n G7TC GPO7 Toggle circuit enable n G7OP GPO7 Output Polarity
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
G6VST[10:8] G6VEND[10:8] G6HST[10:8] G6HEND[10:8] G6ES G6TC
G6TS[1:0]
G6OP
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Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
G7VST[10:8] G7VEND[10:8] G7HST[10:8] G7HEND[10:8] G7ES G7TC
G7TS[1:0]
G7OP
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Version 0.1
- 55 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 GPO8 (DHS/TCON_LP) (TCON feature only) Index Mnemonic Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 50h G8VST-L G8VST[7:0] 51h G8VST-H 52h G8VEND-L G8VEND[7:0] 53h G8VEND-H 54h G8HST-L G8HST[7:0] 55h G8HST-H 56h G8HEND-L G8HEND[7:0] 57h G8HEND-H 58h G8CTRL G8CS[2:0] G8TS[1:0] n G8VST[10:0] Y When Scalar bank register ABh bit 7 = 0 Y G8VST[10:0] Line number that GPO8 start Y When Scalar bank register ABh bit 7 = 1 Y G8VST-L[7:0] GPO[7:0] gating control Y G8VST-H[1:0] O(E)SP / O(E)INV gating control n G8VEND[10:0] Line number that GPO8 end n G8HST[10:0] Pixel number that GPO8 start n G8HEND[10:0] Pixel number that GPO8 end n G8TS[1:0] GPO8 Type Select n G8CS[2:0] GPO8 Combination Select n G8ES GPO8 Early Start Function n G8TC GPO8 Toggle circuit enable n G8OP GPO8 Output Polarity GPO9 (DVS/TCON_FSYNC) Index Mnemonic Bit 7 Bit 6 Bit 5 59h G9VST-L G9VST[7:0] 5Ah G9VST-H 5Bh G9VEND-L G9VEND[7:0] 5Ch G9VEND-H 5Dh G9HST-L G9HST[7:0] 5Eh G9HST-H 5Fh G9HEND-L G9HEND[7:0] 60h G9HEND-H 61h G9CTRL G9CS[2:0] n G9VST[10:0] Line number that GPO9 start n G9VEND[10:0] Line number that GPO9 end n G9HST[10:0] Pixel number that GPO9 start n G9HEND[10:0] Pixel number that GPO9 end n G9TS[1:0] GPO9 Type Select n G9CS[2:0] GPO9 Combination Select n G9ES GPO9 Early Start Function n G9TC GPO9 Toggle circuit enable n G9OP GPO9 Output Polarity GPOA Index 62h 63h 64h
Bit 2
Bit 1
Bit 0
G8VST[10:8] G8VEND[10:8] G8HST[10:8] G8HEND[10:8] G8ES G8TC
G8OP
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Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
G9VST[10:8] G9VEND[10:8] G9HST[10:8] G9HEND[10:8] G9ES G9TC
G9TS[1:0]
G9OP
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Mnemonic GAVST-L GAVST-H GAVEND-L
Bit 7 Bit 6 GAVST[7:0] GAVEND[7:0]
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GAVST[10:8]
Access R/W R/W R/W
Version 0.1
- 56 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003
MST8011A XGA LCD Controller with Analog Interface and Single LVDS Transmitter Preliminary Data Sheet Version 0.1 GPOA Index Mnemonic Bit 7 Bit 6 Bit 5 65h GAVEND-H 66h GAHST-L GAHST[7:0] 67h GAHST-H 68h GAHEND-L GAHEND[7:0] 69h GAHEND-H 6Ah GACTRL GACS[2:0] n GAVST[10:0] Line number that GPOA start n GAVEND[10:0] Line number that GPOA end n GAHST[10:0] Pixel number that GPOA start n GAHEND[10:0] Pixel number that GPOA end n GATS[1:0] GPOA Type Select n GACS[2:0] GPOA Combination Select n GAES GPOA Early Start Function n GATC GPOA Toggle circuit enable n GAOP GPOA Output Polarity
Bit 4
Bit 3
Bit 2 Bit 1 GAVEND[10:8] GAHST[10:8] GAHEND[10:8] GAES GATC
Bit 0
GATS[1:0]
GAOP
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REGISTER TABLE REVISION HISTORY
Date 03/10/03 Bank ADC Scaler TCON ADC Scaler OSD Scaler Scaler Register Y 0x2D Y 0xAB Y 0x05 Y 0x13, 0x15, 0x17, 0x18, 0x26, 0x27, 0x2D Y 0x04, 0x44, 0x4B, 0x50~0x55, 0x5D, 0x89, 0x8A, 0x90, 0x9F, 0xB3, 0xB4, 0xBC, 0xCA, 0xCC, 0xCD, 0xD1, 0xD4, 0xEA, 0xF2, 0xF6, 0xF8 Y 0xFA (deleted) Y 0x01, 0x0E, 0x10 Y 0x88 Y 0x44
04/01/03
04/02/03 05/02/03
Version 0.1
- 57 Copyright (c) 2003 MStar Semiconductor, Inc. All rights reserved.
5/6/2003

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