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| ********** C-MOS ENCAPSULATED PERIPHERAL PROCESSOR --TOP VIEW-- 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VDD (+5V) NC VDD (+5V) GND MB89394-PF(1/3) IL00 VDD (+5V) PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 I/O I I -- I/O I/O I/O I/O I/O I/O I/O I/O -- I I I I I I I I 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SIGNAL GATE0 CLK0 VDD DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 GND A1 A0 W R CS4 CS3 CS2 CS1 PIN No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O I -- I/O I/O I/O I/O I/O I/O I I O -- -- O I/O I/O I I I I SIGNAL CSO VDD C12 C02 C11 C01 C10 C00 INTA1 INTA0 INT1 GND NC INT0 SLCT1 SLCT0 IRQ17 IRQ16 IRQ15 IRQ14 PIN No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VDD (+5V) GND 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 GND NC NC GND 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 I/O I I -- I I I I I I I I -- I I I I I -- O I SIGNAL IRQ13 IRQ12 VDD IRQ11 IRQ10 IRQ07 IRQ06 IRQ05 IRQ04 IRQ03 IRQ02 GND IRQ01 IRQ00 RSLCT RCVDT TRNCLK NC RCVRDY RCVCLK PIN No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 I/O SIGNAL w w w .d ee sh ta a u. t4 om c www..com DTR O VDD -- RTS O DSR I RST I TRNDT O O TRNEMP/STI CTS I I/O SYNC/BRK TRNRDY O CK I GND -- NC -- OUT2 O GATE2 I CLK2 I OUT1 O GATE1 I CLK1 I OUT0 O MB89394-PF(2/3) IL00 A0, A1 C00-C02 CLK0-CLK2 CK CS0-CS4 CTS DB0-DB7 DSR DTR GATE0-GATE2 INT0, INT1 INTA0, INTA1 IRQ00-IRQ07 IRQ10-IRQ17 OUT1-OUT2 R RCVCLK RCVDT RCVRDT RSLCT RST RTS SLCT0, SLCT1 SYNC/BRK TRNCLK TRNDT TRNEMP/STI TRNRDT W ; ADDRESS BUS ; CASCADE CONTROL ; CLOCK IN ; CLOCK FOR REFERANCE OF TIMING ; CHIP SELECT ; CLEAR TO SEND ; DATA BUS ; DATA SET READY ; DATA TERMINAL READY ; GATE IN ; INTERRUPT ; INTERRUPT ACKNOWLEDGE ; INTERRUPT REQUESTS ; INTERRUPT REQUESTS ; COUNT OUT ; READ ; RECEIVER CLOCK ; RECEIVE DATA ; RECEIVER READY ; REGISTER SELECT ; RESET ; REQUEST TO SEND ; SELECT ; SYNCHRONIZATION CHARACTOR/ BREAK CODE DETECT ; TRANSMIT CLOCK ; TRANSMIT DATA ; TRANSMITTER EMPTY/BAUD RATE CLOCK OUT ; TRANSMIT READY ; WRITE 14 13 21 20 19 18 17 A0 A1 CS0 CS1 CS2 CS3 CS4 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 11 10 9 8 7 6 5 4 54 53 51 50 49 48 47 46 30 IRQ00 IRQ01 IRQ02 IRQ03 IRQ04 IRQ05 IRQ06 IRQ07 INTA0 C10 27 C11 25 C12 23 SLCT1 35 INT1 31 CO0 28 CO1 26 CO2 24 SLCT0 36 INT0 34 45 44 42 41 40 39 38 37 29 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 INTA1 64 68 56 69 55 DSR CTS RCVDT SYNC/BRK RSLCT DTR 61 RTS 63 TRNDY 66 TRNRDY 70 RCVRDY 59 TRNEMP/STI 67 60 57 RCVCLK TRNCLK 1 78 75 2 79 76 GATE 0 GATE 1 GATE 2 CLK 0 CLK 1 CLK 2 OUT0 80 OUT1 77 OUT2 74 15 16 65 71 W R RST CK MB89394-PF(3/3) IL00 A0, A1 14,13 R, W 16,15 DB0 I DB7 11 -4 45, 44, 42-37 IRQ10-17 27, 25, 23 C10-12 35 SLCT1 29 31 INTA1 INT1 INTERRUPT CONTROLLER (1) CHIP SELECT ARBITRABLE CIRCUIT CS1 ADDRESS BUS DATA BUS CS0 - 4 21 - 17 R, W DSR CTS RCVDT SYNC/BRK DTR RTS TRNDT TRNRDY RCVRDY 64 55 CS0 RSLCT 54, 53, 51-46 IRQ00-07 28, 26, 24 C0-2 36 SLCT0 30 INTA0 34 INT0 INTERRUPT CONTROLLER (2) 68 56 69 61 63 66 70 59 SERIAL DATA TRANSMITTER / RECEIVER R, W A0 R, W CS3 RST, CK 65 71 A1 PROGRAMMABLE BAUD RATE GENERATOR CS4 PROGRAMMABLE INTERVAL TIMER RCVCLK 60 CS2 1, 75, 78 GATE0-2 2, 76, 79 CLK0-2 80, 77, 74 OUT0-2 TRNCLK 57 R, W A0 TRNEMP /STI 67 R, W A0 |
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