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19-3534; Rev 0; 1/05
Powerline Communication Analog Front-End Transceiver
General Description
The MAX2980 powerline communication analog frontend (AFE) integrated circuit (IC) is a state-of-the-art CMOS device that delivers high performance and low cost. This highly integrated design combines an analogto-digital converter (ADC), digital-to-analog converter (DAC), signal conditioning, and line driver. The MAX2980 substantially reduces previously required system components, while compatible with third-party HomePlug(R) devices. This device interfaces with many companion Digital PHY ICs to provide a complete powerline communication solution. The advanced design of the MAX2980 allows operation without external control, enabling simplified connection to a variety of HomePlug Digital PHY ICs. Additional power-reduction techniques can be employed through the use of various control signals. The MAX2980 is specified over the 0C to +70C commercial temperature range and is offered in a 64-pin TQFP package.
Features
Fully Integrated Line Driver and Receiver Seamless Interface to Digital PHY ICs Fully Integrated 10-Bit ADC and DAC with 50MHz Sampling 54dB Adaptive Gain Control Minimum Line Impedance Capability as Low as 10 3.0V to 3.6V I/O 250mA in Rx Mode and/or 160mA in Tx Mode at 3.3V 64-Pin TQFP Package
MAX2980
Ordering Information
PART MAX2980CCB TEMP RANGE 0C to +70C PIN-PACKAGE 64 TQFP
Applications
Local Area Networking (LAN)
RESETIN AGND STBY ENTX AVDD SWR I.C. I.C.
Pin Configuration
FREEZE DGND 50 AGND AGND AGND DVDD 49 48 47 46 45 44 43 42 41 AVDD 55 AVDD 54
Audio-Over-Powerline Voice-Over-Powerline Security Remote Monitoring and Control Broadband Access (Last-Mile) Powerline-to-WiFi Bridge Powerline-to-DSL Bridge Powerline-to-Ethernet Bridge Powerline-to-USB Bridge
AGND AVDD PLIP PLIN AGND AVDD CEXT REXT AGND AGND PLOP AVDD AGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64
63
62
61
60
59
58
57
56
53
52
51
DGND DAD1 DAD2 DVDD3 DAD3 DAD4 DVDD3 DGND DAD5 DAD6 DVDD3 DAD7 DAD8 DGND DAD9
MAX2980
40 39 38 37 36 35 34 33
Typical Operating Circuit appears at end of data sheet.
PLON AVDD
VREGOUT
ENREAD
HomePlug is a registered trademark of HomePlug Powerline Alliance, Inc.
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For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
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AVDD
17 AGND
18
19 DVDD
20 DGND
21 SDI/O
22 SCLK
23 SHRCV
24
25 CS
26 DVDD
27 DGND
28 AGND
29 AVDD
30 DVDD3
31 CLK
32 AGND
TQFP
________________________________________________________________ Maxim Integrated Products
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DAD0
Powerline Communication Analog Front-End Transceiver MAX2980
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND ......................................................-0.3V to +3.9V DVDD3 to DGND ....................................................-0.3V to +3.9V DVDD to DGND......................................................-0.3V to +2.8V AGND to DGND.....................................................-0.3V to +0.3V All Other Pins..............................................-0.3V to (VDD + 0.3V) Current into Any Pin........................................................100mA Short-Circuit Duration (VREGOUT to AGND) ........................10ms Continuous Power Dissipation (TA = +70C) 64-Pin TQFP (derate 25mW/C above +70C)...........2000mW Operating Temperature Range...............................0C to +70C Junction Temperature ......................................................+150C Storage Temperature Range .............................-40C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION! ESD SENSITIVE DEVICE
ELECTRICAL CHARACTERISTICS
(AVDD = DVDD3 = +3.3V, DVDD = VREGOUT, AGND = DGND = STBY = 0, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Operating Supply Voltage Range SYMBOL AVDD, DVDD3 DVDD Receive mode Clock No clock (Note 1) Clock Quiescent Supply Current IDD Normal operation Transmit mode No clock (Note 1) 175 175 (Note 1) CONDITIONS MIN 3.0 2.5 250 220 250 220 160 100 135 20 5 2.4 (Note 1) (Note 1) 2.0 0.8 VIH = VDD (Note 1) VIL = 0 (Note 1) -5 10 2.1 0.4 +5 2.4 0.4 165 mA V V V V V A A Bits LSB LSB 260 mA 260 TYP MAX 3.6 UNITS V
Clock Receiver disabled, No clock SHRCV = high (Note 1)
Standby Supply Current Regulator Output Output-Voltage High Output-Voltage Low LOGIC-INPUT CHARACTERISTICS Input High Voltage Input Low Voltage Input Leakage Current High Input Leakage Current Low Resolution Integral Nonlinearity Differential Nonlinearity VIH VIL IIH IIL N INL DNL VREGOUT VOH VOL
Clock No clock (Note 1)
ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS
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Powerline Communication Analog Front-End Transceiver
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD3 = +3.3V, DVDD = VREGOUT, AGND = DGND = STBY = 0, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Resolution Integral Nonlinearity Differential Nonlinearity Two-Tone Third-Order Distortion RECEIVER CHARACTERISTICS Common-Mode Voltage Input Impedance per Pin Two-Tone Third-Order Distortion AGC Gain Range Lowpass-Filter Corner Frequency Lowpass-Filter Ripple TRANSMITTER CHARACTERISTICS Common-Mode Voltage Output Impedance per Pin Output-Voltage Swing at 12MHz Short-Circuit Current Two-Tone Third-Order Distortion Lowpass-Filter Corner Frequency Lowpass-Filter Ripple Minimum Line Impedance Capability <1dB output swing variation <1dB linearity variation ISC IM3 Two tones at 17MHz and 18MHz, 1VP-P, differential (Note 1) 35 ZOUT At pins PLOP/PLON Between pins PLOP, PLON, and GND at 12MHz Predriver gain = -6dB Predriver gain = +3dB 1.6 134 2.4 6.0 230 50 21 1.5 10 70 V VP-P diff mA dB MHz dB ZIN IM3 AGC Pins PLIP/PLIN Between pins PLIP, PLIN, and GND at 12 MHz Two tones at 17MHz and 18MHz, 1VP-P, differential 1.6 875 53 54 21 1.5 V dB dB MHz dB SYMBOL N INL DNL IM3 Two tones at 17MHz and 18MHz, 1VP-P, differential CONDITIONS MIN TYP 10 0.4 0.3 54 MAX UNITS Bits LSB LSB dB
MAX2980
DIGITAL-TO-ANALOG CONVERTER (DAC) CHARACTERISTICS
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Powerline Communication Analog Front-End Transceiver MAX2980
TIMING CHARACTERISTICS
(AVDD = DVDD3 = +3.3V, DVDD = VREGOUT, AGND = DGND = STBY = 0, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER CLK Frequency CLK Tolerance CLK Fall to ADC Data Output Valid Time CLK Fall to DAC Data Latch Time tADCO tDACI -25 2 3 SYMBOL CONDITIONS MIN TYP 50 +25 MAX UNITS MHz ppm ns ns
Note 1: Guaranteed by production test at TA = +27C and TA = +70C and by design and characterization at TA = 0C.
Pin Description
PIN 1, 5, 9, 10, 13, 17, 28, 32, 52, 53, 56, 57 2, 6, 12, 15, 16, 29, 54, 55, 60 3 4 7 8 11 14 18 19, 26, 49 20, 27, 34, 40, 47, 50 21 22 23 NAME AGND Analog Ground Analog Power-Supply Voltage. AVDD supply range is 3.0V to 3.6V. Bypass AVDD with a 0.1F capacitor to AGND. AC Powerline Positive Input AC Powerline Negative Input External Capacitor Connection. Connect a 10nF capacitor from CSG to AGND. External Resistor Connection. Connect a 25k resistor from EXT to AGND. AC Powerline Positive Output AC Powerline Negative Output Voltage Regulator Output. Connect VREGOUT to DVDD for normal operation. Digital 2.5V Voltage Input. Connect to VREGOUT for normal operation. Digital Ground Serial Data Input and Output Serial Clock Input Receiver Shutdown Control. Drive SHRCV high to power down the receiver. Drive low for normal operation. Read-Mode Enable Control. Drive ENREAD high to place the DAD [9:0] bidirectional buffers in read mode. Data are transferred from the Digital PHY to the AFE DAC. ENREAD signal frames the transmission. Active-High Carrier-Select Input. Drive CS high to initiate the internal timer. Digital Power-Supply Voltage. DVDD3 supply range is 3.0V to 3.6V. Bypass DVDD3 to DGND with a 0.1F capacitor as close to the pin as possible. 50MHz System Clock Input FUNCTION
AVDD PLIP PLIN CEXT REXT PLOP PLON VREGOUT DVDD DGND SDI/O SCLK SHRCV
24 25 30, 37, 41, 44 31
ENREAD CS DVDD3 CLK
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Powerline Communication Analog Front-End Transceiver MAX2980
Pin Description (continued)
33 35 36 38 39 42 43 45 46 48 51 58, 59 61 62 63 64 DAD9 DAD8 DAD7 DAD6 DAD5 DAD4 DAD3 DAD2 DAD1 DAD0 FREEZE I.C. ENTX SWR RESETIN STBY DAC/ADC Input/Output MSB Data Bit. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 8. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 7. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 6. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 5. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 4. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 3. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 2. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output Data Bit 1. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. DAC/ADC Input/Output LSB Data Bit. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. Active-High Freeze-Mode Enable. Drive FREEZE high to place the AGC adaptation in freeze mode. Drive FREEZE low if the the signal is not available for the companion baseband chip. Internally Connected. Leave these pins floating. Active-High Transmit Enable. Drive ENTX high to enable the transmitter. Drive ENTX low to place the transmitter in tri-state. Active-High Register Write Enable. Drive SWR high to place the registers in write mode. Active-Low Reset Input. Drive RESETIN low to place the MAX2980 in reset mode. Set CLK in freerunning mode during a reset. The minimum reset pulse width is 100ns. Active-High Standby Input. Drive STBY high to place the MAX2980 in standby mode. Drive low for normal operation.
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Powerline Communication Analog Front-End Transceiver MAX2980
Functional Diagram
MAX2980
LPF AGC RX ADC MUX
LNA
LD
BUF
LPF
TX DAC
Detailed Description
The MAX2980 powerline communication AFE integrated circuit is a state-of-the-art CMOS device that delivers high performance and low cost. This highly integrated design combines the ADC, DAC, signal conditioning, and line driver as shown in the Functional Diagram. The MAX2980 substantially reduces previously required system components, while compatible to third-party HomePlug devices. This device interfaces with many companion Digital PHY ICs to provide a complete powerline communication solution. The advanced design of the MAX2980 allows operation without external control, enabling simplified connection to third-party Digital PHY chips. Additional powerresource-management techniques can be employed in Rx and Tx modes through the use of various control signals.
The 50MHz, 10-bit ADC samples the analog signal and converts it to a 10-bit digital stream. The block fully integrates reference voltages and biasing for the input differential signal.
Transmit Channel
The transmit channel consists of a 10-bit digital-to-analog converter (DAC), a lowpass filter, and an adjustable gain transmitter buffer and line driver. The DAC receives the data stream from the Digital PHY IC through the mux block. The 50MHz, 10-bit DAC provides the complementary function to the receive channel. The DAC converts the 10bit digital stream to an analog voltage at a 50MHz rate. The lowpass filter removes spurs and harmonics adjacent to the desired passband to help reduce the out-of- band transmitted frequencies and energy from the DAC output. The transmit buffer and line-driver blocks allow the output level of the lowpass filter to obtain a level necessary to connect directly to the powerline medium, without the use of external amplifiers and buffers. The output level is adjustable between 2.4VP-P diff and 6.0VP-P diff. The line driver can drive resistive loads as low as 10.
Receive Channel
The receiver analog front-end consists of a low-noise amplifier (LNA), a lowpass filter (LPF), and an adaptive gain-control circuit (AGC). An ADC block samples the AGC output. The ADC communicates to the Digital PHY chip through a mux block. The LNA reduces the receive channel input-referred noise by providing some signal gain to the AFE input. The filter blocks remove unwanted noise, and provide the anti-aliasing required by the ADC for accurate sampling. The AGC scales the signal for conversion from analog to digital. The scaling maintains the optimum signal level at the ADC input and keeps the AGC amplifiers out of saturation.
Digital Interface
The digital interface is composed of some control signals and a 10-bit bidirectional data bus for the DAC and ADC. The control signals include a reset line, a transmit request, an I/O detection request, and a receiver shutdown control.
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Powerline Communication Analog Front-End Transceiver
Control Signals
Transmit Enable (ENTX) The ENTX line is used to enable the transmitter of the MAX2980 AFE circuit. With ENTX and ENREAD driven high, data sent to the DAC through DAD [9:0] is conditioned and delivered onto the power line. Read Enable (ENREAD) The ENREAD line sets the direction of the data bus DAD [9:0]. With ENREAD high, data is sent from the Digital PHY to the DAC in the MAX2980 AFE. A low on ENREAD sends data from the ADC to the Digital PHY. Receiver Power-Down (SHRCV) The SHRCV line provides receiver shutdown control. A logic-high on SHRCV powers down the receiver section of the MAX2980 whenever the device is transmitting. The MAX2980 also features a transmit power-saving mode, which reduces supply current from 410mA to 160mA. To enter the transmit power-saving mode, drive SHRCV high 0.1s prior to the end of transmission. Connect SHRCV to ENTX and ENREAD for normal operation. Digital-to-Analog and Analog-to-Digital Converter Input/Output (DAD [9:0]) DAD [9:0] is the 10-bit bidirectional bus connecting the Digital PHY to the MAX2980 DAC and ADC. The bus direction is controlled by ENREAD, as described in the Read Enable section. AGC Control Signal (CS) The CS signal controls the AGC circuit of the receive path in the MAX2980. A logic-low on CS sets the gain circuit on the input signal to continuously adapt for maximum sensitivity. A valid preamble detected by the Digital PHY raises CS to high. While CS is high, the AGC continues to adapt for an additional short duration, then it locks the currently adapted level on the incoming signal. The Digital PHY holds CS high while receiving a transmission, and then lowers CS for continuous adaptation for maximum sensitivity of other incoming signals. AGC Freeze Mode (FREEZE) Use the FREEZE signal to lock the AGC gain. Note if CS or FREEZE is not used, the maximum loss in SNR is 1dB due to modulation effects generated by the AGC circuit on some selective channels. Clock (CLK) The CLK signal provides all timing for the MAX2980. Apply a 50MHz clock to this input. See the timing diagram of Figure 1 for more information.
tCLK 50MHz CLK tADCO ADC DATA OUT tDACI DAC DATA INPUT
MAX2980
Figure 1. ADC and DAC Timing Diagram
Reset Input (RESETIN) The RESETIN signal provides reset control for the MAX2980. To perform a reset, set CLK in free-running mode and drive RESETIN low for a minimum of 100ns. Always perform a reset at power-up. Standby Control (STBY) The MAX2980 features a low-power, shutdown mode that is activated by STBY. Drive STBY high to place the MAX2980 in standby mode. In standby, the MAX2980 consumes only 20mA with a clock and 5mA without a clock.
MAX2980 Control Registers
MAX2980 Serial Interface The 3-wire serial interface controls the MAX2980 operation mode. The SCLK is the serial clock line for register programming. The SDI/O is the I/O serial data input and output for register writing or reading. The SWR signal controls WRITE/READ mode of the serial interface. If SWR is high, the serial interface is in WRITE mode and a new value can be written into MAX2980 registers. Following SWR low-to-high transitions, data are shifted synchronously to (LSB first) registers on the falling edge of the serial clock (SCLK) as illustrated in Figure 2. Note that one extra clock (WR_CLK) is required to write the content of holding the buffer to the appropriate register bank. If SWR is low, the serial interface is in READ mode and the value of the current register can be read. The read operation to a specific register must be followed right after writing to the same register. Following SWR highto-low transitions, data are shifted synchronously to (LSB first) registers on the falling edge of the serial clock (SCLK) as illustrated in Figure 3. The MAX2980 has a set of six READ/WRITE registers; bits A2, A1, A0 are the register address bits.
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Powerline Communication Analog Front-End Transceiver MAX2980
SWR
SWR
SDAT
D0
D1
D2
D15
A0
A1
A2 WR_CLK
SDAT
D0
D1
D2
D12
D13
D14
D15
SCLK
SCLK
Figure 2. Writing Mode Register Timing Diagram
Figure 3. Reading Mode Register Timing Diagram
Table 1. MAX2980 Registers Address
REGISTER R1 (R/W) R2 (R/W) R3 (R/W) R4 (R/W) R5 (R/W) R6 (R/W) A2 0 0 0 0 1 1 A1 0 0 1 1 0 0 A0 0 1 0 1 0 1
MAX2980 AFE Register Maps
Table 2. Register R1 Map
REGISTER BIT NO. R1B0 R1B1 R1B2 R1B3 R1B4 R1B5 R1B6 R1B7 R1B8 R1B9 R1B10 R1B11 R1B12 R1B13 R1B14 DEFAULT LOW HIGH LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW COMMENT Active high, powers down receiver when in transmit mode. Based on SHRCV signal going high (enable SMT1 mode). Active high, powers down transmitter when in receive mode. Based on Tx signal going high (enables SMT2 mode). Active high, powers down DAC when in receive mode. Based on Tx signal going high (SMTDA mode). Active high, powers down entire chip. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved.
R1B15 LOW Reserved. Note: Bits 4-15 control power-down on various blocks.
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Powerline Communication Analog Front-End Transceiver MAX2980
Table 3. Register R2 Map
REGISTER BIT NO. R2B0 R2B1 R2B2 R2B3 R2B4 R2B5 R2B6 R2B7 R2B8 R2B9 R2B10 R2B11 R2B12 R2B13 R2B14 R2B15 DEFAULT LOW LOW LOW HIGH LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Active high, bypass the receive LPF. COMMENT
Note: Bit 0 to Bit 2 and Bits 4-14 must be set low to disable the connection to the test bus.
Table 4. Register R3 Map
REGISTER BIT NO. R3B0 R3B1 R3B2 R3B3 R3B4 R3B5 R3B6 R3B7 R3B8 R3B9 R3B10 R3B11 R3B [15:12] DEFAULT LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW LOW HIGH 0111 Active high, place process tune in continuous mode. Otherwise active only during RESET. Reserved. Reserved. Reserved. These set the predriver gain as follows setting 000 to 111: 3dB, 2dB, 1dB, 0dB, -1dB, -2dB, -3dB, -6dB R3B2 is the LSB. COMMENT
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Powerline Communication Analog Front-End Transceiver MAX2980
Table 5. Register R4 Map
REGISTER BIT NO. R4B0 R4B1 R4B2 R4B3 R4B4 R4B5 R4B [10:6] R4B11 R4B12 R4B13 R4B14 R4B15 DEFAULT LOW HIGH HIGH HIGH LOW LOW 01011 HIGH HIGH HIGH HIGH LOW Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. Reserved. COMMENT
Table 6. Register R5 Map
REGISTER BIT NO. R5B [6:0] R5B [12:7] R5B13 R5B14 R5B15 DEFAULT LOW LOW LOW LOW LOW Set to manually control VGA and offset-cancellation circuits. Low for automatic adaptation. COMMENT
Applications Information
Interfacing to Digital PHY Circuit
The MAX2980 interfaces to the MAX2986 Digital PHY IC using a bidirectional bus to pass the digital data to and from the DAC and ADC. Handshake lines help accomplish the data transfer and operation of the MAX2980. The application circuit diagram of Figure 4 shows the connection of the MAX2980 to the MAX2986 digital baseband chip.
Layout Considerations
A properly designed PC board is an essential part of any high-speed circuit. Use controlled-impedance lines on all frequency inputs and outputs. Use low-inductance connections to ground on all ground pins and wherever the components are connected to ground. Place decoupling capacitors close to all VDD connections. For proper operation, connect the metal exposed paddle at the back of the IC to the PC board ground plane with multiple vias.
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Powerline Communication Analog Front-End Transceiver MAX2980
Table 7. Register R6 Map
REGISTER BIT NO. R6B0 R6B [2:1] R6B3 R6B4 R6B [6:5] R6B7 R6B8 R6B9 R6B [11:10] R6B [13:12] R6B14 R6B15 DEFAULT LOW 00 LOW LOW 00 LOW LOW LOW 10 00 HIGH HIGH Reserved. Reserved. Reserved. Reserved. Active high, allow BYPASS of transmit LPF. COMMENT
DAD[9:0]
MAX2980
ENREAD** ENTX**
PLIP
SHRCV** CS*
MAX2986
POWERLINE HOT POWERLINE INTERFACE NEUTRAL
PLIN
FREEZE* SCLK SWR HOST INTERFACES
PLOP
SDI/0 50MHz CLK
PLON RESETIN STBY *SIGNALS ARE OPTIONAL. **SIGNALS CAN BE CONNECTED TO ONE CONTROL LINE.
CLOCK
Figure 4. Interfacing the MAX2980 to the MAX2986
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11
Powerline Communication Analog Front-End Transceiver MAX2980
Typical Operating Circuit
VDD 3 162 RECEIVER 10nF 162 2 4 VDD 22nF 10nF* N HPF 1 VDD SPARK GAP 22nF 10nF L
1:1
POWERLINE
10 DRIVER 10nF AND 100nF
5k
5k 560pF 3 HPF 4 2 1 3 220pF 270pF 1 *10nF CAPACITOR ON NEUTRAL IS OPTIONAL
MAX2980
=
4 560pF
6.8H
5.6H 2
220pF
270pF
Chip Information
TRANSISTOR COUNT: 64,841 PROCESS: CMOS
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Powerline Communication Analog Front-End Transceiver
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 64L TQFP.EPS
PACKAGE OUTLINE, 64L TQFP, 10x10x1.4mm
MAX2980
21-0083
B
1
2
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Powerline Communication Analog Front-End Transceiver MAX2980
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 64L TQFP, 10x10x1.4mm
21-0083
B
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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