![]() |
|
If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
Datasheet File OCR Text: |
(R) ST19SF32 Smartcard MCU With 32 KBytes EEPROM DATA BRIEFING s s 8 BIT ARCHITECTURE CPU 32 KBytes of USER ROM WITH PARTITIONING SYSTEM ROM FOR LIBRARIES 960 Bytes of RAM WITH PARTITIONING 32 KBytes of EEPROM WITH PARTITIONING - Highly reliable CMOS EEPROM technology 2 2 2 2 s s s - 10 year data retention - 100,000 Erase/Write cycle endurance - Separate Write and Erase cycles for fast "1" programming - 1 to 64 bytes Erase or Program in 1 ms s s Micromodule (D4) SECURITY FIREWALLS FOR MEMORIES VERY HIGH SECURITY FEATURES INCLUDING EEPROM FLASH PROGRAM AND RAM FLASH CLEAR 8 BIT TIMER SERIAL ACCESS, ISO 7816-3 COMPATIBLE 3V 10% or 5V 10% SUPPLY VOLTAGE POWER SAVING STANDBY MODE UP TO 10 MHz INTERNAL OPERATING FREQUENCY CONTACT ASSIGNMENT COMPATIBLE ISO 7816-2 ESD PROTECTION GREATER THAN 5000V *CRT: Chinese Remainder Theorem s s s s s Wafer s s BD.SF32/9809VP3 This is Brief Data from STMicroelectronics. Details are subject to change without notice. For complete data, please contact your nearest Sales Office or SmartCard Products Divison, Rousset, France. Fax: (+33) 4 42 25 87 29 1/2 ST19SF32 HARDWARE DESCRIPTION The ST19SF32, a member of the ST19 device family, is a serial access microcontroller especially designed for very large volume and cost competitive secure portable objects. The ST19SF32 is based on a STMicroelectronics 8 bit CPU core including on-chip memories: 960 Bytes of RAM, 32 KBytes of USER ROM and 32 K Bytes of EEPROM. RAM, ROM and EEPROM memories can be configured into partitions. Access rules from any memory partition to another partition are setup by the user defined Memory Access Control Logic. It is manufactured using the highly reliable ST submicron technology. As all other ST19 family members, it is fully compatible with the ISO standards for Smartcard applications. SOFTWARE DEVELOPMENT Software development and firmware (ROM code/ options) generation are completed by the ST16-19 HDS development system. Figure 1. Block Diagram USER ROM RAM EEPROM 960 Bytes 32 K Bytes 32 K Bytes SYSTEM ROM MEMORY ACCESS FIREWALL SYSTEM ROM FIREWALL INTERNAL BUS CLOCK GENERATOR MODULE 8 BIT TIMER SECURITY ADMINISTRATOR UNPREDICTABLE NUMBER GENERATOR 8 BIT CPU SERIAL I/O INTERFACE CLK RESET Vcc GND I/O SCP 101b/DS 2/2 |
Price & Availability of ST19SF32
![]() |
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |