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Preliminary
M61540FP
6ch Electronic Volume with 5 Input Selector
REJ03F0117-0100Z Rev.1.0 May.31.2004
Description
M61540FP is an audio signal processor for home audio. This IC contains 6 channel electronic volume, gain control, input selector and 2 band tone control.
Features
* Electric Volume * * * * Gain Control Input Selector Multi Channel Input Tone Control 6 channel independent Electronic Volume with High Voltage Transistor. (0 to -99dB/1dBstep, -dB) 6 channel independent Gain Control (0, 6, 12, 18dB) L/R channel 5 Input Selector 6 channel Input Bass: -14 to + 14dB(2dB step), Treble: -14 to + 14dB(2dB step) Can use 2 Input for REC Output Built-in ADC out
* REC Output * ADC Out
Recommended Operating Condition
Supply Voltage Range AVCC = 7.0V(typ), AVEE = -7.0V(typ), DVDD = 3.0 to 5.5V
System Block Diagram
REC OUT (4) (5) Multi Rin Multi Lin Lch Tone RchTone CLOCK DATA MCU I/F 1 Lch 2 3
I nput sel ector
Tone Volume Bass& Treble Bass& Treble Gain Control Lout
Volume
Gain Control Rout
Input ATT
I nput sel ector
1 Rch 2 3
Input ATT Out R Multi for SLin ADC Multi SRin
Multi Out L Cin for ADC Multi SWin
Volume Volume Volume Volume
Gain Control Gain Control Gain Control Gain Control
Cout SWout SLout SRout
GND
(4) (5) REC OUT
VOL GND
DGND
DVDD AVEE AVCC
Rev.1.0, May.31.2004, page 1 of 16
M61540FP
Preliminary
Block Diagram and Pin Configuration
CL OCK BA SR1 ROUT DGND L OUT BA SR2 DA TA COUT SWOUT DV DD
20
19
18
Gain Control
17
16
15
14
13
DVDD
12
11
Gain Control -+
MCU I/F
BASL2 21
+-
10 SLOUT 9 SROUT
Bass /Tre
Gain Control Gain Control -+ Gain Control -+ Gain Control
BASL1 22 TRER 23 TREL 24 AGND 25
50K Lch Vol
8 AGND
-+ -+
Bass /Tre
7 SRIN
50K Rch Vol 25K 25K 25K 25K Cch Vol SWch Vol SLch Vol SRch Vol
6 SLIN Logic 5 SWIN 4 CIN
+ + 50K Input ATT + Input ATT + 50K 50K
INR1 26 INL1 27 INR2 28 INL2 29 INR3 30
50K
50K
50K
3 RIN 2 LIN 1 AGND
50K 50K 50K 50K 50K 50K AVEE AVCC Rch Lch
31
I NL 3
32
A GND
33
34
35
36
37
A V EE
38
A V CC
39
A DCR
40
A DCL
Rev.1.0, May.31.2004, page 2 of 16
I NL 4 (RECL 1) I NR4 (RECR1) I NL 5 (RECL 2) I NR5 (RECR2)
(Top View)
M61540FP
Preliminary
Pin Description
Pin No. 1, 8, 25, 32 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19, 20 21, 22 23 24 26, 28, 30 27, 29, 31 33, 35 34, 36 37 38 39, 40 Name AGND LIN RIN CIN SWIN SLIN SRIN SROUT SLOUT SWOUT COUT DVDD DATA CLOCK DGND ROUT LOUT BASR1, BASR2 BASL1, BASL2 TRER TREL INR1, 2, 3 INL1, 2, 3 INL4, 5/ RECL1, 2 INR4, 5/ RECR1, 2 AVEE AVCC ADCR, ADCL Function Analog Ground Input pin of L channel (Multi) Input pin of R channel (Multi) Input pin of C channel (Multi) Input pin of SW channel (Multi) Input pin of SL channel (Multi) Input pin of SR channel (Multi) Output pin of SR channel Output pin of SL channel Output pin of SW channel Output pin of C channel Power supply to internal logic circuit Input pin of control data Input pin of control clock Ground of internal logic circuit Output pin of R channel Output pin of L channel Frequency characteristic setting pin of R channel tone control (BASS) Frequency characteristic setting pin of L channel tone control (BASS) Frequency characteristic setting pin of R channel tone control (Treble) Frequency characteristic setting pin of L channel tone control (Treble) Input pin of R channel (Input Selector) Input pin of L channel (Input Selector) Input pin of L channel (Input Selector) can use REC output pin Input pin of R channel (Input Selector) can use REC output pin Negative power supply to internal analog circuit Positive power supply to internal analog circuit Output pin for ADC
Rev.1.0, May.31.2004, page 3 of 16
M61540FP
Preliminary
Absolute Maximum Ratings
Parameter Power Supply Power dissipation Thermal derating Operating temperature Storage temperature Note: AVEEDGND25C
THERMAL DERATINGS (MAXIMUM RATING) 2.0
POWER DI SSI PA TI ON pd (W)
1.5
1.46W
1.0
0.88
0.5
0 0 25 50 75 100 125 150
AMBIENT TEMPERATURE Ta ( C )
Recommended Operating Conditions
(Ta=25C, unless otherwise noted.)
Parameter Analog Supply Voltage (Positive) Analog Supply Voltage (Negative) Digital Supply Voltage Logic "H" level Input Voltage Logic "L" level Input Voltage Note: AVEEDGNDRev.1.0, May.31.2004, page 4 of 16
M61540FP
Preliminary
Relationship Between Data and Clock
Data signal is read at the rising edge of CLOCK. Make "H" at the timing which DATA of D0-D23 make latch.
DATA
D0
D1
D2
D3
D21
D22
D23
CLOCK
When DATA is "H", latch signal is created at the falling edge of CLOCK.
Clock and Data Timings
(D0 to D23)
DATA
t cr
LATCH
75% 25% tSLD 75% 50% 25%
CLOCK
tHLD tSHD tHHD
tSLD
tHLD tSC
tr tWHC
tf tWLC
Timing Definition of Digital Block
Limits Parameter CLOCK cycle time CLOCK pulse width ("H" level) CLOCK pulse width ("L" level) Rising time of clock and data Falling time of clock and data DATA setup time (Rising time of clock) DATA setup time (Falling time of clock) DATA hold time ("H" level) DATA hold time ("L" level) CLOCK setup time Symbol tcr tWHC tWLC tr tf tSHD tSLD tHHD tHLD tSC Min 8 3.2 3.2 1.6 1.6 1.6 1.6 1.6 Typ Max 0.8 0.8 s Unit
Rev.1.0, May.31.2004, page 5 of 16
M61540FP
Preliminary
Power on Reset
This IC built-in the power on reset function. The voltage of DVDD (13 pin) -DGND (16 pin) less than 2.6V, the serial DATA can not accept.
(V)
DVDD(3pin) - DGND(6pin)
2.6V
(S) Reset time After reset is canceled, the serial DATA can accept.
Release of reset.
Note: AVEEDGNDData Control Specification
Initialize all data of the 4 formats when Digital Power supply (DVDD) turns on. Prohibit using except specified Data code as follows.
Slot1 D0a D1a D2a D3a D4a D5a D6a D7a D8a (4) L/R Vol Input D9a D10a D11a D12a D13a D14a D15a D16a D17a D18a D19a D20a D21a D22 (6) Treble 0 0 0 D23 0
(1) Input Selector
(2) REC Output
(3) ADC Input ATT
(5) Bass/ Tone control Bypass
0
0
0
0
Slot2 D0b D1b D2b D3b D4b D5b D6b D7b D8b D9b D10b D11b D12b D13b D14b D15b D16b D17b D18b D19b D20b D21b D22 D23 (7) Lch Gain Control (7) Rch Gain Control
(8) Lch Volume
(8) Rch Volume
0
0
0
0
0
1
Slot3 D0c D1c D2c D3c D4c D5c D6c D7c D8c D9c D10c D11c D12c D13c D14c D15c D16c D17c D18c D19c D20c D21c D22 (7) SWch Gain Control D23
(7) Cch Gain Control
(8) Cch Volume
(8) SWch Volume
0
0
0
0
1
0
Slot4 D0d D1d D2d D3d D4d D5d D6d D7d D8d D9d D10d D11d D12d D13d D14d D15d D16d D17d D18d D19d D20d D21d D22 D23 (7) SLch Gain Control (7) SRch Gain Control
(8) SLch Volume
(8) SRch Volume
0
0
0
0
1
1
Note:
No guarantee except for these codes.
Rev.1.0, May.31.2004, page 6 of 16
M61540FP
Preliminary
Setting Code
It's initial setting when power is turned on. (1) Input Selector
Setting ALL OFF IN1 IN2 IN3 IN4* IN5* D0a 0 0 1 1 0 0 D1a 0 1 0 1 0 1 D2a 0 0 0 0 1 1
Note: *No guarantee except for these codes.
(2) REC Output
REC Output Setting OFF ON REC1 D3a 0 1*1 REC2 D4a 0 1*2
*1: When IN4 selected, REC1 can not use. IN4 REC1 D0a D1a D2a ON OFF 0 0 1
D3a 1
*2: When IN5 selected, REC2 can not use. IN5 REC2 D0a D1a D2a ON OFF 0 1 1
D4a 1
(3) ADC Input ATT
ATT Setting 0dB -6dB -12dB -18dB D5a 0 0 1 1 D6a 0 1 0 1
(4) L/R Volume Input
Setting Selector In Multi In D7a 0 1
Rev.1.0, May.31.2004, page 7 of 16
M61540FP
Preliminary It's initial setting when power is turned on.
(5) Bass/Bypass
ATT Setting +14dB +12dB +10dB +8dB +6dB +4dB +2dB 0dB -2dB -4dB -6dB -8dB -10dB -12dB -14dB Bypass*3 D8a 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D9a 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 D10a 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 D11a 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
(6) Treble
ATT Setting +14dB +12dB +10dB +8dB +6dB +4dB +2dB 0dB -2dB -4dB -6dB -8dB -10dB -12dB -14dB D12a 1 1 1 1 1 1 1 1/0 0 0 0 0 0 0 0 D13a 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 D14a 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 D15a 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
*3: Tone control is bypass.
(7) Gain Control
Lch Rch ATT Setting Cch SWch SLch SRch 0dB 6dB 12dB 18dB D0b D9b D0c D9c D0d D9d 0 0 1 1 D1b D10b D1c D10c D1d D10d 0 1 0 1
Rev.1.0, May.31.2004, page 8 of 16
M61540FP (8) 6ch Volume
Preliminary
It's initial setting when power is turned on.
Lch Rch ATT Cch SWch SLch SRch 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -11dB -12dB -13dB -14dB -15dB -16dB -17dB -18dB -19dB -20dB -21dB -22dB -23dB -24dB -25dB -26dB -27dB -28dB -29dB -30dB -31dB -32dB -33dB -34dB -35dB -36dB -37dB -38dB -39dB -40dB D2b D11b D2c D11c D2d D11d 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D3b D12b D3c D12c D3d D12d 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 D4b D13b D4c D13c D4d D13d 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 D5b D14b D5c D14c D5d D14d 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 D6b D15b D6c D15c D6d D15d 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 D7b D16b D7c D16c D7d D16d 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D8b D17b D8c D17c D8d D17d 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Rev.1.0, May.31.2004, page 9 of 16
M61540FP
Lch Rch ATT Cch SWch SLch SRch -41dB -42dB -43dB -44dB -45dB -46dB -47dB -48dB -49dB -50dB -51dB -52dB -53dB -54dB -55dB -56dB -57dB -58dB -59dB -60dB -61dB -62dB -63dB -64dB -65dB -66dB -67dB -68dB -69dB -70dB -71dB -72dB -73dB -74dB -75dB -76dB -77dB -78dB -79dB -80dB -81dB -82dB -83dB -84dB D2b D11b D2c D11c D2d D11d 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3b D12b D3c D12c D3d D12d 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4b D13b D4c D13c D4d D13d 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 D5b D14b D5c D14c D5d D14d 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 D6b D15b D6c D15c D6d D15d 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 D7b D16b D7c D16c D7d D16d 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D8b D17b D8c D17c D8d D17d 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Preliminary
Rev.1.0, May.31.2004, page 10 of 16
M61540FP
Lch Rch ATT Cch SWch SLch SRch -85dB -86dB -87dB -88dB -89dB -90dB -91dB -92dB -93dB -94dB -95dB -96dB -97dB -98dB -99dB -dB D2b D11b D2c D11c D2d D11d 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D3b D12b D3c D12c D3d D12d 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 D4b D13b D4c D13c D4d D13d 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1/0 D5b D14b D5c D14c D5d D14d 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1/0 D6b D15b D6c D15c D6d D15d 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 D7b D16b D7c D16c D7d D16d 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1/0 D8b D17b D8c D17c D8d D17d 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1/0
Preliminary
Note: No guarantee except for these codes.
Electrical Characteristics
Unless otherwise noted, Ta = 25C, AVCC = 7V, AVEE = -7V, DVDD = 5V, f = 1kHz, Volume = 0dB, Input Selector = IN1, Gain Control = 0dB, ADC Input ATT = 0dB, Tone = Bypass (1) Power supply characteristics
Limits Parameter Analog positive power circuit current Analog negative power circuit current Digital power circuit current Symbol AIcc AIee DIdd Min -42 Typ 32 -32 2 Max 42 3 Unit mA mA mA Test condition With AVCC = 7V and AVEE = -7V 38pin current, when no signal is provided With AVCC = 7V and AVEE = -7V 37pin current, when no signal is provided With DVDD = 3.3V, 13pin current, when no signal is provided
Rev.1.0, May.31.2004, page 11 of 16
M61540FP (2) Input/Output characteristics (OVER ALL)
Limits Parameter Input resistance Maximum output voltage Pass gain Total harmonic distortion Symbol Min Rin VOM Gv THD1 THD2 Balance of CBAL mutual channels Output noise voltage Vono1 Vono2 Vono3 Selector separation SS1 SS2 Channel separation CS 17 3.8 -2.0 -- -0.5 -- -- -- Typ 25 4.4 0 Max 33 -- 2.0 Unit Test condition
Preliminary
2 to 7, 26, 27 pin Vrms 2 to 7pin input, 9 to 12,17,18pin output, THD = 1%, RL = 10k, Output Gain Control = +6dB dB 2 to 7,26,27 pin input, 9 to 12,17,18pin output, Vi = 0.3Vrms, FLAT 2 to 7pin input, 9 to12, 17,18 pin output, BW: 400Hz to 30kHz, f = 1kHz, Vo = 0.3Vrms, RL=10k 2 to 7pin input, 9 to 12, 17,18pin output, BW: 400Hz to 30kHz, f = 1kHz, Vo = 2Vrms, RL = 10k 26,27pin input, 17,18pin output, Vi = 0.3Vrms Output Gain Control = 0dB Output Gain Control = +12dB Output Gain Control = 0dB Output Gain Control = +12dB
0.002 0.008 % 0.01 0 1 5 1.5 7.2 1 5 -90 -90 -90 0.1 0.5 3 15 4.5 22 3 15 -70 -70 -70 dB dB
Vrms JIS-A, Rg = 0, 17,18pin output,
Volume = -dB setting JIS-A, Rg = 0, 17,18pin output, Volume = 0dB setting
JIS-A, Rg = 0, 9 to 12pin output, Output Gain Control = 0dB Volume = 0dB setting Output Gain Control = +12dB < Input Selector> Vo = 1Vrms, Rg = 0, RL = 10k, JIS-A < Multi Input Selector > Vo = 1Vrms, Rg = 0, RL = 10k, JIS-A Vo = 1Vrms, Rg = 0, RL = 10k, JIS-A
(3) 6 channel Volume characteristics
Limits Parameter Maximum attenuation Volume gain gang error of mutual channels Symbol ATTmax Dvol Min -- -0.5 Typ 0 Max Unit dB Test condition Vi = 2Vrms, JIS-A, VOL = -dB Volume = 0dB -100 -95
+0.5 dB
(4) Tone control characteristics Unless otherwise noted, Tone ON/OFF = ON
Limits Parameter Tone control voltage gain (Boost/Bass) Tone control voltage gain (Cut/Bass) Tone control voltage gain (Boost/Treble) Tone control voltage gain (Cut/Treble) Balance of mutual channels Symbol G (BASS) B G (BASS) C G (TRE) B G (TRE) C BALT Min +12 -16 +12 -16 -2 Typ +14 -14 +14 -14 0 Max +16 -12 +16 -12 +2 Unit dB dB dB dB dB Test condition f = 100Hz Bass +14dB setting f = 100Hz Bass -14dB setting f = 10kHz Treble +14dB setting f = 10kHz Treble -10dB setting Bass setting +14, -14dB Treble setting +14, -14dB
Rev.1.0, May.31.2004, page 12 of 16
M61540FP
Preliminary
Tone Control
(1) Bass
< Boost >
IN
+
+
OUT
R3
R2 f0 = 1 2 R1(R2+R3)C1C2 (R2+R3)R1C1C2 Q= R1(C1+C2)+R3C1 R1(C1+C2)+(R2+R3)C1 R1(C1+C2)+R3C1 (Hz)
C1 0.047 R1 4.7K
C2 0.15
Gv = 20 log
(dB)
< Cut >
IN
+ +
R2 R3
OUT
f0 =
1 2 R1(R2+R3)C1C2 (R2+R3)R1C1C2
C2 0.15 (Hz)
C1 0.047 R1 4.7K
Q=
R1(C1+C2)+R3C1 R1(C1+C2)+R3C1 R1(C1+C2)+(R2+R3)C1
Gv = 20 log
(dB)
Rev.1.0, May.31.2004, page 13 of 16
M61540FP (2) Treble
Preliminary
< Boost >
IN
+
R5 R4
-
+
OUT
Gv =20 log
(R4+R5)2+ RC2 R4 +RC
2 2
(dB)
RC
0.022

IN
+
R5
-
+
OUT
Gv =20 log
R4 +RC
2
2
2
(dB)
2
(R4+R5) + RC
R4
RC
0.022
Curve of characteristics
Tone gain Gv (dB)
Frequency f(Hz)
Rev.1.0, May.31.2004, page 14 of 16
M61540FP
Preliminary
Application Example
L
4.7K 0.15 0.047 4.7 4.7
R
DVDD 5V
C
SW
MCU
100 0.1
4.7
4.7
20
19
18
Gain Control
17
16
15
14
13
DVDD
12
11
4.7
Gain Control
MCU I/F
SL
0.047 4.7K 0.15 0.022
21
+-+
10
4.7
SR
22 23
Bass /Tre
Gain Control Gain Control Gain Control Gain Control
9 8
-+ -+ -+ -+
0.022
24 25
2.2
Bass /Tre
7
50K Rch Vol 25K 25K 25K 25K Cch Vol SWch Vol SLch Vol SRch Vol
2.2
SRIN
2.2
6
50K Lch Vol
SLIN
Logic 5 4
+ + Input ATT
INR1
2.2
26 27
2.2
2.2
SWIN
50K
INL1
2.2
50K
CIN
INR2
2.2
28 29
2.2
50K
+ Input ATT
50K
3 2 1
2.2
RIN
INL2
2.2
50K
+ -
50K
LIN
INR3
30
50K 50K 50K 50K 50K 50K AVEE AVCC Rch Lch
31
2.2
32
33
2.2
34
2.2
35
2.2
36
2.2
37
38
39
40
I NL 4 (RECL 1)
I NL 5 (RECL 2)
I NR4 (RECR1)
I NR5 (RECR2)
I NL 3
100 0.1100 0.1
ADC
AVEE AVCC 7V -7V
Rev.1.0, May.31.2004, page 15 of 16
M61540FP
Preliminary
Package Dimensions As of January, 2003
Unit: mm
9.0 0.2 7.0 30 21
9.0 0.2
31
20
40 10
11
*0.17 0.05 0.15 0.04
1.40 1.70 Max
1 *0.25 0.05 0.22 0.04
0.13
M
0.65
0.575
1.0 0.575 0 - 8 0.50 0.10
0.10
0.09 0.13+ 0.05 -
*Dimension including the plating thickness Base material dimension
Package Code JEDEC JEITA Mass(reference value)
FP-40B -- Conforms 0.2 g
Rev.1.0, May.31.2004, page 16 of 16
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1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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