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RF1K49092
Data Sheet January 2002
3.5A/2.5A, 12V, 0.050/0.130 Ohm, Logic Level, Complementary LittleFETTM Power MOSFET
This complementary power MOSFET is manufactured using an advanced MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. It is designed for use in applications such as switching regulators, switching converters, motor drivers, relay drivers, and low voltage bus switches. This product achieves full rated conduction at a gate bias in the 3V to 5V range, thereby facilitating true on-off power control directly from logic level (5V) integrated circuits. Formerly developmental type TA49092.
Features
* 3.5A, 12V (N-Channel) 2.5A, 12V (P-Channel) * rDS(ON) = 0.050 (N-Channel) rDS(ON) = 0.130 (P-Channel) * Temperature Compensating PSPICE(R) Model * On-Resistance vs Gate Drive Voltage Curves * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER RF1K49092 PACKAGE MS-012AA BRAND RF1K49092
Symbol
D1 (8) D1 (7)
NOTE: When ordering, use the entire part number. For ordering in tape and reel, add the suffix 96 to the part number, i.e., RF1K4909296.
S1 (1) G1 (2)
D2 (6) D2 (5)
S2 (3) G2 (4)
Packaging
JEDEC MS-012AA
BRANDING DASH
5 1 2 3 4
(c)2002 Fairchild Semiconductor Corporation
RF1K49092 Rev. B
RF1K49092
Absolute Maximum Ratings
TA = 25oC Unless Otherwise Specified N-CHANNEL 12 12 10 3.5 Refer to Peak Current Curve Refer to UIS Curve 2 0.016 -55 to 150 300 260
P-CHANNEL -12 -12 10 2.5 Refer to Peak Current Curve Refer to UIS Curve 2 0.016 -55 to 150 300 260
UNITS V V V A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k, Note 1) . . . . . . . . .VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Pulse Width = 5s). . . . . . . . . . . . . . . . . . . . . ID Pulsed (Figures 5, 26) . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating (Figures 6, 27). . . . . . . . . . . . . EAS Power Dissipation TA = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . Tpkg
W W/oC
oC oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 125oC.
N-Channel Electrical Specifications
PARAMETER Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current
TA = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V, (Figure 13) VGS = VDS, ID = 250A, (Figure 12) VDS = 12V, VGS = 0V VGS = 10V ID = 3.5A, VGS = 5V, (Figures 9, 11) VDD = 6V, ID 3.5A, RL = 1.71, V GS = 5V, RGS = 25 (Figure 10) TA = 25o C TA = 150o C MIN 12 1 VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 9.6V, ID = 3.5A, RL = 2.74 (Figure 15) Pulse width = 1s Device mounted on FR-4 material TYP 18 60 50 60 20 12 0.9 750 700 275 MAX 2 1 50 100 0.050 100 140 25 15 1.2 62.5 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF
oC/W
Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Ambient
IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(5) Qg(TH) CISS COSS CRSS RJA
VDS = 10V, VGS = 0V, f = 1MHz (Figure 14)
N-Channel Source to Drain Diode Specifications
PARAMETER Source to Drain Voltage Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS ISD = 3.5A ISD = 3.5A, dISD/dt = 100A/s MIN TYP MAX 1.25 70 UNITS V ns
(c)2002 Fairchild Semiconductor Corporation
RF1K49092 Rev. B
RF1K49092
P-Channel Electrical Specifications
PARAMETER Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current TA = 25o C, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250A, VGS = 0V, (Figure 34) VGS = VDS, ID = 250A, (Figure 33) VDS = -12V, VGS = 0V VGS = 10V ID = 2.5A, VGS = -5V VDD = -6V, ID 2.5A, RL = 2.40, V GS = -5V, RGS = 25 (Figure 31) TA = 25o C TA = 150o C MIN -12 -1 VGS = 0V to -10V VGS = 0V to -5V VGS = 0V to -1V VDD = -9.6V, ID = 2.5A, RL = 3.84 (Figure 36) Pulse width = 1s Device mounted on FR-4 material TYP 25 65 40 45 19 10 0.8 775 550 150 MAX -2 -1 -50 100 0.130 115 110 24 14 1.1 62.5 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF
oC/W
Gate to Source Leakage Current Drain to Source On Resistance Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at -5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction-to-Ambient
IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(-5) Qg(TH) CISS COSS CRSS RJA
VDS = -10V, VGS = 0V, f = 1MHz (Figure 35)
P-Channel Source to Drain Diode Specifications
PARAMETER Source to Drain Voltage Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS ISD = -2.5A ISD = -2.5A, dISD/dt = -100A/s MIN TYP MAX -1.25 55 UNITS V ns
Typical Performance Curves (N-Channel)
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID , DRAIN CURRENT (A) 0 25 50 75 100 125 TA , AMBIENT TEMPERATURE (oC) 150 0.8 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (oC) 150
0.6 0.4
0.2
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE
(c)2002 Fairchild Semiconductor Corporation
RF1K49092 Rev. B
RF1K49092 Typical Performance Curves (N-Channel)
10
(Continued)
ZJA, NORMALIZED THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM
0.1
t1 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103
0.01 10-3
10-2
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
100
ID, DRAIN CURRENT (A)
TA = 25oC VDSS MAX = 12V 10 5ms 10ms 1 100ms 1s 0.1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) DC
IDM, PEAK CURRENT CAPABILITY (A)
TJ = MAX RATED
200 100
TA = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I VGS = 5V
= I25
150 - TA 125
10
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 1 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 10 0 101
0.01 0.1
1 10 VDS, DRAIN TO SOURCE VOLTAGE (V)
100
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
20 IAS, AVALANCHE CURRENT (A)
25
10
STARTING TJ = 25oC
ID , DRAIN CURRENT (A)
20 VGS = 4V 15
VGS = 10V VGS = 5V VGS = 4.5V
STARTING TJ = 150oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 1 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100
10 VGS = 3V 5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) 5
0
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS
(c)2002 Fairchild Semiconductor Corporation
RF1K49092 Rev. B
RF1K49092 Typical Performance Curves (N-Channel)
25 ID(ON), ON-STATE DRAIN CURRENT (A) rDS(ON), ON-STATE RESISTANCE (m) 25oC 20 -55oC 150oC VDD = 6V
(Continued)
250 I D = 7.0A 200
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 10V
15
150
I D = 3.5A I D = 1.75A
10
100 ID = 0.5A 50
5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 0 0.0 1.5 3.0 4.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V) 7.5
0 2.5
3.5 4.0 4.5 3.0 VGS, GATE TO SOURCE VOLTAGE (V)
5.0
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
140 VDD = 6V, ID = 3.5A, RL = 1.71 tr SWITCHING TIME (ns) 100 80 60 40 20 t D(ON) 0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE () t D(OFF) NORMALIZED ON RESISTANCE 120
2.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 5V, ID = 3.5A 1.5
1.0
tf
0.5
0.0 -80
-40
0 40 80 120 TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 10. SWITCHING TIME vs GATE RESISTANCE
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE 1.5
2.0 ID = 250A 1.5
1.0
1.0
0.5
0.5
0.0 -80
-40
0
40
80
120
160
0.0 -80
-40
TJ, JUNCTION TEMPERATURE (oC)
0 40 80 120 TJ , JUNCTION TEMPERATURE (oC)
160
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
(c)2002 Fairchild Semiconductor Corporation
RF1K49092 Rev. B
RF1K49092 Typical Performance Curves (N-Channel)
1200
(Continued)
12 VDS , DRAIN-SOURCE VOLTAGE (V) VDD = BVDSS 9 VDD = BVDSS 3.75 5.00 VGS , GATE-SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
900
VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD
CISS COSS
6 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS RL = 3.43 IG(REF) = 0.6mA VGS = 5V 0
2.50
600 CRSS 300
3
1.25
0.00 I 20 --------------------I G ( ACT ) G ( REF ) I t, TIME (s)
0 0 2 4 6 8 10 VDS, DRAIN TO SOURCE VOLTAGE (V)
80 --------------------I G ( ACT )
G ( REF )
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms (N-Channel)
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
tON td(ON) tr VDS RL 90%
tOFF td(OFF) tf 90%
+
RG DUT
-
VDD
0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
VGS
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
(c)2002 Fairchild Semiconductor Corporation
RF1K49092 Rev. B
RF1K49092 Test Circuits and Waveforms (N-Channel)
CURRENT REGULATOR VDS (ISOLATED SUPPLY) VDD 12V BATTERY 0.2F 50k 0.3F Qg(5) D G DUT VGS VGS = 1V 0 Ig(REF) 0 IG CURRENT SAMPLING RESISTOR S VDS ID CURRENT SAMPLING RESISTOR Ig(REF) 0 Qg(TH) VGS = 5V SAME TYPE AS DUT VDS VGS = 10V Qg(TOT)
(Continued)
FIGURE 20. GATE CHARGE TEST CIRCUIT
FIGURE 21. GATE CHARGE WAVEFORMS
Typical Performance Curves (P-Channel)
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID , DRAIN CURRENT (A) 0.8 -3.0 -2.5 -2.0 -1.5
0.6 0.4 0.2
-1.0 -0.5 0 25
0
0
25
50 75 100 TA , AMBIENT TEMPERATURE (oC)
125
150
50
75 100 125 TA, AMBIENT TEMPERATURE (oC)
150
FIGURE 22. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 23. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE
10
ZJA, NORMALIZED THERMAL RESPONSE
1
DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM
0.1
t1 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) 102 103
0.01 10-3
10-2
FIGURE 24. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
(c)2002 Fairchild Semiconductor Corporation
RF1K49092 Rev. B
RF1K49092 Typical Performance Curves (P-Channel)
-100 TJ = MAX RATED, TA = 25oC, VDSS(MAX) = -12V
(Continued)
-200 IDM, PEAK CURRENT CAPABILITY (A) -100 VGS = -10V
TA = 25oC
FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I
ID, DRAIN CURRENT (A)
-10
5ms 10ms 100ms 1s DC
= I25
150 - TA 125
-1
-10
VGS = -5V
-0.1 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) -0.01 -0.1 -1 -10 -100
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION -1 10-5 10-4 10-3 10-2 10-1 100 101
VDS, DRAIN TO SOURCE VOLTAGE (V)
t, PULSE WIDTH (s)
FIGURE 25. FORWARD BIAS SAFE OPERATING AREA
FIGURE 26. PEAK CURRENT CAPABILITY
-20 IAS, AVALANCHE CURRENT (A)
-25 VGS = -10V STARTING TJ = 25oC I D, DRAIN CURRENT (A)
-10
-20
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TA = 25oC VGS = -5V
-15 VGS = -4.5V -10 VGS = -4V -5 VGS = -3V 0 -1 -2 -3 -4 -5 VDS, DRAIN TO SOURCE VOLTAGE (V)
STARTING TJ = 150oC
-1 0.1
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BV DSS - VDD) +1] 1 10 tAV, TIME IN AVALANCHE (ms) 100
0
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 27. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 28. SATURATION CHARACTERISTICS
-25 ID(ON), ON-STATE DRAIN CURRENT (A)
rDS(ON), ON-STATE RESISTANCE (m)
-20
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = -6V 25oC
500 - 55oC 150oC ID = -2.5A 400 I D = -1.5A 300 ID = -6.0A
-15
-10
200 I D = -0.5A 100
-5
0 0.0
-1.5
-3.0
-4.5
-6.0
-7.5
0 -2.5
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = -10V -3.0 -3.5 -4.0 -4.5 VGS, GATE TO SOURCE VOLTAGE (V) -5.0
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 29. TRANSFER CHARACTERISTICS
FIGURE 30. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
(c)2002 Fairchild Semiconductor Corporation
RF1K49092 Rev. B
RF1K49092 Typical Performance Curves (P-Channel)
120 100 SWITCHING TIME (ns) 80 60 tD(OFF) 40 20 0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE () tD(ON) NORMALIZED ON RESISTANCE VDD = -6V, ID = -2.5A, RL = 2.40 tr
(Continued)
2.0
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = -5V, ID = -2.5A
1.5
tf
1.0
0.5
0 -80
-40
0 40 80 120 TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 31. SWITCHING TIME AS A FUNCTION OF GATE RESISTANCE
FIGURE 32. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = -250A NORMALIZED GATE THRESHOLD VOLTAGE
2.0 ID = -250A 1.5
1.5
1.0
1.0
0.5
0.5
0.0 -80
-40
0
40
80
120
160
0.0 -80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 33. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 34. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
-12 VDS , DRAIN-SOURCE VOLTAGE (V) -5.00 VGS , GATE-SOURCE VOLTAGE (V) VDD = BVDSS -9 VDD = BVDSS -3.75
1200 CISS C, CAPACITANCE (pF) 900 COSS 600
VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD
-6 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS -3 RL = 3.84 IG(REF) = -0.5mA VGS = -5V
-2.50
CRSS 300
-1.25
0 0 0 -2 -4 -6 -8 VDS, DRAIN TO SOURCE VOLTAGE (V) -10
0.00
20 --------------------I G ( ACT )
I G ( REF )
t, TIME (s)
80 --------------------I G ( ACT )
I G ( REF )
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 36. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
FIGURE 35. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
(c)2002 Fairchild Semiconductor Corporation
RF1K49092 Rev. B
RF1K49092 Test Circuits and Waveforms (P-Channel)
VDS tAV L VARY tP TO OBTAIN REQUIRED PEAK IAS RG 0
+
VDD VDD
0V VGS
DUT tP IAS 0.01
IAS tP BVDSS VDS
FIGURE 37. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 38. UNCLAMPED ENERGY WAVEFORMS
tON td(ON) tr RL 0 10%
tOFF td(OFF) tf 10%
DUT VGS RG
VDD
+
VDS VGS 0
90%
90%
10% 50% PULSE WIDTH 90% 50%
FIGURE 39. SWITCHING TIME TEST CIRCUIT
-VDS (ISOLATED SUPPLY) 0 DUT 12V BATTERY 0.2F 50k 0.3F
FIGURE 40. RESISTIVE SWITCHING WAVEFORMS
CURRENT REGULATOR
Qg(TH)
VDS
VGS= -1V -VGS D G DUT VDD Qg(TOT) +VDS ID CURRENT SAMPLING RESISTOR 0 Ig(REF) Qg(-5) VGS= -10V VGS= -5V
0 Ig(REF) IG CURRENT SAMPLING RESISTOR S
FIGURE 41. GATE CHARGE TEST CIRCUIT
FIGURE 42. GATE CHARGE WAVEFORMS
(c)2002 Fairchild Semiconductor Corporation
RF1K49092 Rev. B
RF1K49092 Soldering Precautions
1. The soldering process creates a considerable thermal stress on any semiconductor component. The melting temperature of solder is higher than the maximum rated temperature of the device. The amount of time the device is heated to a high temperature should be minimized to assure device reliability. Therefore, the following precautions should always be observed in order to minimize the thermal stress to which the devices are subjected. 2. Always preheat the device. 3. The delta temperature between the preheat and soldering should always be less than 100oC. Failure to preheat the device can result in excessive thermal stress which can damage the device. 4. The maximum temperature gradient should be less than 5oC per second when changing from preheating to soldering. 5. The peak temperature in the soldering process should be at least 30 oC higher than the melting point of the solder chosen. 6. The maximum soldering temperature and time must not exceed 260oC for 10 seconds on the leads and case of the device. 7. After soldering is complete, the device should be allowed to cool naturally for at least three minutes, as forced cooling will increase the temperature gradient and may result in latent failure due to mechanical stress. 8. During cooling, mechanical stress or shock should be avoided.
(c)2002 Fairchild Semiconductor Corporation
RF1K49092 Rev. B
RF1K49092 PSPICE Electrical Model
SUBCKT RF1K49092 2 1 3;
CA 12 8 9.77e-10 CB 15 14 9.19e-10 CIN 6 8 7.81e-10 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 14.89 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 1.233e-9 LSOURCE 3 7 0.452e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01
12 GATE 1 9
N-Channel Model rev 9/6/94
DPLCAP 10 5 LDRAIN DRAIN 2
DBREAK RDRAIN
ESG + EVTO 20 + 18 8
6 8 VTO +
11 16 21 6 MOS1 RIN CIN 8 RSOURCE EBREAK MOS2 17 18
+
DBODY
LGATE RGATE
7
LSOURCE 3 SOURCE
S1A 13 8 S1B CA + EGS 6 8 14 13
S2A 15 S2B 13 CB EDS + 14 5 8 IT RBREAK 17 18 RVTO 19 VBAT +
RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 4.91e-3 RGATE 9 20 2.74 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 5e-3 RVTO 18 19 RVTOMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
VBAT 8 19 DC 1 VTO 21 6 0.3215 .MODEL DBDMOD D (IS = 7.00e-13 RS = 2.15e-2 TRS1 = 0.5e-3 TRS2 = 3.68e-6 CJO = 1.28e-9 TT = 1.8e-8) .MODEL DBKMOD D (RS = 1.28e-1 TRS1 = 1.69e-3 TRS2 = -2.0e-6) .MODEL DPLCAPMOD D (CJO = 0.84e-9 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 1.6 3KP = 11.5 5IS = 1e-3 0N = 1 0TOX = 1L = 1 uW = 1u) .MODEL RBKMOD RES (TC1 = 9.15e- 4TC2 = 3.13e-7) .MODEL RDSMOD RES (TC1 = 7.00e-4 TC2 = 5.00e-6) .MODEL RVTOMOD RES (TC1 = -2.155e- 3TC2 = -2.7e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.05 VOFF= -4.05) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.05 VOFF= -6.05) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.72 VOFF= 4.28) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 4.28 VOFF= -0.72) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991.
(c)2002 Fairchild Semiconductor Corporation
RF1K49092 Rev. B
RF1K49092 PSPICE Electrical Model
SUBCKT RF1K49092 2 1 3 ;P-Channel Model rev 10/24/94
CA 12 8 8.75e-10 CB 15 14 8.65e-10 CIN 6 8 7.65e-10 DBODY 5 7 DBDMOD DBREAK 7 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 5 11 17 18 -23.75 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 8 6 1 EVTO 20 6 8 18 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 1.233e-9 LSOURCE 3 7 0.452e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 7.36e-3 RGATE 9 20 6.1 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 4.56e-2 RVTO 18 19 RVTOMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
S1A 12 S1B CA + EGS 6 8 EDS 13 8 14 13 13 CB + 5 8 14 IT GATE 1 DPLCAP 10 5 LDRAIN DRAIN 2
RDRAIN
ESG + EVTO 9 20 + 18 8 LGATE RGATE
6 8 VTO 6 +
+ 16 21 MOS1 RIN CIN 8 RSOURCE 7 EBREAK 17 18 MOS2 11 DBREAK
DBODY
LSOURCE 3 SOURCE
S2A 15 S2B RBREAK 17 18 RVTO 19 VBAT +
VBAT 8 19 DC 1 VTO 21 6 -0.558 .MODEL DBDMOD D (IS = 3.0e-13 RS = 4.4e-2 TRS1 = 1.0e-3 TRS2 = -7.37e-6 CJO = 1.27e-9 TT = 2.2e-8) .MODEL DBKMOD D (RS = 7.84e-2 TRS1 = -4.27e-3 TRS2 = 5.77e-5) .MODEL DPLCAPMOD D (CJO = 2.85e-10 IS = 1e-30 N = 10) .MODEL MOSMOD PMOS (VTO = -2.1423 KP = 9.206 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 9.61e- 4TC2 = -1.09e-6) .MODEL RDSMOD RES (TC1 = 2.10e-3 TC2 = 6.99e-6) .MODEL RVTOMOD RES (TC1 = -1.82e- 3TC2 = 1.47e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 5.47 VOFF= 3.47) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.47 VOFF= 5.47) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.05 VOFF= -3.95) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.95 VOFF= 1.05) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991.
(c)2002 Fairchild Semiconductor Corporation
RF1K49092 Rev. B
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Rev. H4

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