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| (R) EMIF10-1K010F1 A.S.D. TM EMI FILTER INCLUDING ESD PROTECTION MAIN APPLICATIONS Where EMI filtering in ESD sensitive equipment is required: Computers and printers Communication systems Mobile phones MCU Boards s s s s DESCRIPTION The EMIF10-1K010F1 is a highly integrated device designed to suppress EMI / RFI noise in all systems subjected to electromagnetic interferences. The EMIF10 flip-chip packaging means the package size is equal to the die size. That's why EMIF10-1K010F1 is a very small device. Additionally, this filter includes an ESD protection circuitry which prevents the protected device from destruction when subjected to ESD surges up to 15 kV. BENEFITS s s s s s Flip Chip package s s EMI symetrical (I/O) low-pass filter High efficiency in EMI filtering Very low PCB space consuming: 2.6 x 2.6 mm2 Very thin package: 0.65 mm High efficiency in ESD suppression on both input & output PINS (IEC61000-4-2 level 4). High reliability offered by monolithic integration High reducing of parasitic elements through integration & wafer level packaging. PIN CONFIGURATION (Ball Side) A 1 2 3 I3 B I1 I5 C I2 I4 I6 I8 I10 D O1 O3 O5 O7 O9 E O2 O4 O6 O8 O10 BASIC CELL CONFIGURATION Low-pass filter GND GND GND GND I7 I9 Input Output 4 5 Ri/o = 1k Cinput = 100pF TM : ASD is a trademark of STMicroelectronics. July 2002 - Ed: 3C 1/13 EMIF10-1K010F1 COMPLIES WITH FOLLOWING STANDARD: IEC61000-4-2 level 4 15 KV (air discharge) 8 kV (contact discharge) on input & output pins MIL STD 883C - Method 3015-6 Class 3 Filtering Behavior S21 (dB) 0 -10 -20 -30 ESD response to IEC61000-4-2 (16kV Air Discharge) V(in1) V(out1) -40 -50 1 10 100 frequency (MHz) 1,000 Capacitance versus reverse applied voltage. C(pF) 100 90 80 70 60 50 40 30 20 10 0 F=1MHz Vosc=30mV VR(V) 1 2 5 10 2/13 EMIF10-1K010F1 ABSOLUTE MAXIMUM RATINGS (Tamb = 25 C) Symbol VPP Parameter and test conditions ESD discharge IEC61000-4-2, air discharge ESD discharge IEC61000-4-2, contact discharge MIL STD 883C Method 3015-6 Junction temperature Operating temperature range Storage temperature range Value 15 8 25 125 -40 to + 85 -55 to +150 Unit kV Tj Top Tstg C C C ELECTRICAL CHARACTERISTICS (Tamb = 25C) Symbol VBR IRM VRM VCL Rd IPP RI/O Cin Parameters Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic impedance Peak pulse current Series resistance between Input & Output Input capacitance per line slope : 1 / R d IPP VCL VBR VRM IRM IR I V Symbol VBR IRM Rd RI/O Cline At 0V bias IR = 1mA Test conditions Min 6 Typ 8 Max 10 500 Unit V nA VRM = 3V per line IPP = 10A, tp = 2.5s (see note 1) 900 80 1 1000 100 1100 120 pF Note 1: To calculate the ESD residual voltage, please refer to the paragraph "ESD PROTECTION" on page 5. 3/13 EMIF10-1K010F1 TECHNICAL INFORMATION FREQUENCY BEHAVIOR The EMIF10-1K010F1 is firstly designed as an EMI / RFI filter. This low-pass filter is characterized by the following parameters: - Cut-off frequency - Insertion loss - High frequency Fig. A1: Frequency response curve S21 (dB) 0 -10 -20 Figure A1 gives these parameters, in particular the signal rejection at the GSM frequency: - 25dB @ 900Mhz - 14dB @ 1800Mhz -30 -40 -50 1 10 100 frequency (MHz) 1,000 Fig. A2: Measurements conditions TEST BOARD 50 in1 EMIF10 1K010F1 out1 50 Vg 4/13 EMIF10-1K010F1 ESD PROTECTION In addition with the filtering the EMIF10-1K010F1 is particularly optimized to perform ESD protection. ESD protection is based on the use of device which clamps at: Vcl = Vbr + Rd Ipp This protection function is splitted in 2 stages. As shown in Figure A3, the ESD strikes are clamped by the first stage S1 and then its remaining overvoltage is applied to the second stage through the resistor R. Such a configuration makes the output voltage very low at the Vout level. Fig. A3: ESD clamping behavior Rg S1 R=1k S2 Rd Rd Vg Vbr Vinput Voutput Vbr Rload Device to be protected ESD Surge EMIF10-1K010F1 To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical dynamic resistance value Rd. By taking into account these following hypothesis : R>>Rd, Rg>>Rd and Rload>>Rd, it gives these formulas: Rg Vbr + Rd Vg Rg R Vbr + Rd Vin Voutput = R Vinpout = The results of the calculation done for an IEC 1000-4-2 Level 4 Contact Discharge surge (Vg=8kV, Rg=330 ) and Vbr=7V (typ.) give: Vinput = 31.24V Voutput = 7.03V This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at the Vin side. This parasitic effect is not present at the Vout side due the low current involved after the series resistance R. 5/13 EMIF10-1K010F1 LATCH-UP PHENOMENA The early ageing and destruction of IC's is often due to latch-up phenomena which mainly induced by dV/dt. Thanks to its RC structure, the EMIF10-1K010F1 provides a high immunity to latch-up by integration of fast edges. (Please refer to the response of the EMIF10-1K010F1 to a 3 ns edge on Fig. A9) The measurements done here after show very clearly (Fig. A5a & A5b) the high efficiency of the ESD protection : - almost no influence of the parasitic inductances on Vout stage - Vout clamping voltage very close to Vbr for positive surge and close to ground for negative one Fig. A4: Measurement conditions TEST BOARD V(out1) EMIF10 1K010F1 ESD SURGE 16kV Air Discharge V(in1) Fig.A5: Remaining voltage at both stages S1 (Vin1) and S2 (Vout1) during ESD surge V(in1) V(in1) V(out1) V(out1) a: Positive Surge b:Negative Surge Please note that the EMIF10-1K010F1 is not only acting for positive ESD surges but also for negative ones. For negatives surges, it clamps close to ground voltage as shown in Fig. A5b. 6/13 EMIF10-1K010F1 Note: Dynamic resistance measurement Fig. A6: Rd measurement current wave I IPP t t 2 s 2.5 s 2.5s duration measurement wave As the value of the dynamic resistance remains stable for a surge duration lower than 20s, the 2.5s rectangular surge is well adapted. In addition both rise and fall times are optimized to avoid any parasitic phenomenon during the measurement of Rd CROSSTALK BEHAVIOR 1 - Crosstalk phenomena Fig. A7: Crosstalk phenomena RG1 Line 1 VG1 RG2 Line 2 RL1 a 1 VG1 + b12 VG2 VG2 RL2 a 2VG2 + b21VG1 DRIVERS RECEIVERS The crosstalk phenomena are due to the coupling between 2 lines. The coupling factor ( 12 or 21 ) increases when the gap across lines decreases, particularly in silicon dice. In the example above the expected signal on load RL2 is VG2, in fact the actual voltage at this point has got an extra value 21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few kW). The following chapters give the value of both digital and analog crosstalk. 7/13 EMIF10-1K010F1 2 - Digital Crosstalk Fig. A8: Digital crosstalk measurement +5V EMIF10 1K010F1 +5V 74HC04 in1 +5V VG1 74HC04 out2 b21VG1 Square Pulse Generator in2 out1 Figure A8 shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. Figure A9 shows that in such a condition signal from 0 to 5V and rise time of few ns, the impact on the disturbed line is less than 40mV peak to peak. No data disturbance was noted on the concerned line. The measurements performed with falling edges gives an impact within the same range. Fig. A9: Digital crosstalk results VG1 21VG1 8/13 EMIF10-1K010F1 3 - Analog Crosstalk Fig. A10: Analog crosstalk measurement TEST BOARD 50 in1 EMIF10 1K010F1 out2 50 Vg Fig. A11: Typical analog crosstalk results Analog crosstalk (dB) 0 -20 -40 -60 -80 -100 1 10 100 frequency (MHz) 1,000 Figure A10 gives the measurement circuit for the analog application. In Figure A11, the curve shows the effect of cell I1/O1 on cell I2/O2. In usual frequency range of analog signals (up to 100MHz) the effect on disturbed line is less than -47 dB. 9/13 EMIF10-1K010F1 4 - Spice model Fig. A12: Spice model of one EMIF01 cell Fig. A13: Diodes Spice parameters DZ Input 0.1nH 1kW 0.1nH Output BV Cjo IBV IKF 7 50p 1m 1000 10E-15 100p 1 0.3333 1 0.6 100n Dz Dz 0.3nH IS ISR N M RS GND Note: this model is available for an ambient temperature of 27C. VJ TT Fig. A14: Spice simulation: IEC 1000-4-2 Level 4 Contact Discharge response (V) 60 Vinput 50 Voutput 40 (V) 0 Vinput -10 -20 Voutput 30 20 10 0 0 20 40 60 80 100 -30 -40 -50 0 20 time (ns) 40 60 time (ns) 80 100 a: Positive surge b: Negative surge 10/13 EMIF10-1K010F1 Fig. A15: Comparison between PSpice simulation and measured frequency response. S21 (dB) 0 measure -10 -20 -30 -40 -50 1 10 100 frequency (MHz) 1,000 Spice 5 - Aplac model Fig. A16: Aplac model of one EMIF10 cell. Rs Ls 50pH 50m 50pH Ii O1 50m Ls Rs cap_line Port15 50 cap_line Port16 50 Rgnd Lgnd Rgnd Lgnd Rgnd Lgnd Rgnd Lgnd Ii Rseries Oi MODEL = demif10 MODEL = demif10 sub Fig. A17: Aplac model of bump connections. Fig. A18: Aplac model of ground connections. GND1 Rsub GND sub Lbump Rbump I/O Csubump Rsubump + Lhole + cap_hole Rhole 11/13 EMIF01-1K010F1 Fig. A19: Aplac model parameters. Fig. A20: Comparison between Aplac simulation and measured frequency response. EMIF10-1K010F1: Aplac model Aplac 7.60 User: STMicroelectronics Jan 25 2001 0.00 dB - 5.00 - 10.00 - 15.00 - 20.00 - 25.00 - 30.00 - 35.00 - 40.00 - 45.00 - 50.00 1.0M 3.0M 10.0M 30.0M f/Hz 100.0M 300.0M 1.0G aplacvar Cz 57pF aplacvar Rseries 960 aplacvar cap_line 0.8pF aplacvar Ls 0.6nH aplacvar Rbump 50m aplacvar Lbump 50pH aplacvar Rs 0.15 aplacvar Csubump 1.5pF aplacvar Rsubump 0.15 aplacvar Rsub 0.1 aplacvar lhole 1.2nH opt aplacvar Rhole 0.15 aplacvar cap_hole 0.15pF aplacvar Rgnd 0.25 aplacvar lgnd 0.4nH Demif10 diodes model BV=7 IBV=1m CJO=Cz M=0.3333 RS=1 VJ=0.6 TT=100n Aplac Measure ORDERING CODE EMIF 10 - 1K0 10 F 1 Pitch and bump version 1: pitch = 0.5 mm bump = 300 m EMI Filter Nb of lines Resistance value (Ohms) Flip-Chip Capacitance value / 10 (pF) 12/13 EMIF10-1K010F1 PACKAGE MECHANICAL DATA DIE SIZE 500 All dimensions in m 2570 s s s s s Die size: (2570 50) x (2570 50) Die height (including bumps): 650 65 Bump diameter: 315 50 Pitch: 500 50 Weight: 9.2mg 2570 MARKING 500 500 300 s s Bottom side (balls view): Pin A1 missing for die orientation Top side (balls underneath): see the marking on the left. diam 400 2570 FDT YWW 2570 330 100 s YWW: Date code PACKING: EMIF10-1K010F1 is delivered in Tape & Reel (7 inches reel); one Tape & Reel contains 5000 dice. Note: More packing information are available in the application note AN1235: ''Filp-Chip package description and recommandations for use'' Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All rights reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 13/13 650 |
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