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CXP88452/88460
CMOS 8-bit Single Chip Microcomputer
Description The CXP88452/88460 is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time-base timer, high precision timing pattern generation circuit, PWM output, VISS/VASS circuit, 32kHz timer/counter, remote control receiving circuit, VSYNC separator and the measurement circuit which measure signals of capstan FG and drum FG/PG and other servo systems, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. They are integrated into a single chip. Also, the CXP88452/88460 provides sleep/stop functions which enable to lower power consumption. 100 pin QFP (Plastic)
Structure Silicon gate CMOS IC Features * A wide instruction set (213 instructions) which covers various types of data -- 16-bit arithmetic/multiplication and division/boolean bit operation instructions * Minimum instruction cycle 250ns at 16MHz operation 122s at 32kHz operation * Incorporated ROM capacity 52K bytes (CXP88452) 60K bytes (CXP88460) * Incorporated RAM capacity 2048 bytes * Peripheral functions -- A/D converter 8 bits, 12 channels, successive approximation system (Conversion time of 20s/16MHz) -- Serial interface Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channnel Incorporated two-wire 8-bit and 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel -- Timer 8-bit timer/counter, 2 channels 19-bit time-base timer 32kHz timer/counter -- High precision timing pattern generation PPG: Maximum of 19 pins 32 stages programmable circuit RTG: 5 pins, 1 channel 7-bit, 10-satge FIFO (RECCTL control/ATC control), 1channel -- PWM/DA gate output PWM: 12 bits, 2 channels (Repetitive frequency 62.5kHz at 16MHz) DA gate pulse output: 13 bits, 2 channels -- Analog signal input circuit PBCTL amplifier circuit Reel FG comparator -- CTL write/rewrite circuit Recording current control circuit -- Servo input control Capstan FG, Drum FG/PG, CTL, Reel FG input -- VSYNC separator -- FRC capture unit Incorporated 26-bit and 8-stage FIFO -- PWM output 14 bits, 1 channel -- VISS/VASS circuit Pulse duty auto detection circuit -- Remote control receiving circuit 8-bit pulse measurement counter, 6-stage FIFO -- Tri-state output PPG output 2 pins -- High speed head switching circuit * Interruption 22 factors, 15 vectors, multi-interruption possible * Standby mode Sleep/stop * Package 100-pin plastic QFP * Piggy/evaluation chip CXP88400 100-pin ceramic PQFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E98772-PS
EXTAL XTAL TEX TX RST MP VDD Vss
Block Diagram
AVss INT0
2 8 PA0 to PA7 SPC700 CPU CORE
PORT B
AVDD
AVREF
CLOCK GENERATOR/ SYSTEM CONTROL 8
SCL0 SCL1 SDA0 SDA1 FIFO
PORT A
AN0 to AN11
12
NMI
A/D CONVERTER
INT1/NMI INT2
SERIAL INTERFACE UNIT (CH2)
PB0 to PB7
CS0 SI0 SO0 SCK0 2 FIFO ROM 52K/60K BYTES RAM 2048 BYTES
PORT C
SERIAL INTERFACE UNIT (CH0) RAM
8
PC0 to PC7
SI1
SCK1
EC
PORT D
SO1
INTERRUPT CONTROLLER
SERIAL INTERFACE UNIT (CH1)
8
PD0 to PD7
8-BIT TIMER/COUNTER 0
2 6 4
PORT F
PE0, 1, 6, 7
PORT E
TO/DDO
8-BIT TIMER1
PE2 to PE5 PF0 to PF3 4 PF4 to PF7
SYNC 2 2
V SYNC SEPARATOR
PRESCALER/ TIME-BASE TIMER
DRUM SERVO INPUT CONTROL 5 FIFO FRC CAPTURE UNIT
PORT G
RMC
REMOCON INPUT
FIFO 2
PORT H
VISS/VASS REALTIME PULSE GENERATOR RAM CH0 CH1 FIFO
PWM
14-BIT PWM GENERATOR
PWM0 2
PROGRAMABLE PATTERN GENERATOR
DAA0
12-BIT PWM GENERATOR CH0
PWM1 DAA1 4
12-BIT PWM GENERATOR CH1
19
5
ADJ CTLHEAD HEADL 5
CTL R/W CONTROL
RTO3 to RTO7
PORT I
PPO0 to PPO18
-2-
CAPSTAIN
4
PG0 to PG3
EXI0 EXI1 CFG DFG DPG CTLFAMPI RFG0 RFG1
PBCTL AMP REEL COMPARATOR
32kHz TIMER/COUNTER
4 4
PH0 to PH3 PH4 to PH7
8
PI0 to PI7
CXP88452/88460
CXP88452/88460
Pin Assignment (Top View)
PB6/PPO14 PB7/PPO15 PA0/PPO0 PA1/PPO1 PA2/PPO2 PA3/PPO3 PA4/PPO4 PA5/PPO5 PA6/PPO6 PA7/PPO7 PE0/SCK1 PE3/SYNC PE4/EXI0
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PE1/SO1
VDD
NC
VSS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO13 PB4/PPO12 PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0/INT0 PD7/SI0 PD6/SO0 PD5/SCK0 PD4/CS0 PD3/SRVO/TO/DDO/ADJ PD2/PWM PD1/RMC PD0/INT1/NMI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PE5/EXI1 PE6/PWM0/DAA0 PE7/PWM1/DAA1 RFG0 RFG1 ANOUT AMPVDD CTLFAMPO CTLSAMPI CTLAGND CTLFAMPI (-) CTLFAMPI (+) HEADL (-) HEADL (+) CTLHEAD (+) CTLHEAD (-) AMPVSS VDD AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF AVSS PF4/AN8
PH3/SDA1
PH4
TX
TEX
PG1/DFG
PG0/CFG
PH7
PH5
PE2/SI1
PH2/SDA0
PG2/DPG
PG3/EC/INT2
PH1/SCL1
Note) 1. NC (Pin 90) is always connected to VDD. 2. VDD (Pins 63 and 89) are both connected to VDD 3. Vss (Pins 41 and 88) are both connected to GND. 4. MP (Pin 39) is always connected to GND. -3-
PH0/SCL0
PF7/AN11
PF6/AN10
PF5/AN9
PH6
EXTAL
VSS
XTAL
RST
MP
CXP88452/88460
Pin Description Symbol I/O (Port A) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port B) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Data is gated with PPO or RTO contents by OR-gate and they are output. (8 pins) Description
PA0/PPO0 to PA7/PPO7
Output/ Real-time output
Head switching output. Programmable pattern generator (PPG) output. Functions as high precision realtime pulse output port. (19 pins) PB0 and PB2 can be tri-state controlled with PPG.
PB0/PPO8 to PB7/PPO15
Output/ Real-time output
PC0/PPO16 to PC2/PPO18 PC3/RTO3 to PC7/RTO7 PD0/INT1/ NMI PD1/RMC PD2/PWM PD3/TO DDO/ADJ SRVO PD4/CS0 PD5/SCK0 PD6/SO0 PD7/SI0 PE0/SCK1 PE1/SO1 PE2/SI1 PE3/SYNC PE4/EXI0 PE5/EXI1 PE6/PWM0/ DAA0 PE7/PWM1/ DAA1
I/O/ Real-time output
I/O/ Real-time output
Real-time pulse generator (RTG) output. Functions as high precision real-time pulse output port. PC3 can be tri-state controlled with RTG. (5 pins) Input pin to request external interruption and non-maskable interruption. Remote control receiving circuit input pin. 14-bit PWM output pin. Timer/counter, CTL duty detector, 32kHz oscillation adjustment and servo amplifier output pin. Serial chip select (CH0) input pin. Serial clock (CH0) I/O pin. Serial data (CH0) output pin. Serial data (CH0) input pin. Serial clock (CH1) I/O pin. Serial data (CH1) output pin.
I/O/Input/Input I/O/Input I/O/Output I/O/Output/Output/ (Port D) Output/Output 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) I/O/Input I/O/I/O I/O/Output I/O/Input Output/I/O Output/Output Input/Input Input/Input Input/Input Input/Input Output/Output Output/Output -4-
Serial data (CH1) input pin. (Port E) 8-bit port. Bits 2, 3, 4 and 5 Composite sync signal input pin. are for inputs; bits 0, 1, 6 and 7 are for outputs. External input pin for FRC capture unit. (8 pins) (2 pins) DA gate pulse output pin. (2 pins)
PWM output pin. (2 pins)
CXP88452/88460
Description AN0 to AN3 PF0/AN4 to PF3/AN7 PF4/AN8 to PF7/AN11 PG0/CFG PG1/DFG PG2/DPG PG3/EC/ INT2 PH0/SCL0 PH1/SCL1 PH2/SDA0 PH3/SDA1 I/O/I/O Input
I/O
Description
Input/Input
Output/Input
(Port F) Lower 4 bits are for inputs; upper 4 bits are for outputs. Lower 4 bits also serve as standby release input pins. (8 pins) Capstan FG input pin.
Analog input pin to A/D converter. (12 pins)
Input/Input (Port G) 4-bit input port. (4 pins) Input/Input/Input
Drum FG input pin. Drum PG input pin. Input pin to request External event input external interruption. pin for Active when falling timer/counter. edge.
PH4 to PH7
Output
(Port H) Serial clock (CH2) I/O pin. 8-bit I/O port. Upper four bits are for outputs. I/O can be set in a unit of Serial data (CH2) I/O pin. single bits for lower four bits. Lower four bits are N-ch open drain outputs and which can drive 12mA sink current. Upper four bits are for outputs; N-ch open drain output of medium drive voltage (12V) and large current (12mA). (8 pins) Input pin to request external interruption. (Port I) Active when falling edge. 8-bit I/O port. I/O can be set in a unit of single bits. Function as standby release input can be set in a unit of single bits. (8 pins) Input ports. (2 pins) Output port. (1 pin) Output port. (1 pin) Input port. (1 pin) Output port. (1 pin) Input ports. (2 pins) Output ports. (2 pins) I/O ports. (2 pins) Reel FG input pin. Internal waveform output pin analog circuit. PBCTL signal 1st amplifier output. PBCTL signal 2nd amplifier input. Smoothing capacitor connecting pin. Input PBCTL signal with capacitor coupled. During playback, connect to CTLHEAD (-) and CTLHEAD (+) with internal signal. During playback, input pin of PBCTL signal; during recording, output pin of PBCTL signal.
PI0/INT0
I/O/Input
PI1 to PI7 RFG0, RFG1 ANOUT CTLFAMPO CTLSAMPI CTLAGND CTLFAMPI (-) CTLFAMPI (+) HEADL (-) HEADL (+) CTLHEAD (-) CTLHEAD (+) AMPVSS AMPVDD
I/O Input Output Output Input Output Input Output I/O
Analog signal input circuit GND pin. Analog signal input circuit power supply pin. -5-
CXP88452/88460
Symbol EXTAL XTAL TEX TX RST NC MP AVDD AVREF AVSS VDD VSS Input Input Input Output Input Output Input
I/O
Description Connecting pin of crystal oscillator for system clock. When supplying the external clock, input it to EXTAL pin and input the opposite phase clock to XTAL pin. Connecting pin of crystal oscillator for 32kHz timer clock. When used as event counter, input to TEX pin and leave TX pin open. (In this time, feedback resistor is not removed.) System reset pin; active at low level. NC pin. Connect this pin to VDD for normal operation. Test mode input pin. Always connect to GND. Positive power supply pin of A/D converter. Reference voltage input pin of A/D converter. GND pin of A/D converter. Positive power supply pin. GND pin. Connect both Vss pins to GND.
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CXP88452/88460
Input/Output Circuit Formats for Pins Pin Port A PA0/PPO0 to PA7/PPO7 PB4/PPO12 to PB7/PPO15 12 pins Port B Port B
PPO data
Circuit format
After a reset
Ports A and B data
Hi-Z
Internal data bus RD (Port A or Port B) Output becomes active from high impedance by data writing to port data register.
PB0/PPO8 PB2/PPO10
PPO8, PPO10 data PB0, PB2 data
Hi-Z
Internal data bus RD (Port B)
2 pins
PPO9, PPO11 data Output becomes active from high impedance by data writing to port data register.
PPG control/status register bit 0 Tri-state control selection "0" after a reset
PB1/PPO9 PB3/PPO11
PPO9, PPO11 data PB1, PB3 data Internal data bus RD (Port B) Output becomes active from high impedance by data writing to port data register.
Hi-Z
2 pins
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CXP88452/88460
Pin Port C PC0/PPO16 to PC2/PPO18 PC5/RTO5 to PC7/RTO7
PPO, RTO data Port C data
Circuit format
After a reset
Port C direction "0" after a reset Internal data bus RD (Port C) Internal data bus IP
Input protection circuit
Hi-Z
6 pins
RD (Port C direction)
Port C
RTO3 data PC3 data
PC3 direction "0" after a reset
PC3/RTO3
IP Internal data bus RD (Port C) Internal data bus RD (Port C direction) RTO4 data
Hi-Z
1 pin
RTG interruption control register bit 7 Tri-state control selection "0" after a reset RTO4 data PC4 data
PC4/RTO4
PC4 direction "0" after a reset Internal data bus RD (Port C) Internal data bus IP
Hi-Z
1 pin
RD (Port C direction)
-8-
CXP88452/88460
Pin Port D
Port D data
Circuit format
After a reset
PD0/INT1/NMI PD1/RMC PD4/CS0 PD7/SI0
Port D direction "0" after a reset Internal data bus RD (Port D) Internal data bus RD (Port D direction) PD1: Remote control circuit PD0: Interruption circuit PD4, PD7: Serial CH0 Schmitt input IP
Hi-Z
4 pins
Port D
Port D function select "0" after a reset PD2: PD3: 14-bit PWM Timer/counter, CTL duty detection circuit, 32kHz timer, amplifier circuit
PD2/PWM PD3/SRVO/ TO/DDO/ ADJ
MPX
Port D data Port D direction "0" after a reset Internal data bus RD (Port D) Internal data bus IP
Hi-Z
2 pins Port D
RD (Port D direction)
Port D function select "0" after a reset SIO CH0 MPX
PD5/SCK0 PD6/SO0
Port D data Port D direction "0" after a reset Internal data bus RD (Port D) MPX Note) PD5 is schmitt input PD6 is inverter input IP
Hi-Z
2 pins
SIO CH0
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CXP88452/88460
Pin Port E
Port/SCK output select "1" after a reset
Circuit format
After a reset
PE0/SCK1
SIO CH1 MPX Port E data Hi-Z control Internal data bus SIO CH1 RD (Port E)
Hi-Z
IP
1 pin Port E
Port E function select "1" after a reset
PE1/SO1
SIO CH1 MPX Port E data
Hi-Z
Internal data bus
Hi-Z control RD (Port E)
1 pin Port E
Schmitt input
PE2/SI1 PE3/SYNC PE4/EXI0 PE5/EXI1
IP
PE2: SIO CH1 PE3 PE4 : Servo input PE5 Internal data bus RD (Port E)
Hi-Z
4 pins
Note) For PE3/SYNC, CMOS schmitt input or TTL schmitt input can be selected with the mask option.
Port E
Port/DA/PWM select
PE6/PWM0/ DAA0 PE7/PWM1/ DAA1
"1" after a reset DA gate output or PWM output
MPX
High level
Port E data
Internal data bus
2 pins
Hi-Z control RD (Port E)
- 10 -
CXP88452/88460
Pin AN0 to AN3 3 pins Port F
Circuit format
Input multiplexer IP A/D converter
After a reset
Hi-Z
Input multiplexer
PF0/AN4 to PF3/AN7
IP
A/D converter
Hi-Z
Internal data bus
4 pins Port F
RD (Port F)
PF4/AN8 to PF7/AN11
Port F data Internal data bus IP RD (Port F) Port/AD select
Hi-Z
4 pins Port G
"1" after a reset
Input multiplexer
A/D converter
Power ON/OFF control
PG0/CFG PG1/DFG PG2/DPG
Schmitt input IP Servo input Internal data bus RD (Port G)
Hi-Z
3 pins Port G
Schmitt input
Schmitt width selection
PG3/EC/INT2
IP Internal data bus
Hi-Z
RD (Port G)
1 pin
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CXP88452/88460
Pin Port H
SCL, SDA I2C output enable Port H data
Circuit format
After a reset
PH0/SCL0 PH1/SCL1 PH2/SDA0 PH3/SDA1
Internal data bus
Port H direction IP "0" after a reset Schmitt input RD (Port H) Internal data bus RD (Port H direction) SCL, SDA (Serial interface (CH2) circuit) Other serial interface (CH2) pin)
Hi-Z
4 pins Port H
Port H data Internal data bus RD (Port H)
PH4 to PH7
Hi-Z
12V drive voltage, large current 12mA
4 pins Port I
Pull-up resistor "0" after a reset PI0 data
PI0 direction "0" after a reset Internal data bus IP
PI0/INT0
Internal data bus
RD (Port I)
Hi-Z
RD (Port I direction) Internal data bus RD (pull-up resistor) Standby release Interruption circuit Edge detection
1 pin
Pull-up transistors approx. 100k
- 12 -
CXP88452/88460
Pin Port I
Pull-up resistor "0" after a reset Port I data
Circuit format
After a reset
Port I direction "0" after a reset Internal data bus IP
PI1 to PI7
RD (Port I) Internal data bus RD (Port I direction) Internal data bus RD (pull-up resistor) Standby release Edge detection
Hi-Z
7 pins
Pull-up transistors approx. 100k
CTLFAMPI (+) CTLFAMPI (-) CTLFAMPO
CTLAGND CTLFAMPI (+) IP
1/2AMPVDD
CTLFAMPO
IP CTLFAMPI (-)
3 pins
Input pin charge control
Input pin charge control
CTLSAMPI
IP LPF circuit CTLAGND
1/2AMPVDD
1 pin
- 13 -
CXP88452/88460
Pin
AMPVDD
Circuit format
After a reset
CTLAGND 1/2AMPVDD
IP
1 pin
AMPVSS
CTL AMP
AMPVDD
Write current select RTO6
Recording current control circuit
CTLHEAD (+)
IP RTO7 RTO3 AMPVSS HEADL (+) pin
Hi-Z
1 pin
RTG control permission
AMPVDD Write current select RTO7 Recording current control circuit
CTLHEAD (-)
IP RTO6 RTO3 AMPVSS HEADL (-) pin
Hi-Z
1 pin
RTG control permission
HEADL (+)
CTLHEAD (+) pin RTO3 RTG control permission
IP
Hi-Z
1 pin
AMPVSS
HEADL (-)
CTLHEAD (-) pin RTO3 RTG control permission
IP
Hi-Z
1 pin - 14 -
AMPVSS
CXP88452/88460
Pin
Circuit format
After a reset
RFG0 RFG1
IP
Comparator Servo output
Hi-Z
2 pins
EXTAL XTAL
EXTAL
IP
* Shows the circuit composition during oscillation. * Feedback resistor is removed and XTAL outputs High level during stop.
Oscillation
2 pins
XTAL
TEX TX
32kHz timer/counter TEX IP
* Shows the circuit composition during oscillation. * Feedback resistor is removed during 32kHz oscillation circuit stop by software. At that time, TEX pin outputs Low level and TX pin outputs High level.
Oscillation
2 pins
TX
RST
Mask option OP
Pull-up resistor Schmitt input IP
Low level (during a reset)
1 pin
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CXP88452/88460
Absolute Maximum Ratings Item Symbol VDD AVDD Supply voltage AVSS Rating -0.3 to +7.0 AVss to +7.01 -0.3 to +0.3 Unit V V V V V V V V mA mA mA mA mA C C mW
(Vss = 0V reference) Remarks
AMPVDD AMPVSS to +7.02 AMPVSS Input voltage Output voltage Medium drive output voltage High level output current High level total output current VIN VOUT VOUTP IOH IOH IOL Low level output current IOLC Low level total output current Operating temperature Storage temperature Allowable power dissipation 1 2 3 4 IOL Topr Tstg PD 20 130 -20 to +75 -55 to +150 600 -0.3 to +0.3 -0.3 to +7.03 -0.3 to +7.03 -0.3 to +15.0 -5 -50 15
Port H (PH7 to PH4) pin
Total of output pins Other than large current output ports (value per pin) Large current output port4 (value per pin) Total of output pins
QFP package type
AVDD should not exceed VDD + 0.3V. AMPVDD should not exceed VDD + 0.3V. VIN and VOUT should not exceed VDD + 0.3V. The large current output port is port H (PH7 to PH4). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI.
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CXP88452/88460
Recommended Operating Conditions Item Symbol Min. 4.5 3.5 2.7 2.5 Analog supply voltage AVDD AMPVDD VIH High level input voltage VIHS VIHTS VIHEX VIL VILS Low level input voltage VILTS VILEX Operating temperature 1 2 3 4 Topr 4.5 4.5 0.7VDD 0.8VDD 2.2 Max. 5.5 5.5 5.5 5.5 5.5 5.5 VDD VDD VDD V V V V V V V V V V C Unit
(Vss = 0V reference) Remarks Guaranteed operation range for 1/2 and 1/4 frequency dividing clock V Guaranteed operation range for 1/16 frequency dividing clock or during sleep mode Guaranteed operation range by TEX clock Guaranteed data hold operation range during stop 1 2 3 CMOS schmitt input4 TTL schmitt input5 EXTAL pin6 TEX pin7 3 CMOS schmitt input4 TTL schmitt input5 EXTAL pin6 TEX pin7
Supply voltage
VDD
VDD - 0.4 VDD + 0.3 0 0 0 -0.3 -20 0.3VDD 0.2VDD 0.8 0.4 +75
AVDD and VDD should be set to the same voltage. AMPVDD and VDD should be set to the same voltage. Normal input port (each pin of PC, PD2, PD3, PD6, PF0 to PF3, PI1 to PI7 and PH0 to PH3), MP pin Each pin of RST, PD0/INT1/NMI, PD1/RMC, PD4/CS0, PD5/SCK0, PD7/SI0, PE0/SCK1, PE2/SI1, PE3/SYNC, PE4/EXI0, PE5/EXI1, PI0/INT0, PG3/EC/INT2 (For PE3/SYNC, when CMOS schmitt input is selected with mask option.) 5 PE3/SYNC (when TTL schmitt input is selected with mask option.) 6 Specifies only during external clock input. 7 Specifies only during external event input.
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CXP88452/88460
Electrical Characteristics DC Characteristics (VDD = 4.5 to 5.5V) Item High level output voltage Low level output voltage Symbol VOH Pins PA to PD, PE0 to PE1, PE6 to PE7, PF4 to PF7, PH (VOL only) PI PH IIHE IILE Input current IIHT IILT IILR I/O leakage current Open drain output leakage current (N-CH Tr off state) RST1 TEX EXTAL Conditions VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V 0.5 -0.5 0.1 -0.1 -1.5 (Ta = -20 to +75C, Vss = 0V reference) Min. 4.0 3.5 0.4 0.6 1.5 40 -40 10 -10 -400 Typ. Max. Unit V V V V V A A A A A
VOL
IIZ
PA to PF, PG3, PI, MP, VDD = 5.5V, AN0 to AN3, VI = 0, 5.5V RST1 PH4 to PH7 PH0 to PH3 VDD = 5.5V, VOH = 12V VDD = 5.5V, VOH = 5.5V 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 5.5V3 Sleep mode VDD = 5.5V 2.1 37
10
A
ILOH
50 10 50
A A mA
IDD1
IDDS1
8
mA
Supply current2
IDD2
32kHz crystal oscillation (C1 = C2 = 47pF) VDD, VSS VDD = 3.3V Sleep mode VDD = 3V 0.3V 9 35 A 58 100 A
IDDS2
IDDS3
Stop mode (EXTAL and TEX pins oscillation stop) VDD = 5V 0.5V
10
A
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CXP88452/88460
Item
Symbol
Pins
Conditions
Min.
Typ.
Max. Unit
Input capacity
CIN
PC, PD, PE0, PE2 to PE5, PF, PG, PI, CTLHEAD (+), CTLHEAD (-), Clock 1MHz CTLFAMPI (+), 0V other than the measured pins CTLFAMPI (-), CTLSAMPI, RFG, XTAL, TEX
10
20
pF
1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when no resistor is selected. 2 When entire output pins are left open. 3 When setting upper 2 bits (CPU clock selection) of clock control register (CLC: 00FEh) to "00" and operating in high speed mode (1/2 frequency dividing clock).
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CXP88452/88460
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise and fall times Event count clock input pulse width Event count clock input rise and fall times System clock frequency Event count clock input pulse width Event count clock input rise and fall times 1 Symbol fC Pins
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3 10 20 Min. 1 28 200 Typ. Max. 16 Unit MHz ns ns ns 20 ms
XTAL EXTAL XTAL EXTAL XTAL EXTAL EC EC TEX TX TEX TEX
tXL, tXH tCR, tCF tEH, tEL tER, tEF
fC
tsys + 2001
32.768
kHz
tTL, tTH tTR, tTF
s ms
tsys indicates three values according to the contents of the clock control register (CLC; 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
1/fc
VDD - 0.4V EXTAL XTAL 0.4V tXH tCF tXL tCR
Fig. 1. Clock timing
Crystal oscillation Ceramic oscillation External clock 32kHz clock applied condition Crystal oscillation
EXTAL C1
XTAL C2
EXTAL
XTAL C1
TEX
TX C2
74HC04
Fig. 2. Clock applied condition
0.8VDD 0.2VDD
TEX EC
tEH tTH
tEF tTF
tEL tTL
tER tTR
Fig. 3. Event count clock timing - 20 -
CXP88452/88460
(2) Serial transfer (CH0) Item CS0 SCK0 delay time CS0 SCK0 floating delay time CS0 SO0 delay time CS0 SO0 floating delay time CS0 high level width SCK0 cycle time SCK0 high and low level widths SI0 input set-up time (against SCK0 ) SI0 input hold time (against SCK0 ) SCK0 SO0 delay time Note 1) Symbol Pins SCK0
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode SCK0 Output mode Input mode SCK0 Output mode SCK0 input mode SI0 SCK0 output mode SCK0 input mode SI0 SCK0 output mode SCK0 input mode SO0 SCK0 output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 100 100 ns ns
tDCSK
tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200
2tsys + 200 16000/fc
tDCSKF SCK0 tDCSO
SO0
tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO
tsys + 100
8000/fc - 100 -tsys + 100 200 2tsys + 100 100
tsys indicates three values according to the contents of the clock control register (CLC; 00FEh) upper
2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.
- 21 -
CXP88452/88460
tWHCS
0.8VDD CS0 0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 0.2VDD
0.8VDD
tSIK
tKSI
0.8VDD SI0 Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 Output data 0.2VDD
Fig. 4. Serial transfer timing (CH0)
- 22 -
CXP88452/88460
Serial transfer (CH1) (SIO mode) Item SCK1 cycle time SCK1 high and low level widths SI1 input setup time (for SCK1 ) SI1 input hold time (for SCK1 ) SCK1 SO1 delay time Note 1) Symbol Pins SCK1
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Input mode Output mode Input mode SCK1 Output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SO1 SCK1 output mode Min. 2tsys + 200 16000/fc Max. Unit ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
tsys +100
8000/fc - 50 100 200
tsys + 200
100
tsys + 200
100
ns ns
tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper
2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.
tKCY tKL tKH
SCK1 0.8VDD 0.2VDD
tSIK
tKSI
0.8VDD SI1 Input data 0.2VDD
tKSO
0.8VDD SO1 0.2VDD Output data
Fig. 5. Serial transfer CH1 timing (SIO mode) - 23 -
CXP88452/88460
Serial transfer (CH1) (Special mode) (Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item SO1 cycle time SI1 data setup time SI1 data hold time 1 Symbol Pins SO1 SI1 SI1 SI1 1 2 2 Conditions Min. Typ. 104 Max. Unit s s s
tLCY tLSU tLHD
tLCY is specified only when serial mode register (CH1) (SIOM1: 05F2h) lower 2 bits (SO1 clock selection)
are set at 104s. Note) The load of SO1 pin is 50pF + 1TTL.
tLCY
tLCY
SO1
Start bit
Output data bit
0.5VDD
tLCY/2 tLSU tLHD 0.8VDD 0.2VDD
SI1
Input data bit
Fig. 6. Serial transfer CH1 timing (Special mode)
- 24 -
CXP88452/88460
Serial transfer (CH2) Item SCL clock frequency Bus-free time before starting transfer Hold time for starting transfer Clock low level width Clock high level width Setup time for repeated transfers Data hold time Data set-up time SDA, SCL rise time SDA, SCL fall time Setup time for transfer completion
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol fSLC Pins SCL SDA, SCL SDA, SCL SCL SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL 1.6 2.6 1.0 1.0 1.0 1.0 01 100 300 300 Conditions Min. Max. 400 Unit kHz s s s s s s ns ns ns s
tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO
1 The SCL fall time (300ns Max.) is not included in the data hold time.
SDA tBUF tR tF tHD; STA
SCL tHD; STA tSU; STA P S tLOW tHD; DAT tHIGH tSU; DAT St tSU; STO P
Fig. 7. Serial transfer timing (CH2)
Device
Device
RS SDA0 (or SDA1) SCL0 (or SCL1)
RS RS
RS RP
RP
Fig. 8. Device recommended circuit
* A pull-up resistor (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1). * The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300 or less) can be used to reduce the spike noise caused by CRT flashover.
- 25 -
CXP88452/88460
(4) A/D converter characteristics (Ta = -20 to +75C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference) Item Resolution Linearity error Absolute error Conversion time Sampling time Ta = 25C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V Symbol Pins Conditions Min. Typ. Max. 8 1 2 160/fADC1 12/fADC1 AVREF AN0 to AN7 Operating mode AVREF current IREF AVREF Sleep mode Stop mode 32kHz operating mode AVDD - 0.5 0 0.6 AVDD AVREF 1.0 10 Unit Bits LSB LSB s s V V mA A
tCONV tSAMP
VIAN
Reference input voltage VREF Analog input voltage
FFh FEh
Digital conversion value
1 fADC indicates the below values due to the peripheral clock control register (PCC: 05F8h) bit 3 and clock control register (CLC: 00FEh) upper 2 bits. ADCCK
Linearity error
0 (/2 selection) 1 ( selection) fADC = fc/2 fADC = fc/4 fADC = fc/16 fADC = fc fADC = fc/2 fADC = fc/8
PCK1, PCK0 00 ( = fEX/2) 01 ( = fEX/4)
01h 00h VZT Analog input VFT
11 ( = fEX/16)
Fig. 9. Definitions of A/D converter terms
- 26 -
CXP88452/88460
(4) Interruption, reset input Item
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pins INT0 INT1 INT2 NMI PI0 to PI7 RST
tIH
Conditions
Min.
Max.
Unit
External interruption high and low level widths
tIH tIL tRSL
1
s
Reset input low level width
32/fc
tIL
s
INT0 INT1 INT2 NMI PI0 to PI7 (During standby release input) (Falling edge)
0.8VDD 0.2VDD
Fig. 10. Interruption input timing
tRSL
RST 0.2VDD
Fig. 11. Reset input timing
(5) Others Item CFG input high and low level widths Symbol Pins CFG DFG DPG DPG EXI0 EXI1
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Min. 24tFRC + 200 16tFRC + 200 8tFRC + 200 16tFRC + 200 Max. Unit ns ns ns ns ns
tCFH tCFL DFG input tDFH high and low level widths tDFL DPG minimum pulse width tDPW
DPG minimum removal time EXI input high and low level widths Note 1) Note 2)
trem tEIH tEIL
tsys = 2000/fc
8tFRC + 200 + tsys
tFRC = 1000/fc [ns] tsys indicates three values according to the contents of the clock control register (CLC: 00FEh)
upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
- 27 -
CXP88452/88460
tCFH
tCFL
0.8VDD CFG 0.2VDD
tDFH
tDFL
0.8VDD DFG 0.2VDD
tDPW trem
trem
0.8VDD DPG
tEIH
tEIL
EXI0 EXI1
0.8VDD 0.2VDD
Fig. 12. Other timings
- 28 -
CXP88452/88460
Analog Circuit Characteristics (1) Amplifier circuit reference voltage characteristics (AMPVDD = VDD = 5.0V, AMPVSS = Vss = 0V, Ta = -20 to +75C) Item Symbol Pins CTLAGND Conditions Min. 2.20 Typ. 2.45 Max. 2.75 Unit V
Reference level VOR output voltage
(2) CTL 1st amplifier characteristics Item Symbol Pins
(AMPVDD = VDD = 5.0V, AMPVSS = Vss = 0V, Ta = -20 to +75C) Conditions CTLFAMPI (-) = 0V, Gain = 16dB CTLFAMPI (-) = 0V, Gain = 34dB CTLFAMPI (-) = 0V, Gain = 49dB CTLFAMPI (-) = 0V, Gain = 55dB Min. 13.5 31.8 46.5 52.5 Typ. 15.5 33.8 48.5 54.5 Max. 17.5 35.8 dB 50.5 56.5 Unit
Voltage gain1
AVCTL1
CTLFAMPI (-) CTLFAMPI (+)
Output offset voltage
VOSCTL1
CTLFAMPI (-) CTLFAMPI (+)
CTLFAMPI (-), CTLFAMPI (+) = open, Gain = 16dB
-25
0
+25
mV
1 The result after monitoring CTLFAMPO pin when the electrolytic capacitor (10F) is connected to CTLFAMP (-) and CTLFAMP (+). (3) CTL 2nd amplifier characteristics Item Symbol Pins (AMPVDD = VDD = 5.0V, AMPVSS = Vss = 0V, Ta = -20 to +75C) Conditions Gain = 5dB Gain = 8dB Voltage gain1 Gain = 11dB AVCTL2 CTLSAMPI Gain = 14dB Gain = 17dB Gain = 20dB Output offset voltage LPF cut-off frequency VOSCTL2 FCCTL CTLSAMPI CTLSAMPI CTLSAMPI = open, Gain = 5dB 12kHz, fDC - 3dB 20kHz, fDC - 3dB Min. 3.5 6.2 9.0 12.0 15.0 18.0 -30 8 12 Typ. 5.5 8.2 11.0 14.0 17.0 20.0 0 12 20 Max. 7.5 10.2 13.0 16.0 19.0 22.0 +30 24 42 mV kHz dB Unit
- 29 -
CXP88452/88460
Item
Symbol
Pins
Conditions Comparator level = +100mV0-p Comparator level = +150mV0-p Comparator level = +200mV0-p Comparator level = +250mV0-p Comparator level = +300mV0-p Comparator level = +400mV0-p Comparator level = +500mV0-p Comparator level = +600mV0-p
Min. 80 110 160 210 250 340 420 530 850 -90 -110 -150 -200 -240 -340 -430 -540 -870
Typ. 110 150 200 250 290 380 470 570 920 -120 -130 -190 -240 -280 -380 -480 -580
Max. 140 190 240 290 330 420 520 610 990 -150 -190 -230 -280 -320 -420 -530 -620
Unit
Comparator level2
Comparator level = +1000mV0-p VCCTL CTLSAMPI Comparator level = -100mV0-p Comparator level = -150mV0-p Comparator level = -200mV0-p Comparator level = -250mV0-p Comparator level = -300mV0-p Comparator level = -400mV0-p Comparator level = -500mV0-p Comparator level = -600mV0-p Comparator level = -1000mV0-p
mV
-970 -1070
1 The result after monitoring ANOUT pin when the electrolytic capacitor (10F) is connected to CTLSAMPI. 2 The reference value of the comparator level is CTLAGND.
(4) CTL amplifier characteristics (CTL1stAMP + CTL2ndAMP) (AMPVDD = VDD = 5.0V, AMPVSS = Vss = 0V, Ta = -20 to +75C) Item Voltage gain3 Symbol Pins CTLHEAD (-) CTLHEAD (+) Conditions CTLHEAD (-) = 0V, Gain = (16dB + 5dB) CTLHEAD (-) = 0V, Gain = (55dB + 20dB) CTLHEAD (-) = 0V, Gain = (55dB + 20dB) Comparator = 150mV0-p Min. 17.0 70.5 Typ. 20.5 74.5 Max. 23.5 dB 77.0 Unit
AVCTL
Input sensitivity
VSCTL
CTLHEAD (-) CTLHEAD (+)
60
70
140
Vp-p
3 The result when waveform is input from CTLHEAD (+) pin and ANOUT pin is monitored after performing coupling electrolytic capacitor (10F) of CTLHEAD (-) and CTLHEAD (+), and coupling electrolytic capacitor (10F) of HEADL (-) and HEADL (+), CTLFAMPI (-) and CTLFAMPI (+) , and CTLFAMPO and CTLSAMPI. Gain is maximum -1.5dB lowered when waveform is input from CTLHEAD (+) pin.
- 30 -
CXP88452/88460
(5) RECCTL write circuit characteristics Item Symbol Pins
(AMPVDD = VDD = 5.0V, AMPVSS = Vss = 0V, Ta = -20 to +75C) Conditions Write current 2.0mAp-p Write current 3.0mAp-p Write current 4.0mAp-p Write current 5.0mAp-p Min. 0.8 1.4 2.0 2.4 3.0 3.5 4.5 5.0 5.5 Typ. 1.8 2.8 3.8 4.8 6.0 6.8 7.8 8.8 7.7 Max. 3.6 5.0 7.0 8.5 10.0 11.5 13.0 15.0 17.0 mA Unit
Write current1
IOREC
CTLHEAD (-) CTLHEAD (+)
Write current 6.0mAp-p Write current 7.0mAp-p Write current 8.0mAp-p Write current 9.0mAp-p Write current 10.0mAp-p
1 The current which flows when CTLHEAD (-) and CTLHEAD (+) shorts. (6) Auto threshold control circuit (ATC) characteristics (AMPVDD = VDD = 5.0V, AMPVSS = Vss = 0V, Ta = -20 to +75C) Item ATC peak hold circuit initialize voltage value2 Symbol VATCINIT Pins Conditions Voltage = -150mV0-P Voltage = -400mV0-P Gain = 1/6 (16.7%) Gain = 1/5 (20%) Gain = 1/4 (25%) ATC comparator level offset voltage3 VATCOFF Gain = 1/3 (33.3%) Gain = 2/5 (40%) Gain = 1/2 (50%) Gain = 3/5 (60%) Min. -110 -350 Typ. -150 -400 -70 -90 -90 -70 -90 -70 -90 Max. -190 -450 -160 -210 -210 -160 -210 -160 -210 mV mV Unit
2 Reference is CTLAGND. 3 Reference is CTLAGND. When comparator level is generated using ATC, actual comparator level is as follows by the offset voltage inside of ATC. Vin x gain + |offset voltage| Example: Gain = 1/2 Vin x 1/2 + 160 (7) Schmitt characteristics Item RTG schmitt width Symbol SRFG SCFG SDFG SDPG Pins RFG0, RFG1 CFG, DFG, DPG (AMPVDD = VDD = 5.0V, AMPVSS = Vss = 0V, Ta = -20 to +75C) Conditions Schmitt width 1Vp-p Schmitt width 410mVp-p Schmitt width 1Vp-p - 31 - Min. 820 180 700 Typ. 920 300 900 Max. 1020 420 1100 Unit mV
CFG/DFG/DPG
mV
CXP88452/88460
Appendix
(i) (ii)
EXTAL
XTAL Rd
TEX
TX Rd
C1
C2
C1
C2
Fig. 13. Recommended oscillation circuit
Manufacturer
Model
fc (MHz) 8.00
C1 (pF) 10
C2 (pF) 10
Rd ()
Circuit example
RIVER ELETEC CO., LTD.
HC-49/U03
10.00 12.00 16.00 8.00 16 (12) 16 (12) 12 12 30 16 (12) 16 (12) 12 12 18 5 5
0
(i)
KINSEKI LTD.
HC-49/U (-S)
10.00 12.00 16.00
0
(i)
P3
32.768kHz
470k
(ii)
Mask option table Item Reset pin pull-up resistor Input circuit format1 Content Non-existent CMOS schmitt Existent TTL schmitt
1 The input circuit format can be selected for PE3/SYNC pin.
- 32 -
CXP88452/88460
Characteristics Curve
IDD vs. VDD
(fc = 16MHz, Ta = 25C, W09) 100 1/2 dividing mode 1/4 dividing mode 10 1/16 dividing mode Sleep mode 1 40 1/2 dividing mode
IDD vs. fc
(VDD = 5.0V, Ta = 25C, W09)
IDD - Supply current [mA]
IDD - Supply current [mA]
30
20
1/4 dividing mode
32kHz mode
0.1 (100A) 32kHz Sleep mode 0.01 (10A)
10 1/16 dividing mode Sleep mode 0 0 2 3 4 5 6 VDD - Supply voltage [V] 0 5 10 15 fc - System clock [MHz]
- 33 -
CXP88452/88460
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1 80 51 + 0.1 0.15 - 0.05
81
50
+ 0.4 14.0 - 0.1 17.9 0.4
15.8 0.4
A 100 31
1
0.65
+ 0.15 0.3 - 0.1
30 0.13 M + 0.35 2.75 - 0.15
+ 0.2 0.1 - 0.05
0.15
DETAIL A
0.8 0.2
0 to 10
(16.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.7g
- 34 -

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