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NIMD6302R2 HDPlus Dual N-Channel Self-protected Field Effect Transistors with 1:200 Current Mirror FET
HDPlus devices are an advanced HDTMOSTM series of power MOSFET which utilize ON's latest MOSFET technology process to achieve the lowest possible on-resistance per silicon area while incorporating smart features. They are capable of withstanding high energy in the avalanche and commutation modes. The avalanche energy is specified to eliminate guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. This HDPlus device features an integrated Gate-to-Source clamp for ESD protection. Also, this device features a mirror FET for current monitoring. * 3.5% Current Mirror Accuracy in Linear Region * 15% Current Mirror Accuracy in Low Current Saturation Region * IDSS Specified at Elevated Temperature * Avalanche Energy Specified * Current Sense FET * ESD Protected on the Main and the Mirror FET
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in this specification is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
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5.0 AMPERES 30 VOLTS RDS(on) = 50 mW
ISOLATED DUAL PACKAGING
Drain1 Drain2
Gate1
Mirror
Main FET
Gate2
Mirror
Main FET
Mirror1
Source1
Mirror2
Source2
SOIC-8 CASE 751 STYLE 19
MAIN MOSFET MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 MW) Gate-to-Source Voltage Drain Current - Continuous @ TA = 25C - Continuous @ TA = 100C (Note 3) - Pulsed (tpv10 ms) Total Power Dissipation @ TA = 25C (Note 1) Total Power Dissipation @ TA = 25C (Note 2) Thermal Resistance Junction-to-Ambient (Note 1) Junction-to-Ambient (Note 2) Single Pulse Drain-to-Source Avalanche Energy (Note 3) (VDD = 25 Vdc, VGS = 10 Vdc, VDS = 20 Vdc, IL = 15 Apk, L = 10 mH, RG = 25 W) Symbol VDSS VDGR VGS ID ID IDM PD PD RqJA RqJA EAS Value 30 30 "16 6.5 4.4 33 1.3 1.67 96 75 250 mJ Unit Vdc Vdc Vdc Adc Adc Apk W C/W
MARKING DIAGRAM
Source 1 Gate 1 Source 2 Gate 2 1 2 3 4 (Top View) N6302 A Y WW = Specific Device Code = Assembly Location = Year = Work Week N6302 AYWW 8 7 6 5 Mirror 1 Drain 1 Mirror 2 Drain 2
ORDERING INFORMATION
Device NIMD6302R2 Package SOIC-8 Shipping 2500/Tape & Reel
1. Mounted onto min pad board. 2. Mounted onto 1 pad board. 3. Switching characteristics are independent of operating junction temperatures.
(c) Semiconductor Components Industries, LLC, 2002
1
October, 2002 - Rev. 3
Publication Order Number: NIMD6302R2/D
NIMD6302R2
MAIN MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125C) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 175C) Gate-Body Leakage Current (VGS = 12 Vdc, VDS = 0 Vdc) (VGS = 3.0 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) (VDS = VGS, ID = 250 mAdc, TJ = 75C) Threshold Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (Note 4) (VGS = 10 Vdc, ID = 3.0 Adc, TJ @ 25C) (VGS = 10 Vdc, ID = 3.0 Adc, TJ @ 125C) (VGS = 10 Vdc, ID = 3.0 Adc, TJ @ 175C) Static Drain-to-Source On-Resistance (Note 4) (VGS = 4.5 Vdc, ID = 3.0 Adc, TJ @ 25C) (VGS = 4.5 Vdc, ID = 3.0 Adc, TJ @ 125C) (VGS = 4.5 Vdc, ID = 3.0 Adc, TJ @ 175C) Forward Transconductance (Note 4) (VDS = 6.0 Vdc, ID = 15 Adc) DYNAMIC CHARACTERISTICS (Note 5) Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 6.0 Vdc, ID = 2.0 Adc, VGS = 4.5 Vdc) (VDD = 6.0 Vdc, ID = 2.0 Adc, VGS = 10 Vdc, RG = 2.5 W) (VDD = 6.0 Vdc, ID = 2.0 Adc, VGS = 4.5 Vdc, RG = 2.5 W) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 Gate Charge (VDS = 6.0 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) QT Q1 Q2 Q3 4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. 5. Switching characteristics are independent of operating junction temperatures. - - - - - - - - - - - - - - - - 9.2 56.5 35.9 36.3 6.3 2.7 66.5 36.5 3.91 1.0 1.59 1.48 8.03 1.06 1.75 1.54 9.6 75.3 40 40.6 7.0 3.1 70.5 39.4 4.5 1.25 1.95 1.64 13.6 1.36 2.82 1.75 nC nC ns ns (VDS = 6.0 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss - - - 301 265 82 600 350 200 pF VGS(th) 1.0 1.1 - RDS(on) - - - RDS(on) - - - gFS 14.5 52 81 97 19.8 60 90 110 25 35 57 69 50 65 90 1.33 1.17 3.8 2.0 - 4.6 Vdc mV/C mW V(BR)DSS 30 20 IDSS - - - IGSS - - 11 12 18 100 0.065 0.2 11 10 100 100 35 23 - 30 Vdc mV/C mAdc Symbol Min Typ Max Unit
mAdc nAdc
mW
Mhos
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MAIN MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) (Continued)
Characteristic SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Notes 6 & 7) (IS = 3.0 Adc, VGS = 0 Vdc) (IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125C) 3 0 Adc Vdc (IS = 3.0 Adc, VGS = 0 Vdc, TJ = 175C) VSD - - - - - - - 0.79 0.65 0 65 0.58 30.8 14.6 15.2 0.020 0.86 0.72 0 72 0.64 41 18 20.2 0.03 mC Vdc Symbol Min Typ Max Unit
Reverse Recovery Time (Note 7) (IS = 3.0 Adc, VGS = 0 Vdc, 3 0 Adc Vdc dIS/dt = 100 A/ms) Reverse Recovery Stored Charge (Note 7) MIRROR MOSFET CHARACTERISTICS (TJ = 25C unless otherwise noted) Main/Mirror MOSFET Current Ratio Operating in the Saturation Region Main/Mirror Current Ratio Variation versus Temperature Operating in the Saturation Region Main/Mirror MOSFET Current Ratio Operating in the Linear Region Main/Mirror Current Ratio Variation versus Temperature Operating in the Linear Region Main/Mirror MOSFET Current Ratio Operating in the Linear Region Main/Mirror Current Ratio Variation versus Temperature Operating in the Linear Region Main/Mirror MOSFET Current Ratio Operating in the Linear Region Main/Mirror Current Ratio Variation versus Temperature Operating in the Linear Region (VDS = 6.0 Vdc, IDmain = 5.0 mA) (VDS = 6.0 Vdc, IDmain = 5.0 mA, TA = 125C) (VDS = 6.0 Vdc, IDmain = 5.0 mA, TA = 25 to 125C) (VGS = 3.0 Vdc, IDmain = 1.0 A) (VGS = 3.0 Vdc, IDmain = 1.0 A, TA = 175C) (VGS = 3.0 Vdc, IDmain = 1.0 A, TA = -40 to +175C) (VGS = 5.0 Vdc, IDmain = 1.0 A) (VGS = 5.0 Vdc, IDmain = 1.0 A, TA = 175C) (VGS = 5.0 Vdc, IDmain = 1.0 A, TA = -40 to +175C) (VGS = 10 Vdc, IDmain = 1.0 A) (VGS = 10 Vdc, IDmain = 1.0 A, TA = 175C) (VGS = 10 Vdc, IDmain = 1.0 A, TA = -40 to +175C)
trr ta tb QRR
ns
IRAT
170 167 170
200 196 200
230 225 230
-
IDRAT
-
IRAT
166 165 166
172 171 172
178 177 184
-
IDRAT
-
IRAT
150 155 150
155 161 155
160 166 166
-
IDRAT
-
IRAT
141 148 141
146 153 146
155 157 157
-
IDRAT
-
MAIN AND SENSE MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted) Electro-Static Discharge (ESD) Capability Charge Device Model (CDM) Capability Main FET Sense FET Main/Sense FET
- - -
1800 1800 2000
- - -
- - -
V V
6. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperatures.
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TYPICAL ELECTRICAL CHARACTERISTICS
7 VGS = 10 V ID, DRAIN CURRENT (AMPS) 6 5 4 3 2 1 0 2V 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1 9V 8V 7V 6V 7 TJ = 25C ID, DRAIN CURRENT (AMPS) 6 5 4 3 2 TJ = 100C 1 TJ = -55C 0 1 2 3 4 5 6 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 7 TJ = 25C
4V 5V
VDS 10 V
3V
Figure 1. On-Region Characteristics
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W)
Figure 2. Transfer Characteristics
0.07 VGS = 10 V
0.07 TJ = 25C 0.06 0.05 0.04 VGS = 10 V 0.03 0.02 0.01 0 1 2 3 4 5 6 7 VGS = 4.5 V
0.06 0.05 0.04 TJ = 25C 0.03 0.02 0.01 0 1 2 3 4 5 6 TJ = -55C TJ = 100C
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On-Resistance versus Drain Current and Temperature
RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
Figure 4. On-Resistance versus Drain Current and Gate Voltage
1.5 VGS = 10 V ID = 3 A
1000 VGS = 0 V
IDSS, LEAKAGE (nA)
1.25
100
TJ = 125C
1
TJ = 100C 10
0.75
0.5 -50
-25
0
25
50
75
100
0
0
5
10
15
20
25
30
TJ, JUNCTION TEMPERATURE (C)
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-To-Source Leakage Current versus Voltage
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POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP)
800 VGS = 0 V Ciss C, CAPACITANCE (pF) 600 VDS = 0 V
The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
TJ = 25C
400
Crss Ciss
200 Coss 0 -10 Crss -5 VGS 0 VDS 5 10 15 20 25
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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NIMD6302R2
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 12 QT VDS 35 30 25 VGS 6 4 Q1 2 0 Q2 ID = 3 A TJ = 25C 0 1 2 3 4 5 20 15 10 5 0 6 1000 VDD = 30 V ID = 5 A VGS = 10 V 100 t, TIME (ns) tf td(off) tr 10 td(on)
10 8
1 1 10 RG, GATE RESISTANCE (W) 100
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 14. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.
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NIMD6302R2
3.5 IS, SOURCE CURRENT (AMPS) 3 2.5 2 1.5 1 0.5 0 4.00E-01 VGS = 0 V TJ = 25C
6.00E-01
8.00E-01
1.00E+00
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 ms. In addition the
100 ID, DRAIN CURRENT (AMPS) Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.
total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RqJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature.
EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)
300 ID = 15 A 250 200 150 100 50 0 25
10 10 ms 1 VGS = 10 V SINGLE PULSE TC = 25C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100 ms 1 ms 10 ms dc
0.1
0.01 0.1
100
50
75
100
125
150
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (C)
Figure 11. Maximum Rated Forward Biased Safe Operating Area
Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature
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TYPICAL ELECTRICAL CHARACTERISTICS
1 RqJA(t), EFFECTIVE TRANSIENT THERMAL RESPONSE D = 0.5
0.2 0.1 0.1 0.05 0.02 Normalized to RqJA at Steady State (1 pad) SINGLE PULSE 1.0E-02 1.0E-01 1.0E+00 t, TIME (s) 1.0E+01 1.0E+02 1.0E+03
0.01 0.01 1.0E-03
Figure 13. FET Thermal Response
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 14. Diode Reverse Recovery Waveform
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NIMD6302R2 INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process.
0.060 1.52
0.275 7.0
0.155 4.0
0.024 0.6
0.050 1.270
inches mm
SO-8 POWER DISSIPATION The power dissipation of the SO-8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RqJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO-8 package, PD can be calculated as follows:
PD = TJ(max) - TA RqJA
into the equation for an ambient temperature TA of 25C, one can calculate the power dissipation of the device which in this case is 2.0 Watts.
PD =
150C - 25C 62.5C/W
= 2.0 Watts
The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values
The 62.5C/W for the SO-8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal CladTM. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.
SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. * * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.
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NIMD6302R2
TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.
STEP 1 PREHEAT ZONE 1 "RAMP" 200C
STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP"
STEP 4 HEATING ZONES 3 & 6 "SOAK"
DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C
160C
STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205 TO 219C "SPIKE" PEAK AT 170C SOLDER JOINT
150C 100C 100C DESIRED CURVE FOR LOW MASS ASSEMBLIES 5C 140C
SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 15. Typical Solder Heating Profile
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PACKAGE DIMENSIONS
SO-8 CASE 751-07 ISSUE AA
-X- A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDAARD IS 751-07 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 MIRROR 2 DRAIN 1 MIRROR 1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
STYLE 19: PIN 1. 2. 3. 4. 5. 6. 7. 8.
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NIMD6302R2
HDTMOS is a registered trademarks of Semiconductor Components Industries, LLC (SCILLC). Thermal Clad is a registered trademark of the Bergquist Company.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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NIMD6302R2/D

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