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HS-6617RH
August 1995
Radiation Hardened 2K x 8 CMOS PROM
Pinouts
5
Features
* * * * * * * * * * * * * * * Total Dose 1 x 10 RAD (Si) Latch-Up Free >1 x 1012 RAD (Si)/s Field Programmable Functionally Equivalent to HM-6617 Pin Compatible with Intel 2716 Low Standby Power 1.1mW Max Low Operating Power 137.5mW/MHz Max Fast Access Time 100ns Max TTL Compatible Inputs/Outputs Synchronous Operation On Chip Address Latches Three-State Outputs Nicrome Fuse Links Easy Microprocessor Interfacing Military Temperature Range -55oC to +125oC
24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T24 TOP VIEW
A7 A6 A5 A4 A3 A2 A1 A0 Q0 1 2 3 4 5 6 7 8 9 24 VDD 23 A8 22 A9 21 P 20 G 19 A10 18 E 17 Q7 16 Q6 15 Q5 14 Q4 13 Q3
Q1 10 Q2 11 GND 12
Description
The Intersil HS-6617RH is a radiation hardened 16K CMOS PROM, organized in a 2K word by 8-bit format. The chip is manufactured using a radiation hardened CMOS process, and is designed to be functionally equivalent to the HM-6617. Synchronous circuit design techniques combine with CMOS processing to give this device high speed performance with very low power dissipation. On chip address latches are provided, allowing easy interfacing with recent generation microprocessors that use multiplexed address/data bus structure, such as the HS-80C85RH or HS-80C86RH. The output enable control (G) simplifies microprocessor system interfacing by allowing output data bus control, in addition to, the chip enable control. Synchronous operation of the HS-6617RH is ideal for high speed pipe-lined architecture systems and also in synchronous logic replacement functions. Applications for the HS-6617RH CMOS PROM include low power microprocessor based instrumentation and communications systems, remote data acquisition and processing systems, processor control store, and synchronous logic replacement.
A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND
24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F24 TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD A8 A9 P G A10 E Q7 Q6 Q5 Q4 Q3
Ordering Information
PART NUMBER HS1-6617RH-Q HS1-6617RH-8 HS1-6617RH/SAMPLE HS1-6617RH/PROTO HS9-6617RH-Q HS9-6617RH-8 HS9-6617RH/Sample HS9-6617RH/PROTO TEMPERATURE RANGE -55oC to +125oC -55oC to +125oC 25oC -55oC to +125oC -55oC to +125oC -55oC -55oC to +125oC 25oC to +125oC PACKAGE 24 Lead SBDIP 24 Lead SBDIP 24 Lead SBDIP 24 Lead SBDIP 24 Lead Flatpack 24 Lead Flatpack 24 Lead Flatpack 24 Lead Flatpack PIN A Q E G P DESCRIPTION Address Input Data Output Chip Enable Output Enable Program Enable (P Hardwired to VDD, except during programming) DB NA
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
Spec Number File Number
1
518742 3033.3
HS-6617RH Functional Diagram
A10 A9 A8 A7 A6 A5 A4 MSB 7 LATCHED ADDRESS REGISTER LSB E P E 8 16 16 16 16 16 16 16 16 8 Q0 - Q7 7 A A GATED ROW DECODER 128 1 OF 8 128 x 128 MATRIX
GATE COLUMN DECODER PROGRAMMING, & DATA
E E A G
OUTPUT CONTROL 4 A 4
E
LATCHED ADDRESS REGISTER MSB A3 A2 A1 A0 LSB
ALL LINES POSITIVE LOGIC: ACTIVE HIGH THREE STATE BUFFERS: OUTPUT ACTIVE A HIGH
ADDRESS LATCHES & GATED DECODERS: LATCH ON FALLING EDGE OF E GATE ON FALLING EDGE OF G P = HARDWIRED TO VDD EXCEPT DURING PROGRAMMING
TRUTH TABLE E 0 0 1 G 0 1 X MODE Enabled Output Disabled Disabled
Spec Number 2
518742
Specifications HS-6617RH
Absolute Maximum Ratings
Supply Voltage ( All Voltages Reference to Device GND) . . . . +7.0V Input or Output Voltage Applied for All Grades. . . . . . . . . . . . . . . . . GND-0.3V to VDD+0.3V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance JA JC Sidebraze DIP Package . . . . . . . . . . . . . 40oC/W 6oC/W Ceramic Flatpack Package . . . . . . . . . . . 60oC/W 4oC/W Maximum Package Power Dissipation at +125oC Sidebraze DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . 1.251W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.83W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: Sidebraze DIP Package . . . . . . . . . . . . . . . . . . . . . . . .25.0mW/C Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . .16.7mW/C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Supply Voltage Range (VDD) . . . . . . . . . +4.5V to +5.5V Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . . +2.4V to VDD
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Guaranteed and 100% Tested. (NOTES 1, 2) CONDITIONS VDD = 4.5V, IO = -2.0mA VDD = 4.5V, IO = 4.8mA VDD = 5.5V, G = 5.5V, VI/O = GND or VDD VDD = 5.5V, VI = GND or VDD, P Not Tested VDD = 5.5V, IO = 0mA, VI = VDD or GND VDD = 5.5V, G = GND, (Note 3), f = 1MHz, IO = 0mA, VI = VDD or GND VDD = 4.5V (Note 4) GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE -55oC TA +125oC MIN 2.4 -10.0 -1.0 MAX 0.4 10.0 1.0 200 25 UNITS V V A A A mA
PARAMETER High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current Standby Supply Current Operating Supply Current Functional Test NOTES:
SYMBOL VOH1 VOL IOZ II IDDSB IDDOP
-55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC
FT
7, 8A, 8B
-55oC TA +125oC
-
-
-
1. All voltages referenced to device GND. 2. All tests performed with P hardwired to VDD. 3. Typical derating = 20mA/MHz increase in IDDOP. 4. Tested as follows: f = 1MHz, VIH = 2.4V, VIL = 0.8V, IOH = -1mA, IOL = +1mA, VOH 1.5V, VOL 1.5V.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Guaranteed and 100% Tested. LIMITS PARAMETERS Address Access Time SYMBOL TAVQV (NOTES 1, 2, 3) CONDITIONS VDD = 4.5V and 5.5V (Note 4) VDD = 4.5V and 5.5V VDD = 4.5V and 5.5V VDD = 4.5V and 5.5V GROUP A SUBGROUPS 9, 10, 11 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN MAX 120 UNITS ns
Output Enable Access Time Chip Enable Access Time Address Setup Time
TGLQV TELQV TAVEL
9, 10, 11 9, 10, 11 9, 10, 11
20
50 100 -
ns ns ns
Spec Number 3
518742
Specifications HS-6617RH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Guaranteed and 100% Tested. LIMITS PARAMETERS Address Hold Time Chip Enable Low Width Chip Enable High Width Read Cycle Time NOTES: 1. All voltages referenced to device GND. 2. AC measurements assume transition time 5ns; input levels = 0.0V to 3.0V; timing reference levels = 1.5V; output load = 1 TTL equivalent load and CL 50pF. 3. All tests performed with P hardwired to VDD. 4. TAVQV = TELQV + TAVEL. SYMBOL TELAX TELEH TEHEL TELEL (NOTES 1, 2, 3) CONDITIONS VDD = 4.5V and 5.5V VDD = 4.5V and 5.5V VDD = 4.5V and 5.5V VDD = 4.5V and 5.5V GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 TEMPERATURE -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN 25 120 40 160 MAX UNITS ns ns ns ns
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS, AC AND DC LIMITS PARAMETERS Input Capacitance I/O Capacitance Chip Enable Time Output Enable Time Chip Disable Time Output Disable Time Output High Voltage SYMBOL CIN CI/O TELQX TGLQX TEHQZ TGHQZ VOH2 (NOTE 2) CONDITIONS VDD = Open, f = 1MHz VDD = Open, f = 1MHz VDD = 4.5V and 5.5V VDD = 4.5V and 5.5V VDD = 4.5V and 5.5V VDD = 4.5V and 5.5V VDD = 4.5V, IO = 100A NOTES 1, 3 1, 3 3 3 3 3 3 TEMPERATURE TA = +25oC TA = +25oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC -55oC TA +125oC MIN 5 5 VDD0.5V MAX 10 12 50 50 UNITS pF pF ns ns ns ns V
NOTES: 1. All measurements referenced to device GND. 2. All tests performed with P hardwired to VDD. 3. The parameters listed are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after design or process changes which would affect these characteristics.
TABLE 4. POST 100K RAD AC AND DC ELECTRICAL PERFORMANCE CHARACTERISTICS NOTE: All AC and DC parameters are tested at the +25oC pre-irradiation limits.
Spec Number 4
518742
HS-6617RH
TABLE 5. BURN-IN DELTA PARAMETERS (+25oC) PARAMETER Standby Supply Current Input Leakage Current SYMBOL IDDSB IOZ II Output Low Voltage Output High Voltage VOL VOH DELTA LIMITS 10A 1A 100nA 60mV 400mV
TABLE 6. APPLICABLE SUBGROUPS GROUP A SUBGROUPS CONFORMANCE GROUP Initial Test Interim Test PDA Final Test Group A (Note 1) MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 RECORDED FOR -Q 1 (Note 2) 1, (Note 2) RECORDED FOR -8
TESTED FOR -Q 1, 7, 9 1, 7, 9, 1, 7, 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11
TESTED FOR -8 1, 7, 9 1, 7, 9 1, 7 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9 1, 7, 9
Subgroup B5 Subgroup B6 Group C
Sample 5005 Sample 5005 Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, 1, 7, 9 -
1, 2, 3, (Note 2) -
Group D Group E, Subgroup 2 NOTES:
Sample 5005 Sample 5005
1, 7, 9 1, 7, 9
-
1. Alternate Group A testing in accordance with MIL-STD-883 method 5005 may be exercised. 2. Table 5 parameters only
Spec Number 5
518742
HS-6617RH Intersil Space Level Product Flow -Q
Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 2 Samples/Wafer, 0 Rejects 100% Die Attach (Note 1) 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method 2011 Sample - Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition A CSI and/or GSI Pre-Cap (Note 8) 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% External Visual 100% Serialization 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 72 Hours Min, +125oC Min, Method 1015
NOTES: 1. Epoxy or Silver glass die attach shall be permitted. 2. Failures from subgroup 1, 7 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. QCI Subgroup B5 samples are programmed with a checkerboard pattern before life test and pattern tested after life test. Therefore, the Subgroup B5 samples must be considered destruct samples and cannot be shipped as flight quantity. 6. Group B and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include separate line items for Group B Test, Group Samples, Group D Test and Group D Samples. 7. Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When required, the P.O. should include a separate line item for Group D Generic Data. Generic data is not guaranteed to be available and is therefore not available in all cases. 8. CSI and/or GSI inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include separate line items for CSI PreCap inspection, CSI Final Inspection, GSI PreCap inspection, and/or GSI Final Inspection. 9. Data Package Contents: * Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). * Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. * GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. * X-Ray report and film. Includes penetrometer measurements. * Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). * Lot Serial Number Sheet (Good units serial number and lot number). * Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. * Group B and D attributes and/or Generic data is included when required by the P.O. * The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative.
100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% PDA 1, Method 5004 (Note 2) 100% Dynamic Burn-In, Condition D, 240 Hours, +125oC or Equivalent, Method 1015 100% Interim Electrical Test 2(T2) 100% Delta Calculation (T0-T2) 100% PDA 2, Method 5004 (Note 2) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% Radiographic (X-Ray), Method 2012 (Note 3) 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 4) Sample - Group B, Method 5005 (Notes 5 and 6) Sample - Group D, Method 5005 (Notes 6 and 7) 100% Data Package Generation (Note 9) CSI and/or GSI Final (Note 8)
Spec Number 6
518742
HS-6617RH Intersil Space Level Product Flow -8
GAMMA Radiation Verification (Each Wafer) Method 1019, 2 Samples/Wafer, 0 Rejects 100% Die Attach (Note 1) Periodic- Wire Bond Pull Monitor, Method 2011 Periodic- Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition B CSI and/or GSI Pre-Cap (Note 7) 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% External Visual 100% Initial Electrical Test
NOTES: 1. Epoxy or Silver glass die attach shall be permitted. 2. Failures from subgroup 1, 7 and deltas are used for calculating PDA. The maximum allowable PDA = 5%. 3. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 4. QCI Group C samples are programmed with a checkerboard pattern before life test and pattern tested after life test. Therefore, the Group C samples must be considered destruct samples and cannot be shipped as flight quantity. 5. Group B, C and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include separate line items for Group B Test, Group C Test, Group C Samples, Group D Test and Group D Samples. 6. Group C and/or Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When required, the P.O. should include a separate line item for Group C Generic Data and/or Group D Generic Data. Generic data is not guaranteed to be available and is therefore not available in all cases. 7. CSI and/or GSI inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include separate line items for CSI PreCap inspection, CSI Final Inspection, GSI PreCap inspection, and/or GSI Final Inspection. 8. Data Package Contents: * Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). * GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. * Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). * Group B, C and D attributes and/or Generic data is included when required by the P.O. * The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative.
100% Dynamic Burn-In, Condition D, 160 Hours, +125oC or Equivalent, Method 1015 100% Interim Electrical Test 100% PDA, Method 5004 (Note 2) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 3) Sample - Group B, Method 5005 (Note 5) Sample - Group C, Method 5005 (Notes 4, 5 and 6) Sample - Group D, Method 5005 (Notes 5 and 6) 100% Data Package Generation (Note 8) CSI and/or GSI Final (Note 7)
Spec Number 7
518742
HS-6617RH Timing Waveform
TAVQV 3.0V 1.5V 1.5V VALID ADDRESS ADDRESSES TELEL TAVEL TELAX TELEH 3.0V 1.5V E TEHEL G 1.5V TGLQX TELQX VALID DATA TS TELQV TGLQV 1.5V 0V TGHQZ TEHQZ 3.0V 1.5V 1.5V 1.5V 0V VALID ADDRESSES 0V
DATA OUTPUT Q0 - Q7
FIGURE 1. READ CYCLE
Spec Number 8
518742
HS-6617RH Burn-In Circuits
HS-6617RH 24 LEAD SBDIP AND FLATPACK
C1
HS-6617RH 24 LEAD SBDIP AND FLATPACK
C1
VDD VDD VDD VDD VDD VDD VDD VDD
A7 A6 A5 A4 A3 A2 A1 A0 Q0
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VDD A8 A9 P G A10 E Q7 Q6 Q5 Q4 Q3
VDD VDD VDD VDD VDD VDD VDD
F10 F9 F8 F7 F6 F5 F4 F3
A7 A6 A5 A4 A3 A2 A1 A0 Q0
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VDD A8 A9 P G A10 E Q7 Q6 Q5 Q4 Q3
VDD F11 F12 VDD F1 F13 F0
Y
Q1 Q2 GND
Y
Y
Q1 Q2 GND
Y
STATIC CONFIGURATION NOTES: 1. 2. 3. 4. VDD = 6.0V 0.5V C1 = 0.01F (Min) All Resistors = 47k 5% Y = 2.7V 10% NOTES: 1. 2. 3. 4. 5. 6. 7. 8.
DYNAMIC CONFIGURATION VDD = 6.0V 0.5V VIH = 4.5V 10% VIL = 0.8V (Max) C1 = 0.01F (Min) All Resistors = 47k 5% F0 = 100KHz 10%, 40 - 60% duty cycle F1 = F0/2 . . . F13 = F12/2 Y = 2.7V 10%
Irradiation Circuit
HS-6617RH 24 LEAD FLATPACK
VDD
1 2 3 4 5 6 7 8 LOAD LOAD LOAD 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13 LOAD LOAD LOAD LOAD LOAD 47K VSS 47K LOAD = NC NC NC TOGGLE (NOTE 3) VDD
NOTES: 1. Power Supply: VDD = 5.5V 2. All Registors = 47K 3. Pin 18 is toggled from VSS to VDD then back to VSS and held at VSS during irradiation.
Spec Number 9
518742
HS-6617RH Metallization Topology
DIE DIMENSIONS: 164 x 250 x 19 1mils METALLIZATION: Type: Silicon-Aluminum Thickness: 13kA 2kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 1 x 105 A/cm2 SUBSTRATE POTENTIAL: VDD
Metallization Mask Layout
HS-6617RH
(24)VDD (23) A8 (22) A9 (5) A3 (4) A4 (2) A6 (1) A7 (21) P (3)A5
(20) G A2 (6) (19) A10
A1 (7) A0 (8) Q1 (10) Q3 (13) Q4 (14) Q5 (15) Q6 (16) GND (12) Q7 (17) Q0 (9) Q2 (11)
(18) E
Spec Number 10
518742
Semiconductor
HS-6617RH
2K x 8 CMOS PROM
DESIGN INFORMATION
July 1995
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Background Information HS-6617RH Programming
PROGRAMMING SPECIFICATIONS PARAMETER Input "0" Voltage "1" Programming VDD Operating VDD Special Verify Delay Time Rise Time Fall Time Chip Enable Pulse Width Address Valid to Chip Enable Low Time Chip Enable Low to Output Valid Time Programming Pulse Width Input Leakage at VDD = VDDPROG Data Output Current at VDD = VDDPROG Output Pull-Up Resistor Ambient Temperature NOTES: 1. All inputs must track VDD (pin 24) within these limits. 2. VDDPROG must be capable of supplying 500mA. VDDPROG Power Supply tolerence 3% (Max.) 3. See Steps 22 through 29 of the Programming Algorithm. 4. See Step 11 of the Programming Algorithm. 5. All outputs should be pulled up to VDD through a resistor of value Rn. 6. Except during programming (See Programming Cycle Waveforms). SYMBOL VIL VIH VDDPROG VDD1 VDD2 td tr tf TEHEL TAVEL TELQV tpw tIP IOP Rn TA MIN 0.0 VDD-2 10.0 4.5 4.0 1.0 1.0 1.0 50 20 90 -10 5 TYP 0.2 VDD 10.0 5.5 1.0 10.0 10.0 100 +1.0 -5.0 10 25 MAX 0.8 VDD+0.3 10.0 5.5 6.0 10.0 10.0 120 110 10 -10 15 UNITS V V V V V s s s ns ns ns s A mA k
oC
NOTES
6 2
3
4
5
Spec Number 11
518742
HS-6617RH
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
Background Information Programming
The HS-6617 CMOS PROM is manufactured with all bits containing a logical zero (output low). Any bit can be programmed selectively to a logical one (output high) state by following the procedure shown below. To accomplish this, a programmer can be built that meets the specifications shown, or use of an approved commercial programmer is recommended. Programming Sequence of Events
1. Apply a voltage of VDD1 to VDD of the PROM. 2. Read all fuse locations to verify that the PROM is blank (output low). 3. Place the PROM in the initial state for programming: P = VIH, G = VIL. E = VIH, 13. Apply a voltage of VIH to P (pin 21). 14. After a delay of td, apply a voltage of VIL to G (pin 20). 15. After a delay of td, examine the outputs for correct data. If any location verifies incorrectly, it should be considered a programming reject. 16. Repeat steps 3 through 15 for all other bits to be programmed in the PROM.
Post-Programming Verification
17. Place the PROM in the post-programming verification mode: E = VIH, G = VIL, P = VIH, VDD (pin 24) = VDD1. 18. Apply the correct binary address of the word to be verified to the PROM. 19. After a delay of td, apply a voltage of VIL to E (pin 18). 20. After a delay of td, examine the outputs for correct data. If any location fails to verify correctly, the PROM should be considered a programming reject. 21. Repeat steps 17 through 20 for all possible programming locations.
4. Apply the correct binary address for the word to be programmed. No inputs should be left open circuit. 5. After a delay of td, apply voltage of VIL to E (pin 18) to access the addressed word. 6. The address may be held through the cycle, but must be held valid at least for a time equal to td after the falling edge of E. None of the inputs should be allowed to float to an invalid logic level. 7. After a delay of td, disable the outputs by applying a voltage of VIH to G (pin 20). 8. After a delay of td, apply voltage of VIL to P (pin 21). 9. After delay of td, raise VDD (pin 24) to VDDPROG with a rise time of tr. All outputs at VIH should track VDD within VDD-2.0V to VDD+0.3V. This could be accomplished by pulling outputs at VIH to VDD through pull-up resistors of value Rn. 10. After a delay of td, pull the output which corresponds to the bit to be programmed to VIL. Only one bit should be programmed at a time. 11. After a delay of tpw, allow the output to be pulled to VIH through pull-up resistor Rn. 12. After a delay of td, reduce VDD (pin 24) to VDD1 with a fall time of tf. All outputs at VIH should track VDD with VDD-2.0V to VDD+0.3V. This could be accomplished by pulling outputs at VIH to VDD through pull-up resis- tors of value Rn.
Post-Programming Read
22. Apply a voltage of VDD2 = 4.0V to VDD (pin 24). 23. After a delay of td, apply a voltage of VIH to E (pin 18). 24. Apply the correct binary address of the word to be read. 25. After a delay of TAVEL, apply a voltage of VIL to E (pin 18). 26. After a delay of TELQV, examine the outputs for correct data. If any location fails to verify correctly, the PROM should be considered a programming reject. 27. Repeat steps 23 through 26 for all address locations. 28. Apply a voltage of VDD2 = 6.0V to VDD (pin 24). 29. Repeat steps 23 through 26 for all address locations.
Spec Number 12
518742
HS-6617RH
DESIGN INFORMATION (Continued)
The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied.
PROGRAMMING VDDPROG A VIH VIL E VIH VIL td VDDPROG VIH G VIL P VIH VIL td VDDPROG VDD VDD GND tr VDDPROG VIH/VOH Q VIL/VOL td tpw td tf td td VALID
VERIFY
VALID TEHEL
td
READ DATA
FIGURE 2. HS-6617RH PROGRAMMING CYCLE
A
VIH VIL TAVEL VIH VIL TEHEL 6.0V 5.0V 4.0V td td VALID TEHEL TEHEL
E
VDD
0.0V TELQV VOH VOL READ TELQV TELQV
Q
READ
READ
FIGURE 3. HS-6617RH POST PROGRAMMING VERIFY CYCLE
Spec Number 13
518742
HS-6617RH
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
Spec Number 14

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