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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-22005-1E
ASSP Communication Control
IEEE1394-SCSI Tailgate
MB86616
s DESCRIPTION
The MB86616 is the LSI for protocol conversion to connect SCSI devices to the IEEE 1394 bus. This LSI integrates a 1394 controller compliant with the IEEE Standard for High Performance Serial Bus (IEEE Std. 1394-1995, or FireWire standard) and an SCSI protocol controller compliant with the SCSI-Fast20 standard on a single chip. It also incorporates the F2MC-16F as a processor for controlling the individual on-chip controllers, providing ease of control. The IEEE 1394 controller unit has two ports for use in a cable environment and contains a differential transceiver and a comparator. It supports S400 data transfer rates. In addition, it supports the Chain command to continuously issue request packets for data transmission and reception, improving the efficiency of data transfer. The SCSI protocol controller unit conforms to 8-bit Fast20 SCSI, enabling data transfer at a maximum of 20 Mbyte/s. For the SCSI bus terminal, the unit contains a totem pole type of single-end driver/receiver so that it can drive the SCSI bus directly. While inheriting the AT architecture of the F2MC-16/16H family, the instruction set for the F2MC-16F CPU core incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions.
s PACKAGE
144-pin Plastic LQFP
(FPT-144P-M08)
MB86616
s FEATURES
* * * * * * * * * * * * IEEE 1394 Controller Unit Compliant with the IEEE Standard for High Performance Serial Bus (IEEE Std. 1394-1995 Physical and link layer modules integrated on a single chip Two cable ports Data transfer rates supported : S100, S200, S400 Data buffer dedicated to asynchronous transmission/reception 2-Kbyte (1/2/4 bank-switchable) , transmission/reception shared data buffer 128-byte buffer dedicated to asynchronous transmission and 128-byte buffer dedicated to asynchronous reception Automatic separation of the packet header and data upon reception and automatic packetization of information upon transmission 32-bit CRC generation and check functions Chain transfer function for data transfer sequence 4- and 4-conductor cables supported
* SCSI Protocol Controller Unit * Dedicated to initiator operation * FAST-20 data transfer (8-bit) Synchronous transfer : 20 MBps Max. (Maximum offset value of 15) Asynchronous transfer : 5 MBps Max. * Internal 16-byte FIFO data register * Totem pole type of Fast20 single-end driver/receiver * 28-bit transfer byte counter enabling simultaneous transfer of up to 256 Mbytes of data * * * * F2MC-16F Unit Minimum instruction execution time : 40.7 ns (at 24.576 MHz) Instruction set optimized for controller applications Instruction set supporting high-level languages (including C) and multi tasking
* Miscellaneous * Supply voltage : 3.3 V and 5 V power supplies * Package : LQFP-144 (FPT-144P-M08)
2
MB86616
s PIN ASSIGNMENT DRAWING
(TOP VIEW)
VDD3 VSS A06 A07 A08 A09 A10 A11 VSS VDD3 A12 A13 A14 A15 A16 A17 A18 VDD3 VSS TEST2 WR RD TEST3 P74 P75 P76 P90/INT0 P91/INT1 VDD3 VSS P92 P93 CS TEST4 TEST5 TEST6 144 1 140 135 130 125 120 115 109 110 A05 A04 A03 A02 A01 TEST1 VSS VDD3 D15 D14 D13 D12 D11 D10 D09 D08 D07 VSS VDD3 D06 D05 D04 D03 D02 D01 D00 VDD3 VSS N.C. PWR3 PWR2 PWR1 LINKON PMODE VSS VDD3
VDD3 VSS MD0 MD1 MD2 SVSS RST BSY SEL SVSS SVDD5 VSS VDD3 MSG CD IO SVSS ATN REQ ACK SVSS DBP DB7 DB6 SVSS SVDD5 VSS VDD3 DB5 DB4 DB3 SVSS DB2 DB1 DB0 SVSS
108 105
5
100 10
95 15 MB86616 20
90
85 25
80 30
75 35 36 37 40 45 50 55 60 65 70 72 73
AVSS AVDD TPBIAS0 TPA0 TPA0 TPB0 TPB0 AVDD AVSS AVSS AVDD TPBIAS1 TPA1 TPA1 TPB1 TPB1 AVDD AVSS CPS R0 AVDD AVSS RF FIL AVDD AVSS SCLK VSS N.C. TESTP MODEC MODEB MODEA RESET VSS VDD3
(FPT-144P-M08)
3
MB86616
s PIN ASSIGNMENT TABLE
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 4 I/O ID ID ID SI/O SI/O SI/O SI/O SI/O SI/O SI/O SI/O SI/O SI/O SI/O SI/O SI/O SI/O SI/O SI/O SI/O SI/O Pin Name Pin No. VDD3 VSS MD0 MD1 MD2 SVSS RST BSY SEL SVSS SVDD5 VSS VDD3 MSG CD IO SVSS ATN REQ ACK SVSS DBP DB7 DB6 SVSS SVDD5 VSS VDD3 DB5 DB4 DB3 SVSS DB2 DB1 DB0 SVSS 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 I/O ID ID ID ID O ID AO AO AO I AI/O AI/O AI/O AI/O AO AI/O AI/O AI/O AI/O AO Pin Name Pin No. VDD3 VSS RESET MODEA MODEB MODEC TESTP N.C. VSS SCLK AVSS AVDD FIL RF AVSS AVDD R0 CPS AVSS AVDD TPB1 TPB1 TPA1 TPA1 TPBIAS1 AVDD AVSS AVSS AVDD TPB0 TPB0 TPA0 TPA0 TPBIAS0 AVDD AVSS 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 I/O ID O ID ID ID ID/O ID/O ID/O ID/O ID/O ID/O ID/O ID/O ID/O ID/O ID/O ID/O ID/O ID/O ID/O ID/O O ID/O ID/O ID/O ID/O ID/O Pin Name Pin No. VDD3 VSS PMODE LINKON PWR1 PWR2 PWR3 N.C. VSS VDD3 D00 D01 D02 D03 D04 D05 D06 VDD3 VSS D07 D08 D09 D10 D11 D12 D13 D14 D15 VDD3 VSS TEST1 A01 A02 A03 A04 A05 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 I/O ID/O ID/O ID/O ID/O ID/O ID/O ID/O ID/O ID/O ID/O ID/O ID/O ID/O O IU/O IU/O O ID/O ID/O ID/O ID/O ID/O ID/O ID/O IU/O O O O Pin Name VDD3 VSS A06 A07 A08 A09 A10 A11 VSS VDD3 A12 A13 A14 A15 A16 A17 A18 VDD3 VSS TEST2 WR RD TEST3 P74 P75 P76 P90/INT0 P91/INT1 VDD3 VSS P92 P93 CS TEST4 TEST5 TEST6
MB86616
I/O types: ID : Digital input pin (with pull-down resistor) O : Digital output pin ID/O : Digital input/output pin (with pull-down resistor) IU/O : Digital input/output pin (with pull-up resistor) SI/O : SCSI input/output pin AI : Analog input pin AO : Analog output pin AI/O : Analog input/output pin
5
MB86616
s PIN DESCRIPTION
1. IEEE 1394 Interface
Signal name TPA0, TPA1 TPA0, TPA1 TPB0, TPB1 TPB0, TPB1 TPBIAS0, TPBIAS1 I/O I/O I/O I/O I/O O Function TPA positive-signal input/output pin at IEEE 1394 port TPA negative-signal input/output pin at IEEE 1394 port TPB positive-signal input/output pin at IEEE 1394 port TPB negative-signal input/output pin at IEEE 1394 port Common-voltage reference voltage output pin at IEEE 1394 port
2.
SCSI Interface
Signal name REQ, ACK, ATN, MSG, CD, IO, RST, BSY, SEL DB0 to DB7 DBP I/O Function
I/O
SCSI control signal input/output pins
I/O I/O
Input/output pins for SCSI data bus Parity bit input/output pins for SCSI data bus
3. Internal CPU Pins (for Normal Operation Mode)
Note that the pin functions covered in this section are enabled only in the normal operation mode (with the MODEA pin = "L") . Signal name A01 to A18 D00 to D15 WR RD CS P74 to P76 P90 to P93 MD0 to MD2 I/O O I/O O O O Address output pins Data input pins Write strobe signal output pin Read strobe signal output pin Pin to output the external flash ROM chip enable signal. This signal is output for accessing an address from F80000h to FFFFFFh in memory space. General-purpose input/output port pins CPU block mode setting pins. Connect all of these pins to GND on this device. Function
I/O I
6
MB86616
4. CPU Interface (for External CPU Mode)
Note that the pin functions covered in this section are enabled only in the external CPU mode (with the MODEA pin = "H") . Signal name A01 to A09 D00 to D15 CS WR RD INT0 INT1 I/O I I/O I I I O O External CPU address input pin External CPU data input/output pin Pin to input the chip select signal to this device Pin to input the write strobe signal to this device Pin to input the read strobe signal to this device Interrupt request output pin for the IEEE 1394 block Interrupt request output pin for the SCSI block Function
5. Other Pins
Signal name RESET I/O I Function Reset signal input pin. Leave this pin at the "L" level while the IEEE 1394 block is operating with cable supplied power. Pin for setting the operation mode of this device. "L" input : Use the internal CPU. "H" input : Use an external CPU to control this device without using the internal CPU. Connect these pins to GND. Reference clock input pin for the internal PLL (24.576 MHz) Connect this pin to GND via a 5.1 k resistor. External filter circuit connection pin for the internal PLL Connect this pin to GND via a 5.1 k resistor. Pin to input power supplied through the IEEE 1394 cable. The pin detects cable supplied power of 0 to 33 V (an external resistor is required to regulate/divide the voltage) . Connect this pin to GND if the device is not powered through the IEEE 1394 cable. Power input evaluation pin. "L" input : Operate the device with power supplied through the IEEE 1394 cable. (Only the IEEE 1394 block operates with the cable supplied power, with the other blocks left in the reset state.) "H" input : Operate the device with the system power supply. Pins to set the POWER_CLASS bit in the Self-ID packet which is transmitted during operation with power supplied through the IEEE 1394 cable. PWR1 to PWR3 I Note : The POWER_CLASS in the Self-ID packet transmitted during operation with the system power supply depends not on these pins but on the settings of the Pwr bits (Bits 2 to 0) in physical register #4.
MODEA
I
MODEB, MODEC SCLK RF FIL R0
I I O O O
CPS
I
PMODE
I
(Continued)
7
MB86616
(Continued)
Signal name I/O Function Output pin for detection of Link-on packet reception. This pin outputs the "H" level signal upon reception of the Link-on packet during operation with power supplies through the IEEE 1394 cable. The output signal level changes to "L" the moment the PMODE signal becomes "H". The output from this pin remains unchanged with PMODE = "H". Leave this pin open when not in use. Test pin. Leave it open. Leave this pin open.
LINKON
O
TESTP, TEST1 to TEST6 N.C.
O
6. Power/GND Pins
Signal name VDD3 VSS SVDD5 SVSS AVDD AVSS I/O 3.3 V digital power supply pin Digital ground pin 5 V power supply pin for SCSI I/O Ground pin for SCSI I/O 3.3 V analog power supply pin Analog ground pin Function
8
MB86616
s BLOCK DIAGRAM
* Normal Operation Mode
D00 to D15
External interface
A01 to A18
WR
RD
CS
SCLK FIL RF PLL F2MC-16F CPU F2MC-16F bus
RAM 4 kbyte
16 bit Timer x3
Clock frequency divider
CPU bus
External interrupt
TPA0/TPA1 TPA0/TPA1 TPB0/TPB1 TPB0/TPB1 TPBIAS0/TPBIAS1
DREQA IEEE1394 block DWRA DRDA Exchange block
DREQB DWRB DRDB SCSI block
RST BSY SEL MSG CD IO REQ ACK ATN DBP DB0 to DB7
DMA data bus
9
MB86616
* External CPU Mode
D00 to D15
CPU-I/F
SCLK FIL RF PLL CPU bus
Clock frequency divider
A01 to A09
INT0, INT1
WR
RD
CS
RST TPA0/TPA1 TPA0/TPA1 TPB0/TPB1 TPB0/TPB1 TPBIAS0/TPBIAS1 IEEE1394 block DREQA DWRA DRDA Exchange block DREQB DWRB DRDB SCSI block BSY SEL MSG CD IO REQ ACK ATN DBP DB0 to DB7 DMA data bus
10
MB86616
s FUNCTIONS of BLOCKS
* CPU Block This block controls the individual blocks. It incorporates the F2MC-16F as the core and RAM, 16-bit timers (3 channels) , and an external interrupt controller as peripheral circuits. * IEEE 1394 Block This block controls the IEEE 1394 interface. * SCSI Block This block controls the SCSI interface. * PLL Circuit This block generates clock signals for individual blocks from the reference clock signal generated by the clock module. Reference oscillation frequency : 24.576 MHz Clock frequency for CPU block : 24.576 MHz Clock frequency for IEEE 1394 block : 393.216 MHz (for bus) , 49.152 MHz (for internal operation) Clock frequency for SCSI block : 39.322 MHz Clock frequency for Exchange block : 39.322 MHz
11
MB86616
s INTERNAL REGISTERS
1. Memory Space
FFFFFFH (External flash ROM) F80000H Inaccessible area
002300H 002200H 002100H 002000H 001100H Exchange block SCSI block IEEE 1394 block
RAM 000100H 0000C0H 000000H
General registers
CPU block External ROM/external bus mode
12
MB86616
2. CPU Block Internal Registers
Address (HEX) 000000 to 000006 000007 000008 000009 00000A to 00000F 000010 to 000016 000017 000018 000019 000019 to 00002F 000030 000031 000032 000033 to 00003F 000040 000041 000042 000043 000044 000045 000046 to 000047 000048 000049 00004A 00004B 00004C 00004D 00004E to 00004F WRITE operation Register name System reserved area Port-7 data register System reserved area Port-9 data register (reserved) System reserved area Port-7 direction register System reserved area Port-9 direction register (reserved) Interrupt/DTP enable register Interrupt/DTP source register Request level set register (reserved) Timer control status #0 (reserved) 16-bit timer reload #0 (reserved) Timer control status #1 (reserved) 16 bit timer reload #1 (reserved) Abbreviation PDR7 PDR9 DDR7 DDR9 ENIR ENRR ELVR TMCSR0 TMRLR0 TMCSR1 TMRLR1 READ operation Register name System reserved area Port-7 data register System reserved area Port-9 data register (reserved) System reserved area Port-7 direction register System reserved area Port-9 direction register (reserved) Interrupt/DTP enable register Interrupt/DTP source register Request level set register (reserved) Timer control status #0 16 bit timer #0 (reserved) (reserved) Timer control status #1 16 bit timer #1 (reserved) (reserved) Abbreviation PDR7 PDR9 DDR7 DDR9 ENIR ENRR ELVR TMCSR0 TMT0 TMCSR1 TMT1 16-bit timer #1 16-bit timer #0 DTP/external interrupt Resource name Port 7 Port 9 Port 7 Port 9
(Continued)
13
MB86616
Address (HEX) 000050 000051 000052 000053 000054 000055 000056 to 00008F 000090 to 00009E 00009F 0000A0 0000A1 to 0000A2 0000A3 0000A4 0000A5 0000A6 to 0000A7 0000A8 0000A9 0000AA to 0000AF 0000B0 0000B1 0000B2 0000B3 0000B4 0000B5 0000B6
WRITE operation Register name Timer control status #2 (reserved) 16 bit timer reload #2 (reserved) System reserved area Delayed interrupt source generate/reset register Standby control register (reserved) Middle address control register High address control register External pin control register (reserved) Watchdog timer control register Time-base timer control register (reserved) Interrupt control register 0 Interrupt control register 1 System reserved area System reserved area Interrupt control register 4 Interrupt control register 5 System reserved area Abbreviation TMCSR2 TMRLR2 DIRR STBYC MACR HACR EPCR TWC TBTC ICR0 ICR1 ICR4 ICR5
READ operation Register name Timer control status #2 16 bit timer #2 (reserved) (reserved) System reserved area Delayed interrupt source generate/reset register Standby control register (reserved) (reserved) (reserved) (reserved) (reserved) Watchdog timer control register Time-base timer control register (reserved) Interrupt control register 0 Interrupt control register 1 System reserved area System reserved area Interrupt control register 4 Interrupt control register 5 System reserved area Abbreviation TMCSR2 TMT2 DIRR STBYC TWC TBTC ICR0 ICR1 ICR4 ICR5
Resource name
16-bit timer #2
Delayed interrupt Low power consumption External pin External pin External pin Watchdog timer Time-base timer
Interrupt controller
(Continued)
14
MB86616
(Continued)
Address (HEX) 0000B7 0000B8 0000B9 0000BA 0000BB 0000BC 0000BD 0000BE 0000BF WRITE operation Register name Interrupt control register 7 Interrupt control register 8 Interrupt control register 9 Interrupt control register 10 System reserved area System reserved area System reserved area System reserved area Interrupt control register 15 Abbreviation ICR7 ICR8 ICR9 ICR10 ICR15 READ operation Register name Interrupt control register 7 Interrupt control register 8 Interrupt control register 9 Interrupt control register 10 System reserved area System reserved area System reserved area System reserved area Interrupt control register 15 Abbreviation ICR7 ICR8 ICR9 ICR10 ICR15 Interrupt controller Resource name
15
MB86616
3. IEEE 1394 Block Internal Registers
Address (HEX) 002000 002002 002004 002006 002008 00200A 00200C 00200E 002010 002012 002014 002016 002018 00201A 00201C 00201E 002020 002022 002024 002026 002028 00202A 00202C WRITE operation Register name mode-control (reserved) instruction-fetch Interrupt-mask set register (reserved) A-buffer data port transmit register D-buffer data port transmit register (reserved) (reserved) Transmission ASYNC-des-ID set register Transmission ASYNC-PKT-param set register Transmission ASYNC-data-length set register Transmission ASYNC-ex-tcode set register Transmission ASYNC-source-busID set register Transmission ASYNC-rcode set register Transmission ASYNC-des-offset set register (upper) Transmission ASYNC-des-offset set register (middle) Transmission ASYNC-des-offset set register (lower) Total chain data-length set register (upper) Total chain data length set register (lower) Chain transmission des-ID set register Chain transmission des-offset set register (upper) Chain transmission des-offset set register (middle) Abbreviation MCTL INST INTM SADP SDDP SADID SAPP SADL SAET SASID SARC SADOU SADOM SADOL CSDLU CSDLL CDID CDOU CDOM READ operation Register name mode-control flag & status instruction-fetch Interrupt-code display register Reception acknowledge display register A-buffer data port receive register D-buffer data port receive register (reserved) (reserved) (reserved) Reception ASYNC-PKT-param display register Reception ASYNC-data-length display register Reception ASYNC-ex-tcode display register Reception ASYNC-source-ID display register Reception ASYNC-rcode display register Reception ASYNC-des-offset display register (upper) Reception ASYNC-des-offset display register (middle) Reception ASYNC-des-offset display register (lower) Remaining chain data byte counter (upper) Remaining chain data byte counter (lower) Ping time monitor (reserved) (reserved) Abbreviation MCTL FLST INST INTC RACK RADP RDDP RAPP RADL RAET RASID RARC RADOU RADOM RADOL CRBCU CRBCL PTMN
(Continued)
16
MB86616
(Continued)
Address (HEX) 00202E 002030 002032 002034 002036 002038 00203A 00203C to 0000FE WRITE operation Register name Chain transmission des-offset set register (lower) Chain transmission data-length set register Chain retry-limit set register (reserved) (reserved) PHY/LINK register address set register PHY/LINK register access port (Write) (reserved) Abbreviation CDOL CSDL CRLM PLRA WPLAP READ operation Register name (reserved) Received packet transfer rate display register Cycle-timer-monitor display register (upper) Cycle-timer-monitor display register (lower) Revision display register PHY/LINK register address set register PHY/LINK register access port (Read) (reserved) Abbreviation PSPD CTMU CTML REVM PLRA RPLAP
17
MB86616
4. SCSI Block Internal Registers
Address (HEX) 002100 002102 002104 002106 002108 00210A 00210C 00210E 002110 002112 002114 002116 002118 00211A 00211C 00211E 002120 to 0000FE WRITE operation Register name Bus Device ID SCSI Control SCSI Command Transfer Mode Interrupt Sense SCSI Diagnostic Control (reserved) (reserved) Phase Control Extend Transfer Counter Data Register (SCSI output) Temporary (SCSI output) Transfer Counter (High) Transfer Counter (Mid) Transfer Counter (Low) REQ/ACK Timeout Set (reserved) Abbreviation BDID SCTL SCMD TMOD INTS SDGC PCTL TCE DREG TEMP TCH TCM TCL RATO READ operation Register name Bus Device ID SCSI Control SCSI Command Transfer Mode Interrupt Sense Phase Sense SCSI Block Status SCSI Error Status Phase Control Extend Transfer Counter Data Register (SCSI input) Temporary (SCSI input) Transfer Counter (High) Transfer Counter (Mid) Transfer Counter (Low) Modified Byte Counter (reserved) Abbreviation BDID SCTL SCMD TMOD INTS PSNS SSTS SERR PCTL TCE DREG TEMP TCH TCM TCL MBC
5. Exchange Block Internal Registers
Address (HEX) 002200 002202 002204 002206 to 0000FE WRITE operation Register name Mode Control Signal Control Data Port (Input) (reserved) Abbreviation EMOD ESCTL EDPI READ operation Register name Mode Control Signal Sense Data Port (Output) (reserved) Abbreviation EMOD ESSNS EDPO
18
MB86616
s ABSOLUTE MAXIMUM RATINGS
(Vss = 0 V) Parameter Power supply voltage Input voltage Output voltage Ambient storage temperature Operating junction temperature Output current*2 Overshoot Undershoot *1 : For SCSI I/O *2 : Maximum supply current which can flow in steady state. Exceeding it is allowed only within 1 second per LSI unit excluding the SCSI I/O. *3 : Within 50 ns WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Symbol VDD3 VDD5 VI3 VI5*1 VO3 VO5 Tj IO
*1 *1
Rating Min. VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 -55 -40 IOL = 4 mA VDD3 + 1.0 VSS - 1.0
*3 *3
Max. 4.0 6.0 VDD3 + 0.5 VDD5 + 0.5 VDD3 + 0.5 VDD5 + 0.5 +125 +125 14
Unit V V V V V V C C mA V V
Tst
19
MB86616
s RECOMMENDED OPERATING CONDITIONS
(Vss = 0 V) Parameter 3.3 V power supply Power supply voltage 5 V power supply (for SCSI-I/O) CMOS Normal*1 "H" level input voltage CMOS Schmitt*2 SCSI CMOS Normal "L" level input voltage Differential input voltage (for data transfer) Differential input voltage (for arbitration) SCSI IEEE1394 IEEE1394 S100 Common-mode input voltage IEEE1394 Receiving input jitter Receiving input skew Operating temperature *1 : D00 to D15 *2 : MD0 to MD2, RESET, MODEA to MODEC, PMODE, PWR1 to PWR3, A01 to A18, CS, WR, RD, P74 to P76, P90 to P93, TEST2 to TEST6. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. IEEE1394 IEEE1394 S200 S400
*1 *2
Symbol VDD3 VDD5 VIHN VIHS VIHSC VILN VILS VILSC VIDD VIDA VCM100 VCM200 VCM400 Ta
Values Min. 3.0 4.5 VDD3 x 0.65 VDD3 x 0.80 2.0 VSS VSS VSS 118 168 1.165 0.935 0.523 0 Typ. 3.3 5.0 Max. 3.6 5.5 VDD3 + 0.3 VDD3 + 0.3 VDD5 + 0.3 VDD3 x 0.25 VDD3 x 0.20 0.8 260 265 2.515 2.515 2.515 0.315 0.8 70
Unit V V V V V V V V mV mV V V V ns ns C
CMOS Schmitt
20
MB86616
s ELECTRICAL CHARACTERISTICS
1. DC CHARACTERISTICS
The DC characteristics guarantee the worst-case values of static characteristics of the input/output buffers within the recommended operating condition ranges. (1) Digital I/O Pins
(VDD3 = 3.3 0.3 V, Vss = 0 V, Ta = 0 to 70 C) Symbol VOH VOL
*1
Parameter "H" level output voltage "L" level output voltage Output short-circuit current Input leakage current*2 Input resistance Normal Input 3state Input pull-up pull-down
Conditions IOH = -4 mA IOL = 4 mA VO = 0 V or VDD VI = 0 V to VDD VIL = 0 V VIH = VDD
Values Min. VDD - 0.5 VSS -5 25 Typ. 50 Max. VDD 0.4 60 5 200
Unit V V mA A k
IOS ILI ILZ Rpu Rpd
*1 : Maximum current that flows when the output pin is connected to Vdd or Vss, for one second per LSI pin. *2 : The input leakage current may exceed the above value when an input buffer with pull-up or pull-down resistor is used. (2) SCSI I/O Pins
(VDD5 = 5.0 0.5 V, Vss = 0 V, Ta = 0 to 70 C) Symbol VOHSC VOLSC VHYS Conditions IOH = -7 mA IOL = 48 mA Values Min. 2 VSS 0.2 Typ. Max. VDD 0.5 Unit V V V
Parameter "H" level output voltage "L" level output voltage Input hysteresis voltage width
21
MB86616
(3) IEEE 1394 Driver and Comparator * Driver (VDD3 = 3.3 0.3 V, Vss = 0 V, Ta = 0 to 70 C) Parameter Differential output voltage S100 Common-mode output current S200 S400 Off-state voltage S100 Common-mode output voltage S200 S400 Symbol VOD ICM ISP200 ISP400 VOFF VOM VSP200 VSP400 Conditions RL = 56 Driver enable, signaling off S200 speed signaling enable S400 speed signaling enable Driver disable Driver enable, signaling off S200 speed signaling enable S400 speed signaling enable Values Min. 172 -0.81 -2.53 -8.10 1.665 1.438 1.030 Typ. Max. 265 0.44 -4.84 -12.40 20 2.015 2.015 2.015 Unit mV mA mA mA mV V V V
* Comparator (VDD3 = 3.3 0.3 V, Vss = 0 V, Ta = 0 to 70 C) Parameter Common-mode input current H-level detection Arbitration Comparator Z-level detection L-level detection Port-status Comparator connection detection disconnection detection Symbol IIC VACH VACZ VACL VPCH VPCL Conditions Driver disable Values Min. -20 168 -89 1.0 Typ. Max. 20 89 168 0.6 Unit A mV mV mV V V
(4) Supply Current
(VDD3 = 3.3 0.3 V, VDD5 = 5.0 0.5 V, Vss = 0 V, Ta = 0 to 70 C) Symbol IDD3 IDD5 Conditions Values Min. Typ. Max. 300 100 Unit mA mA
Parameter Supply current (3.3 V power supply) Supply current (5.0 V power supply) 22
MB86616
2. AC CHARACTERISTICS
(1) Clock Input Parameter Clock frequency Clock cycle time "H" and "L" level clock pulse widths Clock rise time, clock fall time CPU block Clock input to each IEEE 1394 block block SCSI block Exchange block CPU block machine clock (Note 1) IEEE 1394 bus (Note 2) SCSI bus (Synchronous transfer) Symbol FC tC tWCH, tWCL tCR, tCF FCPU tCPU F1394 FSCSI tSCSI FEXC tCYC F1394B FSCSIB SCLK Pin name Values Min. 15 tcpu 98.304 1.229 Typ. 24.576 1/FC 24.576 1/Fcpu 393.216 39.322 1/Fscsi 39.322 196.608 Max. 3 16 tcpu 393.216 19.661 Unit MHz ns ns ns MHz ns MHz MHz ns MHz ns MHz MHz
Note1 : The maximum value assumes the minimum speed (1/16) set by the clock gear feature. Note2 : The values are transfer rates at S100/S200/S400.
tWCH tCF 0.65 VDD 0.25 VDD
tC tCR
SCLK
tWCL
23
MB86616
(2) Reset Input Parameter "L" level reset pulse width Symbol tWRSL Pin name RESET Values Min. 5 tcp Typ. Max. Unit ns
tWRSL
RESET
24
MB86616
)
(3) External Bus Interface (Flash ROM Interface) 3-1 Bus Read (Load pin capacitance = 30 pF) Symbol tACYC tAVRL tRLRH tRLDV tRHDX Pin name A01 to A18, CS A01 to A18, CS, RD RD RD, D00 to D15 RD, D00 to D15 A01 to A18, CS, D00 to D15 RD, A01 to A18, CS Values Min. (2 + n*) tcyc - 10 tcyc / 2 - 13 (1 + n*) tcyc - 25 0 Max. (1 + n*)tcyc - 30 (3 / 2 + n*)tcyc - 10 Unit ns ns ns ns ns
Parameter Address cycle time Valid addressRD RD "L" level pulse width RD Valid data RDData hold
Valid addressValid data
tAVDV
ns
RDValid address
tRHAX
tcyc / 2 - 20
ns
*: n is the number of wait cycle.(no wait ; n = 0) The number of wait cycle is set by external pin control registor.
tACYC
A01 to A18
CS
tAVRL tRLRH tRHAX
RD
tRHDX tRLDV
D00 to D15
tAVDV
25
MB86616
3-2 Bus Write
(Load pin capacitance = 30 pF) Symbol tACYC tAVWL tWLWH tDVWH tWHDX Pin name A01 to A18, CS A01 to A18, CS, WR WR WR, D00 to D15 WR, D00 to D15 WR, A01 to A18, CS Values Min. (2 + n*) tcyc - 10 tcyc / 2 - 13 (1 + n*) tcyc - 20 (1 + n*) tcyc - 25 tcyc / 2 - 15 tcyc / 2 - 15 Max. Unit ns ns ns ns ns
Parameter Address cycle time Valid addressWR WR "L" level pulse width Written dataWR WRData hold
WRValid address
tWHAX
ns
*: n is the number of wait cycle.(no wait ; n = 0) The number of wait cycle is set by external pin control registor.
tACYC
A01 to A18
CS
tAVWL
tWHAX tWLWH
WR
tDVWH
tWHDX
D00 to D15
(4) IEEE 1394 Driver Parameter Transmission jitter Transmission skew Transmission rise time, fall time * Symbol tJT tDK tDR, tDF Pin name TPA, TPA, TPB, TPB Values Min. Max. 0.15 0.10 1.2 Unit ns ns ns
* : Measurement conditions : CL = 10 pF, RL = 56 26
MB86616
(5) SCSI Interface 5-1 Target Selection Operation (with Arbitration) Parameter SELBSY ID assertBSY IOBSY BSYBSY BSYSEL BSYID hold SELPhase signal output Symbol ts011 ts012 ts013 ts014 ts015 ts016 ts017 Pin name SEL, BSY DB0 to DB7, DBP, BSY IO, BSY BSY BSY, SEL DB0 to DB7, DBP, BSY SEL, IO CD, MSG Values Min. 0 0 0 18 tscsi 0 10 9 tscsi Max. 19 tscsi + 20 10 tscsi + 20 Unit ns ns ns ns ns ns ns
BSY
tS011 tS014 tS015
SEL
tS012 tS016
DB0 to DB7, DBP
tS013 tS017
IO, CD, MSG
27
MB86616
5-2 Target Selection Operation (without Arbitration) Parameter ID assertSEL IOSEL SELBSY BSYSEL BSYID hold SEL Phase signal output Symbol ts021 ts022 ts023 ts015 ts016 ts017 Pin name DB0 to DB7, DBP, SEL IO, SEL SEL, BSY BSY, SEL BSY, DBP DB0 to DB7 SEL, IO, CD, MSG Values Min. 0 0 18 tscsi 0 10 9 tscsi Max. 19 tscsi + 20 10 tscsi + 20 Unit ns ns ns ns ns ns
BSY
tS023 tS015
SEL
tS021 tS016
DB0 to DB7, DBP
tS022 tS017
IO, CD, MSG
28
MB86616
5-3 Initiator Selection Operation (with Arbitration) Parameter Bus freeBSY BSYSelf-ID output BSYSEL SELATN & ID output ID outputBSY BSYSEL & ID hold * : SCSI block TCL register value Symbol ts031 ts032 ts033 ts034 ts035 ts036 Pin name BSY BSY, DBP, DB0 to DB7 BSY, SEL SEL, ATN, DBP, DB0 to DB7 DB0 to DB7, DBP, BSY BSY, SEL, DBP, DB0 to DB7 Values Min. (21 + n*) tscsi 0 128 tscsi - 10 52 tscsi - 10 8 tscsi - 10 8 tscsi Max. (22 + n*) tscsi + 20 15 128 tscsi + 15 52 tscsi + 15 8 tscsi + 15 9 tscsi + 20 Unit ns ns ns ns ns ns
BSY
tS031 tS033 tS035 tS036
SEL
tS032 tS034
DB0 to DB7, DBP
ATN
29
MB86616
5-4 Initiator Selection Operation (without Arbitration) Parameter Bus freeID output ID outputSEL & ATN BSYSEL & ID hold * : SCSI block TCL register value Symbol ts041 ts042 ts036 Pin name DB0 to DB7, DBP DB0 to DB7, DBP, SEL, ATN BSY, SEL, DBP, DB0 to DB7 Values Min. (21 + n*) tscsi 44 tscsi - 15 8 tscsi Max. (22 + n*) tscsi + 10 44 tscsi + 10 9 tscsi + 20 Unit ns ns ns
BSY
tS036
SEL
tS041 tS042
DB0 to DB7, DBP
ATN
30
MB86616
5-5 Target Reselection Operation Parameter Bus freeBSY BSY Self-ID output BSYSEL SELPhase signal & ID output Symbol ts031 ts032 ts033 ts051 Pin name BSY BSY, DBP, DB0 to DB7 BSY, SEL SEL, IO, CD, MSG, DBP, DB0 to DB7 DB0 to DB7, DBP, BSY BSY BSY, SEL, DBP, DB0 to DB7 Values Min. (21 + n*) tscsi 0 128 tscsi - 10 52 tscsi - 10 8 tscsi - 10 8 tscsi 4 tscsi Max. (22 + n*) tscsi + 20 15 128 tscsi + 15 52 tscsi + 15 8 tscsi + 15 9 tscsi + 20 9 tscsi + 20 Unit ns ns ns ns
ID outputBSY BSYBSYoutput BSYoutput SEL & ID hold * : SCSI block TCL register value
ts035 ts052 ts053
ns ns ns
BSY
tS031 tS033 tS035 tS052 tS053
SEL
tS032 tS051
DB0 to DB7, DBP
IO
CD, MSG
31
MB86616
5-6 Initiator Reselection Operation Parameter SELBSY ID assertBSY IOBSY BSYBSY BSYSEL BSYID hold BSYIO hold SELBSY (Output stop) Symbol ts011 ts012 ts061 ts014 ts015 ts016 ts062 ts063 Pin name SEL, BSY DB0 to DB7, DBP, BSY IO, BSY BSY BSY, SEL BSY, DBP, DB0 to DB7 BSY, IO SEL, BSY Values Min. 0 0 0 18 tscsi 0 10 10 8 tscsi Max. 19 tscsi + 20 9 tscsi + 20 Unit ns ns ns ns ns ns ns ns
BSY
tS011 tS014 tS015 tS063
SEL
tS012 tS016
DB0 to DB7, DBP
tS061 tS062
IO
32
MB86616
5-7 Target Asynchronous Transfer (REQ/ACK Timing) Parameter REQACK ACKREQ REQACK ACKREQ (Note 2) ACKREQ (Notes 1, 2) Symbol ts071 ts072 ts073 ts074 ts075 Pin name REQ, ACK ACK, REQ REQ, ACK ACK, REQ ACK, REQ Values Min. 0 0 0 0 8 tscsi Max. 25 25 9 tscsi + 5 Unit ns ns ns ns ns
Note1 : The "ACK rise to REQ fall" time is regulated by (ts072 + ts073 + ts074) or ts075, whichever is longer. Note2 : In the following cases, the time regulation is not applied because data transfer is aborted. * The data register is empty during data output to the SCSI bus. * The data register is full during data input from the SCSI bus.
REQ
tS071 tS072 tS073 tS074
ACK
tS075
33
MB86616
5-8 Target Asynchronous Transfer (Data Output) Parameter IOData bus drive Data output assertREQ ACKData hold Symbol ts081 ts082 ts083 Pin name IO, DBP, DB0 to DB7 DB0 to DB7, DBP, REQ ACK, DBP, DB0 to DB7 Values Min. 33 tscsi 8 tscsi - 5 0 Max. 34 tscsi + 10 Unit ns ns ns
REQ
ACK
tS082 tS083
DB0 to DB7, DBP
tS081
IO
34
MB86616
5-9 Target Asynchronous Transfer (Data Input) Parameter IOData bus driving stop Data setupACK REQData hold Symbol ts091 ts092 ts093 Pin name IO, DBP, DB0 to DB7 DB0 to DB7, DBP, ACK REQ, DBP, DB0 to DB7 Values Min. 0 10 5 Max. 10 Unit ns ns ns
REQ
ACK
tS092 tS093
DB0 to DB7, DBP
tS091
IO
35
MB86616
5-10 Target Synchronous Transfer (REQ/ACK Timing) Parameter REQ assert time REQ negate time ACK assert time ACK negate time ACK cycle time (1) ACK cycle time (2) Symbol ts101 ts102 ts103 ts104 ts105 ts106 Pin name REQ REQ ACK ACK ACK ACK Values Min. n**tscsi n**tscsi 10 10 1 tscsi 3 tscsi Max. Unit ns ns ns ns ns ns
* : Value set in bits 3 to 0 in the SCSI block TMOD register
REQ
tS101 tS102
ACK
tS103 tS105 tS106 tS104
36
MB86616
5-11 Target Synchronous Transfer (REQ Output Delay Time) Parameter REQ output delay time (Note) Symbol ts111 Pin name ACK, REQ Values Min. 3 tscsi Max. 4 tscsi + 10 Unit ns
Note : The minimum time from the reception of ACK in the (N-m) -th byte to the output of REQ in the N-th byte with Maximum offset count = m. The following timing chart assumes that REQ output is aborted because output of REQ in the N-1-th byte has made the number of offsets the maximum offset count = m. The maximum offset count is set by bits 7 to 4 in the SCSI block transfer mode register.
REQ
N-2
N-1 tS111
N
ACK
N-m
37
MB86616
5-12 Target Synchronous Transfer (Data Output) Parameter IOData bus drive Symbol ts081 ts121 Data output assertREQ ts122 REQData hold ts123 Pin name IO, DBP, DB0 to DB7 DB0 to DB7, DBP, REQ DB0 to DB7, DBP, REQ DB0 to DB7, DBP, REQ Values Min. 33 tscsi 8 tscsi - 5 n**tscsi - 5 n**tscsi Max. 34 tscsi + 10 Unit ns ns ns ns
* : Value set in bits 3 to 0 in the SCSI block TMOD register
REQ
tS121 tS123 Asserted data tS081 tS122
DB0 to DB7, DBP
IO
38
MB86616
5-13 Target Synchronous Transfer (Data Input) Parameter IOData bus driving stop Data setupACK ACKData hold Symbol ts091 ts131 ts132 Pin name IO, DBP, DB0 to DB7 DB0 to DB7, DBP, ACK ACK, DBP, DB0 to DB7 Values Min. 0 5 5 Max. 10 Unit ns ns ns
ACK
tS131 tS132
DB0 to DB7, DBP
tS091
IO
39
MB86616
5-14 Initiator Asynchronous Transfer (REQ/ACK Timing) Parameter REQACK (Note 3) ACKREQ REQACK (Note 3) ACKREQ REQACK (Notes 1, 3) REQACK (Notes 2, 3) REQACK (Notes 2, 3) Symbol ts141 ts142 ts143 ts144 ts145 ts146 ts147 Pin name REQ, ACK ACK, REQ REQ, ACK ACK, REQ REQ, ACK REQ, ACK REQ, ACK Values Min. 0 0 0 0 8 tscsi 4 tscsi 8 tscsi Max. 25 1 tscsi 9 tscsi + 5 5 tscsi + 5 9 tscsi + 5 Unit ns ns ns ns ns ns ns
Note1 : Applies to data output to the SCSI bus. The "REQ rise to ACK fall" time is regulated by (ts143 + ts144 + ts141) or ts145, whichever is longer. Note2 : Applies to data input from the SCSI bus. The "REQ rise to ACK fall" time is regulated by (ts143 + ts144 + ts141) or ts146, whichever is longer. The "REQ fall to ACK rise" time is regulated by (ts141 + ts142 + ts143) or ts147, whichever is longer. Note3 : In the following cases, either time regulation is not applied because data transfer is aborted. * The data register is empty during data output to the SCSI bus. * The data register is full during data input from the SCSI bus. * ATN is output upon detection of a parity error during data input from the SCSI bus. * During transfer of the first or last byte
tS145, tS146
REQ
tS141 tS142 tS143 tS144
ACK
tS147
40
MB86616
5-15 Initiator Asynchronous Transfer (Data Output) Parameter IOData bus drive Phase signal assertREQ Data output assertACK REQData hold ACKPhase signal hold Symbol ts151 ts152 ts153 ts154 ts155 Pin name IO, DBP, DB0 to DB7 IO, CD, MSG, REQ DB0 to DB7, DBP, ACK REQ, DBP, DB0 to DB7 ACK, IO, CD, MSG Values Min. 0 30 8 tscsi - 5 0 10 Max. 10 Unit ns ns ns ns ns
REQ
tS152
ACK
tS153 tS154 Asserted data tS151 tS155
DB0 to DB7, DBP
IO
CD, MSG
41
MB86616
5-16 Initiator Asynchronous Transfer (Data Input) Parameter IOData bus drive stop Phase signal assertREQ Data setupREQ ACKData hold ACKPhase signal hold Symbol ts161 ts152 ts162 ts163 ts155 Pin name IO, DBP, DB0 to DB7 IO, CD, MSG, REQ DB0 to DB7, DBP, REQ ACK, DBP, DB0 to DB7 ACK, IO, CD, MSG Values Min. 30 10 5 10 Max. 30 Unit ns ns ns ns ns
REQ
tS152
ACK
tS162 tS163
DB0 to DB7, DBP
tS161 tS155
IO
CD, MSG
42
MB86616
5-17 Initiator Synchronous Transfer (REQ/ACK Timing) Parameter REQ assert time REQ negate time REQ cycle time (1) REQ cycle time (2) ACK assert time ACK negate time Symbol ts171 ts172 ts173 ts174 ts175 ts176 Pin name REQ REQ REQ REQ ACK ACK Values Min. 10 10 1 tscsi 3 tscsi n**tscsi n**tscsi Max. Unit ns ns ns ns ns ns
* : Value set in bits 3 to 0 in the SCSI block TMOD register
tS174 tS173 tS171 tS172
REQ
tS175 tS176
ACK
43
MB86616
5-18 Initiator Synchronous Transfer (ACK Output Delay Time) Parameter ACK output delay time (1) (Notes 1, 2) ACK output delay time (2) (Notes 1, 3) Symbol ts181 ts182 Pin name REQ, ACK REQ, ACK Values Min. 9 tscsi 3 tscsi Max. 12 tscsi + 5 4 tscsi + 5 Unit ns ns
Note1 : The minimum time from the reception of REQ in the N-th byte to the output of ACK in the N-th byte. Note2 : Applies to data input from the SCSI bus, with the maximum offset count set to 8 to 15. The maximum offset count is set by bits 7 to 4 in the SCSI block transfer mode register. Note3 : Applies in any case other than Note 2.
REQ
N-1
N tS181, tS182
N+1
ACK
N-2
N-1
N
44
MB86616
5-19 Initiator Synchronous Transfer (Data Output) Parameter IOData bus drive Phase signal assertREQ Symbol ts151 ts152 ts191 Data output assertACK (Note ) ts192 Pin name IO, DBP, DB0 to DB7 IO, CD, MSG, REQ DB0 to DB7, DBP, ACK DB0 to DB7, DBP, ACK DB0 to DB7, DBP, ACK ACK, IO, CD, MSG Values Min. 0 30 8 tscsi - 5 n**tscsi - 5 n**tscsi Max. 10 Unit ns ns ns ns
ACKData hold
ts193
ns
ACKPhase signal hold
ts155
10
ns
* : Value set in bits 3 to 0 in the SCSI block TMOD register Note : The "data output assert to ACK fall" time is regulated by ts191 or ts192, whichever is shorter.
REQ
tS152
ACK
tS191 tS193 tS192
DB0 to DB7, DBP
tS151
Asserted data tS155
IO
CD, MSG
45
MB86616
5-20 Initiator Synchronous Transfer (Data Input) Parameter IOData bus drive stop Phase signal assertREQ Data setupREQ REQData hold ACKPhase signal hold Symbol ts161 ts152 ts162 ts201 ts155 Pin name IO, DBP, DB0 to DB7 IO, CD, MSG, REQ DB0 to DB7, DBP, REQ REQ, DBP, DB0 to DB7 ACK, IO, CD, MSG Values Min. 30 5 5 10 Max. 30 Unit ns ns ns ns ns
REQ
tS152
ACK
tS162 tS201
DB0 to DB7, DBP
tS161 tS155
IO
CD, MSG
46
MB86616
5-21 Arbitration Failure Parameter Arbitration start BSY & Self-ID output stop Other device's SEL BSY & Self-ID output stop Symbol ts211 Pin name BSY, DBP, DB0 to DB7 SEL, BSY, DB0 to DB7, DBP Values Min. 128 tscsi - 10 8 tscsi Max. 128 tscsi + 15 9 tscsi + 20 Unit ns
ts212
ns
tS211
BSY
tS212
SEL
DB0 to DB7, DBP
47
MB86616
5-22 Selection/Reselection Time-out Parameter TIME OUT interrupt reset SCSI bus clear Symbol ts222 Pin name SEL, IO, DBP, DB0 to DB7 Values Min. 3 tscsi - 10 Max. 3 tscsi + 15 Unit ns
Write strobe
tS221
SEL
DB0 to DB7, DBP
IO
48
MB86616
5-23 Target Disconnect Operation Parameter REL command issue BSY REL command issueSCSI bus clear Symbol ts231 ts232 Pin name BSY REQ, IO, CD, MSG, DBP, DB0 to DB7 Values Min. 3 tscsi - 10 3 tscsi - 10 Max. 3 tscsi + 15 3 tscsi + 15 Unit ns ns
Write strobe
tS231
BSY
tS232
DB0 to DB7, DBP
REQ, IO, CD, MSG
49
MB86616
5-24 Initiator Disconnect Operation Parameter Symbol Pin name BSY, ACK, ATN, DBP, DB0 to DB7 Values Min. Max. 21 tscsi + 20 Unit
BSYSCSI bus clear
ts241
ns
BSY
tS241
DB0 to DB7, DBP
ATN, ACK
50
MB86616
5-25 Reset Condition Detection Parameter Reset condition detection time RSTSCSI bus clear Symbol ts251 ts252 Pin name RST All SCSI bus pins Values Min. 12 tscsi Max. 12 tscsi + 20 Unit ns ns
tS251
RST
tS252
SCSI bus signals other than RST
51
MB86616
5-26 Reset Condition Generation Parameter Write "1" to RST OUT bit RST RSTSCSI bus clear Write "0" to RST OUT bit RST Symbol ts261 ts262 ts263 Pin name RST All SCSI bus pins RST Values Min. Max. 10 10 10 Unit ns ns ns
Write strobe
tS261
RST
tS262
SCSI bus signals other than RST
52
MB86616
(6) IEEE 1394/SCSI/Exchange Block Register Access 6-1 Read Operation Values Min. 10 5 40 5 45 Max. 25
Parameter Address setup Address hold RD "L" level pulse width RDValid data RDData hold WRRD
Symbol tRAVRL tRRHAX tRRLRH tRRLDV tRRHDX tRWHRL
Pin name A01 to A09, CS, RD A01 to A09 CS, RD RD RD, D00 to D15 RD, D00 to D15 WR, RD
Unit ns ns ns ns ns ns
A01 to A09
CS
tRAVRL tRRLRH tRRHAX
RD
tRRHDX tRRLDV
D00 to D15
tRWHRL
WR
53
MB86616
6-2 Write Operation Parameter Address setup Address hold WR "L" level pulse width Data setup Data hold Symbol tRAVWL tRWHAX tRWLWH tRDVWH tRWHDX Pin name A01 to A09, CS, WR A01 to A09 CS, WR WR WR, D00 to D15 WR, D00 to D15 Values Min. 10 5 40 30 5 Max. Unit ns ns ns ns ns
A01 to A09
CS
tRAVWL tRWLWH tRWHAX
WR
tRDVWH tRWHDX
D00 to D15
54
MB86616
6-3 Register Access Recovery Time * Continuous Read/Write Operation Shown below is the timing of continuously reading or writing the register at the same address. Values Min. 25 45 Max.
Parameter RD (WR) RD (WR) RD (WR) RD (WR) (Note)
Symbol tRWHRWL1 tRWHRWL2
Pin name RD/WR WR/RD
Unit ns ns
Note : Applies to access to an internal register of the IEEE 1394 block in forced sleep mode.
tRWHRWL1, 2
RD (WR)
* Write OperationRead Operation Shown below is the timing of reading after writing the register at the same address. Values Min. 80 160 Max.
Parameter WRRD WRRD (Note )
Symbol tWRHRDL1 tWRHRDL2
Pin name WR, RD WR, RD
Unit ns ns
Note : Applies to access to an internal register of the IEEE 1394 block in forced sleep mode.
WR
tWRHRDL1, 2
RD
55
MB86616
* IEEE 1394 Block PHY/LINK Register Read Operation Shown below is the timing from writing the PHY/LINK register address set register (address 002038h) to reading the PHY/LINK access port (address 00203Ah) to access the PHY-LINK register in the IEEE 1394 block. Values Min. 100 200 Max.
Parameter WRRD WRRD (Note )
Symbol tPLWHRL1 tPLWHRL2
Pin name WR, RD WR, RD
Unit ns ns
Note : Applies to access in forced sleep mode.
tPLWHRL1, 2
WR Write to address 002038h RD Read from address 00203Ah
* IEEE 1394 Block PHY/LINK Register Write Operation Shown below is the timing from writing the PHY/LINK register address set register (address 002038h) to writing the PHY/LINK access port (address 00203Ah) to access the PHY-LINK register in the IEEE 1394 block. Values Min. 100 Max.
Parameter WRWR
Symbol tPLWHWL1
Pin name WR
Unit ns
tPLWHWL1, 2
WR Write to address 002038h Write to address 00203Ah
56
MB86616
s SYSTEM CONFIGURATION EXAMPLES
1. Recommended Connection Example of IEEE 1394 Port (1 Port)
TPBIAS 56 1% 1 F 5%
TPA 56 1% TPA
Cable
TPB
Cable
TPB
TPB 56 1% TPB 56 1%
Cable
TPA
Cable
TPA
5.1 k 1%
250 pF 5%
R0 5.1 k 1%
Cable Power Cable 510 k 5% CPS 91 k 5% Cable Ground Power (8 to 33 V)
57
MB86616
2. Recommended Connection Example of Internal PLL Loop Filter
FIL
390 5%
3300 pF 5%
RF 5.1 k 1%
58
MB86616
3. Sample System Configurations
* Normal Mode (Using the Internal CPU)
RESET SCLK MODEA
TPA0 TPA0 TPB0 TPB0 IEEE1394 Connector0
MODEB, MODEC
TPBIAS0
MD0 to MD2
TPA1 MB86616 TPA1 A01 to A18 WR External flash ROM RD CS D00 to D15 PMODE TPB1 TPB1 TPBIAS1 IEEE1394 Connector1
P74 to P76, P90 to P93
PWR1 to PWR3
DB0 to DB7
MSG
REQ
ACK
SCSI Connector
DBP
BSY
RST
ATN
SEL
CD
IO
59
MB86616
* External CPU Mode
RESET SCLK MODEA
TPA0 TPA0 TPB0 TPB0 IEEE1394 Connector0
MODEB, MODEC
TPBIAS0
MD0 to MD2
TPA1 MB86616 TPA1 A01 to A09 WR RD External CPU CS D00 to D15 INT0 INT1 PWR1 to PWR3 PMODE TPB1 TPB1 TPBIAS1 IEEE1394 Connector1
DB0 to DB7
MSG
REQ
ACK
SCSI Connector
60
DBP
BSY
RST
ATN
SEL
CD
IO
MB86616
s ORDERING INFORMATION
Part number MB86616PFV-G-BND Package 144-pin Plastic LQFP (FPT-144P-M08) Remarks
61
MB86616
s PACKAGE DIMENSION
144-pin Plastic LQFP (FPT-144P-M08)
22.000.30(.866.012)SQ 20.000.10(.787.004)SQ 1.70(.67)MAX (Mounting height)
73 72
108 109
0(0)MIN (STAND OFF)
17.50 (.686) REF INDEX
144 37
21.00 (.827) NOM
Details of "A" part 0.15(.006)
0.15(.006) 0.15(.006)MAX 0.40(.016)MAX "A"
LEAD No.
1
36
Details of "B" part
M
0.50(.0197)TYP
0.200.10 (.008.004)
0.08(.003)
0.150.05 (.006.002) 0 10
0.10(.004)
0.500.20(.020.008) "B"
C
2000 FUJITSU LIMITED F144019S-1C-3
Dimensions in mm (inches)
62
MB86616
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fujitsu-fme.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmap.com.sg/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F0008 (c) FUJITSU LIMITED Printed in Japan

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