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The TQ6124 is a 14-bit monolithic digital-to-analog converter. The TQ6124 achieves conversion accuracy by using a segmented architecture, precision current sources, and on-chip nichrome resistors. The only external components required are an external reference and loop control amplifier. The TQ6124 is ideally suited for applications in direct digital synthesis, pixel generation for high-resolution monitors, broadband video generation, and high-speed arbitrary waveform generators.
TQ6124
1 Gigasample/sec, 14-bit Digital-to-Analog Convertor
Features
Figure 1. TQ6124 Block Diagram * 1Gs/s aggregate bandwidth
LSBs
CLK NCLK D0 D1 D2 D3 D4 D5 D6
Intermediate Bits
D7 D8 D9
MSBs
D10 D11 D12 D13
* 14-bit resolution * RF front end * ECL-compatible inputs
Master Latch
* 0.026% DC differential non-linearity * 0.035% DC integral non-linearity
MIXED SIGNAL PRODUCTS
Delay Stages
S1
S2
... ... ...
S14 S15
Segment Encoders
* SFDR: 52 dBc @ FOUT = 75 MHz 48 dBc @ FOUT = 148 MHz 45 dBc @ FOUT = 199 MHz * 1.4 W power dissipation * 44-pin ceramic QFP package or die only
Slave Latch
Current Switches
Applications
* Direct Digital Synthesis * Pixel generation for workstations and high-end monitors
50 ohm R-2R Ladder Network
VO VAA MID_trim LSB_trim VREF VSENSE NVO
* Direct-generation of broadband video for cable TV * High-speed arbitrary waveform generators
Current Source Array
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1
TQ6124
Functional Description
The TQ6124 registers incoming bits in a master latch array. The value of the four most-significant bits is encoded into an n-of-15 thermometer code while the ten low-order bits pass though an equalizing delay stage. All 25 bits are re-registered in a 25-wide slave latch array which drives a set of 25 differential pair switches. These switches steer the corresponding segment and bit currents into the true (VO) and complementary (NVO) outputs. This architecture minimizes glitch impulses by eliminating large mid-scale current transitions. The most-significant bits generate the segment currents, which are of equal weight at 1/16 of the fullscale output (IFS). The ten lower-order bits are divided into two subgroups. The three intermediate bits steer binary-weighted currents of magnitude IFS/32, IFS/64 and IFS/128 to the outputs. The seven least-significant bits steer identical IFS/128 currents into a differential R-2R ladder to generate effective bit currents of IFS/256 to IFS/16384. The DAC output is the sum of the outputs of the segments and the low-order bits. Clock and data inputs are ECL-compatible. The outputs are designed to operate into a 50 load, with internal reverse termination to ground being provided by the R-2R network. External compensation is utilized to minimize the effects of device mismatch. An external op amp senses the sum of the segment, the intermediate bit, and the LSB currents.
Figure 2. TQ6124 Currents
Segments 1 thru 15
VO NVO Q ID9 NQ 1.25mA 2.5mA ID8 .625mA ID7 dummy ID6 .3125mA (x8) dummy .3125mA
To switches for D0 thru D9
.3125mA .3125mA
VREF
VSENSE R SENSE 5.8K R SOURCE 1.2K RSENSE 5.8K R SOURCE 1.2K VAA R SENSE 5.8K R SOURCE 1.2K
MID_trim
LSB_trim
2
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TQ6124
Electrical Specifications
Table 1. Recommended Operating Conditions
Symbol
VSS VAA TC
Parameter
Negative Power Supply Analog Power Supply Case Temperature
Min.
-5.25 -15.5 -20
Nom.
-5.0 -12
Max.
-4.75 -11.5 85
Unit
V V C
Table 2. DC Operating Characteristics Unless otherwise specified, measured over Recommended Operating Conditions with balanced 50 loads, VFS = 1.0 V.
Symbol
IAA ISS VREF IREF VIH VIL II VEREF REREF DNL INL VFS ROUT VO, NVO VZS VSENSE JC
Parameter
VAA Supply Current VSS Supply Current Reference Voltage Reference input current ECL Input High Voltage ECL Input Low Voltage ECL Input Current ECL Reference Voltage ECL Reference Resistance Differential non-linearity Integral non-linearity Full-scale symmetry Full-scale output voltage VO, NVO, output resistance ROUT Matching Output Voltage Zero Scale Voltage Sense output voltage Thermal Impedance
Condition
Min.
Nom.
-75 -285
Max.
-90 -450 VAA + 3.75 25 -0.6 -1.5 25
Unit
mA mA V mA V V mA V ohms %F.S. %F.S. mV V ohms % V mV V C/W MIXED SIGNAL PRODUCTS
VEREF = -1.3 V VEREF = -1.3 V VSS = -5.0 V (Note 2) (Note 2) (Note 1) RL = 50 ohms
VAA + 2.5 -25 -1.1 -2.5 -25
VAA + 3.0
-0.05 -0.05 -8 44 -2.5 -1.125 -50 VAA + 2.5
-1.34 400 0.026 0.035 2 -1.0 50.9 0.15 -40 15
0.05 0.05 8 -1.125 57 2.5 0 0 VAA + 3.75
Notes: 1. Full-scale symmetry is a measure of the balance between VO and NVO. For a full-scale output transition, the change in VO will match the change in NVO to within the specified amount. Any imbalance in the output loads will affect symmetry. 2. Linearity can interpreted as 10 bits at 1/2 LSB or as 11 bits at 1 LSB. The device is monotonic to 10 bits. Linearity is tested with the Mid_trim set for optimal DNL, with the LSB_trim pin open.
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3
TQ6124
Table 3. AC Operating Characteristics
Unless otherwise noted, measured over DC operating characteristics with balanced 50 loads, VFS = 0.8V, VIN = 0.8VP-P, input rise and fall times 300 ps.
Symbol
FCLK tR , tF tDS tDH tCLKHI tCLKLO SFDR*
Parameter
Clock Frequency At full scale Data Setup Time Data Hold Time Clock High Time Clock Low Time Spurious free dynamic range
Condition
10% to 90%
Min.
50 200 300 400
Typ.
Max.
1000 350
Unit
MHz ps ps ps ps
FOUT = 75 MHz FOUT = 148 MHz FOUT = 199 MHz
400 45 45 45
52 52 49
ps dBc dBc dBc
*Note: SFDR testing performed at FCLK = 600 MHz only.
Table 4. Absolute Maximum Ratings
Symbol
VSS VAA VO, NVO VI II VREF IREF TSTG TJ
Parameter
Digital Supply Analog Supply Analog Output Voltage Digital Input Voltage Digital Input Current Reference Voltage Reference Current Power Dissipation Storage Temperature Operating Junction Temperature
Min.
-7.0 -16.0 -2.0 VSS - 0.5 -1.0 VAA-2 -1 -65
Max.
Unit
V V V V mA V mA W C C
2.0 +0.5 +1.0 0 1 5 150 150
Note: Absolute Maximum Ratings are those beyond which the integrity of the device cannot be guaranteed. If the device is subjected to the limits in the absolute maximum ratings, its reliability may be impaired. The Electrical Specifications tables provide conditions for actual device operation.
4
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TQ6124
AC Timing
The low-going transition of CLK latches the data. Production SFDR testing is performed with the clock transitioning in the center of the data eye. The timing of the clock transition with respect to the data can improve SFDR performance. Systems working to optimize SFDR can 'tune' this phase relationship to optimize the desired characteristic.
Figure 3. AC Timing Relationships
tDS Data tDH
Clock
Operating Notes
Current Source Control Loop The full scale output voltage is set through the use of an external op amp, as shown in Figure 4. Nominal full scale output voltage can be achieved by using a voltage source. With this, control voltages on the op amp of around VAA+3V can be set. Adjusting the full scale output voltage can be achieved by toggling the inputs over full scale while adjusting the control voltage to achieve the desired level.
VAA
Figure 4. Adjusting the Full-Scale Output Voltage
VAA
1K 620 20 K +
1 K 20 K 1 K 20 K 1 K MID_TRIM LSB_TRIM
+VIN
AD586
VOUT
VREF
- MC34071
VAA
VAA
VSENSE
VREF Adjustment Range The output full scale voltage range can be set through the VREF input. Figure 5 shows the approximate relationship between VREF and VFS.
Figure 5. Full-Scale Output Voltage vs. VREF
1.2
Full-Scale Output Voltage
1.0 0.8 0.6 0.4 0.2
-1
0
1 2 3 Reference Voltage (vs VAA)
4
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5
MIXED SIGNAL PRODUCTS
TQ6124
Operating Notes (continued)
Power Supplies Optimized performance depends on clean supplies. Utilize very low impedance negative supplies that are decoupled over a wide frequency range. The analog and digital grounds should be isolated at the chip, connecting to a single point ground on the circuit board. ECL Reference The single-ended data inputs switch against an internal reference of -1.3V (nominal). Variations among input buffers, or in VTT, may benefit from adjustments in the reference. The ECL reference pin may be driven externally. Its equivalent load is 400 ohms to -1.3V (nominal). Trim Adjustments The external trim adjustments for the midrange bits and the LSBs is optional. Trimming is performed by monitoring the attribute of greatest concern (INL, DNL, Spurious levels) while minimizing the unwanted effects. Trim inputs should be left open if not used.
Signals
Figure 6. TQ6124 Pinout
40 DGND 39 D 6 38 D 5 37 DGND 44 VSS 43 D9 42 D8 41 D 7 36 D 4 35 D 3 34 VSS
VSS D10 D11 D12 D13 (MSB) DGND DGND DGND CLK NCLK VSS
1 2 3 4 5 6 7 8 9 10 11
33 32 31 30 29 28 27 26 25 24 23
VSS D2 D1 D 0 (LSB) DGND DGND ECLref LSBtrim Midtrim VAA VAA
TQ6124
Top View
12
AGND 13
14 I REF AGND 15 16 NVO
17
AGND 18 AGND 19 20 VSNS 21 V REF
VSS
6
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VAA
VO
22
TQ6124
Table 5. Signal-Pin Descriptions
Signal
DGND AGND D0 thru D13 VO, NVO CLK, NCLK IREF VSENSE VREF VSS VAA Mid_trim LSB_trim ECLref
Pin(s)
6, 7, 8, 28, 29, 37, 40 13, 15, 18, 19 30, 31, 32, 35, 36, 38, 39, 41, 42, 43, 2, 3, 4, 5 17, 16 9, 10 14 20 21 1, 11, 12, 33, 34, 44 22, 23, 24 25 26 27
Description
Ground connection for digital circuitry. Ground connection for analog circuitry. Data inputs. D0 is the least significant bit. ECL levels. True and complementary analog outputs. True and complementary clock inputs. ECL levels. Connect to AGND. Source of dummy currents in the switch array. Sense Output. Reference Input. Digital negative power supply. Analog negative power supply. Trim terminal for mid range bits. Trim terminal for LSB range bits. Optional ECL reference level adjustment. Thevinin equivalent is 1.3V nominally into 400 ohms. Equivalent voltage tracks with digital supply. MIXED SIGNAL PRODUCTS
Typical Performance Data
The graph in Figure 7 shows representative performance data of spurious free dynamic range (SFDR) vs. output frequency performance measured from TQ6124 devices. Data was collected at room temperature; note, however, that SFDR is not strongly dependendent on temperature. Optimum performance is obtained by utilizing as high a clock rate as practical.
Figure 7. SFDR vs. Output Frequency
-65 -60 -55 -50
SFDR
-45 -40 -35 -30 0 50 100 150 200 250 300 350 400 450 500
FOUT
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7
TQ6124
Packaging
Figure 8. 44-pin QFP Package Dimensions Top View
0.805 .650
44
BottomView
Pin 1 Index
1
A
A
Ceramic or metal lid
.050
.015 BSC
All dimensions in inches
Section A-A
Device .125
Seating plane .035 typ. .065
8
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TQ6124
Ordering Information
TQ6124-CM TQ6124-CD ETF6124
Additional Information
1 GS/s 14-bit DAC in 44-pin ceramic QFP 1 GS/s 14-bit DAC -- die only Engineering Test Fixture with TQ6124 device
For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: sales@tqs.com Tel: (503) 615-9000 Fax: (503) 615-8900
For technical questions and additional information on specific applications: Email: applications@tqs.com
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright (c) 1997 TriQuint Semiconductor, Inc. All rights reserved. Revision 1.1.A November 1997
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9
MIXED SIGNAL PRODUCTS

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