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80CL410/83CL410 Low voltage/low power single-chip 8-bit microcontroller with I2C
Product specification IC20 Data Handbook 1995 Jan 20
Philips Semiconductors
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
FEATURES
* Single supply voltage 1.8V to 6.0V * Frequency from DC to 12MHz * 80C51 based architecture
- 4k x 8 ROM (64k external) - 128 x 8 RAM (64k external) - Four 8-bit I/O ports - Two 16-bit timer/counters - A thirteen-source, two-level, nested priority interrupt structure - 10 external interrupts
PIN CONFIGURATION
INT2/P1.0 1 INT3/P1.1 2 INT4/P1.2 3 INT5/P1.3 4 INT6/P1.4 5 INT7/P1.5 6 SCL/INT8/P1.6 7 SDA/INT9/P1.7 8 RST 9 P3.0 10 P3.1 11 INT0/P3.2 12 INT1/P3.3 13 T0/P3.4 14 T1/P3.5 15 WR/P3.6 16 RD/P3.7 17 XTAL2 18 XTAL1 19 VSS 20 44 DIP VSO 40 V DD 39 P0.0/AD0 38 P0.1/AD1 37 P0.2/AD2 36 P0.3/AD3 35 P0.4/AD4 34 P0.5/AD5 33 P0.6/AD6 32 P0.7/AD7 31 EA 30 ALE 29 PSEN 28 P2.7/A15 27 P2.6/A14 26 P2.5/A13 25 P2.4/A12 24 P2.3/A11 23 P2.2/A10 22 P2.1/A9 21 P2.0/A8
DESCRIPTION
The 80CL410/83CL410 (hereafter generically referred to as 8XCL410) is manufactured in an advanced CMOS process that allows the part to operate at supply voltages down to 1.8V and oscillator frequencies down to DC. The 8XCL410 has the same instruction set as the 80C51. The 8XCL410 features a 4k byte ROM (83CL410), 128 bytes RAM (both ROM and RAM are externally expandable to 64k bytes), four 8-bit ports, two 16-bit timer/counters, an I2C serial interface, a thirteen source, two priority level nested interrupt structure, and on-chip oscillator circuitry suitable for quartz crystal, ceramic resonator, RC, or LC. The 8XCL410 has two reduced power modes that are the same as those on the standard 80C51. The special reduced power feature of this part is that it can be stopped and then restarted. Running from an external clock source, the clock can be stopped and after a period of time restarted. The 8XCL410 will resume operation from where it was when the code stopped with no loss of internal state, RAM contents, or Special Function Register contents. If the internal oscillator is used the part cannot be stopped and started, but the power-down mode, which can be terminated via an interrupt, can be used to achieve similar power savings and then restart without loss of on-chip RAM and Special Function Register values.
* Fully static 80C51 CPU * I2C Serial Interface * Two power control modes
- Idle mode - Power-down mode - can be terminated by reset or external interrupt
* Wake-up via external interrupts at port 1 * Single supply voltage 1.8V to 6.0V * Frequency range of DC to 12MHz * On-chip oscillator (quartz crystal, ceramic
resonator, RC, LC)
* Very low power consumption * Operating temperature range:
-40 to +85C
34
1
33
QFP 11 23
12
22
SEE NEXT PAGE FOR QFP PIN FUNCTIONS.
ORDERING CODE
PHILIPS PART ORDER NUMBER PART MARKING ROMless P80CL410HFP ROM P83CL410HFP PHILIPS NORTH AMERICA PART ORDER NUMBER1 ROMless ROM TEMPERATURE C AND PACKAGE -40 to +85, 40-Pin Plastic Dual In-line Package -40 to +85, 40-Pin Plastic Very Small Outline Package -40 to +85, 44-Pin Plastic Quad Flat Pack FREQUENCY 32kHZ to 12MHz Drawing Number SOT129-1
P80CL410HF N P83CL410HF N
P80CL410HFT
P83CL410HFT
P80CL410HF D P83CL410HF D
32kHZ to 12MHz
SOT158-1
P83CL410HFH
32kHZ to 12MHz
SOT307-2
NOTE: 1. Parts ordered by the Philips North America part number will be marked with the Philips part marking. For emulation purposes, the P85CL000 (Piggyback version) with 256 bytes of RAM is recommended. 1995 Jan 20 2
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
PLASTIC QUAD FLAT PACK PIN FUNCTIONS
44 34
LOGIC SYMBOL
VDD XTAL1 VSS
QFP XTAL2 11 23 RST EA 12 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function P1.5/INT7 P1.6/INT8/SCL P1.7/INT9/SDA RST P3.0 NC P3.1 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS NC P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 22 Function Alternate Functions P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE NC EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD NC P1.0/INT2 P1.1/INT3 P1.2/INT4 P1.3/INT5 P1.4/INT6 PSEN ALE Port 1 INT2 INT3 INT4 INT5 INT6 INT7 INT8/SCL INT9/SDA
INT0 INT1 T0 T1 WR RD
Port 3
Port 2
Port 0
1
33
Address and Data Bus
Address Bus
1995 Jan 20
3
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
BLOCK DIAGRAM
FREQUENCY REFERENCE XTAL2 XTAL1 COUNTER (1) T0 T1
OSCILLATOR AND TIMING
PROGRAM MEMORY (4K x 8 ROM)
DATA MEMORY (128 x 8 RAM)
TWO 16-BIT TIMER/EVENT COUNTERS
CPU
10
3
INTERNAL INTERRUPTS
64K BYTE BUS EXPANSION CONTRTOL
PROGRAMMABLE I/O
I2C-BUS SERIAL I/O
EXTERNAL INTERRUPTS (1) (1) Pins shared with parallel port pins.
CONTROL
PARALLEL PORTS, ADDRESS/DATA BUS AND I/O PINS
SDA (1)
SCL
1995 Jan 20
4
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
PIN DESCRIPTION
PIN NO. MNEMONIC QFP VSS VDD P0.0-0.7 16 38 30-37 DIL40/ VSO40 20 40 39-32 TYPE NAME AND FUNCTION
I I I/O
Ground: 0V reference. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Additional functions include: SCL (P1.6): I2C serial bus clock. SDA (P1.7): I2C serial bus data. INT2-INT9 (P1.0-P1.7): Additional external interrupts. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as listed below: INT0 (P3.2): External interrupt 0 INT1 (P3.3): External interrupt 1 T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VDD. Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to 0FFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 0FFFH. Crystal 1: Input to the inverting oscillator amplifier and input for an external clock source. Crystal 2: Output from the inverting oscillator amplifier.
P1.0-P1.7
40-44 1-3
1-8
I/O
7 8 1-8 P2.0-P2.7 18-25 21-28
I/O I/O I I/O
P3.0-P3.7
5, 7-13
10-17
I/O
8 9 10 11 12 13 RST 4
12 13 14 15 16 17 9
I I I I O O I
ALE
27
30
O
PSEN
26
29
O
EA
29
31
I
XTAL1 XTAL2
15 14
19 18
I O
1995 Jan 20
5
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
Table 1. 8XCL410 Special Function Registers
SYMBOL ACC* B* DPTR: DPH DPL IP0*# IP1*# DESCRIPTION Accumulator B register Data pointer (2 bytes): High byte Low byte Interrupt priority 0 Interrupt priority 1 DIRECT ADDRESS E0H F0H BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB E7 F7 E6 F6 E5 F5 E4 F4 E3 F3 E2 F2 E1 F1 E0 F0 RESET VALUE 00H 00H
83H 82H BF B8H F8H - FF PX9 AF BE - FE PX8 AE - EE EX8 C6 IQ8 86 96 A6 B6 - D6 AC BD PS1 FD PX7 AD ES1 ED EX7 C5 IQ7 85 95 A5 B5 - D5 F0 BC - FC PX6 AC - EC EX6 C4 IQ6 84 94 A4 B4 - D4 RS1 BB PT1 FB PX5 AB ET1 EB EX5 C3 IQ5 83 93 A3 B3 GF1 D3 RS0 BA PX1 FA PX4 AA EX1 EA EX4 C2 IQ4 82 92 A2 B2 GF0 D2 OV B9 PT0 F9 PX3 A9 ET0 E9 EX3 C1 IQ3 81 91 A1 B1 PD D1 - B8 PX0 F8 PX2 A8 EX0 E8 EX2 C0 IQ2 80 90 A0 B0 IDL D0 P
00H 00H xx000000B 00H
IEN0*# IEN1*# IRQ1*# IX1# P0* P1* P2* P3* PCON
Interrupt enable 0 Interrupt enable 1 Interrupt request flag Interrupt polarity Port 0 Port 1 Port 2 Port 3 Power control
A8H E8H C0H E9H 80H 90H A0H B0H 87H
EA EF EX9 C7 IQ9 87 97 A7 B7 SMOD D7
00H 00H 00H 00H FFH FFH FFH FFH 0xxx0000B
PSW* S1ADR# S1CON*# S1DAT# S1STA# SP TCON*
Program status word Slave address Serial control Serial data Serial status Stack pointer Timer/counter control Timer/counter mode Timer 0 high byte Timer 1 high byte Timer 0 low byte
D0H DBH
CY
00H 00H
DF D8H DAH D9H 81H 8F 88H TF1 -
DE ENS1
DD STA
DC STO
DB SI
DA AA
D9 CR1
D8 CR0 x0000000B 00H 11111000B 07H
8E TR1
8D TF0
8C TR0
8B IE1
8A IT1
89 IE0
88 IT0 00H
TMOD TH0 TH1 TL0
89H 8CH 8DH 8AH
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H 00H 00H 00H 00H
TL1 Timer 1 low byte 8BH * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs.
1995 Jan 20
6
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
PORT OPTIONS
The pins of port 1 (not P1.6/SCL or P1.7/SDA), port 2, and port 3 may be individually configured with one of the following port options (see Figure 1): Option 1: Standard Port-- quasi-bidirectional I/O with pull-up. The strong booster pull-up p1 is turned on for two oscillator periods after a 0-to-1 transition in the port latch. See Figure 1(a). Option 2: Open Drain--quasi-bidirectional I/O with n-channel open drain output. Use as an output requires the connection of an external pull-up resistor. See Figure 1(b). Option 3: Push-Pull--output with drive capability in both polarities. Under this option, pins can only be used as outputs. See Figure 1(c). The definition of port options for port 0 is slightly different.
Two cases have to be examined. First, accesses to external memory (EA = 0 or access above the built-in memory boundary), and second, I/O accesses.
External Memory Accesses
Option 1: True 0 and 1 are written as address to the external memory (strong pull-up is used). Option 2: An external pull-up resistor is needed for external accesses. Option 3: Not allowed for external memory accesses as the port can only be used as output.
Option 2: Open drain--quasi-bidirectional I/O with n-channel open drain output. Use as an output requires the connection of an external pull-up resistor. See Figure 1(c). Option 3: Push-Pull--output with drive capability in both polarities. Under this option, pins can only be used as outputs. Individual mask selection of the post-reset state is available on any of the above pins. Make your selection by appending "S" or "R" to option 1, 2, or 3 above (e.g., 1S for a standard I/O to be set after RESET or 2R for an open-drain I/O to be reset after RESET. Option S: Set--after reset, this pin will be initialized High. Option R: Reset--after reset, this pin will be initialized Low.
I/O Accesses
Option 1: When writing a 1 to the port latch, the strong pull-up p1 will be on for two oscillator periods. No weak pull-up exists. Without an external pull-up, this option can be used as a high-impedance input.
STRONG PULL-UP TWO OSCILLATOR PERIODS P2 P1 P3
+5V
I/O PIN N
(a)
Q FROM PORT LATCH INPUT DATA READ PORT PIN INPUT BUFFER +5V EXTERNAL PULL-UP I/O PIN N
(b)
Q FROM PORT LATCH
INPUT DATA READ PORT PIN INPUT BUFFER
STRONG PULL-UP
+5V
P1
(c)
N Q FROM PORT LATCH
I/O PIN
Figure 1. Ports
1995 Jan 20
7
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
POWER-DOWN MODE
The instruction setting PCON.1 is the last executed prior to going into the power-down mode. In power-down mode, the oscillator is stopped. The contents of the the on-chip RAM and SFRs are preserved. The port pins output the values held by their respective SFRs. ALE and PSEN are held low. In the power-down mode, VDD may be reduced to minimize power consumption. However, the supply voltage must not be reduced until the power-down mode is active, and must be restored before the hardware reset is applied and frees the oscillator. Reset must be held active until the oscillator has restarted and stabilized. From the power-down mode the part can be restarted by using either the wake-up mode or the Reset Mode.
is detected. This is controlled by the on-chip delay counter. After this, the PD flag will be reset, the controller is now in the Idle mode and the interrupt will be handled in the normal way.
Reset Mode
Setting only the PD bit in the PCON register again forces the controller into the power-down mode, but in this case it can only be restored to normal operation with a direct reset operation. To restore normal operation, the RESET pin has to be kept High for a minimum of 24 oscillator periods. The on-chip delay counter is inactive. The user has to insure that the oscillator is stable before any operation is attempted. Figure 2 illustrates the two possibilities for wake-up.
There are two methods used to terminate the idle mode. Activation of any interrupt will cause PCON to be cleared by hardware; terminating idle mode. The interrupt is serviced, and following the instruction RETI, the next instruction to be executed will be the one following the instruction that put the device in the the idle mode. Flag bits GF0 and GF1 can be used to determine whether the interrupt was received during normal execution or idle mode. For example, the instruction that writes to PCON.0 can also set or clear one or both flag bits. When idle mode is terminated by an interrupt, the service routine can examine the status of the flag bits. The second method of terminating the idle mode is with an external hardware reset. Since the oscillator is still running, the hardware reset is required to be active for only two machine cycles to complete the reset operation. Reset redefines all SFRs, but does not affect the state of the on-chip RAM. The status of the external pins during idle and power-down mode is shown in Table 2. If the power-down mode is activated while accessing external memory, port data held in the special function register P2 is restored to port 2. If the data is a logic 1, the port pin is held high during the power-down mode.
Wake-Up Mode
Setting both PD and IDL bits in the PCON register forces the controller into the power-down mode. Setting both bits enable the controller to be woken-up from the power-down mode via either an enabled external interrupt INT2-INT9, or a reset operation. An external interrupt for an enabled interrupt INT2-INT9 at port 1 starts both the oscillator and the delay counter. To ensure that the oscillator is stable before the controller restarts, the internal clock will remain inactive for 1536 oscillator periods after the interrupt
IDLE MODE
The instruction that sets PCON.0 is the last instruction executed before going into idle mode. In idle mode, the internal clock is stopped for the CPU, but not for the interrupt, timer, and serial port functions. The CPU status is preserved along with the stack pointer, program counter, program status word and accumulator. The RAM and all other registers maintain their data during idle mode. The port pins retain the logical states they held at idle mode activation. ALE and PSEN hold at the logic high level.
Table 2.
Idle Idle Power-down Power-down
External Pin Status During Idle and Power-Down Modes
MODE PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Floating Data Floating PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data
POWER-DOWN
RESET PIN
EXTERNAL INTERRUPT
OSCILLATOR > 24 PERIODS DELAY COUNTER 1536 PERIODS
Figure 2. Wake-Up Operation
1995 Jan 20
8
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
SLAVE ADDRESS S1ADR
GC
SDA ARBITRATION LOGIC
SHIFT REGISTER S1DAT INTERNAL BUS
SCL
BUS CLOCK GENERATOR
7 S1CON 7 S1STA
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Figure 3. Serial I/O
I2C-BUS SERIAL I/O
The serial port supports the twin line I2C-bus. The I2C-bus consists of a data line (SDA) and a clock line (SCL). These lines also function as I/O port lines P1.7 and P1.6 respectively. The system is unique because data transport, clock generation, address recognition and bus control arbitration are all controlled by hardware. The I2C-bus serial I/O has complete autonomy in byte handling and operates in four modes: - Master transmitter - Master receiver - Slave transmitter - Slave receiver These functions are controlled by the S1CON register. S1STA is the status register whose contents may also be used as a vector to various service routines. S1DAT is the data shift register and S1ADR the slave address register. Slave address recognition is performed by hardware. S1CON (D8H) Serial control register
CR2 ENS1 STA STO SI AA CR1 CR0
AA
Assert acknowledge bit. When the AA flag is set, an acknowledge (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when: - own slave address is received - general call address is received (S1ADR.0 = 1) - data byte received while device is programmed as master - data byte received while device is selected slave With AA = 0, no acknowledge will be returned. Consequently, no interrupt is requested when the "own slave address" or general call address is received.
STO
STOP flag. With this bit set while in master mode, a STOP condition is generated. When a STOP condition is detected on the bus, the SIO hardware clears the STO flag. In the slave mode, the STO flag may also be set to recover from an error condition. In this case, no STOP condition is transmitted to the I2C-bus. However, the SIO hardware behaves as if a STOP condition has been received and releases SDA and SCL. The SIO then switches to the "not addressed" slave receiver mode. The STO flag is automatically cleared by hardware. START flag. When the STA bit is set in slave mode, the SIO hardware checks the status of the I2C-bus and generates a START condition if the bus is free. If STA is set while the SIO is in master mode, SIO transmits a repeated START condition. When ENS1 = 0, the SIO is disabled. The SDA and SCL outputs are in a high-impedance state; P1.6 and P1.7 function as open drain ports. When ENS1 = 1, the SIO is enabled. The P1.6 and P1.7 port latches must be set to logic 1.
STA
SI
CR0, CR1, CR2 These three bits determine the serial clock frequency when SIO is in a master mode.
SIO interrupt flag. When the SI flag is set, an acknowledge is returned after any one of the following conditions: - a start condition is generated in master mode - own slave address received during AA = 1 - general call address received while S1ADR.0 and AA = 1 - data byte received or transmitted in master mode (even if arbitration is lost) - data byte received or transmitted as selected slave - stop or start condition received as selected slave receiver or transmitter
ENS1
1995 Jan 20
9
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
S1STA (D9H) Status register
SC4 SC3 SC2 SC1 SC0 0 0 0
MST/REC mode S1STA value 08H - a START condition has been transmitted 10H - a repeated START condition has been transmitted 38H - Arbitration lost while returning ACK 40H - SLA and R have been transmitted, ACK received 48H - SLA and R have been transmitted, ACK received 50H - DATA has been received, ACK returned 58H - DATA has been received, ACK returned SLV/REC mode S1STA value 60H - Own SLA and W have been received, ACK returned 68H - Arbitration lost in SLA, R/W as MST. Own SLA and W have been received, ACK returned 70H - General CALL has been received, ACK returned 78H - Arbitration lost in SLA, R/W as MST. General CALL has been received 80H - Previously addressed with own SLA. DATA byte received, ACK returned 88H - Previously addressed with own SLA. DATA byte received, ACK returned 90H - Previously addressed with general CALL. DATA byte has been received, ACK has been returned 98H - Previously addressed with general CALL. DATA byte has been received, ACK has been returned A0H - A STOP condition or repeated START condition has been received while still addressed as SLV/REC or SLV/TRX
SLV/TRX mode S1STA value A8H - Own SLA and R have been received, ACK returned B0H - Arbitration lost in SLA, R/W as MST. Own SLA and R have been received, ACK returned B8H - DATA byte has been transmitted, ACK received C0H - DATA byte has been transmitted, ACK received C8H - Last DATA byte has been transmitted (AA = logic 0), ACK received Miscellaneous S1STA value 00H - Bus error during MST mode or selected SLV mode, due to an erroneous START or STOP condition F8H - No relevant state interruption available, SI = 0. S1DAT (DAH) Data Shift Register
7 6 5 4 3 2 1 0
S1STA is an 8-bit read-only special function register. S1STA.3-S1STA.7 hold a status code. S1STA.0-S1STA.2 are held LOW. The contents of S1STA may be used as a vector to a service routine. This optimizes response time of the software and consequently that of the I2C-bus. The following is a list of the status codes: Abbreviations used: SLA: 7-bit slave address R: Read bit W: Write bit ACK: Acknowledgement (acknowledge bit = 0) ACK: Not Acknowledge (acknowledge bit = 1) DATA: 8-bit byte to or from the I2C-bus MST: Master SLV: Slave TRX: Transmitter REC: Receiver MST/TRX mode S1STA value 08H - a START condition has been transmitted 10H - a repeated START condition has been transmitted 18H - SLA and W have been transmitted, ACK received 20H - SLA and W have been transmitted, ACK received 28H - DATA of S1DAT has been transmitted, ACK received 30H - DATA of S1DAT has been transmitted, ACK received 38H - Arbitration lost in SLA, R/W or DATA
Data shift register S1DAT This register contains the serial data to be transmitted or data that has just been received. Bit 7 is transmitted or received first, i.e., data is shifted from left to right. S1ADR (DBH) Slave Address Register
7 6 5 4 3 2 1 0
S1ADR.0, GC: 0 = general CALL address is not recognized 1 = general CALL address is recognized S1ADR.7-1: own slave address
This 8-bit register may be loaded with the 7-bit slave address, to which the controller will respond when programmed as a slave receiver/transmitter. The LSB bit (GC) is used to determine whether the general CALL address is recognized.
Table 3.
CR2 0 0 0 0 1 1 1 1 1995 Jan 20
SCL Frequency
BIT RATE (kHz) at fOSC CR1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 fOSC DIVIDED BY 256 224 192 160 960 120 60 not allowed 10 3.58MHz 14.0 16.0 18.6 22.4 3.73 29.8 59.7 - 6MHz 23.4 26.8 31.3 37.5 6.25 50 100 - 12MHz 46.9 53.6 62.5 75.0 12.5 100 - -
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
INTERRUPT SYSTEM
External events and the real-time-driven on-chip peripherals require service by the CPU asynchronous to the execution of any particular section of code. To tie the asynchronous activities of these functions to normal program execution, a multiple-source, two-priority level, nested interrupt system is provided. The 8XCL410 acknowledges interrupt requests from thirteen sources, as follows: - INT0 and INT1 - Timer 0 and timer 1 - I2C-bus serial I/O interrupt - INT2 to INT9 (port 1) Each interrupt vectors to a separate location in program memory for its service routine. Each source can be individually enabled or disabled by corresponding bits in the internal enable registers (IEN0, IEN1) The priority level is selected via the interrupt priority register (IP0, IP1). All enabled sources can be globally disabled or enabled.
IEN1 (E8H) Interrupt enable register
7 EX9 6 EX8 5 EX7 4 EX6 3 EX5 2 EX4 1 EX3 0 EX2
IX1 (E9H) Interrupt polarity register
7 IL9 6 IL8 5 IL7 4 IL6 3 IL5 2 IL4 1 IL3 0 IL2
Bit Symbol Function IEN1.7 EX9 Enable external interrupt 9 IEN1.6 EX8 Enable external interrupt 8 IEN1.5 EX7 Enable external interrupt 7 IEN1.4 EX6 Enable external interrupt 6 IEN1.3 EX5 Enable external interrupt 5 IEN1.2 EX4 Enable external interrupt 4 IEN1.1 EX3 Enable external interrupt 3 IEN1.0 EX2 Enable external interrupt 2 where 0 = interrupt disabled 1 = interrupt enabled IP0 (B8H) Interrupt priority register
7 -- 6 -- 5 PS1 4 -- 3 PT1 2 PX1 1 PT0 0 PX0
Bit IX1.7 IX1.6 IX1.5 IX1.4 IX1.3 IX1.2 IX1.1 IX1.0
Symbol Function IL9 External interrupt 9 polarity level IL8 External interrupt 8 polarity level IL7 External interrupt 7 polarity level IL6 External interrupt 6 polarity level IL5 External interrupt 5 polarity level IL4 External interrupt 4 polarity level IL3 External interrupt 3 polarity level IL2 External interrupt 2 polarity level
External Interrupts INT2-INT9
Port 1 lines serve an alternative purpose as eight additional interrupts INT2-INT9. When enabled, each of these lines can "wake-up" the device from power-down mode. Using the IX1 register, each pin may be initialized to either active high or low. IRQ1 is the interrupt request flag register. Each flag, if the interrupt is enabled, will be set on an interrupt request but it must be cleared by software. IEN0 (A8H) Interrupt enable register
7 EA 6 -- 5 ES1 4 -- 3 ET1 2 EX1 1 ET0 0 EX0
Bit IP0.7 IP0.6 IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0
Symbol Function -- (unused) -- (unused) PS1 I2C SIO interrupt priority level -- (unused) PT1 Timer 1 interrupt prioity level PX1 External interrupt 1 priority level PT0 Timer 0 interrupt prioity level PX0 External interrupt 0 priority level
Writing either a "1" or "0" to an IX1 register bit sets the priority level of the corresponding external interrupt to active High or Low, respectively.
IP1 (F8H) Interrupt priority register
7 6 PX8 5 PX7 4 PX6 3 PX5 2 PX4 1 PX3 0 PX2
Bit Symbol Function IEN0.7 EEA General enable/disable control 0 = no interrupt is enabled 1 = any individually enabled interrupt will be accepted IEN0.6 -- (unused) IEN0.5 ES1 Enable I2C SIO interrupt IEN0.4 -- (unused) IEN0.3 ET1 Enable Timer T1 interrupt IEN0.2 EX1 Enable external interrupt 1 IEN0.1 ET0 Enable Timer T0 interrupt IEN0.0 EX0 Enable external interrupt 0
PX9
Bit IP1.7 IP1.6 IP1.5 IP1.4 IP1.3 IP1.2 IP1.1 IP1.0
Symbol Function PX9 External interrupt 9 priority level PX8 External interrupt 8 priority level PX7 External interrupt 7 priority level PX6 External interrupt 6 priority level PX5 External interrupt 5 priority level PX4 External interrupt 4 priority level PX3 External interrupt 3 priority level PX2 External interrupt 2 priority level
Interrupt priority is as follows: 0 - low priority 1 - high priority
1995 Jan 20
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Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
IRQ1 (C0H) Interrupt request flag register
7 IQ9 6 IQ8 5 IQ7 4 IQ6 3 IQ5 2 IQ4 1 IQ3 0 IQ2
OSCILLATOR CIRCUITRY
The on-chip oscillator circuitry of the 8XCL410 is a single stage inverting amplifier biased by an internal feedback resistor. (See Figure 4.) The oscillator can be operated with a quartz crystal, ceramic resonator, LC network or RC network. See Figure 5 for different configurations. When ordering parts, it is necessary to specify an oscillator option. The options are: RC when an RC network will be used, OSC 2 for oscillator operation below 4MHz, OSC 3 for oscillator operation from 4MHz to 10MHz, OSC 4 for oscillator operation above 10MHz, and 32kHz if 32kHz to 400kHz operation is desired. For operation as a standard quartz oscillator, no external components are needed (except at 32KHz). When using external capacitors, ceramic resonators, coils, and RC networks to drive the oscillator, five different configurations are supported (see Figure 5 and Table 4). In the power-down mode the oscillator is stopped and XTAL1 is pulled high. The oscillator inverter is switched off to ensure no current will flow. To drive the device with an external clock source, apply the external clock signal to XTAL1, and leave XTAL2 to float, as shown in Figure 5(f). There are no requirements on the duty cycle of the external clock, since the input to the internal clocking circuitry is split using a flip-flop. The following options are provided for optimum on-chip oscillator performance. Please state option when ordering: Osc.1: Figure 5(c). An option for 32kHz clock applications with external trimmer for frequency adjustment. A 4.7M bias resistor must be connected in parallel with the crystal. Osc.2: Figure 5(e). An option for low-power, low-frequency operations using LC components or quartz. An option for medium frequency range applications. An option for high frequency range applications. Figure 5(g). An option for an RC oscillator.
Power-on Reset
The 8XCL410 contains on-chip circuitry which switch the port pins to the customer-defined logic level as soon as VDD exceeds 1.3V if the mask option "ON" has been chosen (see Figures 8 and 9). As soon as the minimum supply voltage is reached, the oscillator will start up. However, to ensure that the oscillator is stable before the controller starts, the clock signals are gated away from the CPU for a further 1536 oscillator periods. An hysteresis of approximately 50mV at a typical power-on switching level of 1.3V will ensure correct operation. The on-chip power-on reset circuitry can also be switched off via the mask option "OFF". This option reduces the power-down current to typically 800A and can be chosen if external reset circuitry is used. For applications not requiring the internal reset, option "OFF" should be chosen. An automatic reset can be obtained at power-on by connecting the RST pin to VDD via a 10F capacitor. At power-on, the voltage on the RST pin is equal to VDD minus the capacitor voltage, and decreases from VDD as the capacitor discharges through the internal resistor RRST to ground. The larger the capacitor, the more slowly VRST decreases. VRST must remain above the lower threshold of the Schmitt trigger long enough to effect a complete reset. The time required is the oscillator start-up time, plus 2 machine cycles.
Bit Symbol Function IRQ1.7 IQ9 External interrupt 9 request flag IRQ1.6 IQ8 External interrupt 8 request flag IRQ1.5 IQ7 External interrupt 7 request flag IRQ1.4 IQ6 External interrupt 6 request flag IRQ1.3 IQ5 External interrupt 5 request flag IRQ1.2 IQ4 External interrupt 4 request flag IRQ1.1 IQ3 External interrupt 3 request flag IRQ1.0 IQ2 External interrupt 2 request flag Priority X0 (highest) S1 X5 T0 X6 X1 X2 X7 T1 X3 X8 X4 X9 (lowest) Vector 0003H 002BH 0053H 000BH 005BH 0013H 003BH 0063H 001BH 0043H 006BH 004BH 0073H Source External 0 I2C port External 5 Timer 0 External 6 External 1 External 2 External 7 Timer 1 External 3 External 8 External 4 External 9 SFR Address E9H C0H A8H E8H B8H F8H
Register Function IX1 Interrupt polarity register IRQ1 Interrupt request flag register IEN0 Interrupt enable register IEN1 Interrupt enable register (INT2-INT9) IP0 Interrupt priority register IP1 Interrupt priority register (INT2-INT9)
P80CL410: ROM-less VERSION OF P83CL410
The P80CL410 is a low voltage ROMless version of the P83CL410. The mask options on the P80CL410 are fixed as follows:
* Port Options:
Osc.3: Osc.4: RC:
All ports except P16/P17 have option "1S", i.e., standard port, High after reset. The ports P16/P17 have option "2S", i.e., open drain, High after reset.
* Oscillator option: OSC3 * Power-on Reset option: OFF
The equivalent circuit data of the internal oscillator compares with that of matched crystals. The externally adjustable RC oscillator has a frequency range from 100kHz to 500kHz. (See Figure 7.)
1995 Jan 20
12
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
VDD
To internal timing circuits
PD VDD VDD
Rbias C1i C2i
XTAL1
XTAL2
Figure 4. Oscillator
XTAL1
XTAL2 XTAL1 XTAL2
XTAL1
XTAL2 4.7 MEG
(a) Oscillator Configuration for Quartz Crystal
(b) Quartz Oscillator with External Capacitors (d) Configuration for Ceramic Resonator
(c) Configuration for 32kHz Operation
XTAL1
XTAL2 XTAL1 XTAL2 N.C.
XTAL1 N.C.
XTAL2
VDD
(e) Configuration for LC Network
(f) External Clock Configuration Figure 5. Oscillator Configurations
(g) RC Network Configuration
1995 Jan 20
13
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
Table 4.
Oscillator Type Selection Guide
C1 EXT. C2 EXT. MAX 15 30 15 20 10 15 10 15 50 50 40 40 20 15 40 90 MIN 0 0 0 0 0 0 0 0 40 15 0 0 0 0 10 20 MAX 0 30 15 20 10 15 10 15 50 50 40 40 20 15 40 90 MAXIMUM RESONATOR SERIES RESISTANCE 15k1 600 100 75 60 60 40 20 10 100 10 10 5 6 6 10H = 1 100H = 5 1mH = 75 f (MHz) 0.032 1.0 3.58 4.0 6.0 10.0 12.0 16.0 0.455 1.0 3.58 4.0 6.0 10.0 12.0 OPTION Osc.1 Osc.2 Osc.2 Osc.2 Osc.3 Osc.4 Osc.4 Osc.4 Osc.2 Osc.2 Osc.2 Osc.2 Osc.2 Osc.3 Osc.4 Osc.2 MIN 5 0 0 0 0 0 0 0 40 15 0 0 0 0 10 20
RESONATOR Quartz Quartz Quartz Quartz Quartz Quartz Quartz Quartz PXE PXE PXE PXE PXE PXE PXE LC
NOTE: 1. 32kHz quartz crystals with a series resistance higher than 15k will reduce the guaranteed supply voltage range to 2.5 to 3.5V.
Table 5.
Oscillator Equivalent Circuit Parameters (see Figure 6)
OPTION Osc.1 Osc.2 Osc.3 Osc.4 Osc.1 Osc.2 Osc.3 Osc.4 Osc.1 Osc.2 Osc.3 Osc.4 Osc.1 Osc.2 Osc.3 Osc.4 SYMBOL gm gm gm gm c1i c1i c1i c1i c2i c2i c2i c2i R2 R2 R2 R2 CONDITION T = +25C; VDD = 4.5V T = +25C; VDD = 4.5V T = +25C; VDD = 4.5V T = +25C; VDD = 4.5V MIN - 200 400 1000 - - - - - - - - - - - - TYP 15 600 1500 4000 3.0 8.0 8.0 8.0 23.0 8.0 8.0 8.0 3800 65 18 5.0 MAX - 1000 4000 10000 - - - - - - - - - - - - UNIT s s s s pF pF pF pF pF pF pF pF k k k k
PARAMETER Transconductance
Input capacitance
Output capacitance
Output resistance
1995 Jan 20
14
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
Rf XTAL1 XTAL2
C1i
V1
gm
R2
C2i
Figure 6. Equivalent Circuit Diagram
600
400
fOSC
(kHz)
200
0 0 2 RC (s) 4 6
Figure 7. Frequency as a Function of RC
SWITCHING LEVEL PDR SUPPLY VOLTAGE HYSTERESIS
POWER-ON RESET (INTERNAL)
OSCILLATOR
CPU RUNNING
START-UP 1536 OSCILLATOR TIME PERIODS DELAY
Figure 8. Power-on Reset Switching Level
1995 Jan 20
15
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
VCC
VCC + 10F 8XCL410
RST
RRST
Figure 9. Recommended Power-on Reset Circuitry
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER Supply voltage All input voltages DC current into any input or output Total power dissipation Storage temperature range Operating ambient temperature range Operating junction temperature RATING -0.5 to +6.5 -0.5 to VDD +0.5 5 300 -65 to +150 -40 to +85 125 UNIT V V mA mW C C C
NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
1995 Jan 20
16
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
DC ELECTRICAL CHARACTERISTICS
Tamb = -40C to +85C, VSS = 0V TEST SYMBOL VDD IDD PARAMETER Supply voltage RAM retention voltage in power-down mode Power supply current: Operating1 OSC 1 option OSC 2 option OSC 2 option OSC 3 option OSC 4 option Idle mode2 OSC 1 option OSC 2 option OSC 2 option OSC 3 option OSC 4 option Power-down mode3 VIL VIH IOL IOL1 IOH IIL ITL ILI RRST Input low voltage Input high voltage Output sink current, except SDA, SCL Output sink current, SDA, SCL Output source current (push-pull options only) Logical 0 input current, ports 1, 2, 3 Logical 1-to-0 transition current, ports 1, 2, 3 Input leakage current, port 0, EA Internal reset pull-down resistor VDD = 5V, VOL = 0.4V VDD = 2.5V, VOL = 0.4V VDD = 5V, VOL = 0.4V VDD = 5V, VOH = VDD - 0.4V VDD = 2.5V, VOH = VDD - 0.4V VDD = 5V,VIN = 0.4V VDD = 2.5V,VIN = 0.4V VDD = 5V, VIN = VDD/2 VDD = 2.5V, VIN = VDD/2 VSS < VI < VDD 10 CONDITIONS fCLK (see Figure 13) MIN 1.8 1.0 LIMITS MAX 6.0 -- UNIT V V
fCLK = 32kHz, VDD = 1.8V, Tamb = +25C fCLK = 3.58MHz, VDD = 3V fCLK = 10MHz, VDD = 5V fCLK = 12MHz, VDD = 5V fCLK = 12MHz, VDD = 5V fCLK = 32kHz, VDD = 1.8V, Tamb = +25C fCLK = 3.58MHz, VDD = 3V fCLK = 10MHz, VDD = 5V fCLK = 12MHz, VDD = 5V fCLK = 12MHz, VDD = 5V VDD = 1.8V, Tamb = +25C
-- -- -- -- -- -- -- -- -- -- -- VSS 0.7VDD 1.6 0.7 3.0 1.6 0.7
50 2.5 14 16 20 25 1.0 5.0 7.0 8.5 10 0.3VDD VDD
A mA mA mA mA A mA mA mA mA A V V mA mA mA mA mA
-100 -50 -1.0 -500 10 200
A A mA A A k
NOTES: 1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS, VIH = VDD; XTAL2 not connected; EA = RST = Port 0 = VDD; all open drain outputs connected to VSS. 2. The idle supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS, VIH = VDD; XTAL2 not connected; EA = Port 0 = VDD; RST = VSS; all open drain outputs connected to VSS. 3. The power-down current is measured with all output pins disconnected; XTAL1 not connected; EA = port 0 = VDD; RST = VSS; all open-drain outputs connected to VSS. 4. The RC-oscillator is not implemented in this version. 5. Circuits with "power-on reset" option "OFF" are tested at VDDMIN = 1.8V, with option "ON" (typically 1.3V) are tested at VDDMIN = 2.3V.
1995 Jan 20
17
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
1.8
1.6
1.4
1.2
1.0
IDD (mA)
0.8
1.2MHz
0.6
0.4 32kHz
0.2
0 0 1 2 VDD MIN = 1.8V 3 4 5 6
VDD (V) Typical Operating Current Versus Supply and Frequency (32kHz-1.2MHz) at +25C
1995 Jan 20
18
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
AC ELECTRICAL CHARACTERISTICS
Tamb = -40C to +85C, VSS = 0V1, 2 12MHz CLOCK SYMBOL FIGURE PARAMETER MIN MAX VARIABLE CLOCK MIN MAX UNIT
Program Memory 1/tCLCL tLL tAL tLA tLIV tLC tCC tCIV tCI tCIF tAVI tAFC Data Memory tRR tWW tLA tRD tDFR tLD tAD tLW tAW tDWX tDW tWD tAFR tWHLH 11 12 11, 12 11 11 11 11 11, 12 11, 12 12 11 12 11 11, 12 RD pulse width WR pulse width Address hold time after ALE RD low to valid data in Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data valid to WR Data hold after WR RD low to address float3 43 200 203 23 433 33 12 123 tCLCL-40 - 400 400 48 - 250 97 517 585 300 3tCLCL-50 4tCLCL-130 tCLCL-60 7tCLCL-150 tCLCL-50 12 tCLCL+40 - 6tCLCL-100 6tCLCL-100 tCLCL-35 - 5tCLCL-165 2tCLCL-70 8tCLCL-150 9tCLCL-165 3tCLCL+50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 10 10 10 10 10 10 10 10 10 10 Oscillator frequency ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 0 63 302 0 58 215 125 0 tCLCL-20 5tCLCL-115 127 43 48 233 tCLCL-25 3tCLCL-35 3tCLCL-125 0 2tCLCL-40 tCLCL-40 tCLCL-35 4tCLCL-100 20 MHz ns ns ns ns ns ns ns ns ns ns ns
RD or WR high to ALE high
NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 50pF, load capacitance for all other outputs = 40pF. 3. Interfacing the 8XCL410 to devices with float time up to 75ns is permitted. This limited bus connection will not cause damage to port 0 drivers.
1995 Jan 20
19
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
tLL
ALE
tAL
PSEN
tCC tLC tLIV tCIV tLA tAFC tCI tCIF
PORT 0
A0-A7
INSTR IN
A0-A7
tAVI
PORT 2 A8-A15 A8-A15
Figure 10. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLD tLW
RD
tRR
tAL
PORT 0
tDFR tLA tAFR
DATA IN A0-A7 FROM PCL INSTR IN
A0-A7 FROM RI OR DPL
tAW tAD
PORT 2
tRD
P2.0-P2.7 OR A8-A15 FROM DPH
A8-A15 FROM PCH
Figure 11. External Data Memory Read Cycle
1995 Jan 20
20
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
ALE
tWHLH
PSEN
tLW
WR
tWW
tAL
PORT 0
tDWX tLA tDW
DATA OUT
tWD
A0-A7 FROM RI OR DPL
A0-A7 FROM PCL
INSTR IN
tAW
PORT 2
P2.0-P2.7 OR A8-A15 FROM DPH
A8-A15 FROM PCH
Figure 12. External Data Memory Write Cycle
0.7 VDD 0.9 VDD TEST POINTS 0.4 VDD 0.3 VDD
0.7 VDD
0.3 VDD
Figure 13. AC Testing Input Waveform
ITL 500A
-IIL
IIL 100A 0
VDD/2
VDD
Figure 14. Input Current
1995 Jan 20
21
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
100
16
10
12
f (MHz)
1
IDD (mA)
8 12MHz
0.1
4 8MHz
3.58MHz 0.01 0 1 2 3 VDD (V) NOTE: Below 32kHz, clock has to be supplied externally. 4 5 6 7 0 1 2 3 VDD (V) 4 5 6
Figure 15. Frequency Operating Range
Figure 16. Typical Operating Current as a Function of Frequency and VDD, Tamb = 25C
5
8
4 6
3 fIDLE (mA) 12MHz 2 IPD (A) 4
8MHz 1
2
3.58MHz 0 0 1 2 3 VDD (V) 4 5 6 0 1 2 3 VDD (V) 4 5 6
Figure 17. Typical Idle Current as a Function of Frequency and VDD, Tamb = 25C
Figure 18. Typical Power-Down Current Vs. Frequency and VDD, Tamb = 25oC
1995 Jan 20
22
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
PIGGYBACK SPECIFICATION
The differences between the masked version and the piggyback are described herein.
Features
General Description
The P85CL000HFZ is a piggy-back version with 256 bytes of RAM used for emulation of the P83CL410 microcontroller. The P85CL000HFZ is manufactured in an advanced CMOS technology. The instruction set of the P85CL000HFZ is based on that of the 8051. The device has low power consumption and a wide supply voltage range. The P85CL000HFZ has two software selectable modes of reduced activity for further power reduction: Idle and Power-down. For timing and AC/DC characteristics, please refer to the P83CL410 specifications.
* Full static 80C51 CPU * 8-bit CPU, RAM, I/O in a single
40-lead DIP
* Enhanced architecture with:
- non-page oriented instructions - direct addressing - four eight byte RAM register banks - stack depth up to 128 bytes - multiply, divide, subtract and compare instructions
* Socket for up to 16k external EPROM * 256 bytes RAM, expandable externally to
64K bytes
* Four 8-bit ports, 32 I/O lines * Two 16-bit timer/event counters * External memory expandable up to 128K,
external ROM up to 64K and/or RAM up to 64K
* Thirteen source, thirteen vector interrupt
structure with two priority levels
* STOP and IDLE instructions * Wake-up via external interrupts at port 1 * Single supply voltage of 1.8V to 6.0V * On-chip oscillator (option: oscillator 4) * Very low current consumption * Operating temperature range:
-40 to +85C
* Full duplex serial port (UART) * I2C-bus interface for serial transfer on two
lines
STANDARD PIGGYBACK
Types: P85CL000HFZ Emulation for: P83CL410, P80CL51 List of differences between masked microcontroller and corresponding piggyback: PARAMETER RAM size ROM size Port option Oscillator option Mech. dimensions Current cons. Voltage range ESD MASKED CONTROLLER 128 4k 1, 2, 3 Osc. 1, 2, 3, 4, RC Standard Dual In-Line, Small Outline IDD full specification PIGGYBACK 256 EPROM size dependent (max 16k) 1 Osc. 4 See SOT158A IDD (OSC. 4) + IEPROM full, limited by EPROM not tested (different package)
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
1995 Jan 20
23
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
1995 Jan 20
24
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
VSO40: plastic very small outline package; 40 leads
SOT158-1
1995 Jan 20
25
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
1995 Jan 20
26
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
NOTES
1995 Jan 20
27
Philips Semiconductors
Product specification
Low voltage/low power single-chip 8-bit microcontroller with I2C
80CL410/83CL410
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. (c) Copyright Philips Electronics North America Corporation 1995 All rights reserved. Printed in U.S.A.

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