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High Speed, Half-Duplex iCoupler(R) Isolated RS-485 Transceiver ADM2486
FEATURES
Half-duplex, isolated RS-485 transceiver PROFIBUS(R)-compliant ANSI EIA/TIA 485-A and ISO 8482: 1987(E) compliant 20 Mbps data rate 5 V or 3 V operation (VDD1) High common-mode transient immunity: >25 kV/s Isolated DE status output Receiver open-circuit, fail-safe design Thermal shutdown protection 50 nodes on bus Safety and regulatory approvals UL recognition--2500 Vrms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01 DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000 VIORM = 560 V peak Operating temperature range: -40C to +85C Wide body, 16-lead SOIC package
FUNCTIONAL BLOCK DIAGRAM
VDD1 VDD2
ADM2486
RTS GALVANIC ISOLATION LOGIC SIDE DE
TxD PV RxD RE
A B
BUS SIDE GND2
04604-001
GND1
Figure 1.
APPLICATIONS
Isolated RS-485/RS-422 interfaces PROFIBUS networks Industrial field networks Multipoint data transmission systems
The device employs Analog Devices' iCoupler technology to combine a 3-channel isolator, a three-state differential line driver, and a differential input receiver into a single package. The logic side of the device is powered with either a 5 V or a 3 V supply, and the bus side uses an isolated 5 V supply. The ADM2486 driver has an active-high enable feature. The driver differential outputs and the receiver differential inputs are connected internally to form a differential input/output port that imposes minimal loading on the bus when the driver is disabled or when VDD1 or VDD2 = 0 V. Also provided is an activehigh receiver disable feature that causes the receive output to enter a high impedance state. The device has current-limiting and thermal shutdown features to protect against output short circuits and situations where bus contention might cause excessive power dissipation. The part is fully specified over the industrial temperature range and is available in a 16-lead, wide body SOIC package.
GENERAL DESCRIPTION
The ADM2486 differential bus transceiver is an integrated, galvanically isolated component designed for bidirectional data communication on multipoint bus transmission lines. It is designed for balanced transmission lines and complies with ANSI EIA/TIA-485-A and ISO 8482: 1987(E).
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
ADM2486 TABLE OF CONTENTS
Specifications..................................................................................... 3 Timing Specifications....................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 ADM2486 Characteristics ............................................................... 7 Package Characteristics ............................................................... 7 Regulatory Information............................................................... 7 Insulation and Safety-Related Specifications............................ 7 VDE 0884 Insulation Characteristics ........................................ 8 Pin Configuration and Function Descriptions............................. 9 Test Circuits..................................................................................... 10 Switching Characteristics .............................................................. 11 Typical Performance Characteristics ........................................... 12 Circuit Description......................................................................... 14 Electrical Isolation...................................................................... 14 Truth Tables................................................................................. 14 Power-Up/Power-Down Thresholds ....................................... 14 Thermal Shutdown .................................................................... 15 Receiver Fail-Safe Inputs ........................................................... 15 Magnetic Field Immunity.......................................................... 15 Applications Information .............................................................. 16 Power_Valid Input ..................................................................... 16 Isolated Power Supply Circuit .................................................. 17 Outline Dimensions ....................................................................... 18 Ordering Guide .......................................................................... 18
REVISION HISTORY
3/05--Rev. B to Rev. C Change to Package Characteristics................................................. 7 Changes to Figure 12, Figure 14, and Figure 15 ......................... 11 Change to Power_Valid Input Section......................................... 16 1/05--Rev. A to Rev. B Added PROFIBUS logo ................................................................... 1 11/04--Rev. 0 to Rev. A Changes to Figure 1.......................................................................... 1 Changes to Figure 6........................................................................ 10 Added Figure 22 through Figure 25............................................. 13 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 18
Rev. C | Page 2 of 20
ADM2486 SPECIFICATIONS
2.7 V VDD1 5.5 V, 4.75 V VDD2 5.25 V, TA = TMIN to TMAX, unless otherwise noted. Table 1.
Parameter DRIVER Differential Outputs Differential Output Voltage, VOD Min Typ Max Unit Test Conditions/Comments
2.1 2.1 2.1 |VOD| for Complementary Output States Common-Mode Output Voltage, VOC |VOC| for Complementary Output States Output Short-Circuit Current, VOUT = High Output Short-Circuit Current, VOUT = Low Bus Enable Output Output High Voltage
5 5 5 5 0.2 3 0.2 200 200
V V V V V V V mA mA V V V V V V V V A
60 60 VDD2 - 0.1 VDD2 - 0.3 VDD2 - 0.4
R = , see Figure 3 R = 50 (RS-422), see Figure 3 R = 27 (RS-485), see Figure 3 VTST = -7 V to 12 V, VDD1 4.7, see Figure 4 R = 27 or 50 , see Figure 3 R = 27 or 50 , see Figure 3 R = 27 or 50 , see Figure 3 -7 V VOUT +12 V -7 V VOUT +12 V IODE = 20 A IODE = 1.6 mA IODE = 4 mA IODE = -20 A IODE = -1.6 mA IODE = -4 mA TxD, RTS, RE, PV TxD, RTS, RE, PV TxD, RTS, RE, PV = VDD1 or 0 V
VDD2 - 0.1 VDD2 - 0.2 0.1 0.2 0.1 0.3 0.4
Output Low Voltage
Logic Inputs Input High Voltage Input Low Voltage CMOS Logic Input Current (TxD, RTS, RE, PV) RECEIVER Differential Inputs Differential Input Threshold Voltage, VTH Input Hysteresis Input Resistance (A, B) Input Current (A, B) RxD Logic Output Output High Voltage Output Low Voltage
0.7 VDD1 -10 0.01 0.25 VDD1 10
-200 20 70 30
200
0.6 -0.35 VDD1 - 0.1 VDD1 - 0.4
mV mV k mA mA V V V V mA A
-7 V VCM +12V -7 V VCM +12V -7 V VCM +12V VIN = +12 V VIN = -7 V IOUT = 20 A, VA - VB = 0.2 V IOUT = 4 mA, VA - VB = 0.2 V IOUT = -20 A, VA - VB = -0.2 V IOUT = -4 mA, VA - VB = -0.2 V VOUT = GND or VCC 0.4 V VOUT 2.4 V
VDD1 - 0.2 0.2 0.1 0.4 85 1
Output Short-Circuit Current Three-State Output Leakage Current
7
Rev. C | Page 3 of 20
ADM2486
Parameter POWER SUPPLY CURRENT Logic Side Min Typ Max 1.3 2.9 10.2 0.8 1.1 4.3 Bus Side 53.4 86.7 COMMON-MODE TRANSIENT IMMUNITY1 HIGH FREQUENCY, COMMON-MODE NOISE IMMUNITY
1
Unit mA mA mA mA mA mA mA mA mA kV/s mV
Test Conditions/Comments RTS = 0 V, VDD1 = 5.5 V 2 Mbps, VDD1 = 5.5 V, see Figure 5 20 Mbps, VDD1 = 5.5 V, see Figure 5 RTS = 0 V, VDD1 = 3 V 2 Mbps, VDD1 = 3 V, see Figure 5 20 Mbps, VDD1 = 3 V, see Figure 5 RTS = 0 V 2 Mbps, RTS = VDD1, see Figure 5 20 Mbps, RTS = VDD1, see Figure 5 VCM = 1 kV, transient magnitude = 800 V VHF = +5 V, -2 V < VTEST2 < 7 V, 1 MHz < fTEST < 50 MHz, see Figure 6
3.0
25 100
Common-mode transient immunity is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common-mode is slewed. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. C | Page 4 of 20
ADM2486 TIMING SPECIFICATIONS
2.7 V VDD1 5.5 V, 4.75 V VDD2 5.25 V, TA = TMIN to TMAX, unless otherwise noted. Table 2.
Parameter DRIVER Maximum Data Rate Propagation Delay, tPLH, tPHL RTS-to-DE Propagation Delay Pulse Width Distortion, tPWD Switching Skew, tSKEW Rise/Fall Time, tR, tF Enable Time Disable Time Enable Skew, |tAZH - tBZL|, |tAZL - tBZH| Disable Skew, |tAHZ - tBLZ|, |tALZ - tBHZ| RECEIVER Propagation Delay, tPLH, tPHL Differential Skew, tSKEW Enable Time Disable Time POWER_VALID INPUT Enable Time Disable Time Min 20 25 20 Typ Max Unit Mbps ns ns ns ns ns ns ns ns ns ns ns ns ns s s Test Conditions/Comments
45 35
55 55 5 5 15 53 55 3 5 55 5 13 13 2 5
2 5 43 43 1 2 25 45 3 3 1 3
RLDIFF = 54 , CL1 = CL2 = 100 pF, see Figure 7 See Figure 8 RLDIFF = 54 , CL1 = CL2 = 100 pF, see Figure 7 and Figure 12 RLDIFF = 54 , CL1 = CL2 = 100 pF, see Figure 7 and Figure 12 RLDIFF = 54 , CL1 = CL2 = 100 pF, see Figure 7 and Figure 12 See Figure 9 and Figure 14 See Figure 9 and Figure 14 See Figure 9 and Figure 14 See Figure 9 and Figure 14 CL = 15 pF, see Figure 10 and Figure 13 CL = 15 pF, see Figure 10 and Figure 13 RL = 1 k, CL = 15 pF, see Figure 11 and Figure 15 RL = 1 k, CL = 15 pF, see Figure 11 and Figure 15
Rev. C | Page 5 of 20
ADM2486 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. All voltages are relative to their respective ground. Table 3.
Parameter VDD1 VDD2 Digital Input Voltage (RTS, RE, TxD) Digital Output Voltage RxD DE Driver Output/Receiver Input Voltage Operating Temperature Range Storage Temperature Range Average Output Current per Pin JA Thermal Impedance Lead Temperature Soldering (10 sec) Vapor Phase (60 sec) Infrared (15 sec) Rating -0.5 V to +7 V -0.5 V to +6 V -0.5 V to VDD1 + 0.5 V -0.5 V to VDD1 + 0.5 V -0.5 V to VDD2 + 0.5 V -9 V to +14 V -40C to +85C -55C to +150C -35 mA to +35 mA 73C/W 260C 215C 220C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. C | Page 6 of 20
ADM2486 ADM2486 CHARACTERISTICS
PACKAGE CHARACTERISTICS
Table 4.
Parameter Resistance (Input-Output)1 Capacitance (Input-Output)1 Input Capacitance2 Input IC Junction-to-Case Thermal Resistance Output IC Junction-to-Case Thermal Resistance
1 2
Symbol RI-O CI-O CI JCI JCO
Min
Typ 1012 3 4 33 28
Max
Unit pF pF C/W C/W
Test Conditions f = 1 MHz Thermocouple located at center of package underside
Device considered a 2-terminal device: Pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together, and Pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together. Input capacitance is from any input data pin to ground
REGULATORY INFORMATION
The ADM2486 has been approved by the following organizations: Table 5.
Organization UL Approval Type Recognized under 1577 component recognition program. File E214100 Notes In accordance with UL1577, each ADM2486 is proof tested by applying an insulation test voltage 3000 V rms for 1 sec (current leakage detection limit = 5 A). In accordance with VDE 0884, each ADM2486 is proof tested by applying an insulation test voltage 1050 VPEAK for 1 sec (partial discharge detection limit = 5 pC).
CSA VDE
Approved under CSA Component Acceptance Notice #5A. File 205078. Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01 Complies with DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01, DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000 File 2471900-4880-0001
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol L(I01) L(I02) Value 2500 7.45 min 8.1 min 0.017 min >175 IIIa Unit V rms mm mm mm V Conditions 1-minute duration. Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance along body. Insulation distance through insulation. DIN IEC 112/VDE 0303 Part 1. Material Group (DIN VDE 0110, 1/89, Table 1).
CTI
Rev. C | Page 7 of 20
ADM2486
VDE 0884 INSULATION CHARACTERISTICS
This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data must be ensured by means of protective circuits. An asterisk (*) on the physical package denotes VDE 0884 approval for 560 V peak working voltage. Table 7.
Description Installation Classification per DIN VDE 0110 for Rated Mains Voltage 150 V rms 300 V rms 400 V rms Climatic Classification Pollution Degree (DIN VDE 0110, Table 1) Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method b1 VIORM x 1.875 = VPR, 100% Production Tested, tm = 1 sec, Partial Discharge < 5 pC Input-to-Output Test Voltage, Method a (After Environmental Tests, Subgroup 1) VIORM x 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC (After Input and/or Safety Test, Subgroup 2/3) VIORM x 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC Highest Allowable Overvoltage (Transient Overvoltage, tTR = 10 sec) Safety-Limiting Values (Mximum Value Allowed in the Event of a Failure. See Figure 21.) Case Temperature Input Current Output Current Insulation Resistance at Ts, VIO = 500 V Symbol Characteristic I to IV I to III I to II 40/85/21 2 560 1050 Unit
VIORM VPR
VPEAK VPEAK
896 VPR VTR 672 4000
VPEAK VPEAK VPEAK
TS IS, INPUT IS, OUTPUT RS
150 265 335 >109
C mA mA
Rev. C | Page 8 of 20
ADM2486 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD1 1 GND11 2 RxD 3
16 VDD2
ADM2486
15 GND21
14 NC TOP VIEW (Not to Scale) 13 RE 4 B 12 A 11 NC 5 10 DE 9
RTS 5 TxD 6
4 PV 7
GND11 8 NC = NO CONNECT
GND21
1 PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED.
EITHER OR BOTH MAY BE USED FOR GND1. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. EITHER OR BOTH MAY BE USED FOR GND2.
Figure 2. Pin Configuration
Table 8.
Pin No. 1 2, 8 3 4 5 6 7 9, 15 10 11, 14 12 13 16 Mnemonic VDD1 GND1 RxD RE RTS TxD PV GND2 DE NC A B VDD2 Function Power Supply (Logic Side). Ground (Logic Side). Receiver Output Data. This output is high when (A - B) > 200 mV, and low when (A - B) < -200 mV. The output is three-stated when the receiver is disabled, that is, when RE is driven high. Receiver Enable Input. This is an active-low input. Driving this input low enables the receiver, and driving it high disables the receiver. Request to Send Input. Driving this input high enables the driver, and driving it low disables the driver. Transmit Data Input. Data to be transmitted by the driver is applied to this input. Power_Valid. Used during power-up and power-down. See the Applications Information section. Ground (Bus Side). Driver Enable Status Output. This output signals the driver enable or disable status to other devices on the bus. DE is high when the driver is enabled and low when the driver is disabled. No Connect. Noninverting Driver Output/Receiver Input. When the driver is disabled, or when VDD1 or VDD2 is powered down, Pin A is put into a high impedance state to avoid overloading the bus. Inverting Driver Output/Receiver Input. When the driver is disabled, or when VDD1 or VDD2 is powered down, Pin B is put into a high impedance state to avoid overloading the bus. Power Supply (Bus Side).
Rev. C | Page 9 of 20
04604-003
ADM2486 TEST CIRCUITS
R VOD R
04604-005
A
VOC
CL1 RLDIFF CL2
04604-007
B
Figure 3. Driver Voltage Measurement
Figure 7. Driver Propagation Delay
375
DE 150
GALVANIC ISOLATION
VOD3
60
VTEST
04604-006
RTS 50pF
375
TxD
Figure 4. Driver Voltage Measurement
RxD RE
A B
DE RTS
GALVANIC ISOLATION
150
Figure 8. RTS-to-DE Propagation Delay
TxD
VDD2 A B 195
VCC A 110 S1 B
04604-004
RxD RE VDD1 GND1
110 195 GND2
TxD
S2
04604-009
50pF
VOUT
VDD2
GND2
RTS
Figure 5. Supply-Current Measurement Test Circuit
A
Figure 9. Driver Enable/Disable
GALVANIC ISOLATION
TxD
VDD2 195 B A 110 470nF 195 GND2 50 22k
04604-010
Figure 10. Receiver Propagation Delay
50 FTEST, 110nF VHF
VCM(HF)
RxD
2.2k RECEIVE GND2 ENABLE VDD1 100nF
+1.5V S1 -1.5V RE CL RL VOUT
04604-012
RTS
DE
B
RE
VOUT CL
VCC
GND1
VDD2 100nF
GND2
VTEST2
S2
04604-013
Figure 6. High Frequency Common-Mode Noise Test Circuit
RE IN
Figure 11. Receiver Enable/Disable
Rev. C | Page 10 of 20
04604-008
VDD1
GND1
VDD2
GND2
ADM2486 SWITCHING CHARACTERISTICS
VDD1 0.5VDD1 0V B 1/2VO VO A 0.5VDD1
0.7VDD1
tPALH tPBLH
tPBHL tPAHL
RTS
0.5VDD1
0.5VDD1 0.3VDD1
tZL
tSKEW tPWD = |tPALH - tPAHL|, |tPBLH - tPBHL| tSKEW
tLZ
A, B
2.3V
VOH + 0.5V
VOH A, B VOL
90% POINT
90% POINT
tZH
2.3V
tHZ
VOH - 0.5V
VOL VOH
10% POINT
tR
tF
04604-011
A, B
0V
Figure 12. Driver Propagation Delay, Rise/Fall Timing
Figure 14. Driver Enable/Disable Timing
0.7VDD1 RE
A-B
0.5VDD1
0.5VDD1 0.3VDD1
0V
0V
tZL
1.5V O/P LOW
tLZ
tPLH
tPHL VOH
RxD
VOL + 0.5V VOL
tZH
O/P HIGH RxD 0V
tHZ
VOH
04604-020
RxD
1.5V
tSKEW = |tPLH - tPHL|
1.5V
VOL
Figure 13. Receiver Propagation Delay
04604-019
1.5V
VOH - 0.5V
Figure 15. Receiver Enable/Disable Timing
Rev. C | Page 11 of 20
04604-021
10% POINT
ADM2486 TYPICAL PERFORMANCE CHARACTERISTICS
1.4 1.2 IDD1 _RCVR_ENABLE @ 5.5V
SUPPLY CURRENT (mA)
1.0 0.8 IDD2 _DE_ENABLE @ 5.5V
1
0.6
2
0.4 0.2
4
04604-029
0 -40 25 TEMPERATURE (C) 85
CH1 2.00V CH3 2.00V
CH2 2.00V CH4 2.00V
M20.0ns A CH2 T 6.00000ns
3.12V
Figure 16. Unloaded Supply Current vs. Temperature
Figure 19. Driver/Receiver Propagation Delay, Low to High (RLDiff = 54 , CL1 = CL2 = 100 pF)
50 45 40 35
RECEIVER tPLH RECEIVER tPHL
1
TIME (ns)
30 25 20 15 10 5
04604-026
3
4
0 -40 25 TEMPERATURE (C) 85
CH1 5.00V CH3 2.00V
CH2 2.00V CH4 2.00V
M20.0ns A CH1 T -444.400ns
2.60V
Figure 17. Driver Propagation Delay vs. Temperature
Figure 20. Driver/Receiver Propagation Delay, High to Low (RLDiff = 54 , CL1 = CL2 = 100 pF)
350
50 45 40 35
TIME (ns)
DRIVER tBHL DRIVER tALH
SAFETY-LIMITING CURRENT (mA) 300
250 SIDE 2 200
30 25 20 15 10 5
DRIVER tBLH
DRIVER tAHL
150 SIDE 1 100 50 0 0 50 100 150 CASE TEMPERATURE (C) 200
04604-027
-40
25 TEMPERATURE (C)
85
Figure 18. Receiver Propagation Delay vs. Temperature
Figure 21. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per VDE 0884
Rev. C | Page 12 of 20
04604-018
0
04604-028
04604-025
ADM2486
0 4.78
-5 OUTPUT CURRENT (mA) OUTPUT VOLTAGE (V)
04604-031
4.76
-10
4.74
-15
4.72
-20
4.70
-25
4.68
04604-033
-30 3.04 3.30 3.56 4.07 4.31 4.55 3.82 OUTPUT VOLTAGE (V) 4.79 5.00
4.66 -40
-25
-10
20 35 50 5 TEMPERATURE (C)
65
80
Figure 22. Output Current vs. Receiver Output High Voltage
Figure 24. Receiver Output High Voltage vs. Temperature I = -4 mA
35 30 OUTPUT CURRENT (mA)
0.32
0.30 OUTPUT VOLTAGE (V)
04604-032
25 20 15
0.28
0.26
0.24
10
0 0 0.23 0.46 0.69 0.93 1.17 1.42 1.67 OUTPUT VOLTAGE (V) 1.93 2.20
0.20 -40
-25
-10
20 35 50 5 TEMPERATURE (C)
65
80
Figure 23. Output Current vs. Receiver Output Low Voltage
Figure 25. Receiver Output Low Voltage vs. Temperature I = -4 mA
Rev. C | Page 13 of 20
04604-034
5
0.22
ADM2486 CIRCUIT DESCRIPTION
ELECTRICAL ISOLATION
In the ADM2486, electrical isolation is implemented on the logic side of the interface. Therefore, the part has two main sections: a digital isolation section and a transceiver section (see Figure 26). Driver input and request-to-send signals, applied to the TxD and RTS pins, respectively, and referenced to logic ground (GND1), are coupled across an isolation barrier to appear at the transceiver section referenced to isolated ground (GND2). Similarly, the receiver output, referenced to isolated ground in the transceiver section, is coupled across the isolation barrier to appear at the RxD pin referenced to logic ground. Table 9. Transmitting
Supply Status VDD1 VDD2 On On On On On On On Off Off On Off Off Inputs RTS H H L X X X TxD H L X X X X Output A B H L L H Z Z Z Z Z Z Z Z DE H H L L L L
Table 10. Receiving
Supply Status VDD1 VDD2 On On On On On On Off Off On On On On On Off On Off Inputs A - B (V) >0.2 <-0.2 -0.2 < A - B < 0.2 Inputs open X X X X
iCoupler Technology
The digital signals are transmitted across the isolation barrier using iCoupler technology. This technique uses chip-scale transformer windings to couple the digital signals magnetically from one side of the barrier to the other. Digital inputs are encoded into waveforms that are capable of exciting the primary transformer winding. At the secondary winding, the induced waveforms are then decoded into the binary value that was originally transmitted.
VDD1 ISOLATION BARRIER VDD2
RE
L or NC L or NC L or NC L or NC H L or NC L or NC L or NC
Output RxD H L I H Z H H L
A TxD ENCODE DECODE D B
POWER-UP/POWER-DOWN THRESHOLDS
The power-up/power-down characteristics of the ADM2486 are in accordance with the supply thresholds shown in Table 11. Upon power-up, the ADM2486 output signals (A, B, RxD, and DE) reach their correct state once both supplies have exceeded their thresholds. Upon power-down, the ADM2486 output signals retain their correct state until at least one of the supplies drops below its power-down threshold. When the VDD1 powerdown threshold is crossed, the ADM2486 output signals reach their unpowered states within 4 s. Table 11. Power-Up/Power-Down Thresholds
Supply VDD1 VDD1 VDD2 VDD2 Transition Power-up Power-down Power-up Power-down Threshold (V) 2.0 1.0 3.3 2.4
RTS
ENCODE
DECODE
DE
RxD
DECODE
ENCODE
R
GND1
GND2
Figure 26. ADM2486 Digital Isolation and Transceiver Sections
TRUTH TABLES
The truth tables in this section use these abbreviations:
Letter H I L X Z NC Description High level Indeterminate Low level Irrelevant High impedance (off) Disconnected
Rev. C | Page 14 of 20
04604-022
RE
DIGITAL ISOLATION
TRANSCEIVER
ADM2486
THERMAL SHUTDOWN
The ADM2486 contains thermal shutdown circuitry that protects the part from excessive power dissipation during fault conditions. Shorting the driver outputs to a low impedance source can result in high driver currents. The thermal sensing circuitry detects the increase in die temperature under this condition and disables the driver outputs. This circuitry is designed to disable the driver outputs when a die temperature of 150C is reached. As the device cools, the drivers are re-enabled at a temperature of 140C.
100.000
MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kGAUSS)
10.000
1.000
0.100
0.010
The receiver input includes a fail-safe feature that guarantees a logic high RxD output when the A and B inputs are floating or open-circuited.
10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz)
100M
Figure 27. Maximum Allowable External Magnetic Flux Density
MAGNETIC FIELD IMMUNITY
Because iCouplers use a coreless technology, no magnetic components are present, and the problem of magnetic saturation of the core material does not exist. Therefore, iCouplers have essentially infinite dc field immunity. The analysis below defines the conditions under which this may occur. The ADM2486's 3 V operating condition is examined because it represents the most susceptible mode of operation. The limitation on the iCoupler's ac magnetic field immunity is set by the condition in which the induced error voltage in the receiving coil (the bottom coil in this case) is made sufficiently large, either to falsely set or reset the decoder. The voltage induced across the bottom coil is given by
-d 2 V = rn ; n = 1, 2, . . . , N dt
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kGauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse and is the worst-case polarity, it reduces the received pulse from >1.0 V to 0.75 V. This is well above the 0.5 V sensing threshold of the decoder. Figure 28 shows the magnetic flux density values in terms of more familiar quantities such as maximum allowable current flow at given distances away from the ADM2486 transformers.
1000.00
MAXIMUM ALLOWABLE CURRENT (kA)
DISTANCE = 1m 100.00 DISTANCE = 5mm 10.00 DISTANCE = 100mm 1.00
where, if the pulses at the transformer output are greater than 1.0 V in amplitude: = magnetic flux density (gauss) N = number of turns in receiving coil rn = radius of nth turn in receiving coil (cm) The decoder has a sensing threshold of about 0.5 V; therefore, there is a 0.5 V margin in which induced voltages can be tolerated. Given the geometry of the receiving coil and an imposed requirement that the induced voltage is, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 27.
0.10
10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz)
100M
Figure 28. Maximum Allowable Current for Various Current-to-ADM2486 Spacings
At combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.
Rev. C | Page 15 of 20
04604-017
0.01 1k
04604-016
RECEIVER FAIL-SAFE INPUTS
0.001 1k
ADM2486 APPLICATIONS INFORMATION
POWER_VALID INPUT
To avoid chatter on the A and B outputs caused by slow powerup and power-down transients on VDD1 (>100 s/V), the device features a power_valid (PV) digital input. This pin should be driven low until VDD1 exceeds 2.0 V. When VDD1 is greater than 2.0 V, this pin should be driven high. Conversely, upon powerdown, PV should be driven low before VDD1 reaches 2.0 V. If the PV pin is driven with an open-drain output, the recommended value for the pull-up resistor is a 10 k resistor, bypassed with a 100 pF capacitor to GND1 (see Figure 30). The power_valid input can be driven, for example, by the output of a system reset circuit such as the ADM809Z, which has a threshold voltage of 2.32 V.
VDD1 VDD1 2.32V 2.0V VDD1
VDD1 10k RESET 100pF
ADM809Z
PV
ADM2486
GND1
2.32V 2.0V
tPOR
RESET
04604-030
Figure 30. Driving PV with an Open-Drain Output
VDD1
ADM809Z
RESET
PV
ADM2486
GND1
VDD1
2.32V 2.0V
2.32V 2.0V
tPOR
RESET
04604-023
Figure 29. Driving PV with ADM809Z
Rev. C | Page 16 of 20
ADM2486
ISOLATED POWER SUPPLY CIRCUIT
The ADM2486 requires isolated power capable of 5 V at 100 mA to be supplied between the VDD2 and GND2 pins. If no suitable integrated power supply is available, a discrete circuit, such as the one in Figure 31, can be used. A center-tapped transformer provides electrical isolation. The primary winding is excited with a pair of square waveforms that are 180 out of phase with each other. A pair of Schottky diodes and a smoothing capacitor are used to create a rectified signal from the secondary winding. The ADP667 linear voltage regulator provides a regulated power supply to the ADM2486's bus-side circuitry. To create the pair of square waves, a D-type flip-flop with complementary Q/Q outputs is used. The flip-flop can be connected so that output Q follows the clock input signal. If no local clock signal is available, a simple digital oscillator can be implemented with a hex-inverting Schmitt trigger and a resistor and capacitor. In this case, values of 3.9 k and 1 nF generate a 364 kHz square wave. A pair of discrete NMOS transistors, switched by the Q/Q flip-flop outputs, conduct current through the center tap of the primary transformer, winding in an alternating fashion.
VCC 100nF 3.9k BS107A
ISOLATION BARRIER SD103C 5V IN OUT 22F 10F
VCC 100nF
PR D
CLR Q VCC BS107A
74HC74A CLK 1nF 74HC14A Q 78253 SD103C
ADP667
SET GND SHDN
VCC VDD1 VDD2
ADM2486
04604-024
GND1
GND2
Figure 31. Isolated Power Supply Circuit
Rev. C | Page 17 of 20
ADM2486 OUTLINE DIMENSIONS
10.50 (0.4134) 10.10 (0.3976)
16 9
7.60 (0.2992) 7.40 (0.2913)
1 8
10.65 (0.4193) 10.00 (0.3937)
1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122)
2.65 (0.1043) 2.35 (0.0925)
0.75 (0.0295) x 45 0.25 (0.0098)
SEATING PLANE
8 0.33 (0.0130) 0 0.20 (0.0079)
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 32. 16-Lead Standard Small Outline Package [SOIC] Wide Body (RW-16) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model ADM2486BRW ADM2486BRW-REEL ADM2486BRWZ1 ADM2486BRWZ-REEL1
1
Data Rate (Mbps) 20 20 20 20
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 16-Lead, Wide Body SOIC 16-Lead, Wide Body SOIC 16-Lead, Wide Body SOIC 16-Lead, Wide Body SOIC
Quantity 47 1,000 47 1,000
Package Option RW-16 RW-16 RW-16 RW-16
Z = Pb-free part.
Rev. C | Page 18 of 20
ADM2486 NOTES
Rev. C | Page 19 of 20
ADM2486 NOTES
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04604-0-3/05(C)
Rev. C | Page 20 of 20

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