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| Features * Programmable DMUX Ratio: - 1:4: Data Rate Max = 1 Gsps - PD (8b/10b) < 4.3/4.7 W (ECL 50 output) - 1:8: Data Rate Max = 2 Gsps - PD (8b/10b) < 6/6.9 W (ECL 50 output) - 1:16 with 1 TS8388B or 1 TS83102G0B and 2 DMUX Parallel Output Mode 8-/10-bit ECL Differential Input Data DataReady or DataReady/2 Input Clock Input Clock Sampling Delay Adjust Single-ended Output Data: - Adjustable Common Mode and Swing - Logic Threshold Reference Output - (ECL, PECL, TTL) Asynchronous Reset Synchronous Reset ADC + DMUX Multi-channel Applications: - Stand-alone Delay Adjust Cell for ADCs Sampling Instant Alignment Differential Data Ready Output Built-in Self Test (BIST) Dual Power Supply VEE = -5V, VCC = +5V Radiation Tolerance Oriented Design (More than 100 Krad (Si) Expected) TBGA 240 (Cavity Down) Package * * * * * * DMUX 8-/10-bit 2 GHz 1:4/8 TS81102G0 * * * * * * * * Description The TS81102G0 is a monolithic 10-bit high-speed (up to 2 GHz) demultiplexor, designed to run with all kinds of ADCs and more specifically with Atmel's high-speed ADC 8-bit 1 Gsps TS8388B and ADC 10-bit 2 Gsps TS83102G0B. The TS81102G0 uses an innovative architecture, including a sampling delay adjust and tunable output levels. It allows users to process the high-speed output data stream down to processor speed and uses the very high-speed bipolar technology (25 GHz NPN cut-off frequency). Rev. 2105C-BDC-11/03 1 Block Diagram Figure 1. Block Diagram Data Path DEMUXDelAdjCtrl Clock Path (to be confirmed) SyncReset AsyncReset ClkInType RatioSel ClkIn FS/8 NAP delay B2 delay BIST 8/10 mux 8/10 ClkPar even master latch even slave latch odd master latch odd slave latch mux Phase control RstGen Reset Counter (8 stage shift register) 8 8 Counter Status Latch Sel Even/Odd [1..8/10] Port Selection Clock 8 FS/8 8 Data Output Clock 1 8/10 3 A[0..7/9] RefA C[0..7/9] RefC E[0..7/9] RefE G[0..7/9] RefG B[0..7/9] RefB D[0..7/9] RefD F[0..7/9] RefF H[0..7/9] RefH DataReady generation Even Ports Odd Ports DR/DR 2 TS81102G0 2105C-BDC-11/03 ADCDelAdjOut ADCDelAdjIn ADCDelAdjCtrl SwiAdj VplusDOut VCC GND VEE DIODE RatioSel I[0..7/9] NbBit BIST TS81102G0 Internal Timing Diagram This diagram corresponds to an established operation of the DMUX with Synchronous Reset. Figure 2. Internal Timing Diagram 500 ps min Data In DR In = Fs DR/2 In = Fs/2 = ClkPar Master Even Latch Master Odd Latch Slave Even Latch Slave Odd Latch Synchronous reset = Fs/8 Internal reset pulse Port Select A Port Select B Port Select C Port Select D Port Select E Port Select F Port Select G Port Select H Latch Select A Latch Select B Latch Select C Latch Select D Latch Select E Latch Select F Latch Select G Latch Select H A to H Port Out A to H LatchOut DROut N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N+10 N+11 N+12 N+13 N+14 N+15 N+16 N+17 N+18 N+19 N+20 N+21 N+22 N+23 N+24 N+25 N+26 N+27 N+28 N+29 N+30 N+31 N N+2 N+4 N+6 N+8 N+10 N+12 N+14 N+16 N+18 N+20 N+22 N+24 N+26 N+28 N+30 N+1 N+3 N+5 N+7 N+9 N+11 N+13 N+15 N+17 N+19 N+21 N+23 N+25 N+27 N+29 N+31 N N+2 N+4 N+6 N+8 N+10 N+12 N+14 N+16 N+18 N+20 N+22 N+24 N+26 N+28 N+30 N+1 N+3 N+5 N+7 N+9 N+11 N+13 N+15 N+17 N+19 N+21 N+23 N+25 N+27 N+29 N N+8 N+16 N+24 N+1 N+9 N+17 N+25 N+2 N+10 N+18 N+26 N+3 N+11 N+19 N+27 N+4 N+12 N+20 N+5 N+13 N+21 N+6 N+14 N+22 N+7 N+15 N+23 N to N+7 N+8 to N+15 N+16 to N+23 3 2105C-BDC-11/03 Functional Description The TS81102G0 is a demultiplexer based on an advanced high-speed bipolar technology featuring a cutoff frequency of 25 GHz. Its role is to reduce the data rate so that the data can be processed at the DMUX output. The TS81102G0 provides 2 programmable ratios: 1:4 and 1:8. The maximum data rate is 1 Gsps for the 1:4 ratio and 2 Gsps for the 1:8 ratio. The TS81102G0 is able to process 8 or 10-bit data flows. The input clock can be an ECL differential signal or single-ended DC coupled signal. Moreover it can be a DataReady or DataReady/2 clock. The input digital data must be an ECL differential signal. The output signals (Data Ready, digital data and reference voltage) are adjustable with VplusD independent power supply. Typical output modes are ECL, PECL or TTL. The Data Ready output is a differential signal. The digital output data and reference voltages are single-ended signals. The TS81102G0 is started by an Asynchronous Reset. A Synchronous Reset enables the user to re-synchronize the output port selection and to minimize loss of data that could occur within the DMUX. A delay adjust cell is available to ensure a good phase between the DMUX' input clock and input data. Another delay adjust cell is available to control the ADCss sampling instant alignment, in case of the ADCs interleaving. A 10-bit generator is implemented in the TS81102G0, the Built-In Self Test (BIST). This test sequence is very useful for testing the DMUX at first use. A fine tuning of the output swing is also available. The TS81102G0 can be used with the following Atmel ADCs: * * TS8388B(F/FS/GL), 8-bit 1 Gsps ADC TS83102G0B, 10-bit 2 Gsps ADC 4 TS81102G0 2105C-BDC-11/03 TS81102G0 Main Function Description Programmable DMUX Ratio The conversion ratio is programmable: 1:4 or 1:8. Figure 3. Programmable DMUX Ratio Input Words: 1,2,3,4,5,6,7,8,... Output Words: PortA PortB 1:4 PortC PortD PortE PortF PortG PortH Input Words: 1,2,3,4,5,6,7,8,... 1 2 3 4 5 6 7 8 ... not used not used not used not used Output Words: PortA PortB 1:8 PortC PortD PortE PortF PortG PortH 1 2 3 4 5 6 7 8 9 ... 10 11 12 13 14 15 16 Parallel Output Mode Figure 4. Parallel Mode ClkIn DR PortA PortB PortC PortD PortE PortF PortG PortH N N+1 N+2 N+3 N+4 N+5 N+6 N+7 Input Clock Sampling Delay Adjust (DEMUXDELADJCTRL) The input clock phase can be adjusted with an adjustable delay (from 250 to 750 ps). This is to ensure a proper phase between the clock and input data of the DMUX. 5 2105C-BDC-11/03 Asynchronous Reset (ASYNCRESET) Figure 5. Asynchronous Reset CLKIN AsyncReset Port A selected Port B selected Port C selected Port D selected Port E selected Port F selected Port G selected Port H selected The Asynchronous Reset is a master reset of the port selection, which works on TTL levels. It is active on the high level. During an asynchronous reset, the clock must be in a known state. It is used to start the DMUX. When it is active, it paralyzes the outputs (the output clock and output data remain at the same level as before the asynchronous reset). When it comes back to its low level, the DMUX starts: the outputs are active and the first processed data is on port A. Synchronous Reset (SYNCRESET) Figure 6. Synchronous Reset FS DR/2 SyncReset = FS/8 Internal reset pulse Port A selected Port B selected Port C selected Port D selected Port E selected Port F selected Port G selected Port H selected The DMUX can be synchronously reset to a programmable state depending on the conversion ratio. The clock must not be stopped during reset. The synchronization signal is a clock (SyncRest) whose frequency is FS/8*n where n is an integer (n = 1,2,3,...) in 1:8 mode and FS/4*n in 1:4 mode. The front edge of this clock is synchronized with Clkln inside the DMUX, and generates a 200 ps reset pulse. This reset pulse occurs during a fixed level of Clkln. If the DMUX was synchronized with Syncreset previous to a possible loss of synchronization, then the output data is immediately correct, no modification can be seen at the output of the DMUX, and no data is lost ("Internal Timing Diagram" on page 3). If the DMUX was not synchronized with SyncReset previous to a possible loss of synchronization, then the output data and data ready of the DMUX are changed. The output data is correct after a number of input clocks corresponding to the pipeline delay ("Timing Diagrams with Synchronous Reset" on page 19). 6 TS81102G0 2105C-BDC-11/03 TS81102G0 Counter Programmable State Pipeline Delay When the counter is reset, its initial states depends on the conversion ratio: * * 1:8: counting on 8 bits, 1:4: counting on 4 bits. The maximum pipeline delay depends on the conversion ratio: * * 1:8: pipeline delay = 7 1:4: pipeline delay = 3 8-/10-bit, with NAP Mode for the 2 Unused Bit ECL Differential Input Data The DMUX is a 10-bit parallel device. The last two bits (bits 8 and 9) may not be used, and the corresponding functions are set to nap mode to reduce power consumption. Input data are ECL compatible (Voh = -0.8V, Vol = -1.8V). The minimum swing required is 100 mV differential. All inputs have a 100 differential termination resistor. The middle point of these resistors is connected to ground through a 10 pF capacitor. Figure 7. ECL Differential Input Data Gnd ClkIn ClkInb 50 50 10 pF 50 Differential Output Data The output clock for the ADC is generated through a 50 loaded long tailed. The 50 resistor is connected to the ground pad via a diode. The levels are (on the 100 differential termination resistor): Vol = -1.4V, Voh = -1.0V. Figure 8. 50 Differential Output Data Gnd 50 ADCDelAdjOut 50 ADCDelAdjOutb 7 2105C-BDC-11/03 Single-ended Output Data To reduce the pin number and power consumption of the DMUX, the eight output ports are single-ended. To reach the high frequency output (up to 250 MHz) with a reasonable power consumption, the swing must be limited to a maximum of 500 mV. The common mode is adjustable from -1.3V to +2V, with Vplus DOut pins. To ensure better noise immunity, a reference level (common mode) is available (one level by output port). The output buffers are of ECL type (open emitters - not resistive adapted impedances). They are designed for a 15 mA average output current, and may be used with a 50 termination impedance. Figure 9. Single-ended Output Data VPlusDOut PadOut Vee Following are three application examples for these buffers: ECL/PECL/TTL. Please note that it is possible to have any other odd output format as far as current (36 mA max) and voltage (Vplus Dout - VEE 8.3V) limits are not overridden. The maximum frequency in TTL output mode depends on the load to be driven. Table 1. Examples of Application of Buffers Parameter VplusDout Vtt Swing Reference Voh Vol Load Average Output Current Output Data rate max. ECL 0 -2 0.5 -1.3 -0.8 -1.8 50 14 250 PECL 3.3 1.3 0.5 2 2.5 1.5 50 14 250 TTL 3.3 0 1 1.5 2.5 0.5 75 15 250 Unit V V V V V V mA Msps This corresponds to the "Adjustable Logic Single" in the pinout description. The "Adjustable Single" buffers for reference voltage are the same buffers, but the information available at the output of these buffers is more like analog than logic. Note: The Max Output Data Rate is given for a typical 50/2 pF load. 8 TS81102G0 2105C-BDC-11/03 TS81102G0 Differential Data Ready Output The front edge of the DataReady output occurs when data is available on the corresponding port. The frequency of this clock depends on the conversion ratio (1:8 or 1:4), with a duty cycle of 50%. The definition is the same as for single-ended output data, but the buffers are differential. This corresponds to the "Adjustable Logic Differential" in the pinout description. Built-in Self Test (BIST) A pseudo-random 10-bit generator is implemented in the DMUX. It generates a 10-bit signal in the output of the DMUX, with a period of 512 input clocks. The probability of occurrence of codes is uniformly spread over the 1024 possible codes: 0 or 1/1024. Note that the 256 codes of bits 1 to 8 occur at least once. They start with a BIST command, in phase with the FS/8 clock on Port A. The logic output obtained on the A to H ports depends on the conversion ratio. The driving clock of BIST is Clkln. The ClklnType must be set to `1' (DataReady ADC clock) to have a different 10-bit code on each output. The complete BIST sequence is available on request. Specifications Absolute Maximum Ratings Table 2. Absolute Maximum Ratings Parameter Positive supply voltage Positive output buffer supply voltage Negative supply voltage Analog input voltages Symbol VCC VPLUSD VEE ADCDelAdjCtrl, ADCDelAdjCtrlb or DMUXDelAdjCtrl, DMUXDelAdjCtrlb or SwiAdj Clkln or Clklnb or I[0...9] or I[0...9]b or SyncReset or SyncResetb or ADCDelAdjln or ADCDelAdjlnb Clkln - Clklnb or I[0...9] - I[0...9]b or SyncReset - Syncresetb or ADCDelAdjln ADCDelAdjlnb Voltage range for each pad Differential voltage range Voltage range for each pad Comments Value GND to 6 GND to 4 GND to -6 -1 to +1 Unit V V V V -1 to +1 -2.2 to +0.6 V ECL 50 input voltage Maximum difference between ECL 50 input voltages Minimum differential swing Maximum differential swing 0.1 V 2 9 2105C-BDC-11/03 Table 2. Absolute Maximum Ratings (Continued) Parameter Data output current Symbol A[0...9] to H[0...9] or RefA to RefH or DR or DRb Clkln Type RatioSel NbBit AsyncReset BIST DIODE DIODE Tj Tstg Comments Maximum current Value 36 Unit mA TTL input voltage GND to VCC V Maximum input voltage on diode for temperature measurement Maximum input current on diode Maximum junction temperature Storage temperature Note: 700 8 135 -65 to 150 mV mA C C Absolute maximum ratings are limiting values, to be applied individually, while other parameters are within specified operating conditions. Long exposure to maximum rating may affect device reliability. The use of a thermal heat sink is mandatory. See "Thermal and Moisture Characteristics" on page 26. Recommended Operating Conditions Table 3. Recommended Operating Conditions Recommended Value Parameter Positive supply voltage Positive output buffer supply voltage Positive output buffer supply voltage Positive output buffer supply voltage Negative supply voltage Operating temperature range Symbol VCC VPLUSD VPLUSD VPLUSD VEE TJ Commercial grade: "C" Industrial grade: "V" ECL output compatibility PECL output compatibility TTL output compatibility Comments Min 4.45 - - - -5.25 Typ 5 0 3.3 3.3 -5 0 < Tc; Tj < 90 -40 < Tc; Tj < 110 Max 5.25 - - - -4.75 Unit V V V V V C 10 TS81102G0 2105C-BDC-11/03 TS81102G0 Electrical Operating Characteristics Tj (typical) = 70C. Full Temperature Range: -40C < Tc; Tj < 110C. (Guaranteed temperature range are depending on part number) Table 4. Electrical Specifications Test Level Value Min Typ Max Unit Note Parameter Power Requirements Positive supply voltage VCC VPLUSDOUT ECL PECL TTL Negative supply voltage VEE Supply Currents ECL (50) and PECL (50) VCC (for every configuration) 1:8, 8 bits 1:8, 10 bits 1:4, 8 bits 1:4, 10 bits TTL (75) VCC (for every configuration) 1:8, 8 bits 1:8, 10 bits 1:4, 8 bits 1:4, 10 bits Nominal power dissipation ECL (50) 1:8, 8 bits 1:8, 10 bits 1:4, 8 bits 1:4, 10 bits Symbol VCC - VPLUSD VPLUSD VPLUSD VEE 1 4.75 - -0.25 3.135 3.135 -5.25 5 - 0 3.3 3.3 -5 5.25 - 0.25 3.465 3.465 -4.75 V - V V V V (1) 1 ICC IPLUSD IEE IPLUSD IEE IPLUSD IEE IPLUSD IEE ICC IPLUSD IEE IPLUSD IEE IPLUSD IEE IPLUSD IEE 1 - 540 - 640 - 270 - 320 - - 760 - 900 - 380 - 450 - 31 1180 719 1140 790 590 592 720 634 31 1610 872 1770 980 810 670 880 729 - 1820 - 2240 - 910 - 1120 - - 2440 - 3010 - 1220 - 1510 - mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA (1) 1 PD PD PD PD 1 5.2 5.9 3.9 4.2 5.6 6.4 4.1 4.5 6 6.9 4.3 4.7 W W W W 11 2105C-BDC-11/03 Table 4. Electrical Specifications (Continued) Test Level Value Min 5.8 6.6 4.2 4.6 6.8 7.8 4.7 5.2 Typ 6.2 7.1 4.4 4.8 7.3 8.4 4.9 5.5 Max 6.6 7.6 4.6 5.1 7.7 9 5.1 5.8 Unit W W W W W W W W Note Parameter PECL (50) 1:8, 8 bits 1:8, 10 bits 1:4, 8 bits 1:4, 10 bits TTL (75) 1:8, 8 bits 1:8, 10 bits 1:4, 8 bits 1:4, 10 bits Delay Adjust Control DMUXDelAdjCtrl differential voltage 250 ps 500 ps 750 ps Input current ADCDelAdjCtrl differential voltage 250 ps 500 ps 750 ps Input current Digital Outputs ECL Output (assuming VPLUSD = 0V, SWIADJ = 0V, 50 termination resistor on board) Logic "0" voltage Logic "1" voltage Reference voltage PECL Output (assuming VPLUSD = 3.3V, SWIADJ = 0V, 50 termination resistor on board) Logic "0" voltage Logic "1" voltage Reference voltage TTL Output (assuming VPLUSD = 3.3V, SWIADJ = 0V, 75 termination resistor on board) Logic "0" voltage Logic "1" voltage Reference voltage Output level drift with temperature (data and DR outputs) Symbol PD PD PD PD PD PD PD PD 1 1 DDAC - IDDAC ADAC - IADAC - - - - - - - - - - - -0.5 0 0.5 - - -0.5 0 0.5 - - - - - - - - - - - V V V mA V V V mA VOL VOH VREF 1 - - - -2.12 -1.16 -1.40 - - - V V V VOL VOH VREF 1 - - - 1.27 2.44 1.83 - - - V V V VOL VOH VREF - 1 - - - - 0.9 2.31 1.2 -1.3 - - - - V V V mV/C - 12 TS81102G0 2105C-BDC-11/03 TS81102G0 Table 4. Electrical Specifications (Continued) Test Level 1 Value Min - Typ -0.9 Max - Unit mV/C Note Parameter Output level drift with temperature (reference outputs) Digital Inputs ECL Input Voltages Logic "0" voltage Logic "1" voltage Symbol - VIL VIH 1 - -1.1 - - -1.4 - V V V V TTL Input Voltages - - 0.8 Logic "0" voltage VIL 1 VIH 2.0 - - Logic "1" voltage Note: 1. The supply current IPLUSD and the power dissipation depend on the state of the output buffers: - the minimum values correspond to all the output buffers at low level, - the maximum values correspond to all the output buffers at high level, - the typical values correspond to an equal sharing-out of the output buffers between high and low levels. Switching Performance and Characteristics 50% clock duty cycle (CLKIN, CLKINB). Tj (typical) = 70C. Full temperature range: -40C < Tc; Tj < 110C. (Guaranteed temperature ranges depend on the part number) See Timing Diagrams Figure 10 on page 16 to Figure 19 on page 21. Table 5. Switching Performances Test Level Value Min Typ Max Unit Note Parameter Input Clock Maximum clock frequency 1:8 ratio 1:4 ratio Clock pulse width (high) Clock pulse width (low) Clock Path pipeline delay DR input clock DR/2 input clock Clock rise/fall time Asynchronous Reset Asynchronous Reset pulse width Setup time from Asynchronous to Clkln Rise/fall time for (10% - 90%) Symbol FMAX TC1 TC2 TCPD TCPD TRCKIN TFCKIN - - - - 2 1 100 100 - - - - - - - 981 1084 100 2.2 1.1 - - - - - GHz ps ps ps ps ps (1) (2) - PWAR TSAR TRAR TFAR - - - 1000 - 1000 - 1500 - - - - ps ps ps 13 2105C-BDC-11/03 Table 5. Switching Performances (Continued) Test Level Value Min Typ Max Unit Note Parameter Synchronous Reset Setup time from SyncReset to Clkln DR input clock DR/2 input clock Hold time from Clkln to SyncReset DR input clock DR/2 input clock Rise/fall for (10% - 90%) Input Data Setup time from I[0...9] to Clkln DR input clock DR/2 input clock Hold time from Clkln to I[0...9] DR input clock DR/2 input clock Rise/fall for (10% - 90%) Output Data Data output delay DR input clock DR/2 input clock Data pipeline delay DR input clock, 1:4 ratio DR input clock, 1:8 ratio DR/2 input clock, 1:4 ratio DR/2 input clock, 1:8 ratio Rise/fall for (10% - 90%) Data Ready Data ready Falling edge DR input clock DR/2 input clock Data ready Rising edge DR input clock DR/2 input clock Asynchr; Reset to DataReady delay Synchr. Reset to DataReady delay Rise/fall for (10% - 90%) Rising edge uncertainty Built-In Self Test Hold time from Clkln to BIST Symbol TSSR - - - - - 100 -580 -477 780 677 - - - - - - ps ps ps ps ps (3) (4) THSR TSRR/TFSR - - (5) (6) TSCKIN - - - - - 100 -794 -691 994 891 - - - - - - ps ps ps ps ps (7) (8) THCKIN TRDI/TFDI - - (9) (10) TOD - - - - - - - - 1820 1717 3 7 3/2 7/2 497/484 - - - - - - - ps ps (11) (12) TPD - Number of input clock ps (13) TROD/tfod - (14) TDRF - - - - - - - - - 1856 1753 1828 1725 1918 1037 450 62 - - - - - - - - ps ps ps ps ps ps ps ps (15) (16) TDRR TARDR TSRDR TRDR/TFDR JITTER - - - - - (17) (18) (19) (20) (21) THBIST - - - - ps (22) 14 TS81102G0 2105C-BDC-11/03 TS81102G0 Table 5. Switching Performances (Continued) Test Level - - Value Min - 1000 Typ 1000 - Max - - Unit ps ps Note Parameter Setup time from Bist to Clkln Rise/fall time for (10% - 90%) ADC Delay Adjust Input frequency Input pulse width (high) Input pulse width (low) Input rise/fall time Output rise/fall time Data output delay (typical delay adjust setting) Output delay drift with temperature Symbol TSBIST TRBIST/ TFBIST FMADA TC1ADA TC2ADA TRIADA/ TFIADA TROADA/ TFOADA TADA TADAT - - - - - - - 2 90 90 100 100 - - - - - - - - 150 150 145 104 784 896 2.5 2.2 - - - - - - - - - GHz ps ps ps ps ps ps/C (23) (24) (25) Output delay uncertainly JITADA - - 30 - ps Notes: 1. TCPD is tuned with DMUXDelAdjCtrl: TCPD = 981 250 ps. 2. TCPD is tuned with DMUXDelAdjCtrl: TCPD = 1084 250 ps. 3. TSSR depends on DMUXDelAdjCtrl: TSSR = -580 250 ps. TSSR < 0 because of Clock Path internal delay. 4. TSSR depends on DMUXDelAdjCtrl: TSSR = -477 250 ps. TSSR < 0 because of Clock Path internal delay. 5. THSR depends on DMUXDelAdjCtrl: THSR = 780 250 ps. 6. THSR depends on DMUXDelAdjCtrl: THSR = 677 250 ps. 7. TSCKIN depends on DMUXDelAdjCtrl: TSCKIN = -794 250 ps. TSCKIN < 0 because of Clock Path internal delay. 8. TSCKIN depends on DMUXDelAdjCtrl: TSCKIN = -691 250 ps. TSCKIN < 0 because of Clock Path internal delay. 9. THCKIN depends on DMUXDelAdjCtrl: THCKIN = 994 250 ps. 10. THCKIN depends on DMUXDelAdjCtrl: THCKIN = 891 250 ps. 11. TOD depends on DMUXDelAdjCtrl: TOD = 1820 250 ps. TOD is given for ECL 50/2 pFoutput load. 12. TOD depends on DMUXDelAdjCtrl: TOD = 1717 250 ps. TOD is given for ECL 50/2 pFoutput load. 13. TPD is the number of Clkln clock cycle from selection of Port A to selection of Port H in 1:8 conversion mode, and from selection of Port A to selection of Port D in 1:4 conversion mode. It is the maximum number of Clkln clock cycle, or pipeline delay, that a data has to stay in the DMUX before being sorted out. This maximum delay occurs for the data sent to Port A. For instance, the data sent to Port H goes directly from the input to the Port H, and its pipeline is 0. But even for this data, there is an additional delay due to physical propagation time in the DMUX. 14. TROD and TFOD are given for ECL 50/2 pF output load. In TTL mode, the TROD and TFOD are twice the ones for ECL. (For other termination topology, apply proper derating value 50 ps/pF in ECL, 100 ps/pF in TTL mode.) 15. TDRF depends on DMUXDelAdjCtrl: TDRF = 1856 250 ps. It is given for ECL 50/2 pF output load. 16. TDRF depends on DMUXDelAdjCtrl: TDRF = 1753 250 ps. It is given for ECL 50/2 pF output load. 17. TDRR depends on DMUXDelAdjCtrl: TDRR = 1858 250 ps. It is given for ECL 50/2 pF output load. 18. TDRR depends on DMUXDelAdjCtrl: TDRR = 1725 250 ps. It is given for ECL 50/2 pF output load. 19. TARDR is given for ECL 50/2 pF output load. 20. TSRDR is given for ECL 50/2 pF output load. It is minimum value since RstSync clock is synchronized with Clkln clock. 21. TRDR and TFDR are given for ECL 50/2 pF output load. 22. THBIST depends on the configuration of the DMUX. There must be enough Clkln clock cycles to have all the 512 codes, (see different Timing Diagrams). 23. With transmission line (ZO = 50) and output load R = 50; C = 2 pF. 24. Without output load. 25. With transmission line (ZO = 50) and output load R = 50; C = 2 pF. 15 2105C-BDC-11/03 Input Clock Timings Figure 10. Input Clock TC2 TFCKIN TC1 TRCKIN TC2 TFCKIN TC1 TRCKIN Clkln TSCKIN Data [0..9] THCKIN TSCKIN THCKIN d1 d2 d3 d4 d5 d1 d2 d3 d4 d5 Clkln Type = 1 DataReady Mode (DR) Clkln Type = 0 DataReady/2 Mode (DR/2) ADC Delay Adjust Timing Diagram Figure 11. ADC Delay Adjust Timing Diagram TC2ADA TFIADA TC1ADA TRIADA ADCDelAdjIn TADA TFOADA TROADA ADCDelAdjOut 16 TS81102G0 2105C-BDC-11/03 TS81102G0 Timing Diagrams with Asynchronous Reset With a nominal tuning of DMUXDelAdj at a frequency of 2 GHz, d1 and d2 data is lost because of the internal clock's path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins to obtain good setup and hold times between Clkln and the data. Figure 12. Start with Asynchronous Rest, 1:8 Ratio, DR Mode TRAR PWAR TFAR ASyncReset TPD Clkn TCPD Internal Port Selection (not available out of the DEMUX) I[0..9] A[0..9] B[0..9] C[0..9] D[0..9] E[0..9] F[0..9] G[0..9] H[0..9] TARDR A d1 d2 B d3 C d4 D d5 E d6 F d7 G d8 TOD H d9 A d10 B d11 C d12 D d13 E d14 F d15 G d16 TOD H d17 d10 d3 d11 d4 d5 d6 d7 d8 TROD/TFOD d9 TDRR TDRF TRDR d12 d13 d14 d15 d16 d17 TFDR DR With a nominal tuning of DMUXDelAdj at 2 GHz, d1 and d2 data is lost because of the internal clock's path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins to obtain good setup and hold times between Clkln and the input data. This timing diagram does not change with the opposite phase of Clkln. Figure 13. Start with Asynchronous Rest, 1:8 Ratio, DR/2 Mode TRAR PWAR TFAR ASyncReset TPD Clkn TCPD TCPD B d1 d2 d3 C d4 D d5 E d6 F d7 G d8 TOD H d9 A d10 B d11 C d12 D d13 E d14 F d15 G d16 TOD d10 d3 d11 H d17 Internal Port Selection (not available out of the DEMUX) I[0..9] A[0..9] B[0..9] C[0..9] D[0..9] E[0..9] F[0..9] G[0..9] H[0..9] TARDR A d4 d12 d5 d6 d13 d14 d7 d15 d8 TROD/TFOD d9 TDRR TDRF TRDR d16 d17 TFDR DR 17 2105C-BDC-11/03 With a nominal tuning of DMUXDelAdj, at 1 GHz (1:4 mode) d1 data is lost because of the internal clock's path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins and is used to obtain good setup and hold times between Clkln and the input data. Figure 14. Start with Asynchronous Reset, 1:4 Ratio, DR Mode TRAR PWAR TFAR ASyncReset TPD Clkn TCPD Internal Port Selection (not available out of the DEMUX) A B C D A B C D I[0..9] d1 d2 d3 TOD d4 d5 d6 d7 TOD d8 A[0..9] d5 B[0..9] d2 d6 C[0..9] d3 d7 D[0..9] TARDR TDRR TDRF TDRR d4 d8 TROD/TFOD DR TRDR TFDR With a nominal tuning of DMUXDelAdj, at 1 GHz (1:4 mode) d1 data is lost because of the internal clock's path propagation delay TCPD. TCPD is tuned with DMUXDelAdjCtrl pins and is used to obtain good setup and hold times between Clkln and the input data. This timing diagram does not change with the opposite phase of Clkln. Figure 15. Start with Asynchronous Reset, 1:4 Ratio, DR/2 Mode TRAR PWAR TFAR ASyncReset TPD Clkn TCPD TCPD B C D A B C Internal Port Selection (not available out of the DEMUX) A I[0..9] d1 d2 d3 TOD d4 d5 d6 d7 TOD d8 A[0..9] d5 B[0..9] d2 d6 C[0..9] d3 d7 D[0..9] TARDR TDRR TDRF d4 d8 TROD/TFOD DR TRDR TFDR 18 TS81102G0 2105C-BDC-11/03 TS81102G0 Timing Diagrams with Synchronous Reset Following is an example of the Synchronous Reset's utility in case of de-synchronization of the DMUX output port selection. The de-synchronization event happens after the selection of Port D. DMUXDelAdjCtrl value is nominal. TSSR < 0 because of Clkln's internal propagation delay TCPD. After selection of Port C, instead of selecting Port D, the de-synchronization makes the port selection to restart on Port A. Since Port H was not selected, the data is not output to the ports but the last data (d1 to d8) is latched until the next selection of Port H. d9 to d16 are lost. The synchronous Reset ensures a re-synchronization of the port selection. Figure 16. Synchronous Reset, 1:8 Ratio, DR Mode THSR THSR THSR SyncReset TSSR TSSR TSSR Clkn I[0..9] d0 d1 Internal Port Selection A (not available out of the DEMUX) A[0..9] B[0..9] C[0..9] D[0..9] E[0..9] F[0..9] G[0..9] H[0..9] TDRR TDRF B d2 C d3 D d4 E d5 F d6 d7 TCPD G H TOD d8 A d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 TCPD B C A B C D E d1 d2 d3 d4 d5 d6 d7 d8 TSRDR A B C D E F G H TOD A B C d17 d18 d19 d20 d21 d22 d23 d24 TDRR TDRF D DR Period of uncertainty due to desynchronization Example of the Synchronous Reset's utility in case of de-synchronization of the DMUX output port selection. The de-synchronization event happens after the selection of Port D. DMUXDelAdjCtrl value is nominal. TSSR < 0 because of Clkln's internal propagation delay TCPD. After selection of Port C, instead of selecting Port D, the de-synchronization makes the port selection to restart on Port A. Since Port H was not selected, the data is not output to the ports but the last data (d1 to d4) is latched until the next selection of Port H. d5 to d8 are lost. The synchronous Reset ensures a re-synchronization of the port selection. 19 2105C-BDC-11/03 Figure 17. Synchronous Reset, 1:4 Ratio, DR Mode THSR SyncReset TSSR Clkn TCPD I[0..9] Internal Port Selection (not available out of the DEMUX) A[0..9] B[0..9] C[0..9] D[0..9] DR d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 B C D A B C D A B C TOD D A B C D d1 d2 d3 d4 TDRF TDRR d9 d10 d11 d12 Period of uncertainty due to desynchronization Example of Synchronous Reset's utility in case of de-synchronization of the DMUX output port selection. The de-synchronization event happens after the selection of Port D. DMUXDelAdjCtrl value is nominal. TSSR < 0 because of Clkln's internal propagation delay TCPD. After selection of Port C, instead of selecting Port D, the de-synchronization makes the port selection to restart on Port A. Since Port H was not selected, the data is not output to the ports but the last data (d1 to d8) is latched until the next selection of Port H. d9 to d16 are lost. The synchronous Reset ensures a re-synchronization of the port selection. Figure 18. Synchronous Reset, 1:8 ratio, DR/2 Mode THSR THSR THSR SyncReset Clkn I[0..9] d0 d1 B d2 C d3 D d4 E TOD d5 F TSSR TSRR TSRR d6 Internal Port Selection (not available out of the DEMUX) A A[0..9] B[0..9] C[0..9] D[0..9] E[0..9] F[0..9] G[0..9] H[0..9] d7 TCPD H d8 A d9 B d10 d11 d12 d13 C A B C d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 TCPD D d1 d2 d3 d4 d5 d6 d7 d8 TSDRR E A B C D E F G H A TOD d17 d18 d19 d20 d21 d22 d23 d24 TDRR TDRF B C D G TDRF DR Period of uncertainty due to desynchronization Example of Synchronous Reset's utility in case of de-synchronization of the DMUX output port selection. The de-synchronization event happens after the selection of Port D. DMUXDelAdjCtrl value is nominal. TSSR < 0 because of Clkln's internal propagation delay TCPD. After selection of Port C, instead of selecting Port D, the de-synchronization makes the port selection to restart on Port A. Since Port H was not selected, the data is not output to the ports but the last data (d1 to d4) is latched until the next selection of Port H. d5 to d8 are lost. The synchronous Reset ensures a re-synchronization of the port selection. 20 TS81102G0 2105C-BDC-11/03 TS81102G0 Figure 19. Synchronous Reset, 1:4 ratio, DR/2 Mode THSR SyncReset TSSR Clkn I[0..9] Internal Port Selection (not available out of the DEMUX) A[0..9] B[0..9] C[0..9] D[0..9] DR Period of uncertainty due to desynchronization d1 d2 d3 d4 d5 d6 d7 TCPD B C D A B C A A B C TOD d1 d2 d3 d4 TDRF d9 d10 d11 d12 TDRR D A B C D d8 d9 d10 d11 d12 d13 d14 d15 d16 Note: In case of low clock frequency and start with asynchronous reset, only the first data is lost and the first data to be processed is the second one. This data is output from the DMUX through port B. 21 2105C-BDC-11/03 Explanation of Test Levels Table 6. Explanation of Test Levels Num 1 2 3 4 5 Notes: Characteristics 100% production tested at +25C.(1) 100% production tested at +25C, and sample tested at specified temperatures.(1) Sample tested only at specified temperatures. Parameter is guaranteed by design and characterization testing (thermal steady-state conditions at specified temperature). Parameter is a typical value only. 1. The level 1 and 2 tests are performed at 50 MHz. 2. Only MIN and MAX values are guaranteed (typical values are issuing from characterization results). 22 TS81102G0 2105C-BDC-11/03 TS81102G0 Package Description Pin Description Table 7. TS81102G0 Pin Description Type Digital Inputs Name I[0...9] Clkln Outputs A[0...9] H[0...9] Levels Differential ECL Differential ECL Adjustable Logic Single Adjustable Logic Differential Adjustable Single Comments Data input. On-chip 100 differential termination resistor. Clock input (Data Ready ADC). On-chip 100 differential termination resistor. Data ready for port A to H. Common mode is adjusted with VplusDOut. Swing is adjusted with SwiAdj. 50 termination possible. Data ready for channel A to H. Common mode is adjusted with VplusDOut. Swing is adjusted with SwiAdj. 50 termination possible. Reference voltage for output channels A to H. Common mode is adjustable with VplusDOut. 50 termination possible. DataReady or Dataready/2: logic 1: Data Ready. DMUX ratio; logic 1: 1:4 Reset and Switch of built-in Self Test (BIST): logic 0: BIST active. Swing fine adjustment of output buffers. Diode for chip temperature measurement. Number of bit 8 or 10: logic 1: 10-bit. Asynchronous reset: logic 1: reset on. Synchronous reset: active on rising edge. Control of the delay line of DataReady input: differential input = -0.5V: delay = 250 ps differential input = 0V: delay = 500 ps differential input = 0.5V: delay = 750 ps Control of the delay line for ADC: differential input = - 0.5V: delay = 250 ps differential input = 0V: delay = 500 ps differential input = 0.5V: delay = 750 ps Stand-alone delay adjust input for ADC. Differential termination of 100 inside the buffer. Stand-alone delay adjust output for ADC. Common ground. Digital negative power supply. Common mode adjustment of output buffers. Digital positive power supply. DR RefA RefH Control Signals ClklnType RatioSel Bist SwiAdj Diode NbBit TTL TTL TTL 0V 0.5V Analog TTL TTL Differential ECL Differential analog input of 0.5V around 0V common mode Differential analog input of 0.5V around 0V common mode Differential ECL 50 differential output Ground 0V Power -5V Adjustable power from 0V to +3.3V Power +5V Synchronization AsyncReset SyncReset DMUXDelAdjCtrl ADCDelAdjCtrl ADCDelAdjln ADCDelAdjOut Power Supplies GND VEE VPlusDOut VCC 23 2105C-BDC-11/03 TBGA 240 Package - Pinout Row A A A A A A A A A A A A A A A A A A A B B B B B B B B B B B B B B B B B B B C C C C C C C C C C C C C C C C C C C D D D Col 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 Name NC E3 E5 E7 E9 C0 C2 C4 C6 C8 REFA A1 A3 A5 A7 A9 DEMUXDELADJCTRL RSTSYNCB NC E1 E2 E4 E6 E8 REFC C1 C3 C5 C7 C9 A0 A2 A4 A6 A8 ASYNCRESET DEMUXDELADJCTRLB RSTSYNC REFE E0 VEE VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VPLUSDOUT VPLUSDOUT GND GND GND DIODE G8 G9 VEE Row D D D D D D D D D D D D D D D D E E E E E E E E F F F F F F F F G G G G G G G G H H H H H H H H J J J J J J J J K K K K Col 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 Name VEE VEE VPLUSDOUT VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT GND VCC VCC GND I0B I0 G6 G7 VPLUSDOUT VEE VEE VEE I1B I1 G4 G5 GND GND GND GND I2B I2 G2 G3 VEE VEE VEE VEE I3B I3 G0 G1 GND GND GND GND CLKINB CLKIN DR REFG VPLUSDOUT VCC VEE VEE I4B I4 SWIADJ DRB VEE VEE Row K K K K L L L L L L L L M M M M M M M M N N N N N N N N P P P P P P P P R R R R R R R R T T T T T T T T T T T T T T T T Col 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name VEE GND I5B I5 H9 RATIOSEL VPLUSDOUT VPLUSDOUT VEE VEE I6B I6 H7 H8 GND GND GND GND I7B I7 H5 H6 VPLUSDOUT VPLUSDOUT VEE VEE I8B I8 H3 H4 GND GND GND GND I9B I9 H1 H2 VPLUSDOUT VPLUSDOUT VEE GND ADCDELADJOUT ADCDELADJOUTB REFH H0 VEE VEE VEE VPLUSDOUT VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VPLUSDOUT GND VEE Row T T T U U U U U U U U U U U U U U U U U U U V V V V V V V V V V V V V V V V V V V W W W W W W W W W W W W W W W W W W W Col 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Name VEE ADCDELADJIN ADCDELADJINB F8 F9 VEE VPLUSDOUT VPLUSDOUT VPLUSDOUT VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VEE VPLUSDOUT VPLUSDOUT VPLUSDOUT GND GND GND GND F7 F6 F4 F2 F0 D9 D7 D5 D3 D1 REFD B8 B6 B4 B2 B0 BIST CLKINTYPE ADCDELADJCTRL NC F5 F3 F1 REFF D8 D6 D4 D2 D0 B9 B7 B5 B3 B1 REFB NBBIT ADCDELADJCTRLB NC 24 TS81102G0 2105C-BDC-11/03 TS81102G0 Figure 20. TBGA 240 Package: Bottom View 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RstSyncb Demuxdeladjctrcl A9 A7 A5 A3 A1 REFA C8 C6 C4 C2 C0 E9 E7 E5 E3 A E1 RstSync Demuxdeladjctrclb Asyncreset A8 A6 A4 A2 A0 C9 C7 C5 C3 C1 REFC E8 E6 E4 E2 B C D E F G H J K L M N P R T U V W DIODE GND GND GND VPLUSD VPLUSD VPLUSD VEE VPLUSD VEE VPLUSD VEE VPLUSD VPLUSD VPLUSD VPLUSD VEE E0 REFE I0 I0b GND VCC VCC GND VPLUSD VEE VPLUSD VEE VPLUSD VEE VPLUSD VPLUSD VEE VEE VEE G9 G8 I1 I1b VEE VEE VEE VPLUSD G7 G6 I2 I2b GND GND GND GND G5 G4 I3 I3b VEE VEE VEE VEE G3 G2 CLK CLKb GND GND GND GND G1 G0 I4 I4b VEE VEE VCC VPLUSD REFG DR I5 I5b GND VEE VEE VEE DRb SWIadj I6 I6b VEE VEE VPLUSD VPLUSD RATIOSEL H9 I7 I7b GND GND GND GND H8 H7 I8 I8b VEE VEE VPLUSD VPLUSD H6 H5 I9 I9b GND GND GND GND H4 H3 ADCdelayadjoutB ADCdelayadjout GND VEE VPLUSD VPLUSD H2 H1 ADCdelayadjinB ADCdelayadjin VEE VEE GND VPLUSD VPLUSD VEE VPLUSD VEE VPLUSD VEE VPLUSD VPLUSD VEE VEE VEE H0 REFH GND GND GND GND VPLUSD VPLUSD VPLUSD VEE VPLUSD VEE VPLUSD VEE VPLUSD VPLUSD VPLUSD VPLUSD VEE F9 F8 ADCDELADJCTRL CLKINTYPE BIST B0 B2 B4 B6 B8 REFD D1 D3 D5 D7 D9 F0 F2 F4 F6 F7 ADCDELADJCTRLb NbBIT REFB B1 B3 B5 B7 B9 D0 D2 D4 D6 D8 REFF F1 F3 F5 25 2105C-BDC-11/03 Outline Dimensions Figure 21. Package Dimension - 240 Tape Ball Grid Array 11 Corner D 0.10 -A-B- 10 19 17 15 13 11 9 7 5 3 1 18 16 14 12 10 8 6 4 2 A B C D E F G H J K L M N P R T U V W e E E1 45 degree 0.5 mm chamfer (4 PLCS) e Detail B D1 Top View Ref. A A1 D D1 E E1 b c M N aaa ccc e g P Dimensional References Min. Nom. 1.30 1.50 0.50 0.60 24.80 25.00 22.86 (BSC.) 24.80 25.00 22.86 (BSC.) 0.60 0.75 0.90 0.80 19.00 240.00 1.27 TYP. 0.35 0.15 Max. 1.70 0.70 25.20 25.20 0.90 1.00 0.15 0.25 - Bottom View Notes: 1. All dimensions are in millimeters. 2. "e" represents the basic solder ball grid pitch. 3. "M" represents the basic solder ball matrix size, and symbol "N" is the maximum allowable number of balls after depopulating. 4 "b" is measured at the maximum solder ball diameter parallel to primary datum - C - g Detail A g 5 Dimension "aaa" is measured parallel to primary datum - C b 0.30 M C A M B M 0.30 M C 6 Primary datum - C - and seatin plane are defined by the spherical crowns of the solder balls. 7. Package surface shall be black oxide. 8. Cavity depth various with die thickness. 9. Substrate material base is copper. 10 Bilateral tolerance zone is applied to each side of package body. Side View 4 Detail B A1 C P A ccc C 11 45 deg. 0.5 mm chamfer corner and white dot for pin 1 identification. -C- 6 Detail A 5 aaa C Thermal and Moisture Characteristics Thermal Resistance from Junction to Case: RTHJC The Rth from junction to case for the TBGA package is estimated at 1.05C/W that can be broken down as follows: * * * * Silicon: 0.1C/W Die attach epoxy: 0.5C/W (thickness # 50 m) Copper block (back side of the package): 0.1C/W Black Ink: 0.251C/W. 26 TS81102G0 2105C-BDC-11/03 TS81102G0 Thermal Resistance from Junction to Ambient: RTHJA A pin-fin type heat sink of a size 40 mm x 40 mm x 8 mm can be used to reduce thermal resistance. This heat sink should not be glued to the top of the package as Atmel cannot guarantee the attachment to the board in such a configuration. The heat sink could be clipped or screwed on the board. With such a heat sink, the Rthj-a is about 6C/W (if we take 10C/W for Rth from the junction to air through the package and heat sink in parallel with 15C/W from the junction to the board through the package body, through balls and through board copper). Without the heat sink, the Rth junction to air for a package reported on-board can be estimated at 13 to 20C/W (depending on the board used). The worst value 20C/W is given for a 1-layer board (13C for a 4-layer board). Thermal Resistance from Junction to Bottom of Balls The thermal resistance from the junction to the bottom of the balls of the package corresponds to the total thermal resistance to be considered from the silicon's die junction to the interface with a board. This thermal resistance is estimated to be 4.8C/W max. The following diagram points out how the previous thermal resistances were calculated for this packaged device. Figure 22. Thermal Resistance from Junction to Bottom of Balls DEMUX - Axpproximative Model for 240 TBGA Assumptions: Square die 7.0 x 7.0 = 49 mm, 75 m thick Epoxy/Ag glue, 0.40 mm copper thickness under die, Sn60Pb40 columns diameter 0.76 mm, 23 x 23 mm TBGA Case were all Bottom of Balls are connected to infinite heatsink (values are in C/Watt) Silicon Junction Typical values (values are in C/Watt) Silicon Junction Silicon Die 49 mm 0.10 0.10 = 0.95Watt/C Epoxy/Ag glue = 0.025Watt/C 0.60 0.60 Reduction Reduction Copper base (Top half of thickness) = 25Watt/C 0.05 1.70 0.05 0.25 1.87 1.43 Tape + glue over balls = 0.02Watt/C 0.05 1.70 0.25 Silicon Junction 2.45 Silicon Junction Copper base 3.55 2.47 1.74 2.47 1.99 Black ink 0.25 0.40 0.31 Balls PbSn = 0.40Watt/C Top of package 2 internal 2 external rows rows (104 balls) (136 balls) Infinite heatsink at bottom of balls Infinite heatsink Infinite heatsink at bottom of balls at bottom of balls Thermal Resistance Junction to case typical = 0.10 + 0.60 + 0.05 + 0.05 + 0.25 = 1.05C/W Thermal Resistance Junction to case Max = 1.40C/W Thermal Resistance Junction to bottom of balls = 4.8C/W Max 27 2105C-BDC-11/03 Temperature Diode Characteristic The theoretical characteristic of the diode according to the temperature when I = 3 mA is depicted below. Figure 23. Temperature Diode Characteristic Vdiode 1.0 DiodeT I = 3 mA dV/dT = 1.32 mV/C 900m (V) 800m 700m -70.0 -20.0 30.0 80.0 130.0 Temperature (C) Moisture Characteristic This device is sensitive to moisture (MSL3 according to the JEDEC standard). The shelf life in a sealed bag is 12 months at < 40C and < 90% relative humidity (RH). After this bag is opened, devices that might be subjected to infrared reflow, vapor-phase reflow, or equivalent processing (peak package body temperature 220C) must be: * * mounted within 168 hours at factory conditions of 30C/60% RH, or stored at 20% RH. The devices require baking before mounting, if the humidity indicator is > 20% when read at 23C 5C. If baking is required, the devices may be baked for: * * 192 hours at 40C + 5C/-0C and < 5% RH for low temperature device containers, or 24 hours at 125C 5C for high-temperature device containers. 28 TS81102G0 2105C-BDC-11/03 TS81102G0 Detailled Cross Section The following diagram depicts a detailed cross section of the DMUX TBGA package. Figure 24. TBGA 240: 1/2 Cross Section Copper Heatspreader Die Attach Epoxy/Ag Block overcoat Adhesive Solder Mask Metal 2 side Polyimide Tape Silicon Die Block Epoxy resin encapsulant Gold wires Copper traces and Solder Balls Pads on metal 1 side Sn/Pb/Ag 62/36/2 Eutectic Solder Balls Solder Mask Metal 1 side In the DMUX package shown above, the die's rear side is attached to the copper heat spreader, so the copper heat spreader is at -5V. It is necessary to use a heat sink tied to the copper heat speader. Moreover, there is only a little layer of painting over the copper heat spreader which does not isolate it. It is therefore recommended to either isolate the heat sink from the other components of the board or to electrically isolate the copper heat spreader from the heat sink. In the latter case, one should use adequate low Rth electrical isolation. 29 2105C-BDC-11/03 Applying the TS81102G0 DMUX The TSEV81102G0 DMUX evaluation board is designed to be connected with the TSEV8388G and TSEV83102G0 ADC evaluation boards. Figure 25. TSEV81102G0 DMUX Evaluation Boards VplusD = 0V 3.3V s-e or diff. (2 GHz) Vee = -5V FS Vcc = +5V (125 MHz) 8x8b/10b single A[0..9] H[0..9] CLOCK BUFFER DEMUX Clkln (1 GHz) 8b/10b diff. Data Bus Data Ready I[0..9] (1 - 2 GHz) 1b diff. Clkln delay DR RefA RefH Analog Input ADC (250 MHz) 1b diff. ECL + ref ECL Rload = 50 Vih = -1.0V Vil = -1.4V Delay adjust control Number of bits (8/10) VplusD = ground Rload = 50 Vtt = -2V Voh = -0.8V Vol = -1.8V Synchronous or Asynchronous Reset 8bits 1 GHz TS8388B 10bits 2 GHz TS83102G0 TTL + ref VplusD = 3.3V Rload 75 Vtt = ground Voh = 2.5V Vol = 0.5V TS81102G0 PECL + ref VplusD = 3.3V Rload = 50 Vtt = 1.3V Voh = 2.5V Vol = 1.5V Please refer to the "ADC and DMUX Application Note" for more information. 30 TS81102G0 2105C-BDC-11/03 ASIC (DC) 8 ref TS81102G0 ADC to DMUX Connections The DMUX inputs configuration has been optimized to be connected to the TS8388B ADC. The die in the TBGA package is up. For the ADC, different types of packages can be used such as CBGA with die up or the CQFP68 down. The DMUX device being completely symmetrical, both ADC packages can be connected to the TBGA package of the DMUX crisscrossing the lines (see Table 8). Table 8. ADC to DMUX Connections ADC Digital Outputs CQFP68 Package D0 D1 D2 D3 D4 D5 D6 D7 - - Note: DMUX Data Inputs TBGA Package I7 I6 I5 I4 I3 I2 I1 I0 18 not connected 19 not connected ADC Digital Outputs CBGA Package D0 D1 D2 D3 D4 D5 D6 D7 - - DMUX Data Inputs TBGA Package I0 I1 I2 I3 I4 I5 I6 I7 18 not connected 19 not connected The connection between the ADC evaluation board and the DMUX evaluation board requires a 4-pin shift to make the D0 pin match either the I7 or I0 pin of the DMUX evaluation board. 31 2105C-BDC-11/03 TSEV81102G0TP: Device Evaluation Board General Description The TSEV81102G0TP DMUX Evaluation Board (EB) is designed to simplify the characterization and the evaluation of the TS81102G0 device (2 Gsps DMUX). The DMUX EB enables testing of all the DMUX functions: Synchronous and Asynchronous reset functions, selection of the DMUX ratio (1:4 or 1:8), selection of the number of bits (8 or 10), output data common mode and swing adjustment, die junction temperature measurements over military temperature range, etc. The DMUX EB has been designed to enable easy connection to Atme's ADC Evaluation Boards (such as TSEV8388BGL or TSEV83102G0BGL) for an extended functionality evaluation (ADC and DMUX multi-channel applications). The DMUX EB comes fully assembled and tested, with a TS81102G0 device implemented on the board and a heat sink assembled on the device. 32 TS81102G0 2105C-BDC-11/03 TS81102G0 Ordering Information Table 9. Ordering Information Part Number JTS81102G0-1V1A TS81102G0CTP TS81102G0VTP TSEV81102G0TPZR3 Package Die TBGA 240 TBGA 240 TBGA 240 Temperature Range Ambient "C" grade 0C < Tc; Tj < 90C "V" grade -40C < Tc; Tj < 110C Ambient Screening Visual inspection Standard Standard Prototype Evaluation board (delivered with heatsink) Comments Datasheet Status Description Table 10. Datasheet Status Datasheet Status Objective specification This datasheet contains target and goal specifications for discussion with customer and application validation. This datasheet contains target or goal specifications for product development. This datasheet contains preliminary data. Additional data may be published later; could include simulation results. This datasheet contains also characterization results. This datasheet contains final product specification. Validity Before design phase Target specification Valid during the design phase Preliminary specification -site Valid before characterization phase Preliminary specification -site Product specification Limiting Values Valid before the industrialization phase Valid for production purposes Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application Information Where application information is given, it is advisory and does not form part of the specification. Life Support Applications These products are not designed for use in life-support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Atmel for any damages resulting from such improper use or sale. 33 2105C-BDC-11/03 Addendum This section has been added to the description of the device for better understanding of the synchronous reset operation. It puts particular stress on the setup and hold times defined in the switching characteristics table (Table 5), linked with the device performances when used at full speed (2 Gsps). It first describes the operation of the synchronous reset in case the DMUX is used in DR mode and then when used in the DR/2 mode. As a reminder, the synchronous reset has to be a signal frequency of Fs/8N in 1:8 ratio or Fs/4N in 1:4 ratio, where N is an integer. The effect of the synchronous reset is to ensure that at each new port selection cycle, the first port to be selected is port A. The synchronous reset ensures the internal cyclic synchronization of the device during operation. It is also highly recommended in the case of multichannel applications using 2 synchronized DMUXs. Synchronous Reset Operation SETUP and HOLD Timings The setup and hold times for the reset are defined as follows: * SETUP from SynchReset to Clkin: Required delay between the rising edge of the reset and the rising edge of the clock to ensure that the reset will be taken into account at the next clock edge. If the reset rising edge occurs at less than this setup time, it will be taken into account only at the second next rising edge of the clock. A margin of 100ps has to be added to this setup time to compensate for the delays from the drivers and lines. * HOLD from Clkin and SynchReset: Minimum duration of the reset signal at a high level to be taken into account by the DMUX. This means that the reset signal has to satisfy 2 requirements: a frequency of Fs/8N or Fs/4N (N is an integer) depending on the ratio and a duty cycle such that it is high during at least the hold time. Operation in DR Mode In DR mode, the DMUX input clock can run at up to 2 GHz in 1:8 ratio or 1 GHz in 1:4 ratio. Both cases are described in the following timing diagrams. Figure 26. Synchronous Reset Operation in DR Mode, 1:4 ratio, 1GHz (Full Speed) - Principle of Operation Fs Sync_RESET 34 TS81102G0 2105C-BDC-11/03 TS81102G0 Figure 27. Synchronous Reset Operation in DR Mode, 1:4 ratio, 1GHz (Full Speed) - TIMINGS Fs Time Zones Allowed for the reset Sync_RESET Note: The clock edge to which the reset applies is the one identified by the arrow. If the reset rising edge had occurred in the second allowed window, the reset would have been effective on the third clock rising edge (not represented, on the right of the edge represented with the arrow). Figure 28. Synchronous Reset Operation in DR Mode, 1:8 ratio, 2 GHz (Full-speed) - Principle of Operation Fs Sync_RESET Figure 29. Synchronous Reset Operation in DR Mode, 1:8 ratio, 2 GHz (Full-speed) - Timings Fs Times Zones Allowed for the reset Sync_RESET Note: The clock edge to which the reset applies is the one identified by the arrow. If the reset rising edge had occurred in the second allowed window, the reset would have been effective on the fourth clock rising edge (last clock rising edge, on the right of the edge represented with the arrow). This case is the most critical one with only a 300 ps window for the reset. 35 2105C-BDC-11/03 Operation in DR/2 Mode In DR/2 mode, the DMUX input clock can run at up to 1 GHz in 1:8 ratio or 500 MHz in 1:4 ratio, since the DR/2 clock from the ADC is half the sampling frequency. Both cases are described in the following timing diagrams. Figure 30. Synchronous Reset Operation in DR/2 Mode, 1:4 ratio, 500MHz (Full Speed) - Principle of Operation Fs/2 Sync_RESET Figure 31. Synchronous Reset Operation in DR/2 Mode, 1:4 ratio, 500 MHz (Full-speed) - Timings Fs/2 Times Zones Allowed for the reset Sync_RESET Note: The clock edge to which the reset applies is the one identified by the arrow. If the reset rising edge had occurred in the first allowed window (on the left), the reset would have been effective on the first represented clock rising edge (first clock rising edge of the schematic, on the left of the edge represented with the arrow). Figure 32. Synchronous Reset Operation in DR/2 Mode, 1:8 ratio, 1GHz (Full Speed) - Principle of Operation Fs/2 Sync_RESET 36 TS81102G0 2105C-BDC-11/03 TS81102G0 Figure 33. Synchronous Reset Operation in DR/2 Mode, 1:8 ratio, 1GHz (Full-speed) - Timings Fs/2 Times Zones Allowed for the reset Sync_RESET Note: The clock edge to which the reset applies is the one identified by the arrow. If the reset rising edge had occurred in the second allowed window, the reset would have been effective on the fourth clock rising edge (not represented, on the right of the edge represented with the arrow). 37 2105C-BDC-11/03 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131, USA TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA TEL 1(719) 576-3300 FAX 1(719) 540-1759 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Literature Requests www.atmel.com/literature (c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. Other terms and product names may be the trademark of others. Printed on recycled paper. 2105C-BDC-11/03 0M |
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