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NJU6678
PRELIMINARY 104-common x 132-segment BIT MAP LCD DRIVER
GENERAL DESCRIPTION The NJU6678 is a bit map LCD driver to display graphics or characters. It contains 21,120 bits display data RAM, microprocessor interface circuits, instruction decoder, 132-segment and 104-common drivers. The bit image display data is transferred to the display data RAM by serial or 8-bit parallel interface. The NJU6678 displays 104 x 132 dots graphics or 8-character 6-line by 16 x 16 dots character. It oscillates by built-in OSC circuit without any external components. Furthermore, the NJU6678 features Partial Display Function which creates up to 2 blocks of active display area and optimizes duty cycle ratio. This function sets optimum boosted voltage by the combination with both of programmable 5-time voltage booster circuit and 201step electrical variable resistor. As result, it reduces the operating current. The operating voltage from 2.5V to 3.3V and low operating current are useful for small size battery operating items. FEATURES Direct Correspondence between Display Data RAM and LCD Pixel Display Data RAM - 21,120 bits (1.5 times over than display size) 236 LCD Drivers - 104-common and 132-segment Direct Microprocessor Interface for both of 68 and 80 type MPU Serial Interface Partial Display Function (2 blocks of active display area and automatic duty cycle ratio selection) Easy Vertical Scroll by the variable start line address and over size display data RAM Programmable Bias selection ; 1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11 bias Common Driver Order Assignment by mask option Version NJU6678A NJU6678B C0 to C103(Pin name) C103(Pin Com0 Com0 to Com103 Com103 Com103 Com103 to Com0 Com0 PACKAGE OUTLINE
NJU6678CL
Useful Instruction Set Display Data Read/Write, Display ON/OFF Cont, Inverse Display, Page Address Set, Display Start Line Set, Partial Display, Bias Select, Column Address Set, Status Read, All On/Off, Voltage Booster Circuits Multiple Select(Maximum 5-time), n-Line Inverse, Read Modify Write, Power Saving, ADC Select, etc. Power Supply Circuits for LCD; Programmable Voltage Booster Circuits(5-time Maximum), Regulator, Voltage Follower x 4 Precision Electrical Variable Resistance Low Power Consumption Operating Voltage Package Outline C-MOS Technology --- 2.5V to 3.3V --- COF / TCP / Bumped Chip Mar.2000 Ver.2.1 LCD Driving Voltage --- 6.0V to 17V
NJU6678
PAD LOCATION
S10 2 S10 3
S104 S105
S28 S29
S27 S26
Y
S130 S131 C103 C102
X
S1 S0 C5 1 C5 0
C53 C52
C1 C0
Chip Center Chip Size Chip Thickness Bump Size Pad pitch Bump Height Bump Material
VD D V1 V2 V3 V4 V5 VR C1 C1 C2 C2 + C3 C3 C4 C4 + V OU T VS S D7( SI) D6( S CL) D5 D4 D3 D2 D1 D0 RD WR A0 CS O S C2 O S C1 T1 T2 VSS RE S CE L 68 P/S VD D D UM MY7 D UM MY6 D UM MY5 D UM MY4 D UM MY3 D UM MY2 D UM MY1 D UM MY0
+
: : : : : : :
X=0um,Y=0um X=5.36mm,Y=5.31mm 675um + 30um 45um x 83um 60um(Min) 15um TYP. Au
+
NJU6678
TERMINAL DESCRIPTION
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Terminal DUMMY0 DUMMY1 DUMMY2 DUMMY3 DUMMY4 DUMMY5 DUMMY6 DUMMY7 VDD P/S CEL68 RES V SS T2 T1 OSC 1 OSC2 CS A0 WR RD D0 D1 D2 D3 D4 D5 D 6(SCL) D 7(SI) V SS V OUT C4
+
Chip Size 5.36 x 5.31mm (Chip Center X=0um,Y=0um)
X= um -2250 -2190 -2130 -2070 -2010 -1950 -1890 -1830 -1747 -1666 -1596 -1487 -1417 -1347 -1238 -1168 -1049 -979 -861 -791 -667 -510 -289 -69 152 372 592 813 1033 1191 1261 1331 1401 1471 1541 1611 1681 1751 1821 1891 1961 2031 2101 2171 2241 2311 2523 2523 2523 2523 Y= um -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2497 -2370 -2310 -2250 -2190 PAD No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Terminal C4 C5 C6 C7 C8 C9 C 10 C 11 C 12 C 13 C 14 C 15 C 16 C 17 C 18 C 19 C 20 C 21 C 22 C 23 C 24 C 25 C 26 C 27 C 28 C 29 C 30 C 31 C 32 C 33 C 34 C 35 C 36 C 37 C 38 C 39 C 40 C 41 C 42 C 43 C 44 C 45 C 46 C 47 C 48 C 49 C 50 C 51 S0 S1 X= um 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 Y= um -2130 -2070 -2010 -1950 -1890 -1830 -1770 -1710 -1650 -1590 -1530 -1470 -1410 -1350 -1290 -1230 -1170 -1110 -1050 -990 -930 -870 -810 -750 -690 -630 -570 -510 -450 -390 -330 -270 -210 -150 -90 -30 30 90 150 210 270 330 390 450 510 570 630 690 750 810
C4C3+ C3
-
C2+ C2C1
+
C1VR V5 V4 V3 V2 V1 VDD C0 C1 C2 C3
NJU6678
PAD No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Terminal S2 S3 S4 S5 S6 S7 S8 S9 S 10 S 11 S 12 S 13 S 14 S 15 S 16 S 17 S 18 S 19 S 20 S 21 S 22 S 23 S 24 S 25 S 26 S 27 S 28 S 29 S 30 S 31 S 32 S 33 S 34 S 35 S 36 S 37 S 38 S 39 S 40 S 41 S 42 S 43 S 44 S 45 S 46 S 47 S 48 S 49 S 50 S 51 X= um 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2523 2250 2190 2130 2070 2010 1950 1890 1830 1770 1710 1650 1590 1530 1470 1410 1350 1290 1230 1170 1110 1050 990 930 870 Y= um 870 930 990 1050 1110 1170 1230 1290 1350 1410 1470 1530 1590 1650 1710 1770 1830 1890 1950 2010 2070 2130 2190 2250 2310 2370 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 PAD No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Terminal S 52 S 53 S 54 S 55 S 56 S 57 S 58 S 59 S 60 S 61 S 62 S 63 S 64 S 65 S 66 S 67 S 68 S 69 S 70 S 71 S 72 S 73 S 74 S 75 S 76 S 77 S 78 S 79 S 80 S 81 S 82 S 83 S 84 S 85 S 86 S 87 S 88 S 89 S 90 S 91 S 92 S 93 S 94 S 95 S 96 S 97 S 98 S 99 S 100 S 101 X= um 810 750 690 630 570 510 450 390 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -390 -450 -510 -570 -630 -690 -750 -810 -870 -930 -990 -1050 -1110 -1170 -1230 -1290 -1350 -1410 -1470 -1530 -1590 -1650 -1710 -1770 -1830 -1890 -1950 -2010 -2070 -2130 Y= um 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497 2497
NJU6678
PAD No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 Terminal S 102 S 103 S 104 S 105 S 106 S 107 S 108 S 109 S 110 S 111 S 112 S 113 S 114 S 115 S 116 S 117 S 118 S 119 S 120 S 121 S 122 S 123 S 124 S 125 S 126 S 127 S 128 S 129 S 130 S 131 C 103 C 102 C 101 C 100 C 99 C 98 C 97 C 96 C 95 C 94 C 93 C 92 C 91 C 90 C 89 C 88 C 87 C 86 C 85 C 84 X= um -2190 -2250 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 Y= um 2497 2497 2370 2310 2250 2190 2130 2070 2010 1950 1890 1830 1770 1710 1650 1590 1530 1470 1410 1350 1290 1230 1170 1110 1050 990 930 870 810 750 690 630 570 510 450 390 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -390 -450 PAD No. 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 Terminal C 83 C 82 C 81 C 80 C 79 C 78 C 77 C 76 C 75 C 74 C 73 C 72 C 71 C 70 C 69 C 68 C 67 C 66 C 65 C 64 C 63 C 62 C 61 C 60 C 59 C 58 C 57 C 56 C 55 C 54 C 53 C 52 X= um -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 -2524 Y= um -510 -570 -630 -690 -750 -810 -870 -930 -990 -1050 -1110 -1170 -1230 -1290 -1350 -1410 -1470 -1530 -1590 -1650 -1710 -1770 -1830 -1890 -1950 -2010 -2070 -2130 -2190 -2250 -2310 -2370
NJU6678
BLOCK DIAGRAM
C0 VS S V DD V1 to V5 5 COM Driver S EG Driver COM Driver C51 S0 S131 C103 C52
C1+ C1C2+ C2C3+ C3C4+ C4-
Shi ft V oltage Generator Reg is t er
Shift Re gis t e r COM SEG Timing Generator
D isp lay
Da ta
La t ch
Output Assignment
Register
VR T1,T2
Row Addr ess Dec oder
Line Address Decoder
C ount er Line
Display Data RAM
160 x 132
Buffer
R egis ter
Culumn Address Decoder Display Culumn A ddress Counter Timing Generator Culumn A ddress Register OSC1 Mu lt ip lexe r OSC. OS C2
Instruction Decoder
Pa ge
Addr ess
I/O
Sta t us
BF
Bus
Ho lde r
In t e rna l
Bu s
Res et
MPU
Interface
RES CS A0
RD
CEL68 WR P/S
D0 to D7 (SI,SCL)
Start Line Regis ter
NJU6678
TERMINAL DESCRIPTION No. 1 to 8 9,46 13,30 45 44 43 42 41 Symbol
DUMMY0 to DUMMY7
I/O Dummy Terminals. These terminals are insulated.
Power
Function
VDD VSS V1 V2 V3 V4 V5
VDD=+3V LCD Driving Voltage Supplying Terminal. When the internal voltage booster is not used, supply each level of LCD driving voltage from outside with following relation. VDD>V1>V2>V3>V4>V5 When the internal power supply is on, the internal circuits generate and supply following LCD bias voltage from V1 to V4 terminals.
Bias
1/4Bias 1/5Bias 1/6Bias 1/7Bias 1/8Bias 1/9Bias 1/10Bias 1/11 Bias
GND VSS=0V
Power
V1 V 5+ 3 / 4 V L C D V 5+ 4 / 5 V L C D V 5+ 5 / 6 V L C D V 5+ 6 / 7 V L C D V 5+ 7 / 8 V L C D V 5+ 8 / 9 V L C D V 5+ 9/10V L C D V 5+ 10/11VLCD
V2 V 5+ 2 / 4 V L C D V 5+ 3 / 5 V L C D V 5+ 4 / 6 V L C D V 5+ 5 / 7 V L C D V 5+ 6 / 8 V L C D V 5+ 7 / 9 V L C D V 5+ 8/10V L C D V 5+9/11V L C D
V3 V 5+ 2 / 4 VLCD V 5+ 2 / 5 VLCD V 5+ 2 / 6 VLCD V 5+ 2 / 7 VLCD V 5+ 2 / 8 VLCD V 5+ 2 / 9 VLCD V 5 +2/10V L C D V 5+2/11V L C D
V4 V 5 + 1 / 4 VLCD V 5 + 1 / 5 VLCD V 5 + 1 / 6 VLCD V 5 + 1 / 7 VLCD V 5 + 1 / 8 VLCD V 5 + 1 / 9 VLCD V 5+ 1/10V L C D V5 +1/11V L C D
(VLCD=VDD-V5) 38,39 36,37 34,35 32,33 31 40 15 14 C1 ,C1 C2 +,C2C3 +,C3C4 +,C4VOUT VR T1 T2
+ -
O
Step up capacitor connecting terminals. Voltage booster circuit (Maximum 5-time)
O I I
Step up voltage output terminal. Connect the step up capacitor between this terminal and VSS . Voltage adjust terminal. V5 level is adjusted by external bleeder resistance connecting between VDD and V5 terminal. LCD bias voltage control terminals. ( *:Don't Care)
T1 L H H T2 * L H Voltage booster Cir. Available Not Avail. Not Avail. Voltage Adj. Available Available Not Avail. V/F Cir. Available Available Available
22 to 29
D0 to D7
(SI) (SCL)
I/O P/S="H" : Tri-state bi-directional Data I/O terminal in 8-bit parallel operation. P/S="L" : D7=Serial data input terminal. D 6=Serial data clock signal input terminal. Data from SI is loaded at the rising edge of SCL and latched as the parallel data at 8th rising edge of SCL. I Connect to the Address bus of MPU. The data on the D 0 to D7 is distinguished between Display data and Instruction by status of A0.
A0 Distin. H Display Data L Instruction
19
A0
12 18
RES CS
I I
Reset terminal. When the RES terminal goes to "L", the initialization is performed. Reset operation is executing during "L" state of RES. Chip select terminal. Data Input/Output are available during CS ="L".
NJU6678
No 21 Symbol RD(E) I/O I Function RD signal of 80 type MPU input terminal. Active "L" During this signal is "L" , D0 to D7 terminals are output. Enable signal of 68 type MPU input terminal. Active "H" Connect to the 80 type MPU WR signal. Actie "L". The data on the data bus input syncronizing the rise edge of this signal. The read/write control signal of 68 type MPU input terminal.
R/W State H Read L Write
20
WR(RW)
I
11
CEL68
I
MPU interface type selection terminal.
CEL68 State
10 P/S I
H 68 Type
L 80 Type
serial or parallel interface selection terminal.
P/S "H" "L"
Chip Select Data/Command
Data D0
to
Read/Write
serial Clock
CS CS
A A0
D7
RD,WR Write Only
SCL(D6)
SI(D7)
RAM data and status read operation do not work in mode of the serial interface. In case of the serial interface (P/S="L"),RD and WR must be fixed "H" or "L", and D0 to D5 are high impedance. 16 17 47
to
OSC1 OSC2 98 C0
to
I O
System clock input terminal for Maker testing.(This terminal should be Open) For external clock operation, the clock shoud be input to OSC1 terminal. LCD driving signal output terminals. Segmet output terminals:S 0 to S1 3 1 Common output terminals:C 0 to C1 0 3 Segment output terminal The following output voltages are selected by the combination of FR and data in the RAM.(non of the n-line inverse functions)
RAM Data H FR H L H L Output Voltage Normal V DD V5 V2 V3 Reverse V2 V3 V DD V5
C 51
99
to
230
S0
to S1 3 1
O
L
282
to
231
C52
to
O
Common output terminal The following output voltages are selected by the combination of FR and status of common.
Scan data H FR H L H L Output Voltage V5 VDD V1 V4
C1 0 3
L
NJU6678
Functional Description (1) Description for each blocks (1-1) Busy Flag (BF) While the internal circuits are operating, the busy flag (BF) is "1" and any instruction excepting for the status read are inhibited . The busy flag goes to "1" from D7 terminal when status read instruction is executed. D7 When enough cycle time over than tCYC indicated in " BUS TIMING CHARACTERISTICS" is ensured, no tCYC need to check the busy flag for reduction of the MPU loads. (1-2)Display Start Line Register The Display start Line Register is a pointer register which indicates the address in the Display Data RAM corresponding with COM0(normally it display the top line in the LCD Panel). This register also operates for COM0 vertical display scroll, the display page change and so on. The Display Start Line Set instruction sets the display start address of the Display Data RAM represented in 8-bit to this register. (1-3) Line Counter The Line Counter generates the line address of display data RAM by the count up operation synchronizing the common cycle after the reset operation at the status change of internal FR signal. (1-4) Column Address Counter The column address counter is 8-bit pre-settable counter addressing the column address of display data RAM as shown in Fig. 1. It is incremented (+1) up to (84)H by the Display Data Read/Write instruction execution. (84)H It stops the count up operation at (84)H, and it does not count up non existing address area over than (84)H by (84)H (84)H the count lock function. This count lock is released by new column address set. The column address counter is independent of the Page Register. By the Address Inverse Instruction, the column address decoder inverse the column address of Display Data RAM corresponding to the Segment Driver. (1-5) Page Register The page register gives a page address of Display Data RAM as shown in Fig. 1. When the MPU accesses the data with the page change, the page address set instruction is required. (1-6) Display Data RAM Display Data RAM is the bit map RAM consisting of 21,120 bits to memorize the display data corresponding to each pixel of LCD panel. The each bit in the Display Data RAM corresponds to the each pixel of the LCD panel and controls the display by following bit data. When Normal Display : On="1" , Off="0" When Inverse Display : On="0" , Off="1" The Display Data RAM outputs 132-bit parallel data in the area addressed by the line counter, and these data are set into the Display Data Latch. The access operation from MPU to the display data RAM and the data output from the display data RAM are so controlled to operate independently that the data rewriting does not influence with any malfunctions to the display.The relation between column address and segment output can inverse by the Address Inverse Instruction ADC as shown in Fig.1.
(1-7) Common Driver Assignment The scanning order can be assigned by mask option as shown on Table 1. Table 1
COM Outputs Terminals PAD No.
Pin name
47 C0 COM0 C O M 103
98 C 51 C O M 51 C O M 52
231 C 103 C O M 103 COM0
282 C52 C O M 52 C O M 51
Ver.A Ver.B
NJU6678
Page Address DATA D0 D1 D2 D4,D3,D2,D1,D0 (0,0,0,0,0) D3 D4 D5 D6 D7 D0 D1 D2 D4,D3,D2,D1,D0 (0,0,0,0,1) D3 D4 D5 D6 D7 D0 D1 D2 D4,D3,D2,D1,D0 (0,0,0,1,0) D3 D4 D5 D6 D7 D0 D1 : : : : : : : : D6 D7 D0 D1 D2 D4,D3,D2,D1,D0 (0,1,1,1,0) D3 D4 D5 D6 D7 D0 D1 D2 D4,D3,D2,D1,D0 (0,1,1,1,1) D3 D4 D5 D6 D7 D0 D1 : : : : : : : : D6 D7 D0 D1 D2 D4,D3,D2,D1,D0 (1,0,0,1,1) D3 D4 D5 D6 D7 | Column Address A D C D 0= " 0 " D 0= " 1 " 00 83 0 | 01 82 1 | 02 81 2 | 03 80 3 | 04 | 05 | 06 | 07 | 08 | 09 | | | | | | | 80 03
128
Display Pattern
Line Address
For example the Display start line is 10 H
00 01 02 Pege 0 03 04 05 06 07 08 09 0A 0B Pege 1 0C 0D 0E 0F 10 11 12 13 Pege 2 14 15 16 17 18 19 : : : : : : : : 6E 6F 70 71 72 Pege 14 73 74 75 76 77 78 79 7A Pege 15 7B 7C 7D 7E 7F 80 81 : : : : : : : : 96 97 98 99 9A 9B Pege 19 9C 9D 9E 9F | | | 83 00
131
Cn Out C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 : : : : C94 C65 C96 C97 C98 C99 C100 C101 C102 C103
7A 7B 7C 7D 7E 7F 09
122
81 82 02 01
129 130
7F 7E 7D 7C 4 5 6 7
7B 7A 8 9
08
123
07
124
06
125
05
126
04
127
Segment Output
Fig.1 Correspondence with Display Data RAM Address
NJU6678
(1-8) Reset Circuit Reset circuit operates the following initializations when the condition of RES terminal goes to "L" level. Initialization 1 Display Off 2 Normal Display (Non-inverse display) 3 ADC Select : Normal (ADC Instruction D0 ="0") D0 4 Read Modify Write Mode Off 5 Internal Power supply (Voltage Booster) circuits Off 6 Static Drive Off 7 Driver Output Off 8 Clear the serial interface register 9 Set the address(00)H to the Column Address Counter address(00)H 10 Set the 1st Line in the Display Start Line Register.page (00)H to the Page Address Register (00)H 11 Set the page "0" to the Page Address Register 12 Set the EVR register to (FF)H (FF)H 13 Set the All display(1/104 duty) 14 Set the Bias select(1/11 Bias) 15 Set the 5-Time Voltage Booster 16 Set the n line turn over register (0)H (0)H The RES terminal should be connected to the Reset terminal of MPU for the initialization at the mean time with MPU as shown in "MPU Interface Example". The period of reset signal requires over than 10us RES="L" level input as shown in "Electrical Characteristics". After 1us from the rise edge of RES signal, the operation goes to normal. When the internal LCD power supply is not used, the external LCD power supply into the NJU6678 must be turned on during RES = "L". Although the condition of RES="L" clear each registers and initialize as above, the oscillation circuit and the output terminal conditions (D0 to D7 ) are not influenced. The initialization must be (D0 D7 performed using RES terminal at the power on, to prevent hung up or any incorrect operations. The reset Instruction performs the initialization procedures from No.8 to No.16 as shown in above. Note) The noise into the RES terminal should be eliminated to avoid the error on the application with the careful design. (1-9) LCD Driving (a) LCD Driving Circuits LCD driving circuits are consisted of 236 multiplexers which operate as 132 Segment drivers and 104 Common drivers. 104 Common drivers with the shift register scan the common display signal. The combination of the Display data, COM scan signal and FR signal form into the LCD driving output voltage. The output wave form is shown in the Fig. 7. (b) Display Data Latch Circuits Display Data Latch stores 132-bit display data temporarily which is output to LCD driver circuits at a common cycle from Display Data RAM addressed by Line Counter. The instructions of Display On/Off, Display inverse ON/OFF and Static Drive On/Off control only the data in Display Data Latch, therefore, the data in the Display Data RAM is not changed. (c) Line Counter and Latch signal of Latch Circuits The clock to Line Counter and latch signal to the Latch Circuits are generated from the internal display clock (CL). The line address of Display Data RAM is renewed synchronizing with display clock(CL). 132 bits display data are latched in display latch circuits synchronizing with display clock, and then output to the LCD driving circuits. The display data transfer to the LCD driving circuits is executed independently with RAM access by the MPU. (d) Display Timing Generator Display Timing Generator generates the timing signal for the display system by combination of the master clock CL and Driving Signal FR ( refer to Fig.2 ). The Frame Signal FR and LCD alternative signal generate LCD driving waveform of the two frame alternative driving method or n-Line inverse driving method.
NJU6678
(e)Common Timing Generation The common timing is generated by display clock. -Waveform of Display Timing(without the n-line inverse functions, the line inverse register in set to 0)
103 104 1 2 3 4 5 6 7 8 101 102 103 104 1 2 3 4 5
C L
F R
C 0
VDD V1 V4 V5 VDD V1 V4 V5
C 1
R MD T A AA VDD V2 V3 V5
Sn
Fig.2 -Waveform of Display Timing(with the n-line inverse function, n=7, the line inverse register in set to 6)
103 104 1 2 3 4 5 6 7 8 101 102 103 104 1 2 3 4 5
C L
F R
C 0
VDD V1 V4 V5 VDD V1 V4 V5
C 1
R MD T A AA VDD V2 V3 V5
Sn
Fig.3
NJU6678
(f) Oscillation Circuit The Oscillation Circuit is a low power CR oscillator incorporating with Resistor and Capacitor. It generates clocks for display timing signal source and voltage booster circuits. The oscillation circuit output frequency is divided as shown in below for display clock CL. -The relation between duty and divide
Duty Divide 1/8 1/50 1/16 1/25 1/24 1/16 1/32 1/12 1/40 1/10 1/48,56 1/8 1/64,72 1/6 1/80,88 1/5 1/96,104 1/4
(g) Power Supply Circuit Internal Power Supply Circuit generate the High voltage and Bias voltage for the LCD. The power Supply Circuit consists of Voltage Booster (5-Time maximum) Circuits, Regulator Circuits, and Voltage Followers. The internal Power Supply is designed for small size LCD panel, therefore it is not suitable for the large size LCD panel application. If the contrast is not good in the large size LCD panel application, please supply the external. The suitable values of the capacitors connecting to the V1 to V 5 terminals and the voltage booster circuit, and V1 V5 the feedback resistors for V5 operational amplifier depend on the LCD panel. And the power consumption with V5 the LCD panel is depending on the display pattern. Please evaluate with actual LCD module. The operation of internal Power Supply Circuits is controlled by the Internal Power Supply On/Off Instruction. When the Internal Power Supply Off Instruction is executed, all of the voltage booster circuits, regulator circuits, voltage follower circuits are turned off. In this time, the bias voltage of V1, V2, V3, V4, and V5 for the V1 V2 V3 V4 V5 LCD should be supplied from outside, terminals C1+, C1-, C2+, C2-, and VR should be open. The status of internal power supply is selected by T1 and T2 terminal. Furthermore the external power supply operates with T1 T2 some of internal power supply function.
T1 L H H T2 L/H L H Voltage Booster ON OFF OFF Voltage Adj. ON ON OFF Buffer(V/F) ON ON ON Ext.Pow Supply VOUT V5,VOUT Open Open Open C1+,C1- to C4+,C4VR Term.
When (T1, T2)=(H, L), C1+, C1-, C2+, C2-,C3+, C3-, C4+, C4- terminals for voltage booster circuits are open (T1 T2 because the voltage booster circuits doesn't operate. Therefore LCD driving voltage to the VOUT terminal VOUT should be supplied from outside. When (T1, T2)=(H, H), terminals for voltage booster circuits and VR are open, because the voltage booster (T1 T2 circuits and Voltage adjust circuits do not operate.
NJU6678
Power Supply applications (1)External power supply operation. (2)Internal power supply operation. (Voltage Booster, Voltage Adj., Buffer(V/F)) Internal power supply ON (instruction) (T1,T (T1,T2)=(L,L)
VDD T 1 V1 V2 V3 V4 V5 VOUT VSS T2
+
VDD T 1 V1
+
T 2 C1+ C1C2+
+ +
V2 V3
+
+
V4
+
C2+
V5
+
C3+ C3C4+ C4+
VOUT VSS VDD
VR
V5
(3)External power supply operation with Voltage Adjustment,3 Buffer(V/F) Internal power supply ON (Instruction) (T1,T2) = (H,L) (T1,T2
(4)External power supply operation adjusted Voltage to V5. Internal power supply (Instruction) (T1,T2) =(H,H) (T1,T2
VDD
+
VDD T 1
+
T 1 V1 T 2 V2 V3
V1 T 2
+ +
V2
+
+
V3
+ +
V4
+
V4 V5 VOUT VSS VR V5
V5 VO UT VSS VDD
: These switches should be open during the power save mode.
NJU6678
(2) Instruction The NJU6678 distinguishes the signal on the data bus by combination of A0, RD and WR. The decode of the instruction and execution performs depending on the internal timing only neither the external clock. In case of serial interface, the data input as MSB first serially. The Table. 4 shows the instruction codes of the NJU6678. (*:Don't Care) Table 4. Instruction Code
Code Instruction
A0 RD WR
Description D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0 1 LCD Display ON/OFF 0:OFF 1:ON Determine the Display Line of RAM to the COM0. (Set the Higher order 4bits) Determine the Display Line of RAM to the COM0. (Set the Lower order 4bits) Set the Higher order 1bit page of DD RAM to the Page Address Register Set the Lower order 4 bit page of DD RAM to the Page Address Register Set the Higher order 4 bits Column Address to the Reg. Set the Lower order 4 bits Column Address to the Reg. 0 Read out the internal Status 0 1 0
(1)
Display ON/OFF
Display Start Line Set (2) High Order 4bits Display Start Line Set Lower Order 4bits (3) Page Address Set High Order 1bits Page Address Set Lower Order 4bits (4) Column Address Set High Order 4bits Column Address Set Lower Order 4bits (5) Status Read
0
1
0
0
1
0
1
High Order Address
0
1
0
0
1
1
0
Lower Order Address * * *
Hi.
0
1
0
0
1
0
0
0
1
0
1
1
0
0
Lower Order Page Address High Order Column Add .
0
1
0
0
0
0
1
0
1
0
0
0
0
0
Lower Order Column Add. 0 0 0
0
0
1
Status
(6)
Write Display Data
1
1
0
Write Data
Write the data into the Display Data RAM Read the data from the Display Data RAM
(7)
Read Display Data
1
0
1
Read Data
(8)
Normal or Inverse of ON/OFF Set Whole Display ON /Normal Display Sub instruction table mode Partial Display 1st Block, Set Start display unit 1st Block, Set The number of display units 2nd Block, Set Start display unit 2nd Block, Set The number of display units Partial display on
0
1
0
1
0
1
0
0
1
1
0 1 0 1 0
Inverse the ON and OFF Display 0:Normal 1:Inverse Whole Display Turns ON 0:Normal 1:Whole Disp. ON Set the Sub instruction table.
(9)
0
1
0
1
0
1
0
0
1
0
(10)
0
1
0
0
1
1
1
0
0
0
(11)
0
1
0
0
0
0
0
Start display unit
Set the Start display unit of 1st Block.
0
1
0
0
0
0
1
number of display units Start display unit
Set the number of display units of 1st Block. Set the Start display unit of 2nd Block. Set the number of display units of 2nd Block. 0 It comes off the mode to set and a display is executed.
0
1
0
0
0
1
0
0
1
0
0
0
1
1
number of display units 0 0 0
0
1
0
0
1
0
0
(12)
n-line Inverse Drive Set Register Set Higher order 2 bits Register Set Lower order 4 bits n-line Inverse Drive Set is executed. 0 1 0 0 1 0 1 * * higher order Set the number of inverse drive line. Set the number of inverse drive line. 0 The execution of the line inverse drive.
0
1
0
0
1
1
0
Lower order
0
1
0
0
1
1
1
0
0
0
(13)
EVR Register Set EVR Register Set Higher order 4 bits EVR Register Set Lower order 4 bits EVR Register Set is executed. 0 1 0 1 0 0 0 EVR Data Higher order EVR Data Lower order 0 0 0 0 Set the V 5 output level to the EVR register. (Higher order 4 bits) Set the V 5 output level to the EVR register. (Lower order 4 bits) The execution of the EVR.
0
1
0
1
0
0
1
0
1
0
1
0
1
0
(14)
End of sub instruction table mode
0
1
0
0
1
1
1
0
0
0
1
It ends the setting of sub instruction table.
NJU6678
(*:Don't Care)
Instruction
A0 RD W R
Code D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 * 0 0 0 0 0 0 0 0 0 0 Bias
Boost Multiple
Description Select the bias (8 Patterns) Set the Booster circuits Read Modify Write mode D 0 =0:On D0=1:End Initialize the internal Circuits
(15) (16) (17) (18) (19) (20)
Bias Select
Voltage Booster Circuits Multiple Select
0 0 0 0 0 0
1 1 1 1 1 1
0 0 0 0 0 0
Read Modify Write /End Reset Internal Power Supply ON/OFF LCD Driving Voltage Set Power Save (Dual Command)
0 1 0 1
0 1 0
0 0:Int. Power Supply OFF 1 1:Int. Power Supply ON 0 1 Set LCD Driving Voltage after the internal (external) power supply is turned on Set the Power Save Mode (LCD Display OFF +Whole Display Turns ON)
(21)
(22)
ADC Select
0
1
0
1
0
1
0
0
0
0
0 1
Set the DD RAM vs Segment D 0 =0:Normal D0=1:Inverse
NJU6678
(3) Explanation of Instruction Code (3-1) Display On/Off This instruction executes whole display On/Off without relationship of the data in the Display Data RAM and internal conditions. R/W
A0 0 RD 1 WR 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 D
D 0:Display Off 1:Display On
(3-2) Display Start Line This instruction sets the line address of Display Data RAM corresponding the COM0 terminal (the highest position line of display in normal application). The display area is fixed automatically by number of display line which corresponds the display duty ratio from the pointed line address as the start line. This instruction realizes the vertical smooth scroll with extra display RAM or the page address change by dynamic line addressing. In this time, the contents of RAM are not changed.
A0 0 0 RD 1 1 R/W WR 0 0 D7 0 0 D6 1 1 D5 0 1 D4 1 0 D3 A7 A3 D2 A6 A2 D1 A5 A1 D0 A4 A0
A7 0 0
A6 0 0
A5 0 0
A4 0 0 : :
A3 0 0
A2 0 0
A1 0 0
A0 0 1
Line Address(HEX) 0 1 : :
1
0
0
1
1
1
1
1
9F
(3-3) Page Address Set When MPU accesses the Display Data RAM, the page address must be selected before the data writing. The access to the Display Data RAM is available by the page and column address set (Refer the Fig. 1). The page address change does not influence with the display.
R/W WR 0 0
A0 0 0
RD 1 1
D7 0 1
D6 1 1
D5 0 0
D4 0 0
D3 * A3
D2 * A2
D1 * A1
D0 A4 A0
(*:Don't Care)
A4 0 0
A3 0 0
A2 0 0 : :
A1 0 0
A0 0 1
Page 0 1 : :
1
0
0
1
1
19
NJU6678
(3-4) Column Address When MPU accesses the Display Data RAM, the page address (refer(3-3) ) and column address set are required before the data writing. The column address set requires twice address set which are higher order 4 bits address set and lower order 4 bits. When the MPU accesses the Display Data RAM sequentially, the column address is increase one by one automatically, therefore, the MPU can access only the data sequentially without address set. After writing 1page data, page address setting is required due to page address doesn't increase automatically. The increment of the column address is stopped at the address of (83)H automatically, and the page address is (83)H not changed even if the column address increase to (83)H and stop. In this time the page address is not (83)H changed.
A0 0 0 RD 1 1 R/W WR 0 0 D7 0 0 D6 0 0 D5 0 0 D4 1 0 D3 A7 A3 D2 A6 A2 D1 A5 A1 D0 A4 A0
Higher Order Lower Order
A7 0 0
A6 0 0
A5 0 0
A4 0 0
A3 0 0 : :
A2 0 0
A1 0 0
A0 0 1
Column Address(HEX) 0 1 : :
1
0
0
0
0
0
1
1
83
(3-5) Status Read This instruction reads out the internal status of "BUSY", "ADC", "ON/OFF" and "RESET".
R/W WR 1
A0 0
RD 0
D7 BUSY
D6 ADC
D5
ON/OFF
D4
RESET
D3 0
D2 0
D1 0
D0 0
BUSY
: BUSY=1 indicate the operating or the Reset cycle. The instruction can be input after the BUSY status change to "0". : Indicate the output correspondence of column (segment) address and segment driver. 0 :Counterclockwise Output (Inverse) Column Address 131-n <---> Segment Driver n 1 :Clockwise Output (Normal) Column Address n <---> Segment Driver n
ADC
(Note) The data "0=Inverse" and "1=Normal" of ADC is inverted with the ADC select Instruction of "1=Inverse" and "0=Normal". ON/OFF : Indicate the whole display On/Off status. 0 : Whole Display "On 1 : Whole Display "Off" (Note) The data "0=On" and "1=Off" of Display On/Off status read out is inverted with the Display On/Off instruction data of "1=On" and "0=Off". RESET : Indicate the initializing by RES signal or reset instruction. 0: 1 : Initialization Period
NJU6678
(3-6) Write Display Data This instruction writes the 8-bit data on the data bus into the Display Data RAM. The column address increases "1" automatically after data writing, therefore, the MPU can write the 8-bit data into the Display Data RAM continuously without any address setting after the start address setting.
A0 1 RD 1 R/W WR 0 D7 D6 D5 D4 D3 D2 D1 D0
WRITE DATA
(3-7) Read Display Data This instruction reads out the 8-bit data from Display Data RAM addressed by the column and page address. The column address increase "1" automatically after data reading out, therefore, the MPU can read out the 8bit data from the Display Data RAM without any address setting after the start address setting. One time of dummy read must operate after column address set as the explanation in "(5-4) Access to the Display Data RAM and Internal Register". In the serial interface mode, the display data is not read out.
A0 1 RD 0 R/W WR 1 D7 D6 D5 D4 D3 D2 D1 D0
READ DATA
(3-8) Normal or Inverse On/Off Set This instruction changes the condition of display turn on and off as normal or inverse. The contents of Display Data RAM is not changed by this instruction execution.
A0 0 RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 D
D 0 : Normal 1 : Inverse
RAM data "1" correspond to "On" RAM data "0" correspond to "On"
(3-9) Whole Display On This instruction turns on the all pixels independent of the contents of Display Data RAM. In this time, the contents of Display Data RAM is not changed and kept. This instruction takes precedence over the "Normal or Inverse On/Off Set Instruction".
A0 0 RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 D
D 0 : Normal Display 1 : Whole Display turn on When Whole Display On Instruction is executed in the Display Off status, the internal circuits go to the power save mode (refer to the (s) Power Save).
NJU6678
(3-10) Sub Instruction table mode This instruction switches the instruction table from the main to the sub. The sub instruction table contains instructions of partial display, n-line inverse drive set and EVR register set as mentioned in (11), (12) and (13). The instruction of sub instruction table mode must be executed before above 3 sub instructions execution. The instruction of end of sub instruction table mode (14) switches the instruction table from the sub to the main. If any main instructions are written in the sub instruction mode, the NJU6678 will malfunction.
A0 0
RD 1
R/W WR 0
D7 0
D6 1
D5 1
D4 1
D3 0
D2 0
D1 0
D0 0
-Set sub Instruction table flow is shown below:
Sub Instruction table mode
Switches to Sub instruction table mode.
Set sub instructions.
End of Sub Instruction table mode.
Switches to Main instruction mode.
NJU6678
(3-11) Partial Display This instruction divides the active display area in a LCD panel to 13 units consisting of 8 commons per unit and displays one or two blocks of active display area consisting of a unit or more. In the partial display mode, the display duty ratio is set automatically according to the number of unit in a block or two. Therefore, the partial display function realizes to go down the LCD driving voltage according to the display duty ratio. As a result, the operation current of display system is much saved against the full display mode. The display units
U NIT U NIT U NIT U NIT U NIT U NIT U NIT U NIT U NIT U NIT U NIT U NIT U NIT 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 (8 c m o o m ns) (8 c m o o m ns)
104-common
132-segment Partial display instruction The partial display operates by the combination of instructions which area unit number of start position start unit block in the display area and a number of display unit from start position to end as a block. The number of block is set up to two.
A0 0 RD 1 R/W WR 0 D7 0 D6 0 D5 0 D4 0 D3 D D2 D D1 D D0 D
Start display unit The number of display units Start display unit The number of display units
1st Block
0 1 0 0 0 0 1 D D D D
0
1
0
0
0
1
0
D
D
D
D
2nd Block
0 1 0 0 0 1 1 D D D D
After execution of the next instruction, the display mode is changed to the partial display and the duty is changed automatically.
0 1 0 0 1 0 0 0 0 0 0
Partial display on
D :unit number (Hex.) Note) In case of full display (1/104 duty), all of units on the display are selected when the first start unit is set to "0" (0,0,0,0) and the second number of display unit is set to "13" (1,1,0,1). In this time, the second block settings are ignored. In case of only one block display, the second block settings are ignored when the second start unit is set to "0" (0,0,0,0) and the second display unit number is set to "0" (0,0,0,0). Keep the order of partial display instruction sequence. Do not set over "UNIT 12" the display data in DD RAM are assigned continuously from page 0 for all of display block, even if non-display area is existed between the first block and the second.
NJU6678
The example of partial display setting UNIT 0 UNIT 1 UNIT 2 UNIT 3 UNIT 4 UNIT 5 UNIT 6 UNIT 7 UNIT 8 UNIT 9 UNIT 10 UNIT 11 UNIT 12 1st Block
2nd Block
active display-block
The above partial display condition is set as follows: 1)Set sub instruction mode
A0 0 RD 1 R/W WR 0 D7 0 D6 1 D5 1 D4 1 D3 0 D2 0 D1 0 D0 0
Set sub instruction mode.
2)Set partial display conditions
A0 0 RD 1 R/W WR 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
1st Block, Set start display unit to "0" 1st Block, Set the number of display units to "2" 2nd Block, Set start display unit to "4" 2nd Block, Set the number of display units to "5" Partial display on.
0
1
0
0
0
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
1
0
1
0
1
0
1
0
0
1
0
0
0
0
0
0
In this case, 1/56 duty. (Duty=1/(number of display units x 8))
3)End sub instruction mode
A0 0 RD 1 R/W WR 0 D7 0 D6 1 D5 1 D4 1 D3 0 D2 0 D1 0 D0 1
End sub instruction mode. Back to main instruction mode.
Although the partial display instruction changes duty cycle ratio automatically and display area, LCD driving voltage, Bias and others are not changed. Therefore, the instruction of LCD driving voltage "OFF" (D=0) must be set before partial display operation, and the other instructions such as the n-line inverse drive set, EVR register set, bias select and voltage booster select should be set for optimum display-contrast. The "End of sub instruction mode" is required before these instructions in order to prevent momentary flickering.
NJU6678
-Set Partial Display flow is shown below:
Internal Power Supply OFF
Sub Instruction Table Mode
Partial Display
n-line Inverse Drive Set EVR Register Set End Sub Instruction Table Mode Bias Select
Voltage Booster Times Select Wait Time Internal Power Supply ON
(3-12) n-line Inverse Drive Mode This instruction sets a line number for inversion of LCD driving signal levels between "1" and "0". It reduces the stripe shadow(crosstalk) and stabilizes display quality. The n-line inverse number is set according to the n-line result of actual LCD panel display. The instructions must be input in order of followings. These instructions are sub instruction sets and must be set after (3-10)Sub instruction table mode.
R/W WR 0
A0 0
RD 1
D7 0
D6 1
D5 0
D4 1
D3 *
D2 *
D1 A5
D0 A4
Higher order Low order (*:Don't Care)
0
1
0
0
1
1
0
A3
A2
A1
A0
A5 0 0
A4 0 0
A3 0 0 : :
A2 0 0
A1 0 0
A0 0 1
Inverse line 2 : :
1
1
1
1
1
1
64
The actual operation starts after following instruction.
R/W WR 0
A0 0
RD 1
D7 0
D6 1
D5 1
D4 1
D3 0
D2 0
D1 0
D0 0
NJU6678
(3-13) EVR Register Set This instruction controls voltage adjustment circuits of internal LCD power supply and changes LCD driving voltage "V5". Finally, it adjusts the contrast of LCD display. By setting a data into EVR register, V5 output voltage selects one condition out of 201-voltage conditions. The range of V5 voltage is adjusted by setting V5 external resistors as mentioned in "(4)(b) Voltage Adjust Circuits". This instruction is sub instruction and it must be set after (3-10) Sub instruction table mode.
A0 0
RD 1
R/W WR 0
D7 1
D6 0
D5 0
D4 0
D3 A7
D2 A6
D1 A5
D0 A4
0
1
0
1
0
0
1
A3
A2
A1
A0
A7 0
A6 0
A5 1
A4 1 : :
A3 0
A2 1
A1 1
A0 1
V LCD Low : :
1
1
1
1
1
1
1
1
High
VLCD=V DD-V 5 LCD=V DD-V When EVR doesn't use, set the EVR register to (1,1,1,1,1,1,1,1).
The actual operation starts after following instruction.
A0 0 RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0
(3-14) End of Sub instruction table mode "End of sub instruction table mode" instruction switches instruction table from sub to main. (11)Partial display, (12)n-line inverse drive mode, and (13)EVR are sub instruction sets on the sub instruction table. The instruction of "END of sub instruction mode" must be set after these sub instruction sets. The NJU6678 may occur incorrect operation if any main instructions on the main instruction table are input in mode of sub instruction table.
A0 0 RD 1 R/W WR 0 D7 0 D6 1 D5 1 D4 1 D3 0 D2 0 D1 0 D0 1
NJU6678
(3-15) Bias Select This instruction decides the value of LCD driving voltage bias ratio. Especially, the bias should be selected for display quality in partial mode.
R/W A0 0 A2 0 0 0 0 1 1 1 1 RD 1 WR 0 A1 0 0 1 1 0 0 1 1 D7 1 D6 0 A0 0 1 0 1 0 1 0 1 D5 1 D4 1 Bias 1/4 1/5 1/6 1/7 1/8 1/9 1/10 1/11 D3 * D2 A2 D1 A1 D0 A0
(*:Don't Care)
(3-16) Voltage Booster Circuit Multiple Select This instruction Selects a voltage boost time. The multiple must be selected the voltage boost times according to the maximum boost times by the external capacitors connections or less. Especially, the multiple should be selected for display quality and saving operation current in partial display mode.
R/W A0 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 1 D3 0 D2 0 D1 A1 D0 A0
Command A1 0 0 1 1 A0 0 1 0 1
Booster Multiple 5times external 4times external 3times external 2times external capacitors capacitors capacitors capacitors connections connections connections connections 2-time 3-time 2-time 4-time 3-time 2-time 5-time 4-time 3-time 2-time
NJU6678
(3-17) Read Modify Write/End This instruction sets the Read Modify Write Mode for the column address increment control. In mode of the Read Modify Write, the column address increases "1" automatically when the Display Data Write Instruction is executed, but the address does not change when the Display Data Read Instruction is executed. This status is continued until End instruction execution. When the End instruction (D=1) is input, the column address goes back to the start address before the Read Modify Write instruction input. This function reduces the load of MPU for repeating the display data change in the fixed area (ex. cursor blink). D="1" to release the Read Modify Write mode and the column address back to the address where the read modify write mode setting.
R/W WR 0
A0 0
RD 1
D7 1
D6 1
D5 1
D4 0
D3 0
D2 0
D1 0
D0 D
D 0 : Read Modify Write On 1 : End Note) In mode of the Read Modify Write, any instructions except for Column Address Set can execute.
- Sequence of cursor blink display
Page Address Set
Set to the Start Address of Cursor Display
Column Address Set
Read Modify Write
Start the Read Modify Write
Dummy Read
Read the Data as dummy
Data Read
Data inverse by MPU
Data Write
Dummy Read
Data Read
Data Write
End
End the Read Modify Write
NO Finish?
YES
NJU6678
(3-18) Reset This instruction executes the following initialization. Initialization (1) Set the Address (00)H into the Column Address Counter. (00)H (2) Set the Address (00)H into the Display Start Line Register. (00)H (3) Set the page "0" into the Page Address Register. (4) Set 0 to the EVR Register to (FF)H. (FF)H (5) Set the All display(1/104 duty) (6) Set the Bias select(1/11 Bias) (7) Set the 5-Time Voltage Booster. (8) Set the n-line inverse register (0)H (0)H In this time, the Display Data RAM is not influenced.
R/W WR 0
A0 0
RD 1
D7 1
D6 1
D5 1
D4 0
D3 0
D2 0
D1 1
D0 0
The reset signal input to the RES terminal (hardware reset) must be input for the power on initialization. Reset instruction does not perform completely in stead of hardware reset using the RES terminal.
(3-19) Internal Power Supply ON/OFF This instruction set the condition of internal Power Supply On/Off. Voltage Booster circuits, Voltage Regulator and Voltage Follower operate at On. To operate the voltage booster circuits, the oscillation circuits must be operating.
A0 0 RD 1 R/W WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 D
D 0 : Internal Power Supply Off 1 : Internal Power Supply On The internal Power Supply must be Off when external power supply using. *1 The set up period of internal power supply On depends on the step up capacitors, voltage stabilizer capacitors, VDD and VLCD. Therefore it requires the actual evaluation using the LCD module to get the correct time. (Refer to the (4)(d) Fig.4)
NJU6678
(3-20) LCD Driving Voltage Set This instruction controls LCD driving waveform output through the COM/SEG terminals.
A0 0 RD 1 R/W WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 1 D0 D
D 0 : LCD driving waveform output Off 1 : LCD driving waveform output On The NJU6678 contains low power LCD driving voltage generator circuit reducing own operation current. Therefore, it requires the following sequence procedures at power on for the power source stabilized operation.
- LCD driving power supply ON/OFF sequences The following sequences are required when the power supply is turned On/Off. When the power supply is turned on again after the turn off (by the power save instruction), the power save release sequence ((3-21) Power Save) is required. Turn ON sequence
Output Assign. Register Set
Turn OFF sequence
Display OFF Whole Display ON Internal Power Supply OFF or External Power Supply OFF LCD Driving Voltage Set to OFF
EVR Register Set Internal Power Supply ON or External Power supply ON (Wait Time) *1 LCD Driving Voltage Set to ON
*1 The wait time depends on the C1 to C9, COUT capacitors (refer (4) (d)Fig.4), VDD and VLCD voltage. C1 C9 COUT VDD VLCD Therefore it requires the actual evaluation using the LCD module to get the correct time. (Refer to the following graph.)
The wait time [Typical performance]
100 80 Time[ms] 60 40 20 0 0 0.2 0.4 0.6 C3 to C7[uF] 0.8 1 1.2
T.B.D.
Cout=1 to 4.7[uF]
VDD=2.7V,VLCD=7V,Ta=25C
NJU6678
(3-21) Power Save(Dual Command) When both of Display Off and Whole Display On are executed, the internal circuits go to the power save mode and the operating current is reduced as some as the stand by current. The internal status in the Power Save Mode is shown in follows; (1) (2) (3) (4) Stop the Oscillation Circuits and Internal Power Supply Circuits operation. Stop the LCD driving. Segment and Common drivers output VDD level. VDD Keep the display data and operating mode just before the power save mode. All of LCD driving bias voltage fix to the VDD level. VDD
The power save and its release perform according to the following sequences. Power Save Sequence
Display OFF
Power Save Release Sequence
Normal Display Display ON (Wait Time) LCD Driving Voltage Set to ON (Whole Display OFF)
Whole Display ON
LCD Driving Voltage Set to OFF
*1 In the power save sequence, the power save mode is started after the second instruction "whole Display ON". *2 In the power save release sequence, the power save mode is released after the Normal Display instruction (Whole display OFF). The instruction of display ON is input at any timing after the instruction of normal display in power save release sequence. *3 Until "LCD driving voltage set to ON" execution, NJU6678 operating current is higher than usual state and all COM/SEG terminals output VDD level continuously. VDD *4 In case of the external power supply for LCD driving, it should be turned off and made condition like as unconnection or connected to VDD before the power save mode or at the same time. In this time, VOUT VDD VOUT terminal should be made condition like as disconnection or connected to the lowest voltage of the system (V5 (V 5 level from the external power supply). (3-22) ADC Select This instruction set the correspondence of column address in the Display Data RAM and segment driver output. (See Fig. 1.) By this instruction, the order of segment output can be changed by the software, and no restriction of the LSI placement against the LCD panel.
A0 0 RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 D
D 0 : Clockwise Output (Normal) 1 : Counterclockwise Output (Inverse)
NJU6678
(4) Internal Power Supply (a) 5-time voltage booster circuits 5-time voltage booster circuits connecting five capacitors between C1+ and C1-, C2+ and C2-, C3+ and C3-, C4+ and C4-, VSS and VOUT boost the voltage of VDD - VSS to negative voltage (V DD Common) and output the VSS VOUT VDD VSS (VDD boosted voltage from the VOUT terminal. It selects one of boost time from 2 to 5 times by external capacitors VOUT connection. Furthermore, it also selects one of boost time by "Voltage Booster circuits multiple select" instruction. The boost voltage and the voltage booster circuits are shown in below. Voltage Booster circuits requires the clock signals from internal oscillation circuit, therefore, the oscillation circuits must be operating when voltage boost operation. The boost voltage times are shown in below. When 5-time voltage boost operation, the operation voltage of VDD-V OUT should be less than 17V. VDD-V VDD=+3V DD=+3V VSS= + 0V SS= VOUT=-VDD=-3V OUT=-V DD=-3V VOUT=-2VDD=-6V OUT=-2VDD=-6V VOUT=-3VDD=-9V OUT=-3VDD=-9V VOUT=-4VDD=-12V OUT=-4VDD=-12V 2-time voltage 3-time voltage 4-time voltage 5-time voltage
Examples for connecting the capacitors 5-time voltage
VSS C+ 1 C1 C 2+ C 2C+ 3 C 3C 4+ C4 VO T U
+ + + + +
4-time voltage
VSS C+ 1 C1 C 2+ C 2C+ 3 C 3C 4+ C4 VT OU
+ + + +
3-time voltage
VSS C+ 1 C1 C 2+ C 2C+ 3 C 3C 4+ C4 VO T U
+ + +
2-time voltage
VSS C+ 1 C1 C 2+ C 2C+ 3 C 3C 4+ C4 VO T U
+ +
NJU6678
(b)Voltage Adjust Circuits The boosted voltage of VOUT output from V5 through the voltage adjust circuits for LCD driving. The output VOUT V5 voltage of V5 is adjusted by changing the Ra and Rb within the range of | V5 | < | VOUT |. The output voltage V5 V5 VOUT is calculated by the following formula. VLCD = VDD-V 5 = (1+Rb/Ra)V REG VDD-V5 (1+Rb/Ra)VREG
(1)
VDD VREG R a R 1 V R R 2
V5
R 3
R b
Fig. 3 The voltage of VREG is a standard voltage produced from built-in bleeder resistance. VREG is possible to be VREG VREG fine-adjusted by EVR functions mentioned in (c). For fine-adjustment of V5, R2 as variable resistor, R1 and R3 as fixed constant should be connected to VDD VDD terminal, VR and V5, as shown in Fig.3. V5,
[ Design example for R1, R2 and R3 / Reference ] - R1+R2+R3=5M (Determined by the current flown between VDD-V 5 ) R1+R2+R3=5M VDD-V5 - Variable voltage range by the R2. -6V to -7.5V (V LCD=VDD-V 5 --> 9.0V to 10.5V) (VLCD=VDD-V5 (Determined by the LCD electrical characteristics) - VREG=3V(In case of EVR=(FF)H) VREG=3V(In EVR=(FF)H - R1, R2 and R3 are calculated by above conditions and the formula of (1) to below; R1=2.0M R1=2.0M , R2=0.5M , R3=2.5M R2=0.5M R3=2.5M * If the power supply voltage between VDD and VSS changes, V5 changes too. Therefore the power supply VDD VSS V5 voltage should be stabilized for V5 stable operation. V5
NJU6678
(c) Contrast Adjustment by the EVR function The EVR controls voltage of VREG by instruction and changes voltage of V5 . VREG V5 As result, LCD display contrast is adjusted by V5. The EVR selects a voltage of VREG in the following 201 V5 VREG conditions by setting 6bits data into the EVR register. In case of EVR operation, T1 terminal and T2 require to set couples of value as (L,L),(L,H) and (H,L) excepting T1 T2 for (H,H) and the internal power supply must turn on by instruction. (37)H to (4F)H available for use. If keeping 3% precision set EVR over (4F)H.
EVR register : : (0,1,0,0,1,1,1,1) : : (1,1,1,1,1,1,0,1) (1,1,1,1,1,1,1,0) (1,1,1,1,1,1,1,1) V REG[ V ] : : (124/300) x (VDD -V S S) : : (298/300) x (VDD -V S S) (299/300) x (VDD -V S S) (300/300) x (VDD -V S S) V LCD Low : : : : : : High
: : (4F)H : : (FD)H (FE)H (FF)H
Adjustable range of the LCD driving voltage by EVR function The adjustable range is decided by the power supply voltage VDD and the ratio of external resistors VDD Ra and Rb. [ Design example for the adjustable range / Reference ] - Condition VDD=3.0V, VSS=0V VDD=3.0V, VSS=0V Ra=1M Rb=4M Ra=1M , Rb=4M ( Ra:Rb=1:4 ) The adjustable range and the step voltage are calculated as follows in the above condition. In case of setting (4F)H in the EVR register, (4F)H VLCD = ((Ra+Rb)/Ra)VREG ((Ra+Rb)/Ra)VREG = (5/1) x [(124/300) x 3.0] = 6.2V In case of setting (FF)H in the EVR register, (FF)H VLCD = ((Ra+Rb)/Ra)VREG ((Ra+Rb)/Ra)VREG = (5/1) x [(300/300) x 3.0] = 15.0V
Min.(4F)H Max.(FF)H 15.0 [V]
Adjustable Range Step Voltagre
6.2
-------------------
50
[mV]
* In case of VDD=3V VDD=3V
NJU6678
*) The VLCD operating temperature. Please refer to the following graphs. VLCD (conditions) VDD = 3V VDD Ra=1M Rb=4M Ra=1M , Rb=4M ( Ra:Rb = 1:4 ) Five times voltage
VLCD vs. Temperature (Typical Performance)
16 14 12 10 8 6 4 2 0
-30 -20 -10
VLCD [V]
T.B.D.
VLCD EVR=(FF)H VLCD EVR=(4F)H
0
10
20
30
40
50
60
70
80
Ta [oC]
NJU6678
(d) LCD Driving Voltage Generation Circuits The LCD driving bias voltage of V1,V2,V 3,V4 are generated internally by dividing the V5 voltage with the V1,V2 ,V4 V5 internal bleeder resistance. And it is supplied to the LCD driving circuits after the impedance conversion with voltage follower circuit. As shown in Fig. 4, Five capacitors are required to connect to each LCD driving voltage terminal for voltage stabilizing. And the value of capacitors C5, C6, C7, C8 and C9 are determined depending on the actual LCD panel display evaluation. Using the internal Power Supply Using the external Power Supply
VSS
VSS C 1+ C 1C 2+ C 2C 3+ C 3C 4+ C 4-
C1 COU T
+
C 1+ C 1-
+
C2
+
C 2+ C 2-
C3
+
C 3+ C 3-
C4
+
C 4+ C 4V OU T
NJU6678
V O UT
NJU6678
R3 V5 V5
R2
VR
VR
R1 VD D
V DD V1
+ + + + +
C5 C6 C7 C8 C9
V1 V2 V3 V4 V5
E xternal Voltage Generator
V2 V3 V4 V5
Reference set up value VLCD=VDD-V5 = 9.0 to 10.5V
COUT C1 to C4, C9 C5 to C8 R1 R2 R3 to 1uF to 1uF 0.1 to 0.47uF 2.0M 0.5M 2.5M
Fig.4 *1 Short wiring or sealed wiring to the VR terminal is required due to the high impedance of VR terminal. *2 Following connection of VOUT is required when external power supply using. VOUT When VSS > V5 --- VOUT=V 5 VSS V5 VOUT=V When VSS < V5 --- VOUT=VSS VSS V5 VOUT=VSS
NJU6678
(5) MPU Interface (5-1) Interface type selection NJU6678 interfaces with MPU by 8-bit bidirectional data bus (D7 to D0) or serial (SI:D7). The 8 bit parallel or (D7 D0 (SI:D7 serial interface is determined by a condition of the P/S terminal connecting to "H" or "L" level as shown in Table 5. In case of the serial interface, status and RAM data read out operation is impossible. Table 5
P/S H L Type Parallel Serial CS CS CS A0 A0 A0 RD RD WR WR CEL68 CEL68 D7 D7 SI D6 D6 SCL D 0 to D5 D 0 to D5 Hi-Z
(5-2) Parallel Interface The NJU6678 interfaces to 68 or 80 type MPU directly when the parallel interface (P/S="H") is selected. 68 type MPU or 80 is determined by the condition of CEL68 terminal connecting to "H" or "L" as shown in table 6. Table 6
CEL68 H L Type 68 type MPU 80 type MPU CS CS CS A0 A0 A0 RD E RD WR R/W WR D0 to D7 D0 to D7 D0 to D7
(5-3) Discrimination of Data Bus Signal The NJU6678 discriminates the mean of signal on the data bus by the combination of A0, E, R/W, and (RD,WR) signals as shown in Table 7. Table 7
Common A0 1 1 0 0 68 type R/W 1 0 1 0 RD 0 1 0 1 80 type WR 1 0 1 0 Function Read Display Data Write Display Data Status Read Write into the Register(Instruction)
(5-4) Serial Interface.(P/S="L") Serial interface circuits consist of 8 bits shift register and 3 bits counter. SI and SCL input are activated when the chip select terminal CS set to "L"and P/S terminal set to "L". The 8 bits shift register and 3 bits counter are reset to the initial condition when the chip is not selected. The data input from SI terminal is MSB first like as the order of D7,D6,- - - - D0, and the data are entered into the shift register synchronizing with the rise edge of D7,D6 D0, the serial clock SCL. The data in the shift register are converted to parallel data at the 8th serial clock rise edge input. Discrimination of the display data or instruction of the serial input data is executed by the condition of A0 at the 8th serial clock rise edge. A0="H" is display data and A0="L" is instruction. When RES terminal becomes "L" or CS terminal becomes "H" before 8th serial clock rise edge, NJU6678 recognizes them as a instruction data incorrectly. Therefore a unit of serial data must be structured by 8-bit. The time chart for the serial interface is shown in Fig. 5. To avoid the noise trouble, the short wiring is required for the SCL input. Note) The read out function, such as the status or RAM data read out, is not supported in this serial interface .C S
SI SL C A 0 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 D7 D 6 1 0
Fig. 5
NJU6678
(5-5) Access to the Display Data RAM and Internal Register. The NJU6678 is operating as one of pipe-line processor by the bus-holder connecting to the internal data bus to adjust the operation frequency between MPU and the Display Data RAM or Internal Register. For example, when the MPU reads out the data from the Display Data RAM, the read out data in the data read cycle (dummy read) is held in the bus-holder, then it is read out from the bus-holder to the system bus at the next data read cycle. When the MPU writes the data into the Display Data RAM, the data is held in the busholder, then it is written into the Display Data RAM by the next data write cycle. Therefore high speed data transmission between MPU and NJU6678 is available because of it is not limited by the tACC and tDS as display data RAM access time and is limited by the system cycle time (R) or (W). tACC tDS If the cycle time is not be kept in the MPU operation, NOP should be inserted to the system instead of the waiting operation. The read out operation does not read out the data in the pointed address just after the address set operation. And second read out operation can read out the data correctly from the pointed address. Therefore, one dummy read operation is required after address setting or write cycle as shown in FIG. 6. Write Operation
MU P W R DT AA N
N1 +
N+ 2
N3 +
Inter nal Ti min g
I/O B uffer
N
N+ 1
N2 +
N3 +
W R
Read Operation
MP U WR RD DA TA N
Address Set N
N
Dummy Read
n
Data Read n
n+1
Data Read n+1
Internal Timing
W R RD Column Address I/O Buffer
N N n
N+1 n+1
N+2 n+2
Fig.6 (5-6) Chip Select CS is Chip Select terminal. In case of CS="L", the interface with MPU is available. In case of CS="H", the D0 D0 to D7 are high impedance and A0, RD, WR, D7(SI) and D6(SCL) inputs are ignored. If the serial interface is D7 D7 D6 selected when CS="H",the shift register and the counter are reset. However, the reset is always operated in any conditions of CS.
NJU6678
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage (1) Supply Voltage (2) Supply Voltage (3) Input Voltage Operating Temperature Storage Temperature SYMBOL VDD V5 V 1 to V4 V IN To p r T stg -55 to +100 (TCP) RATINGS -0.3 to +5.0 V D D- 17.0 to VD D +0.3 V 5 to VD D+ 0.3 -0.3 to VD D +0.3 -30 to +80 -55 to +125 (Chip)
(Ta=25 (Ta=25 C)
UNIT V V V V
C C
Note 1) If the LSI are used on condition above the absolute maximum ratings, the LSI may be destroyed. Using the LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the electric characteristics conditions will cause malfunction and poor reliability. Note 2) All voltage values are specified as VSS=0 V. VSS=0 Note 3) The relation : VDD > V1 > V2 > V3 > V4 > V5 ; VDD > VSS > VOUT must be maintained. VDD V1 V2 V3 V4 V5 VDD VSS VOUT Note 4) Decoupling capacitor should be connected between VDD and VSS due to the stabilized operation for VDD VSS the voltage converter. (VDD=2.5V to 3.3V, VSS=0V, Ta=-30 to +80C ) +80
CONDITIONS MIN. 2.5 VDD -17.0 VLCD = VDD -V 5 D0...D7,A0, CS,RES,RD,WR,CEL68, P/S Terminals D0...D7 IOH=-0.5mA Terminals IOL= 0.5mA All Input terminals VLCD =15.0V VLCD =8.0V during Power save Mode Display V LCD=12.0V Accessing f CYC =200kHz Ta=25C
VDD-0.5VLCD
ELECTRICAL CHARACTERISTICS (1)
PARAMETE Operating Voltage(1) OperatingVoltage(2) Input Voltage Output Voltage High Low High Low Level Level Level Level SYMBOL V DD V5 V 1,V 2 V 3,V 4 V IHC1 VILC1 VOHC11 VOLC11 ILIO RON1 RON2 ID D Q IDD12 IDD21
TYP.
MAX. 3.3 VDD -6.0 V DD
VDD-0.5VLCD
UNIT Note V V V V V V uA k uA uA 6 7 8 9 5
V5 0.8V DD V SS 0.8V DD V SS - 1.0 2.0 3.0 0.05 15 600
V DD 0.2VDD V DD 0.2VDD 1.0 3.0 4.5 5 40 800
Input Leakage Current Driver On-resistance Stand-by Current Operating Current
NJU6678
PARAMETER Input Terminal Capacitance Oscillation Frequency Output Volt.
SYMBOL
CIN fOSC V OUT1 RTRI
CONDITIONS A0,CS,RES,RD,WR,CEL68, P/S,T1,T2,D 0...D 7 Ta=25C Ta=25C V S S-Vout, 5-time voltage booster, V D D=3V V D D=3V;C OUT =4.7uF 5-time voltage booster Voltage Booster Circuit "OFF"
MIN
TYP 10
MAX
UNIT Note pF
26 VD D-15.0V
32
38 V D D-14.5V
kHz V
On-resistance
2000
4000
Adjustment range of LCD Voltage Driving Volt. Booster Voltage Follower Operating Current Voltage Reg.
VOUT2 Voltage Adjustment Circuit "OFF" V D D=3V, VLCD =12V COM/SEG Terminals Open No Access Display Checkered pattern V D D=3V,Ta=25C, V REG=4F to FFH
VD D-17.0V
VD D-6.0V
V 10
V5 IOUT1 IOUT2 IOUT3 V REG%
VD D-17.0V 160 35 25
VD D-6.0V 320 70 50 3
V
uA
11
%
12
Note 5) NJU6678 can operate wide operating range, but it is not guarantee immediate voltage changing during the accessing of the MPU. Note 6) Apply to the High-impedance state of the D0 to D7 terminals. D0 D7 Note 7) RON is the resistance values between power supply terminals(V 1, V2, V3, V4) and each output RON terminals(V1 V2 V3 V4 terminals of common and segment supplied by 0.1V. This is specified within the range of supply voltage (2). Note 8,9,11) Apply to current after "LCD Driving Voltage Set". Note 8) Apply to the external display clock operation in no access from the MPU and no use internal power supply circuits. Note 9) Apply to the condition of cyclic (tcyc) inverted data input continuously in no use internal power supply circuits. The operating current during the accessing is proportionate to the access frequency. In the no accessing period, it is as same as IDD1X. IDD1X. Note 10) LCD driving voltage V5 can be adjusted within the voltage follower operating range. V5 Note 11) Each operating current of voltage supply circuits block is specified under below table conditions.
Status SYMBOL IO U T 1 IO U T 2 IO U T 3 T1 L H H T2 * L H Internal Oscillator Validity Validity Validity
Operating Condition Voltage Booster Validity Invalidity Invalidity Voltage Adjustment Validity Validity Invalidity Voltage Follower Validity Validity Validity
External Voltage Supply (Input Terminal) Unuse Use(V O U T ) Use(V O U T ,V 5)
(* = Don't Care) Note 12) Apply to the precision of the voltage between VDD and V5 with EVR function. VDD V5
NJU6678
MEASUREMENT BLOCK DIAGRAM :IOUT1 :IOUT1
VDD VR V5
A
VS C S 1+ +
NJU6678
C1-C2+ + + C 2- C3+ + C3 -C4+ + C4VU OT
T 1
T 2
:IOUT2 :IOUT2
VDD VR V5
A
VS C+ S 1
NJU6678
C-C + 1 2 C2 C+ 3 C -C + 34 C4 VU OT
T 1
T 2
:IOUT3 :IOUT3
VDD VR V5
A
VS C+ S 1
NJU6678
C-C + 1 2 C2 C+ 3 C -C + 34 C4 VU OT
T 1
T 2
ELECTRICAL CHARACTERISTICS (2)
PARAMETER Reset time Reset "L" Level Pulse Width SYMBOL tR tRW CONDITIONS RES Terminal RES Terminal
(VDD=2.5V to 3.3V, VSS=0V, Ta=-30 to +80C ) +80
MIN 1.0 10 TYP MAX UNIT Note us us 13 14
Note 13) Specified from the rising edge of RES to finish the internal circuit reset. Note 14) Specified minimum pulse width of RES signal. Over than tRW "L" input should be required for correct tRW reset operation.
NJU6678
BUS TIMING CHARACTERISTICS - Read/Write operation sequence (80 Type MPU)
tCYC8 A 0,C S tAW8 tCCL tCCH tA H8
WR R, D
tDS8
tDH8
D0 to D7 ( rite) W
tf
tr
tA CC
tCH8
D0 to D7 ( ea R d)
(VDD= (V DD= 2.5V to 3.3V ,Ta=-30 to +80C ) 3.3V,Ta=-30 +80
PARAMETER Address Hold Time Address Set Up Time System Cycle WR Time RD
WR,"L"
A0,CS Terminals
SYMBOL tAH8 tAW8
tCYC8 (W)
MIN. 10 0 270 350 50 200 220 150 35 15 0
TYP.
MAX.
CONDITION
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns
220
Control Pulse Width
RD,"L"
WR,"H"
WR,RD Terminals
RD,"H"
Data Set Up Time Data Hold Time RD Access Time Output Disable Time Rise Time, Fall Time
D0 to D7 Terminals
CS, WR, RD, A0, D0 to D7 Terminals
tCYC8 (R) tCCL(W) tCCL(R) tCCH(W) tCCH(R) tDS8 tDH8 tACC8 tCH8 tr,tf
160
120 50 15
CL=100pF
Note 15) Rise time (t r) and fall time (t f ) of input signal should be less than 15ns. (tr (tf Note 16) Each timing is specified based on 0.2xVDD and 0.8xVDD. 0.2xVDD 0.8xVDD.
NJU6678
- Read/Write operation sequence (68 Type MPU)
tCYC6 tE WL E tA W6 RW / tr tEWH tf tA H6
A0, S C tDS6 D0 to D7 ( rite) W tACC6 D0 to D7 ( ea R d) tO H6 tDH6
(VDD= (V DD= 2.5V to 3.3V ,Ta=-30 to +80C ) 3.3V,Ta=-30 +80
SYMBOL PARAMETER Address Hold Time tAH6 Address Set Up Time A0,CS,R/W tAW6 Terminals tCYC6(W) System Cycle Time(W) System Cycle Time(R) tCYC6(R) Read"H" Write"H" Enable Pulse Width Read"L" Write"L" Data Set Up Time Data Hold Time Access Time Output Disable Time
tEWH E Terminal tEWL tDS6 tDH6 tACC6 tOH6 tr,tf
D0 to D7 Terminals
A0, CS, R/W, E, D0 to D7 Terminals
MIN. 10 0 270 350 200 50 220 150 35 15 0
TYP.
MAX.
CONDITION UNIT
220
160
200 50 15
CL=100pF
ns ns ns ns ns ns ns ns ns ns ns ns ns
Rise Time, Fall Time
Note 17) tCYC6 indicates the E signal cycle during the CS activation period. The System Cycle Time must be tCYC6 required after CS becomes active. Note 18) Rise time (t r) and fall time (t f ) of input signal should be less than 15ns. (tr (tf Note 19) Each timing is specified based on 0.2xVDD and 0.8xVDD. 0.2xVDD 0.8xVDD.
NJU6678
- Write operation sequence (Serial Interface)
tCSS C S
tCS H
tSAS A 0
tSAH
tSCYC tSLW SL C tSHW
tS DS SI
tSDH
tf
tr
(VDD= (V DD= 2.5V to 3.3V ,Ta=-30 to +80C ) 3.3V,Ta=-30 +80
PARAMETER SYMBOL Serial Clock cycle tSCYC SCL SCL "H" pulse width tSHW Terminal SCL "L" pulse width tSLW Address Set Up Time tSAS A0 Terminal Address Hold Time tSAH Data Set Up Time tSDS SI Terminal Data Hold Time tSDH CS-SCL Time CS Terminal SCL, A0, CS, SI Terminals tCSS tCSH tr,tf MIN. 120 40 80 0 150 25 10 10 300 15 TYP. MAX. CONDITION UNIT ns ns ns ns ns ns ns ns ns ns
Rise Time, Fall Time
Note 20) Rise time (t r) and fall time (t f ) of input signal should be less than 15ns. (tr (tf Note 21) Each timing is specified based on 0.2xVDD and 0.8xVDD. 0.2xVDD 0.8xVDD. Note 22) In case of instruction set continuously, it is required to wait more than 450ns between the instruction and next as follows. SCL 8th clock SCL 1st clock
SCL
Instruction N
450 ns SCL"L"pulse width (Between the instruction and next)
Instruction N+1
NJU6678
LCD DRIVING WAVEFORM
0 VD D FR VSS VDD V1 V2 C OM 0 V3 V4 V5 VDD V1 V2 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 C OM 2 VDD V1 V2 V3 V4 V5 C OM 1 V3 V4 V5
1
2
3
4
1 21 3 00
0
1
2
3
4
5
1 21 3 0 0
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
SEG0
SEG1
SEG2
SEG3
SEG4
VDD V1 V2 SEG0 V3 V4 V5 VDD V1 V2 SEG1 V3 V4 V5
V5 V4 V3 V2 V1 COM0-SEG0 VD D
-V1 -V2 -V3 -V4 -V5
V5 V4 V3 V2 V1 COM0-SEG1 VD D
-V1 -V2 -V3 -V4 -V5
Fig.7
NJU6678
APPLICATION CIRCUIT - Microprocessor Interface Example The NJU6678 interfaces to 80 type or 68 type MPU directly. And the serial interface also communicate with MPU.
- 80 Type MPU
VCC A0 A0 VDD CEL68 A0 to A7 IORQ CS
Decoder NJU6678
MPU
D0 to D7 RD WR GND RES
D0 to D7 RD WR RES VSS P/S
RESET
- 68 Type MPU
VCC VDD CEL68 A0 to A15 VMA CS
A0
A0
Decoder NJU6678
MPU
D0 to D7 E R/W GND RES
D0 to D7 E R/W RES VSS P/S
RESET
- Serial Interface
VCC
A0
A0
VDD CEL68
A1 to A7
CS
Decoder MPU
Port1 Port2 SI SCL P/S GND RES RES VSS
NJU6678
VDD OR GND
RESET
NJU6678
LCD Panel Interface Example
LCD Pan el (104 x 132)
C0
C 51
S0
S 131
C 103
C52
NJU6678
BOTTOM VIEW
CAUTION The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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