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a
Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs and 10-Bit Data Input ADV7195
FUNCTIONAL BLOCK DIAGRAM
SHARPNESS FILTER CONTROL AND ADAPTIVE FILTER CONTROL
FEATURES INPUT FORMATS YCrCb in 2 10-Bit (4:2:2) or 3 10-Bit (4:4:4) FormatCompliant to SMPTE-293M (525p), ITU-R.BT1358 (625p), SMPTE274M (1080i), SMPTE296M (720p) and Any Other High-Definition Standard Using Async Timing Mode RGB in 3 10 Bit (4:4:4) Format OUTPUT FORMATS YPrPb Progressive Scan (EIA-770.1, EIA-770.2) YPrPb HDTV (EIA-770.3) RGB Levels Compliant to RS-170 and RS-343A 11-Bit + Sync (DAC A) 11-Bit DACs (DAC B, DAC C) PROGRAMMABLE FEATURES Internal Test Pattern Generator with Color Control Y/C Delay ( ) Gamma Correction Individual DAC On/Off Control 54 MHz Output (2 Oversampling) Sharpness Filter with Programmable Gain/Attenuation Programmable Adaptive Filter Control Undershoot Limiter VBI Open Control I2C(R) Filter CGMS-A (525p) 2-Wire Serial MPU Interface Single Supply 3.3 V Operation 52-MQFP Package APPLICATIONS Progressive Scan/HDTV Display Devices MPEG at 81 MHz Progressive Scan/HDTV Projection Systems Digital Video Systems High Resolution Color Graphics Image Processing/Instrumentation Digital Radio Modulation/Video Signal Reconstruction
ADV7195
CGMS MACROVISION 11-BIT+ SYNC DAC
Y0-Y9
TEST PATTERN GENERATOR AND DELAY AND GAMMA CORRECTION CHROMA 4:2:2 TO 4:4:4 (SSAF) CHROMA 4:2:2 TO 4:4:4 (SSAF)
LUMA SSAF
DAC A (Y)
Cr0-Cr9
11-BIT DAC 2 INTERPOLATION
11-BIT DAC
DAC B
Cb0-Cb9
DAC C
CLKIN HORIZONTAL SYNC VERTICAL SYNC BLANKING RESET
TIMING GENERATOR I2C MPU PORT
SYNC GENERATOR
DAC CONTROL BLOCK
VREF RESET COMP
The ADV7195 has three separate 10-bit-wide input ports that accept data in 4:4:4 10-bit YCrCb or RGB or 4:2:2 10-bit YCrCb. This data is accepted in progressive scan format at 27 MHz or HDTV format at 74.25 MHz or 74.1758 MHz. For any other high-definition standard but SMPTE293M, ITU-R BT.1358, SMPTE274M or SMPTE296M the Async Timing Mode can be used to input data to the ADV7195. For all standards, external horizontal, vertical, and blanking signals or EAV/SAV codes control the insertion of appropriate synchronization signals into the digital data stream and therefore the output signals. The ADV7195 outputs analog YPrPb progressive scan format complying to EIA-770.1, EIA-770.2; YPrPb HDTV complying to EIA-770.3; RGB complying to RS-170/RS-343A. The ADV7195 requires a single 3.3 V power supply, an optional external 1.235 V reference and a 27 MHz clock in Progressive Scan Mode or a 74.25 MHz (or 74.1758 MHz) clock in HDTV mode. In Progressive Scan Mode, a sharpness filter with programmable gain allows high-frequency enhancement on the luminance signal. Programmable Adaptive Filter Control, which may be used, allows removal of ringing on the incoming Y data. The ADV7195 supports CGMS-A data control generation. The ADV7195 is packaged in a 52-lead MQFP package.
GENERAL DESCRIPTION
The ADV7195 is a triple high-speed, digital-to-analog encoder on a single monolithic chip. It consists of three high-speed video D/A converters with TTL-compatible inputs.
I2C is a registered trademark of Philips Corporation.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
ADV7195
TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1 3.3 V SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 V DYNAMIC-SPECIFICATIONS . . . . . . . . . . . . . . . . . . 4 3.3 V TIMING-SPECIFICATIONS . . . . . . . . . . . . . . . . . . 5 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 8 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 9 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 10 Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Undershoot Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Internal Test Pattern Generator . . . . . . . . . . . . . . . . . . . . 10 Y/CrCb Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 54 MHz Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PROGRAMMABLE SHARPNESS FILTER . . . . . . . . . . . 10 PROGRAMMABLE ADAPTIVE FILTER CONTROL . . 11 INPUT/OUTPUT CONFIGURATION . . . . . . . . . . . . . . 11 MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 11 REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 13 Subaddress Register (SR7-SR0) . . . . . . . . . . . . . . . . . . . 13 Register Select (SR6-SR0) . . . . . . . . . . . . . . . . . . . . . . . . 13 PROGRESSIVE SCAN MODE . . . . . . . . . . . . . . . . . . 14 MODE REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MR0 (MR07-MR00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MR0 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output Standard Selection (MR00-MR01) . . . . . . . . . . . 14 Input Control Signals (MR02-MR03) . . . . . . . . . . . . . . . 14 Input Standard (MR04) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reserved (MR05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DV Polarity (MR06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reserved (MR07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MODE REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 MR1 (MR17-MR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 MR1 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pixel Data Enable (MR10) . . . . . . . . . . . . . . . . . . . . . . . . 16 Input Format (MR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Test Pattern Enable (MR12) . . . . . . . . . . . . . . . . . . . . . . 16 Test Pattern Hatch/Frame (MR13) . . . . . . . . . . . . . . . . . 16 VBI Open (MR14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Undershoot Limiter (MR15-MR16) . . . . . . . . . . . . . . . . 16 Sharpness Filter (MR17) . . . . . . . . . . . . . . . . . . . . . . . . . 16 MODE REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MR1 (MR27-MR20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 MR2 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 17 Y Delay (MR20-MR22) . . . . . . . . . . . . . . . . . . . . . . . . . 17 Color Delay (MR23-MR25) . . . . . . . . . . . . . . . . . . . . . . 17 CGMS Enable (MR26) . . . . . . . . . . . . . . . . . . . . . . . . . . 17 CGMS CRC (MR27) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MODE REGISTER 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 MR3 (MR37-MR30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 MR3 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 18 HDTV Enable (MR30) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Reserved (MR31-MR32) . . . . . . . . . . . . . . . . . . . . . . . . . 18 DAC A Control (MR33) . . . . . . . . . . . . . . . . . . . . . . . . . 18 DAC B Control (MR34) . . . . . . . . . . . . . . . . . . . . . . . . . 18 DAC C Control (MR35) . . . . . . . . . . . . . . . . . . . . . . . . . 18 Interpolation (MR36) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Reserved (MR37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 MODE REGISTER 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 MR4 (MR47-MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 MR4 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 18 Timing Reset (MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 MODE REGISTER 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 MR5 (MR57-MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 MR5 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 18 Reserved (MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 RGB Mode (MR51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Sync on PrPb (MR52) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Color Output Swap (MR53) . . . . . . . . . . . . . . . . . . . . . . 19 Gamma Curve (MR54) . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Gamma Correction (MR55) . . . . . . . . . . . . . . . . . . . . . . 19 Adaptive Mode Control (MR56) . . . . . . . . . . . . . . . . . . . 19 Adaptive Filter Control (MR57) . . . . . . . . . . . . . . . . . . . 19 COLOR Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CY (CY7-CY0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 COLOR CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CCR (CCR7-CCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 COLOR CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CCB (CCB7-CCB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 MODE REGISTER 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 MR6 (MR67-MR60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 MR6 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 20 MR67-MR60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CGMS DATA REGISTERS 2-0 . . . . . . . . . . . . . . . . . . . . 20 CGMS2 (CGMS27-CGMS20) . . . . . . . . . . . . . . . . . . . . 20 CGMS1 (CGMS17-CGMS10) . . . . . . . . . . . . . . . . . . . . 20 CGMS0 (CGMS07-CGMS00) . . . . . . . . . . . . . . . . . . . . 20 FILTER GAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 FG (FG7-FG0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 FG BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Filter Gain A (FG3-FG0) . . . . . . . . . . . . . . . . . . . . . . . . 21 Filter Gain B (FG4-FG7) . . . . . . . . . . . . . . . . . . . . . . . . 21 GAMMA CORRECTION REGISTERS 0-13 (GAMMA CORRECTION 0-13) . . . . . . . . . . . . . . . . . . 21 SHARPNESS FILTER CONTROL AND ADAPTIVE FILTER CONTROL . . . . . . . . . . . . . . . . . 22 SHARPNESS FILTER MODE . . . . . . . . . . . . . . . . . . . . . 22 ADAPTIVE FILTER MODE . . . . . . . . . . . . . . . . . . . . . . . 22 ADAPTIVE FILTER GAIN 1 . . . . . . . . . . . . . . . . . . . . . . 23 AFG1 (AFG1)7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ADAPTIVE FILTER GAIN 2 . . . . . . . . . . . . . . . . . . . . . . 23 AFG2 (AFG2)7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ADAPTIVE FILTER GAIN 3 . . . . . . . . . . . . . . . . . . . . . . 23 AFG3 (AFG3)7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
-2-
REV. A
ADV7195
ADAPTIVE FILTER THRESHOLD A . . . . . . . . . . . . . . . 23 AFTA AFTA7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ADAPTIVE FILTER THRESHOLD B . . . . . . . . . . . . . . . 23 AFTB AFTB7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ADAPTIVE FILTER THRESHOLD C . . . . . . . . . . . . . . . 23 AFTC AFTC7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATIONS EXAMPLES . . . . . . . . . . . . . . . . . . . . 24 Sharpness Filter Application . . . . . . . . . . . . . . . . . . . . . . 24 Adaptive Filter Control Application . . . . . . . . . . . . . . . . . 25 HDTV MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 MODE REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 MR0 (MR07-MR00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 MR0 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 26 Output Standard Selection (MR00-MR01) . . . . . . . . . . . 26 Input Control Signals (MR02-MR03) . . . . . . . . . . . . . . . 26 Reserved (MR04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Input Standard (MR05) . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DV Polarity (MR06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Reserved (MR07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 MODE REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 MR1 (MR17-MR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 MR1 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 27 Pixel Data Enable (MR10) . . . . . . . . . . . . . . . . . . . . . . . . 27 Input Format (MR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Test Pattern Enable (MR12) . . . . . . . . . . . . . . . . . . . . . . 27 Test Pattern Hatch/Frame (MR13) . . . . . . . . . . . . . . . . . 27 VBI Open (MR14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Reserved (MR15-MR17) . . . . . . . . . . . . . . . . . . . . . . . . . 27 MODE REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 MR1 (MR27-MR20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 MR2 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 28 Y Delay (MR20-MR22) . . . . . . . . . . . . . . . . . . . . . . . . . 28 Color Delay (MR23-MR25) . . . . . . . . . . . . . . . . . . . . . . 28 Reserved (MR26-MR27) . . . . . . . . . . . . . . . . . . . . . . . . . 28 MODE REGISTER 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 MR3 (MR37-MR30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 MR3 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 28 HDTV Enable (MR30) . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Reserved (MR31-MR32) . . . . . . . . . . . . . . . . . . . . . . . . . 28 DAC A Control (MR33) . . . . . . . . . . . . . . . . . . . . . . . . . 28 DAC B Control (MR34) . . . . . . . . . . . . . . . . . . . . . . . . . 28 DAC C Control (MR35) . . . . . . . . . . . . . . . . . . . . . . . . . 28 Reserved (MR36-MR37) . . . . . . . . . . . . . . . . . . . . . . . . . 28 MODE REGISTER 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 MR4 (MR47-MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 MR4 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 29 Timing Reset (MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Reserved (MR41-MR47) . . . . . . . . . . . . . . . . . . . . . . . . . 29 MODE REGISTER 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 MR5 (MR57-MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 MR5 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 29 Reserved (MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 RGB Mode (MR51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Sync on PrPb (MR52) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Color Output Swap (MR53) . . . . . . . . . . . . . . . . . . . . . . 29 Reserved (MR54-MR57) . . . . . . . . . . . . . . . . . . . . . . . . . 29 DAC TERMINATION AND LAYOUT CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PC BOARD LAYOUT CONSIDERATIONS . . . . . . . . . . 30 Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . 31 Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . 31 Video Output Buffer and Optional Output Filter . . . . . . . 31 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 36
REV. A
-3-
ADV7195-SPECIFICATIONS
3.3 V SPECIFICATIONS
Parameter STATIC PERFORMANCE Resolution (Each DAC) Integral Nonlinearity1 Differential Nonlinearity1 DIGITAL OUTPUTS Output Low Voltage, VOL Output High Voltage, VOH Three-State Leakage Current Three-State Output Capacitance DIGITAL AND CONTROL INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Current, IIN Input Capacitance, CIN ANALOG OUTPUTS Full-Scale Output Current Output Current Range DAC-to-DAC Matching Output Compliance Range, VOC Output Impedance, ROUT Output Capacitance, COUT VOLTAGE REFERENCE (External) Reference Range, VREF POWER REQUIREMENTS IDD2
(VAA = 3.15 V to 3.45 V, VREF = 1.235 V, RSET = 2470 to 70 C] unless otherwise noted, TJMAX = 110 C.)
Min Typ 11 1.5 0.9 Max
, RLOAD = 300
Unit Bits LSB LSB V V A pF V V A pF mA mA mA mA % V k pF V mA mA mA mA
. All specifications TMIN to TMAX [0 C
Test Conditions
2.0 0.4
2.4 10 4 2 0.8 0 4 3.92 2.54 3.92 2.39 0 4.25 2.83 4.25 2.66 1.4 1.4 100 7 1.235 25 51 40 11 0.65
ISINK = 3.2 mA ISOURCE = 400 A VIN = 0.4 V
VIN = 0.0 V or VDD
4.56 3.11 4.56 2.93
DAC A DAC B, DAC C DAC A DAC B, DAC C
1.112
1.359 35 60
IAA3, 4 IPLL Power Supply Rejection Ratio
15
6.0
12
mA
1x Interpolation 2x Interpolation HDTV Mode (With fCLK = 7425 MHz) 1x Interpolation, 2x Interpolation, and HDTV Mode 1x Interpolation, 2x Interpolation, and HDTV Mode
0.01
%/%
NOTES 1 Guaranteed by characterization. 2 IDD or the circuit current is the continuous current required to drive the digital core without I PLL. 3 IAA is the total current required to supply all DACs, including the V REF circuitry. 4 All DACs On. Specifications subject to change without notice.
3 V DYNAMIC-SPECIFICATIONS
Parameter Luma Bandwidth Chroma Bandwidth Signal-to-Noise Ratio Chroma/Luma Delay Inequality
Specifications subject to change without notice.
(VAA = 3.15 V to 3.45 V, VREF = 1.235 V, RSET = 2470 TMIN to TMAX [0 C to 70 C] unless otherwise noted.)
Typ 13.5 6.75 64 0 Max
, RLOAD = 300
Unit
. All specifications
Min
MHz MHz dB Luma Ramp Unweighted ns
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REV. A
ADV7195 3.3 V TIMING-SPECIFICATIONS
Parameter
MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth, t1 SCLOCK Low Pulsewidth, t 2 Hold Time (Start Condition), t 3 Setup Time (Start Condition), t 4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t 6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t 8 RESET Low Time ANALOG OUTPUTS Analog Output Delay, t62 Analog Output Skew CLOCK CONTROL AND PIXEL PORT 3 fCLK
1
(VAA = 3.15 V to 3.45 V, VREF = 1.235 V, RSET = 2470 TMIN to TMAX [0 C to 70 C] unless otherwise noted.)
Typ Max 400 Unit kHz s s s s ns ns ns s ns ns ns MHz MHz MHz ns ns ns ns ns ns Clock Cycles Clock Cycles Conditions
, RLOAD = 300
. All specifications
Min 0 0.6 1.3 0.6 0.6 100
After this Period the 1st Clock Is Generated Relevant for Repeated Start Condition
300 300 0.6 100 10 0.5 27 74.25 81 21.5 22.0 3.4 3.2 3.4 3.2
Progressive Scan Mode HDTV Mode ASYNC Timing Mode and 1x Interpolation
Clock High Time, t9 Clock Low Time, t10 Data Setup Time, t11 Data Hold Time, t 12 Control Setup Time, t 11 Control Hold Time, t 12 Pipeline Delay Pipeline Delay
5.0 5.0 2.0 4.5 7.0 4.0 16 29
For 4:4:4 Pixel Input Format at 1x Oversampling For 4:4:4 or 4:2:2 Pixel Input Format at 2x Oversampling
NOTES 1 Guaranteed by characterization. 2 Output delay measured from 50% point of rising edge of CLOCK to the 50% point of DAC output full-scale transition. 3 Data: Cb/Cr(9-0), Cr(9-0), Y(9-0); Control: HSYNC/SYNC, VSYNC/TSYNC, DV. Specifications subject to change without notice.
REV. A
-5-
ADV7195
CLOCK
t9
R0
t10
R1 R2 Rxxx Rxxx
PIXEL INPUT DATA
G0
G1
G2
G3
Gxxx
Gxxx
B0
B1
B2
B3
Bxxx
Bxxx
t12 t11
t9 - CLOCK HIGH TIME t10 - CLOCK LOW TIME t11 - DATA SETUP TIME t12 - DATA HOLD TIME
Figure 1. 4:4:4 RGB Input Data Format Timing Diagram
CLOCK
t9
Y0
t10
Y1 Y2 Yxxx Yxxx
PIXEL INPUT DATA
Cb0
Cr0
Cb1
Cr1
Cbxxx
Crxxx
t12 t11
t9 - CLOCK HIGH TIME t10 - CLOCK LOW TIME t11 - DATA SETUP TIME t12 - DATA HOLD TIME
Figure 2. 4:2:2 Input Data Format Timing Diagram
CLOCK
t9
Y0
t10
Y1 Y2 Yxxx Yxxx
PIXEL INPUT DATA
Cb0
Cb1
Cb2
Cb3
Cbxxx
Cbxxx
Cr0
Cr1
Cr2
Cr3
Crxxx
Crxxx
t12 t11
t9 - CLOCK HIGH TIME t10 - CLOCK LOW TIME t11 - DATA SETUP TIME t12 - DATA HOLD TIME
Figure 3. 4:4:4 YCrCb Input Data Format Timing Diagram
-6-
REV. A
ADV7195
HSYNC
VSYNC A DV
PIXEL DATA
Y
Y
Y
Y
Cr
Cr
Cr
Cr
Cb B
Cb
Cb
Cb
AMIN = 16 CLK CYCLES (525P) AMIN = 12 CLK CYCLES (625P) AMIN = 44 CLK CYCLES (1080I) AMIN = 70 CLK CYCLES (720P)
BMIN = 122 CLK CYCLES (525P) BMIN = 132 CLK CYCLES (625P) BMIN = 236 CLK CYCLES (1080I) BMIN = 300 CLK CYCLES (720P)
Figure 4. Input Timing Diagram
t5 t3
SDA
t3
t6 t1
SCL
t2
t7
t4
t8
Figure 5. MPU Port Timing Diagram
REV. A
-7-
ADV7195
ABSOLUTE MAXIMUM RATINGS 1
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage on Any Digital Pin . . . . GND - 0.5 V to VAA + 0.5 V Ambient Operating Temperature (TA) . . . . . -40C to +85C Storage Temperature (TS) . . . . . . . . . . . . . -65C to +150C Infrared Reflow Soldering (20 sec) . . . . . . . . . . . . . . . 225C Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . . 220C IOUT to GND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VAA
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Analog Output Short Circuit to any Power Supply or Common can be of an indefinite duration.
ORDERING GUIDE
Model ADV7195KS
Temperature Range 0C to 70C
Package Description Plastic Quad Flatpack
Package Option S-52
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7195 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
GND Cb/Cr[0]
Cb/Cr[1]
Cb/Cr[2]
Cb/Cr[3] Cb/Cr[4]
Cb/Cr[5] Cb/Cr[6]
Cb/Cr[7]
Cb/Cr[8]
Cb/Cr[9] ALSB
52 51 50 49 48 47 46 45 44 43 42 41 40
RESET
39 VREF 38 RSET 37 COMP 36 DAC B 35 VAA 34 DAC A/Y OUTPUT 33 AGND 32 DAC C 31 SDA 30 SCL 29 HSYNC/SYNC 28 VSYNC/TSYNC 27 DV
VDD 1 Y[0] 2 Y[1] 3 Y[2] 4 Y[3] 5 Y[4] 6 Y[5] 7 Y[6] 8 Y[7] 9 Y[8] 10 Y[9] 11 VDD 12 GND 13
PIN 1 IDENTIFIER
ADV7195
TOP VIEW (Not to Scale)
14 15 16 17 18 19 20 21 22 23 24 25 26
Cr[0] Cr[1]
Cr[2]
Cr[3]
Cr[4]
Cr[5]
Cr[6] Cr[7]
Cr[8] Cr[9]
-8-
VAA CLKIN
AGND
REV. A
ADV7195
PIN FUNCTION DESCRIPTIONS
Pin 1, 12 2-11 13, 52 14-23
Mnemonic VDD Y0-Y9 GND Cr0-Cr9
Input/Output P I G I
Function Digital Power Supply 10-Bit Progressive Scan/HDTV Input Port for Y Data. Input for G data when RGB data is input. Digital Ground 10-Bit Progressive Scan/HDTV Input Port for Color Data in 4:4:4 Input Mode. In 4:2:2 mode this input port is not used. Input port for R data when RGB data is input. Analog Power Supply Pixel Clock Input. Requires a 27 MHz reference clock for standard operation in Progressive Scan Mode or a 74.25 MHz (74.1758 MHz) reference clock in HDTV mode. Analog Ground Video Blanking Control Signal Input VSYNC, Vertical Sync Control Signal Input or TSYNC Input Control Signal in Async Timing Mode HSYNC, Horizontal Sync Control Signal Input or SYNC Input Control Signal in
Async Timing Mode
24, 35 25
VAA CLKIN
P I
26, 33 27 28 29 30 31 32 34 36 37 38
AGND DV VSYNC/ TSYNC HSYNC/ SYNC SCL SDA DAC C DAC A DAC B COMP RSET
G I I I I I/O O O O O I
39 40 41
VREF RESET ALSB
I/O I I
42-51
Cb/Cr9-0
I
MPU Port Serial Interface Clock Input MPU Port Serial Data Input/Output Color Component Analog Output of Input Data on Cb/Cr9-0 Input Pins Y Analog Output Color Component Analog Output of Input Data on Cr9-Cr0 Input Pins Compensation Pin for DACs. Connect 0.1 F Capacitor from COMP pin to VAA. A 2470 resistor for input ranges 64-940 and 64-960 (output standards EIA770.1-EIA-770.3) must be connected from this pin to ground and is used to control the amplitudes of the DAC outputs. For input ranges 0-1023 (output standards RS-170, RS-343A) the RSET value must be 2820 . Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V) This input resets the on-chip timing generator and sets the ADV7195 into Default Register setting. Reset is an active low signal. TTL Address Input. This signal sets up the LSB of the MPU address. When this pin is tied high, the I2C filter is activated, which reduces noise on the I2C Interface. When this pin is tied low, the input bandwidth on the I2C interface is increased. 10-Bit Progressive scan/HDTV input port for color data. In 4:2:2 mode the multiplexed CrCb data must be input on these pins. Input port for B data when RGB is input.
REV. A
-9-
ADV7195
FUNCTIONAL DESCRIPTION Digital Inputs Control Signals
The digital inputs of the ADV7195 are TTL-compatible. 30-bit YCrCb or RGB pixel data in 4:4:4 format or 20-bit YCrCb pixel data in 4:2:2 format is latched into the device on the rising edge of each clock cycle at 27 MHz in Progressive Scan Mode or 74.25 MHz or 74.1785 MHz in HDTV mode. It is also possible to input 3 x bit RGB data in 4:4:4 format to the ADV7195. It is recommended to input data in 4:2:2 mode to make use of the chroma SSAFs on the ADV7195. As can be seen in Figures 6 and 7, this filter has 0 dB passband response and prevents signal components being loaded back into the frequency band. In 4:4:4 input mode, the video data is already interpolated by the external input device and the chroma SSAFs of the ADV7195 are bypassed.
ATTEN 10dB RL -10.0dBm VAVG 1 10dB/ MKR 0dB 3.18MHz
The ADV7195 accepts sync control signals accompanied by valid 4:2:2 or 4:4:4 data. These external horizontal, vertical, and blanking pulses (or EAV/SAV codes) control the insertion of appropriate sync information into the output signals.
Analog Outputs
The analog Y signal is output on the 11-bit + Sync DAC A, the color component analog signals on the 11-bit DAC B and DAC C conforming to EIA-770.1 or EIA-770.2 standards in PS mode or EIA-770.3 in HDTV mode. RSET has a value of 2470 (EIA-770.1, EIA-770.2, EIA-770.3), RLOAD has a value of 300 . For RGB outputs conforming to RS-170/RS-343A output standards RSET must have a value of 2820 .
Undershoot Limiter
A limiter can be applied to the Y data before it is applied to the DACs. Available limit values are -1.5 IRE, -6 IRE, -11 IRE below blanking. This functionality is available in Progressive Scan Mode only.
I2C Filter
A selectable internal I2C filter allows significant noise reductions on the I2C interface. In setting ALSB high, the input bandwidth on the I2C lines is reduced and pulses of less than 50 ns are not passed to the I2C controller. Setting ALSB low allows greater input bandwidth on the I2C lines.
Internal Test Pattern Generator
START 100kHz RBW 10kHz
STOP VBW 300Hz
20.00MHz SWP 17.0SEC
The ADV7195 can generate a crosshatch pattern (white lines against a black background). Additionally, the ADV7195 can output a uniform color pattern. The color of the lines or uniform field/frame can be programmed by the user.
Y/CrCb Delay
Figure 6. ADV7195 SSAF Response to a 2.5 MHz Chroma Sweep Using 4:2:2 Input Mode
The Y output and the color component outputs can be delayed wrt the falling edge of the horizontal sync signal by up to four clock cycles.
Gamma Correction
ATTEN 10dB RL -10.0dBm
VAVG 4 10dB/
MKR -3.00dB 3.12MHz
Gamma correction may be performed on the luma data. The user has the choice to use either of two different gamma curves, A or B. At any one time one of these curves is operational if gamma correction is enabled. Gamma correction allows the mapping of the luma data to a user-defined function.
54 MHz Operation
In Progressive Scan mode, it is possible to operate the three output DACs at 54 MHz or 27 MHz. The ADV7195 is supplied with a 27 MHz clock synced with the incoming data. If required, a second stage interpolation filter interpolates the data to 54 MHz before it is applied to the three output DACs. The second stage interpolation filter is controlled by MR36. After applying a Reset, it is recommended to toggle this bit. Before toggling this bit, 3Ehex must be written to Address 09hex.
PROGRAMMABLE SHARPNESS FILTER
START 100kHz RBW 10kHz
STOP VBW 300Hz
20.00MHz SWP 17.0SEC
Figure 7. Conventional Filter Response to a 2.5 MHz Chroma Sweep Using 4:4:4 Input Mode
Sharpness Filter Mode is applicable to the Y data only in Progressive Scan Mode. The desired frequency response can be chosen by the user in programming the correct value via the I2C. The variation of frequency responses can be seen in the figures on the following pages.
-10-
REV. A
ADV7195
PROGRAMMABLE ADAPTIVE FILTER CONTROL
10 0 -10 -20 -30
If the Adaptive Filter Mode is enabled (Progressive Scan Mode only), it is possible to compensate for large edge transitions on the incoming Y data. Sensitivity and attenuation are all programmable over the I2C. For further information refer to Sharpness Filter Control and Adaptive Filter Control section.
INPUT/OUTPUT CONFIGURATION
-40 -50 -60
Table I shows possible input/output configurations when using the ADV7195.
Table I.
Input Format YCrCb Progressive Scan 4:2:2 4:4:4 YCrCb HDTV 4:2:2 4:4:4 RGB Progressive Scan 4:4:4 RGB HDTV 4:4:4 Async Timing Mode All Inputs
10 0 -10 -20 -30 -40 -50 -60 -70 -80 0
Output 2x 1x or 2x 1x 1x 2x 1x 1x
-70 -80 0
5
10
15
20
25
30
Figure 10. Interpolation Filter-CrCb Channels/Cr 4:4:4 Input Data
MPU PORT DESCRIPTION
The ADV7195 support a 2-wire serial (I2C-compatible) microprocessor bus driving multiple peripherals. Two inputs, Serial Data (SDA) and Serial Clock (SCL) carry information between any device connected to the bus. Each slave device is recognized by a unique address. The ADV7195 has four possible slave addresses for both read and write operations. These are unique addresses for each device and are illustrated in Figure 11. The LSB sets either a read or write operation. Logic Level "1" corresponds to a read operation while Logic Level "0" corresponds to a write operation. A1 is set by setting the ALSB pin of the ADV7195 to Logic Level "0" or Logic Level "1." When ALSB is set to "0," there is greater input bandwidth on the I2C lines, which allows high-speed data transfers on this bus. When ALSB is set to "1," there is reduced input bandwidth on the I2C lines, which means that pulses of less than 50 ns will not pass into the I2C internal controller. This mode is recommended for noisy systems.
1 1 0 1 0 1 A1 ADDRESS CONTROL SETUP BY ALSB READ/WRITE CONTROL 0 WRITE 1 READ X
5
10
15
20
25
30
Figure 8. 2x Interpolation Filter 4-Channel
10
Figure 11. Slave Address
0 -10 -20 -30 -40 -50 -60 -70 -80 0
5
10
15
20
25
30
Figure 9. Interpolation Filter-CrCb Channels/Cr 4:2:2 Input Data
To control the various devices on the bus the following protocol must be followed. First the master initiates a data transfer by establishing a Start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that an address/data stream will follow. All peripherals respond to the Start condition and shift the next eight bits (7-bit address + R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCL lines waiting for the Start condition and the correct transmitted address. The R/W bit determines the direction of the data.
REV. A
-11-
ADV7195
A Logic "0" on the LSB of the first byte means that the master will write information to the peripheral. A Logic "1" on the LSB of the first byte means that the master will read information from the peripheral. The ADV7195 acts as a standard slave device on the bus. The data on the SDA pin is 8 bits long supporting the 7-bit addresses plus the R/W bit. It interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses autoincrement, allowing data to be written to or read from the starting subaddress. A data transfer is always terminated by a Stop condition. The user can also access any unique subaddress register on a one-by-one basis without having to update all the registers. Stop and Start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCL high period the user should issue only one Start condition, one Stop condition or a single Stop condition followed by a single Start condition. If an invalid subaddress is issued by the user, the ADV7195 will not issue an acknowledge and will return to the idle condition. If in autoincrement mode, the user exceeds the highest subaddress, the following action will be taken: 1. In Read Mode, the highest subaddress register contents will continue to be output until the master device issues a no-acknowledge. This indicates the end of a read. A noacknowledge condition is where the SDA line is not pulled low on the ninth pulse. 2. In Write Mode, the data for the invalid byte will not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7195 and the part will return to the idle condition.
SDATA SCLOCK
S
17
8
9
17
8
9
17 DATA
8
9 ACK
P STOP
START ADDR R/W ACK SUBADDRESS ACK
Figure 12. Bus Data Transfer
Figure 12 illustrates an example of data transfer for a read sequence and the Start and Stop conditions. Figure 13 shows bus write and read sequences.
WRITE SEQUENCE
S
SLAVE ADDR A(S) LSB = 0
SUB ADDR
A(S)
DATA
A(S) LSB = 1
DATA
A(S) P
READ SEQUENCE
S
SLAVE ADDR A(S) S = START BIT P = STOP BIT
SUB ADDR
A(S) S SLAVE ADDR
A(S)
DATA
A(M)
DATA
A(M) P
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO ACKNOWLEDGE BY SLAVE A(M) = NO ACKNOWLEDGE BY MASTER
Figure 13. Write and Read Sequence
-12-
REV. A
ADV7195
REGISTER ACCESSES Subaddress Register (SR7-SR0)
The MPU can write to or read from all of the registers of the ADV7195 except the Subaddress Registers, which are write-only registers. The Subaddress Register determines which register the next read or write operation accesses. All communications with the part through the bus begin with an access to the Subaddress Register. A read/write operation is performed from/to the target address which then increments to the next address until a Stop command on the bus is performed.
REGISTER PROGRAMMING
The Communications Register is an 8-bit write-only register. After the part has been accessed over the bus and a read/ write operation is selected, the subaddress is set up. The Subaddress Register determines to/from which register the operation takes place. Figure 14 shows the various operations under the control of the Subaddress Register. "0" should always be written to SR7.
Register Select (SR6-SR0)
These bits are set up to point to the required starting address.
The following section describes the functionality of each register. All registers can be read from as well as written to unless otherwise stated.
SR7 SR7 ZERO SHOULD BE WRITTEN HERE SR6 SR5 SR4 SR3 SR2 SR1 SR0
ADV7195 SUBADDRESS REGISTER ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h SR6 SR5 SR4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 SR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 SR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MODE REGISTER 0 MODE REGISTER 1 MODE REGISTER 2 MODE REGISTER 3 MODE REGISTER 4 MODE REGISTER 5 COLOR Y COLOR CR COLOR CB MODE REGISTER 6 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED FILTER GAIN CGMS DATA REGISTER 0 CGMS DATA REGISTER 1 CGMS DATA REGISTER 2 GAMMA CORRECTION REGISTER 0 GAMMA CORRECTION REGISTER 1 GAMMA CORRECTION REGISTER 2 GAMMA CORRECTION REGISTER 3 GAMMA CORRECTION REGISTER 4 GAMMA CORRECTION REGISTER 5 GAMMA CORRECTION REGISTER 6 GAMMA CORRECTION REGISTER 7 GAMMA CORRECTION REGISTER 8 GAMMA CORRECTION REGISTER 9 GAMMA CORRECTION REGISTER 10 GAMMA CORRECTION REGISTER 11 GAMMA CORRECTION REGISTER 12 GAMMA CORRECTION REGISTER 13 ADAPTIVE FILTER GAIN 1 ADAPTIVE FILTER GAIN 2 ADAPTIVE FILTER GAIN 3 ADAPTIVE FILTER THRESHOLD A ADAPTIVE FILTER THRESHOLD B ADAPTIVE FILTER THRESHOLD C
Figure 14. Subaddress Registers in Progressive Scan Mode
SR7 SR7 ZERO SHOULD BE WRITTEN HERE
SR6
SR5
SR4
SR3
SR2
SR1
SR0
ADV7195 SUBADDRESS REGISTER ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h SR6 SR5 SR4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SR3 0 0 0 0 0 0 0 0 1 SR2 0 0 0 0 1 1 1 1 0 SR1 0 0 1 1 0 0 1 1 0 SR0 0 1 0 1 0 1 0 1 0 MODE REGISTER 0 MODE REGISTER 1 MODE REGISTER 2 MODE REGISTER 3 MODE REGISTER 4 MODE REGISTER 5 COLOR Y COLOR CR COLOR CB
Figure 15. Subaddress Registers in HDTV Mode
REV. A
-13-
ADV7195
PROGRESSIVE SCAN MODE
MODE REGISTER 0 MR0 (MR07-MR00) (Address (SR4-SR0) = 00H) Input Control Signals (MR02-MR03)
These control bits are used to select whether data is input with external horizontal, vertical and blanking sync signals or if the data is input with embedded EAV/SAV codes. An Asynchronous timing mode is also available using TSYNC, SYNC and DV as input control signals. These control signals have to be programmed by the user. Figure 17 shows an example of how to program the ADV7195 to accept a different high definition standard but SMPTE293M, SMPTE274M, SMPTE296M or ITU-R.BT1358 standard.
Input Standard (MR04)
Figure 16 shows the various operations under the control of Mode Register 0.
MR0 BIT DESCRIPTION Output Standard Selection (MR00-MR01)
These bits are used to select the output levels for the ADV7195. If EIA-770.2 (MR01-00 = "00") is selected, the output levels will be: 0 mV for blanking level, 700 mV for peak white for the Y channel, 350 mV for Pr, Pb outputs and -300 mV for Sync. Sync insertion on the Pr, Pb channels is optional. If EIA-770.1 (MR01-00 = "01") is selected, the output levels will be: 0 mV for blanking level, 714 mV for peak white for the Y channel, 350 mV for Pr, Pb outputs and -286 mV for Sync. Optional sync insertion on the Pr, Pb channels is not possible. If Full I/P Range (MR01-00 = "10") is selected, the output levels will be: 0 mV for blanking level, 700 mV for peak white for the Y channel, 350 mV for Pr, Pb outputs and -300 mV for Sync. Sync insertion on the Pr, Pb channels is optional. This mode is used for RS-170, RS-343A standard output compatibility. Refer to Figures 61 to 64 for output level plots.
Select between 525p progressive scan input or 625p progressive scan input.
Reserved (MR05)
A "0" must be written to this bit.
DV Polarity (MR06)
This control bit allows the user to select the polarity of the DV input control signal to be either active high or active low. This is in order to facilitate interfacing from I to P Converters which use an active low blanking signal output.
Reserved (MR07)
A "0" must be written to this bit.
MR07
MR06
MR05
MR04
MR03
MR02
MR01
MR00
MR07 ZERO MUST BE WRITTEN TO THIS BIT
MR05 ZERO MUST BE WRITTEN TO THIS BIT
INPUT STANDARD MR04 0 525P 1 625P 0 0 1 1
INPUT CONTROL SIGNALS MR03 MR02 0 1 0 1 HSYNC/VSYNC/DV EAV/SAV TSYNC/SYNC/DV RESERVED OUTPUT STANDARD SELECTION MR01 MR00 0 0 1 1 0 1 0 1 EIA-770.2 EIA-770.1 FULL I/P RANGE RESERVED
DV POLARITY MR06 0 ACTIVE HIGH 1 ACTIVE LOW
Figure 16. Mode Register 0
-14-
REV. A
ADV7195
Table II must be followed when programming the control signals in Async Timing Mode.
Table II. Truth Table
SYNC 1 -> 0
TSYNC 0
DV 0 or 1 50% Point of Falling Edge of Tri-Level Horizontal Sync Signal, A 25% Point of Rising Edge of Tri-Level Horizontal Sync Signal, B 50% Point of Falling Edge of Tri-Level Horizontal Sync Signal, C 50% Start of Active Video, D 50% End of Active Video, E
0
0 -> 1
0 or 1
0 -> 1
0 or 1
0
1 1
0 or 1 0 or 1
0 -> 1 1 -> 0
CLK SYNC TSYNC DV SET MR06 = 1 PROGRAMMABLE INPUT TIMING
HORIZONTAL SYNC
ACTIVE VIDEO
ANALOG OUTPUT
81 A
66 B
66 C
243 D
1920 E
Figure 17. Async Timing Mode--Programming Input Control Signals for SMPTE295M Compatibility
525 VIDEO OUTPUT
1
12
13
42
43
HSYNC
VSYNC DV
Figure 18. DV Input Control Signal in Relation to Video Output Signal
REV. A
-15-
ADV7195
MODE REGISTER 1 MR1 (MR17-MR10) (Address (SR4-SR0) = 01H) VBI Open (MR14)
This bit enables or disables the facility of VBI data insertion during the Vertical Blanking Interval. For this purpose Lines 13 to 42 of each frame can be used for VBI when SMPTE293M standard is used, or Lines 6 to 43 when ITU-R.BT1358 standard is used.
Undershoot Limiter (MR15-MR16)
Figure 20 shows the various operations under the control of Mode Register 1.
MR1 BIT DESCRIPTION Pixel Data Enable (MR10)
When this bit is set to "0," the pixel data input to the ADV7195 is blanked such that a black screen is output from the DACs. When this bit is set to "1," pixel data is accepted at the input pins and the ADV7195 outputs the standard set in "Output Standard Selection" (MR01-00). This bit also must be set to "1" to enable output of the test pattern signals.
Input Format (MR11)
This control limits the Y signal to a programmable level in the active video region. Available limit levels are -1.5 IRE, -6 IRE, -11 IRE. Note that this facility is only available when Interpolation is enabled (MR36 = "1").
Sharpness Filter (MR17)
It is possible to input data in 4:2:2 format or at 4:4:4 format at 27 MHz.
Test Pattern Enable (MR12)
Enables or disables the internal test pattern generator.
Test Pattern Hatch/Frame (MR13)
This control bit enables or disables the Sharpness Filter Mode. This bit must be set to "1" for any values programmed into the Filter Gain Register to take effect. It must also be set to "1" when Adaptive Filter mode is used. Refer to Sharpness Filter Control and Adaptive Filter Control section.
100 IRE
If this bit is set to "0," a crosshatch test pattern is output from the ADV7195 (for example, in SMPTE293M, 11 horizontal and 11 vertical white lines, four pixels wide are displayed against a black background). The crosshatch test pattern can be used to test monitor convergence. If this bit is set to "1," a uniform colored frame/field test pattern is output from the ADV7195. The color of the lines or the frame/field is by default white but can be programmed to be any color using the Color Y, Color Cr, Color Cb registers.
0 IRE -6 IRE -40 IRE
Figure 19. Undershoot Limiter, Programmed to -6 IRE
MR17
MR16
MR15
MR14
MR13
MR12
MR11
MR10
SHARPNESS FILTER MR17 0 DISABLE 1 ENABLE
VBI OPEN MR14 0 DISABLE 1 ENABLE UNDERSHOOT LIMITER MR16 MR15 0 0 0 1 1 0 1 1 DISABLE -11 IRE -6 IRE -1.5 IRE
TEST PATTERN ENABLE MR12 0 DISABLE 1 ENABLE
PIXEL DATA ENABLE MR10 0 DISABLE 1 ENABLE
TEST PATTERN HATCH/FRAME MR13 0 HATCH 1 FIELD/FRAME 0 1
INPUT FORMAT MR11 4:4:4 Y Cr Cb 4:2:2 Y Cr Cb
Figure 20. Mode Register 1
-16-
REV. A
ADV7195
MODE REGISTER 2 MR1 (MR27-MR20) (Address (SR4-SR0) = 02H)
The CGMS data bits are programmed into the CGMS Data Registers 0-2. For more information refer to CGMS Data Registers section.
CGMS CRC (MR27)
Figure 22 shows the various operations under the control of Mode Register 2.
MR2 BIT DESCRIPTION Y Delay (MR20-MR22)
This bit enables the automatic Cyclic Redundancy Check when CGMS is enabled.
This control bit delays the Y signal with respect to the falling edge of the horizontal sync signal by up to four pixel clock cycles. Figure 21 demonstrates this facility.
Color Delay (MR23-MR25)
NO DELAY Y DELAY Y OUTPUT
MAX DELAY NO DELAY
This control allows delay of the color signals with respect to the falling edge of the horizontal sync signal by up to four pixel clock cycles. Figure 21 demonstrates this facility.
CGMS Enable (MR26)
When this bit is set to "1," CGMS data is inserted on Line 41 in 525p mode. The CGMS conforms to CGMS-A EIA-J CPR1204-1, Transfer Method of Video ID information using vertical blanking interval (525p System), March 1998 and IEC61880, 1998, video systems (525/60)--video and accompanied data using the vertical blanking interval--analog interface.
PrPb DELAY
PrPb OUTPUT
MAX DELAY
Figure 21. Y and Color Delay
MR27
MR26
MR25
MR24
MR23
MR22
MR21
MR20
CGMS ENABLE MR26 0 DISABLE 1 ENABLE CGMS CRC MR27 0 DISABLE 1 ENABLE
COLOR DELAY MR25 MR24 MR23 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 PCLK 1 PCLK 2 PCLK 3 PCLK 4 PCLK
Y DELAY MR22 MR21 MR20 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 PCLK 1 PCLK 2 PCLK 3 PCLK 4 PCLK
Figure 22. Mode Register 2
REV. A
-17-
ADV7195
MODE REGISTER 3 MR3 (MR37-MR30) (Address (SR4-SR0) = 03H) MODE REGISTER 4 MR4 (MR47-MR40) (Address (SR4-SR0) = 04H)
Figure 23 shows the various operations under the control of Mode Register 3.
MR3 BIT DESCRIPTION HDTV Enable (MR30)
Figure 24 shows the various operations under the control of Mode Register 4.
MR4 BIT DESCRIPTION Timing Reset (MR40)
When this bit is set to "1," the ADV7195 reverts to HDTV mode (refer to HDTV mode section). When set to "0" the ADV7195 is set up in Progressive Scan Mode (PS Mode).
Reserved (MR31-MR32)
Toggling MR40 from low to high and low again resets the internal horizontal and vertical timing counters.
MODE REGISTER 5 MR5 (MR57-MR50) (Address (SR4-SR0) = 05H)
A "0" must be written to these bits.
DAC A Control (MR33)
Setting this bit to "1" enables DAC A, otherwise this DAC is powered down.
DAC B Control (MR34)
Figure 25 shows the various operations under the control of Mode Register 5.
MR5 BIT DESCRIPTION Reserved (MR50)
Setting this bit to "1" enables DAC B, otherwise this DAC is powered down.
DAC C Control (MR35)
This bit is reserved for the revision code.
RGB Mode (MR51)
Setting this bit to "1" enables DAC C, otherwise this DAC is powered down.
Interpolation (MR36)
When RGB mode is enabled (MR51 = "1") the ADV7195 accepts unsigned binary RGB data at its input port. This control is also available in Async Timing Mode.
Sync on PrPb (MR52)
This bit enables the second stage interpolation filters. When this bit is enabled (MR36 = "1"), data is sent at 54 MHz to the DAC output stage. After Reset it is recommended to toggle this bit. Before toggling this bit, 3Ehex must be written to address 09hex to guarantee correct operation.
Reserved (MR37)
By default, the color component output signals Pr, Pb do not contain any horizontal sync pulses. They can be inserted when MR52 = "1." This facility is only available when Output Standard Selection has been set to EIA-770.2 (MR01-00 = "00") or Full Input Range (MR01-00 = "10"). This control is not available in RGB mode.
A "0" must be written to this bit.
MR37
MR36
MR35
MR34
MR33
MR32
MR31
MR30
MR37 ZERO MUST BE WRITTEN TO THIS BIT
DAC B CONTROL MR34 0 POWER-DOWN 1 NORMAL
MR32 ZERO MUST BE WRITTEN TO THIS BIT
HDTV ENABLE MR30 0 DISABLE 1 ENABLE
INTERPOLATION MR36 0 DISABLE 1 ENABLE
DAC C CONTROL MR35 0 POWER-DOWN 1 NORMAL
DAC A CONTROL MR33 0 POWER-DOWN 1 NORMAL
MR31 ZERO MUST BE WRITTEN TO THIS BIT
Figure 23. Mode Register 3
MR47
MR46
MR45
MR44
MR43
MR42
MR41
MR40
MR47 - MR41 ZERO MUST BE WRITTEN TO THESE BITS
TIMING RESET MR40
Figure 24. Mode Register 4
-18-
REV. A
ADV7195
MR57 MR56 MR55 MR54 MR53 MR52 MR51 MR50 ADAPTIVE MODE CONTROL MR56 0 MODE A 1 MODE B ADAPTIVE FILTER CONTROL MR57 0 MODE A 1 MODE B GAMMA CORRECTION MR55 0 DISABLE 1 ENABLE COLOR OUTPUT SWAP MR53 0 1 DAC B = Pr DAC C = Pr RGB MODE MR51 0 DISABLE 1 ENABLE
GAMMA CURVE MR54 0 CURVE A 1 CURVE B
SYNC ON PrPb MR52 0 DISABLE 1 ENABLE
MR50 RESERVED FOR REVISION CODE
Figure 25. Mode Register 5
Color Output Swap (MR53)
Adaptive Filter Control (MR57)
By default, DAC B is configured as the Pr output and DAC C as the Pb output. In setting this bit to "1" the DAC outputs can be swapped around so that DAC B outputs Pb and DAC C outputs Pr. Table III demonstrates this in more detail. This control is also available in RGB mode.
Table III. Relationship Between Color Input Pixel Port, MR53 and DAC B, DAC C Outputs In 4:4:4 Input Mode
This bit enables the Adaptive Filter Control when set to "1." Sharpness Filter must be enabled as well (MR17 = "1"). The Adaptive Filter Controls is explained in more detail under Sharpness Filter Control and Adaptive Filter Control section.
COLOR Y CY (CY7-CY0) (Address (SR4-SR0) = 06H)
CY7 CY6 CY5 CY4 CY3 CY2 CY1 CY0
Color Data Input on Pins Cr9-0 Cb/Cr9-0 Cr9-0 Cb/Cr9-0
In 4:2:2 Input Mode
MR53 0 0 1 1
Analog Output Signal DAC B DAC C DAC C DAC B
CY7 - CY0 COLOR Y VALUE
Figure 26. Color Y Register
COLOR CR CCR (CCR7-CCR0) (Address (SR4-SR0) = 07H)
CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0
Color Data Input on Pins Cr9-0 Cb/Cr9-0 Cb/Cr9-0
Gamma Curve (MR54)
MR53 0 or 1 0 1
Analog Output Signal Not Operational DAC C (Pb) DAC C (Pr)
CCR7 - CCR0 COLOR CR VALUE
Figure 27. Color Cr Register
COLOR CB CCB (CCB7-CCB0) (Address (SR4-SR0) = 08H)
CCB7 CCB6 CCB5 CCB4 CCB3 CCB2 CCB1 CCB0
This bit selects which of the two programmable gamma curves is to be used. When setting MR54 to "0," the gamma correction curve selected is Curve A. Otherwise Curve B is selected. Each curve will have to be programmed by the user as explained in the Gamma Correction Registers section.
Gamma Correction (MR55)
To enable Gamma Correction, and therefore activate the gamma curve programmed by the user, this bit must be set to "1." Otherwise the programmable Gamma Correction facility is bypassed. Programming of the gamma correction curves is explained in the Gamma Correction Registers section.
Adaptive Mode Control (MR56)
CCB7 - CCB0 COLOR CB VALUE
Figure 28. Color Cb Register
For this control to be effective, Adaptive Filter Control must be enabled (MR57 = "1") as well as the Sharpness Filter (MR17 = "1"). For filter plots, refer to Sharpness Filter Control and Adaptive Filter Control section.
These three 8-bit-wide registers are used to program the output color of the internal test pattern generator, be it the lines of the crosshatch pattern or the uniform field test pattern and are available in PS mode and HDTV mode. The standard used for the values for Y and the color difference signals to obtain white, black and the saturated primary and complementary colors conforms to the ITU-R BT 601-4 standard.
REV. A
-19-
ADV7195
Table IV shows sample color values to be programmed into the color registers when Output Standard Selection is set to EIA-770.2 (MR01-00 = "00").
Table IV. Sample Color Values for EIA-770.2 Output Standard Selection CGMS DATA REGISTERS 2-0 CGMS2 (CGMS27-CGMS20) (Address (SR4-SR0) = 13H)
This 8-bit-wide register contains the last four CGMS data bits, (C16-C19) of the CGMS data stream.
CGMS27 CGMS26 CGMS25 CGMS24 CGMS23 CGMS22 CGMS21 CGMS20
Sample Color White Black Red Green Blue Yellow Cyan Magenta
Color Y Value 235 (EB) 16 (10) 81 (51) 145 (91) 41 (29) 210 (D2) 170 (AA) 106 (6A)
Color Cr Value 128 (80) 128 (80) 240 (F0) 34 (22) 110 (6E) 146 (92) 16 (10) 222 (DE)
Color Cb Value
CGMS27 - CGMS24 CGMS23 - CGMS20 CGMS2
128 (80) 128 (80) 90 (5A) 54 (36) 240 (F0) 16 (10) 166 (A6) 202 (CA)
ZERO MUST BE WRITTEN TO THESE BITS
Figure 30. CGMS2 Data Register
CGMS1 (CGMS17-CGMS10) (Address (SR4-SR0) = 12H)
This 8-bit-wide register contains C8-C15 of the CGMS data stream.
CGMS17 CGMS16 CGMS15 CGMS14 CGMS13 CGMS12 CGMS11 CGMS10
MODE REGISTER 6 MR6 (MR67-MR60) (ADDRESS (SR4-SR0) = 09H)
Figure 29 shows the various operations under the control of Mode Register 6.
MR6 BIT DESCRIPTION MR67-MR60
CGMS17 - CGMS10 CGMS1
Figure 31. CGMS1 Data Register
CGMS0 (CGMS07-CGMS00) (Address (SR4-SR0) = 11H)
The value 3EHex must be written to this register before the PLL is reset (reset MR36) to guarantee correct operation of the ADV7195.
MR67 MR66 MR65 MR64 MR63 MR62 MR61 MR60
This 8-bit-wide register contains the first eight CGMS data bits, (C0-C7) of the CGMS data stream.
CGMS07 CGMS06 CGMS05 CGMS04 CGMS03 CGMS02 CGMS01 CGMS00
MR67 ZERO MUST BE WRITTEN TO THIS BIT
MR64
ONE MUST BE WRITTEN TO THIS BIT
MR62 ONE MUST BE WRITTEN TO THIS BIT
MR60
ZERO MUST BE WRITTEN TO THIS BIT
MR66
ZERO MUST BE WRITTEN TO THIS BIT
MR65
ONE MUST BE WRITTEN TO THIS BIT
MR63
ONE MUST BE WRITTEN TO THIS BIT
MR61
ZERO MUST BE WRITTEN TO THIS BIT
CGMS07 - CGMS00 CGMS0
Figure 29. Mode Register 6
Figure 32. CGMS0 Data Register
+700mV REF 70 10% C0 C1 C2 C3 C4 C5 C6 C7 C8 BIT1 BIT3 BIT5 BIT7 BIT9 BIT11 BIT13 BIT15
CRC SEQUENCE BIT17 BIT19
C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV
BIT2
BIT4
BIT6
BIT8
BIT10
BIT12
BIT14
BIT16
BIT18
BIT20
-300mV 5.8 s 0.15 s 6T
21.2 s 0.22 s 22T
T = 1/(fH 33) = 963ns fH = HORIZONTAL SCAN FREQUENCY T 30ns
Figure 33. CGMS Waveform
-20-
REV. A
ADV7195
FILTER GAIN FG (FG7-FG0) (Address (SR4-SR0) = 10H)
Figure 34 shows the various operations under the control of the Filter Gain register.
FG7 FG6 FG5 FG4 FG3 FG2 FG1 FG0
The response of the curve is programmed at seven predefined locations. In changing the values at these locations the gamma curve can be modified. Between these points linear interpolation is used to generate intermediate values. Considering the curve to have a total length of 256 points, the seven locations are at: 32, 64, 96, 128, 160, 192, 224. Locations 0, 16, 240, and 255 are fixed and cannot be changed. For the length of 16 to 240 the gamma correction curve has to be calculated as below: y = x where y = gamma corrected output. x = linear input signal. = gamma power factor. To program the gamma correction registers, the seven values for y have to be calculated using the following formula: yn = [x(n-16)/(240 - 16)] x (240-16) + 16 where x(n-16) = Value for x along x-axis at points: n = 32, 64, 96, 128, 160, 192, or 224. = Value for y along the y-axis, which has to be written yn into the gamma correction register. Example: y32 = [(16/224)0.5 x 2 24] + 16 = 76* y64 = [(48/224)0.5 x 224] + 16 =120* y96 = [(80/224)0.5 x 224] + 16 = 150* y128 = [(112/224)0.5 x 224] + 16 = 174*
*Rounded to the nearest integer.
FG7-FG4 FILTER GAIN B 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 -8 -7 -6 -5 -4 -3 -2 -1
FG3-FG0 FILTER GAIN A 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 -8 -7 -6 -5 -4 -3 -2 -1
Figure 34. Filter Gain Register
FG BIT DESCRIPTION Filter Gain A (FG3-FG0)
These bits are used to program the gain A value, which varies from response -8 to response +7 and are applied to Filter A.
Filter Gain B (FG4-FG7)
These bits are used to program the gain B value, which varies from response -8 to response +7, and are applied to Filter B. Refer to Sharpness Filter Control and Adaptive Filter Control section for more detail.
GAMMA CORRECTION REGISTERS 0-13 (GAMMA CORRECTION 0-13) (Address (SR5-SR0) = 14H-21H)
The above will result in a gamma curve shown on the next page, assuming a ramp signal as an input.
300 GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT
GAMMA-CORRECTED AMPLITUDE
The Gamma Correction Registers are 14 8-bit-wide registers. They are used to program the gamma correction Curves A and B. Generally, gamma correction is applied to compensate for the nonlinear relationship between signal input and brightness level output (as perceived on the CRT). It can also be applied wherever nonlinear processing is used. Gamma correction uses the function: SignalOUT = (Signal IN ) where = gamma power factor. Gamma correction is performed on the luma data only. The user has the choice of two different curves, Curve A or Curve B. At any one time only one of these curves can be used.
250 SIGNAL OUTPUT 200 0.5 150
100 SIGNAL INPUT 50
0
0
50
100
150 LOCATION
200
250
Figure 35. Signal Input (Ramp) and Signal Output for Gamma 0.5
REV. A
-21-
ADV7195
300 GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT FOR VARIOUS GAMMA VALUES
GAMMA-CORRECTED AMPLITUDE
INPUT SIGNAL: STEP
250 SIGNAL OUTPUTS 200 0.3 0.5 150
T PU IN AL 1.5 GN SI
1.4 1.3 1.2
SHARPNESS AND ADAPTIVE FILTER CONTROL MODE
1.5
7 6 5 4 3 2
MAGNITUDE
100
1.1 1.0 0.9 0.8 0.7 0.6 0.5 0 2 4
1 0 -1 -2 -3 -4 -5 -6 -7 -8
1.8
50
0
0
50
100
150 LOCATION
200
250
Figure 36. Signal Input (Ramp) and Selectable Gamma Output Curves
The gamma curves shown in Figure 36 are examples only, any user-defined curve is acceptable in the range of 16-240.
SHARPNESS FILTER CONTROL AND ADAPTIVE FILTER CONTROL
6 8 FREQUENCY - MHz
10
12
14
1.5 1.4 1.3 1.2
7 6 5 4 3 2 1 0 -1 -2 -3
Three Filter modes are available on the ADV7195: one Sharpness Filter mode and two Adaptive Filter modes.
MAGNITUDE
SHARPNESS FILTER MODE
To enhance or attenuate the Y signal in the frequency ranges shown in Figure 37, the following register settings must be used: Sharpness Filter must be enabled (MR17 = "1") and Adaptive Filter Control must be disabled (MR57 = "0"). To select one of the 256 individual responses, the according gain values for each filter, which range from -8 to +7, must be programmed into the Filter Gain register.
ADAPTIVE FILTER MODE
1.1 1.0 0.9 0.8 0.7 0.6 0.5 0 2 4 6 8 FREQUENCY - MHz 10 12
-4 -5 -6 -7 -8
14
MAGNITUDE RESPONSE - Linear Scale
The Adaptive Filter Threshold A, B, C registers, the Adaptive Filter Gain 1, 2, 3 registers, and the Filter Gain register are used in Adaptive Filter mode. To activate the Adaptive Filter control, Sharpness Filter must be enabled (MR17 = "1") and Adaptive Filter Control must be enabled (MR57 = "1"). The derivative of the incoming signal is compared to the three programmable threshold values: Adaptive Filter Threshold A, B, C. The edges can then be attenuated with the settings in Adaptive Filter Gain 1, 2, 3 registers and Filter Gain register. According to the settings of the Adaptive Mode control (MR56), two Adaptive Filter Modes are available: 1. Mode A: is used when Adaptive Filter Mode (MR56) is set to "0." In this case, Filter B (LPF) will be used in the adaptive filter block. Also, only the programmed values for Gain B in the Filter Gain, Adaptive Filter Gain 1, 2, 3 are applied when needed. The Gain A values are fixed and cannot be changed. 2. Mode B: is used when Adaptive Filter Mode (MR56) is set to "1." In this mode a cascade of Filter A and Filter B is used. Both settings for Gain A and Gain B in the Filter Gain, Adaptive Filter Gain 1, 2, 3 become active when needed.
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0
2
4
6 8 FREQUENCY - MHz
10
12
14
FREQUENCY RESPONSE IN SHARPNESS FILTER MODE WITH KA = 3 and KB = 7
Figure 37. Frequency Response in Sharpness Filter Mode
-22-
REV. A
ADV7195
ADAPTIVE FILTER GAIN 1 AFG1 (AFG1)7-0 (Address (SR5-SR0) = 22H)
AFG37 AFG36 AFG35 AFG34 AFG33 AFG32 AFG31 AFG30 AFG37-AFG34 GAIN B AFG33-AFG30 GAIN A
This 8-bit-wide register is used to program the gain applied to signals that lie above Adaptive Filter Threshold A but are smaller than Adaptive Filter Threshold B. Gain A and Gain B values vary from -8 to +7. Settings for (AFG1)3-0 have no effect unless Adaptive Mode Control is set to Mode B (MR56 = "1").
AFG17 AFG16 AFG15 AFG14 AFG13 AFG12 AFG11 AFG10
Figure 40. Adaptive Filter Gain 3 Register
ADAPTIVE FILTER THRESHOLD A AFTA AFTA7-0 (Address (SR5-SR0) = 25H)
AFG17-AFG14 GAIN B
AFG13-AFG10 GAIN A
This 8-bit-wide register is used to program the threshold value for small edges. The recommended programmable threshold range is from 16-235, although any value in the range of 0-255 can be used.
AFTA7 AFTA6 AFTA5 AFTA4 AFTA3 AFTA2 AFTA1 AFTA0
Figure 38. Adaptive Filter Gain 1 Register
ADAPTIVE FILTER GAIN 2 AFG2 (AFG2)7-0 (Address (SR5-SR0) = 23H)
AFTA7-AFTA0 ADAPTIVE FILTER THRESHOLD A
This 8-bit-wide register is used to program the gain applied to signals that lie above Adaptive Filter Threshold B but are smaller than Adaptive Filter Threshold C. Gain A and Gain B values vary from -8 to +7. Settings for (AFG2)3-0 have no effect unless Adaptive Mode Control is set to Mode B (MR56 = "1").
AFG27 AFG26 AFG25 AFG24 AFG23 AFG22 AFG21 AFG20
Figure 41. Adaptive Filter Threshold A Register
ADAPTIVE FILTER THRESHOLD B AFTB AFTB7-0 (Address (SR5-SR0) = 26H)
This 8-bit-wide register is used to program the threshold value for medium edges and has priority over Adaptive Threshold A. The recommended programmable threshold range is from 16-235, although any value in the range of 0-255 can be used.
AFTB7 AFTB6 AFTB5 AFTB4 AFTB3 AFTB2 AFTB1 AFTB0
AFG27-AFG24 GAIN B
AFG23-AFG20 GAIN A
AFTB7-AFTB0 ADAPTIVE FILTER THRESHOLD B
Figure 39. Adaptive Filter Gain 2 Register
ADAPTIVE FILTER GAIN 3 AFG3 (AFG3)7-0 (Address (SR5-SR0) = 24H)
Figure 42. Adaptive Filter Threshold B Register
ADAPTIVE FILTER THRESHOLD C AFTC AFTC7-0 (Address (SR5-SR0) = 27H)
This 8-bit-wide register is used to program the gain applied to signals that lie above Adaptive Filter Threshold C. Gain A and Gain B values vary from -8 to +7. Settings for (AFG3)3-0 have no effect unless Adaptive Mode Control is set to Mode B (MR56 = "1"). The gain applied to signals that lie below Adaptive Threshold A is programmed in the Filter Gain register. At any one time only one of the following registers is active: AFG1, AFG2, AFG3, FG. The gain values can be preprogrammed and become active whenever the threshold conditions for the according register are met. To program the Adaptive Filter Gain registers the same register settings are used as for the Filter Gain register.
This 8-bit-wide register is used to program the threshold value for large edges and has priority over Adaptive Threshold A and B. The recommended programmable threshold range is from 16-235, although any value in the range of 0-255 can be used.
AFTC7 AFTC6 AFTC5 AFTC4 AFTC3 AFTC2 AFTC1 AFTC0
AFTC7-AFTC0 ADAPTIVE FILTER THRESHOLD C
Figure 43. Adaptive Filter Threshold C
REV. A
-23-
ADV7195
SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATION EXAMPLES Sharpness Filter Application
The effect of the sharpness filter can also be seen when using the internally generated crosshatch pattern.
Table VI.
The sharpness filter can be used to enhance or attenuate the Y video output signal. The following register settings were used to achieve the results shown in Figure 44a and Figure 44b. Input data was generated by an external signal source.
Table V.
Address 00hex 01hex 02hex 03hex 04hex 05hex 09hex Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6
Register Setting 00hex 85hex 00hex 38hex 00hex 00hex 3Ehex
Address 00hex 01hex 02hex 03hex 04hex 05hex 09hex 10hex 10hex 10hex 10hex 10hex 10hex Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Filter Gain Filter Gain Filter Gain Filter Gain Filter Gain Filter Gain
Register Setting 40hex 81hex 00hex 78hex 00hex 00hex 3Ehex 00hex (a) 08hex (b) 04hex (c) 40hex (d) 80hex (e) 22hex (f)
TEK RUN T
T
TRIG'D
TEK RUN T
T
TRIG'D
(A) R2 (B) R4 R1 1
(D)
(E)
(C) 1 CH1 500mV REF4 500mV M 4.00 s CH1 ALL FIELDS 4.00 s T 9.99976ms R2 CH1 500mV REF2 500mV M 4.00 s CH1 ALL FIELDS 9.99976ms
(F)
4.00 s T
(a)
(b)
Figure 44. Sharpness Filter Control with Different Gain Settings for Filter Gain
-24-
REV. A
ADV7195
In toggling MR17 (Sharpness Filter Enable/Disable) and setting the Filter Gain register value to 99hex it can be seen that the line contours of the crosshatch pattern change their sharpness.
Adaptive Filter Control Application
Figure 46 shows the output signal when changing the Adaptive Filter Mode to Mode B (MR56 = "1").
TEK RUN T T TRIG'D
Figure 45 shows a typical signal to be processed by the Adaptive Filter Control block.
TEK RUN T
4
T
TRIG'D
4
M 100ns CH4 CH4 100mV ALL FIELDS 12.8222ms T
Figure 46. Output Signal from Adaptive Filter Control
M 100ns CH4 CH4 100mV ALL FIELDS 12.8222ms T
Figure 45. Input Signal to Adaptive Filter Control
The Adaptive Filter Control can also be demonstrated using the internally generated crosshatch test pattern and toggling the Adaptive Filter Control Bit (MR57) using the following register settings:
Table VIII.
The following register settings were used to obtain the results shown in Figure 47, i.e., to remove the ringing on the Y signal. Input data was generated by an external signal source.
Table VII.
Address A00hex 01hex 02hex 03hex 04hex 05hex 06hex 07hex 08hex 09hex 10hex 22hex 23hex 24hex 25hex 26hex 27hex Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Color Y Color Cr Color Cb Mode Register 6 Filter Gain Adaptive Filter Gain 1 Adaptive Filter Gain 2 Adaptive Filter Gain 3 Adaptive Filter Threshold A Adaptive Filter Threshold B Adaptive Filter Threshold C
Register Setting 40hex 85hex 00hex 78hex 00hex 80hex 6Chex 52hex 52hex 3Ehex 00hex AChex 9Ahex 88hex 28hex 3Fhex 64hex
Address 00hex 01hex 02hex 03hex 04hex 05hex 09hex 10hex 22hex 23hex 24hex 25hex 26hex 27hex Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Filter Gain Adaptive Filter Gain 1 Adaptive Filter Gain 2 Adaptive Filter Gain 3 Adaptive Filter Threshold A Adaptive Filter Threshold B Adaptive Filter Threshold C
Register Setting 40hex 81hex 00hex 78hex 00hex 80hex 3Ehex 00hex AChex 9Ahex 88hex 28hex 3Fhex 64hex
TEK RUN T
T
TRIG'D
4
M 100ns CH4 CH4 100mV ALL FIELDS 12.8222ms T
Figure 47. Output Signal from Adaptive Filter Control
REV. A
-25-
ADV7195
HDTV MODE
MODE REGISTER 0 MR0 (MR07-MR00) (Address (SR4-SR0) = 00H)
Figure 49 shows an example of how to program the ADV7195 to accept a different high definition standard but SMPTE293M, SMPTE274M, SMPTE296M or ITU-R.BT1358 standard.
Reserved (MR04)
Figure 50 shows the various operations under the control of Mode Register 0.
MR0 BIT DESCRIPTION Output Standard Selection (MR00-MR01)
A "0" must be written to this bit.
Input Standard (MR05)
Select between 1080i or 720p input.
DV Polarity (MR06)
These bits are used to select the output levels from the ADV7195. If EIA-770.3 (MR01-00 = "00") is selected, the output levels will be: 0 mV for blanking level, 700 mV for peak white (Y channel), 350 mV for Pr, Pb outputs and -300 mV for tri-level sync. If Full Input Range (MR01-00 = "10") is selected, the output levels will be 700 mV for peak white for the Y channel, 350 mV for Pr, Pb outputs and -300 mV for Sync. This mode is used for RS-170, RS-343A standard output compatibility. Sync insertion on the Pr, Pb channels is optional. For output levels, refer to the Appendix.
Input Control Signals (MR02-MR03)
This control bit allows to select the polarity of the DV input control signal to be either active high or active low.
Reserved (MR07)
A "0" must be written to this bit.
Table IX. Truth Table
SYNC 1 -> 0
TSYNC 0
DV 0 or 1 50% Point of Falling Edge of Tri-Level Horizontal Sync Signal, A 25% Point of Rising Edge of Tri-Level Horizontal Sync Signal, B 50% Point of Falling Edge of Tri-Level Horizontal Sync Signal, C 50% Start of Active Video, D 50% End of Active Video, E
These control bits are used to select whether data is input with external horizontal, vertical and blanking sync signals or if the data is input with embedded EAV/SAV codes. An Asynchronous timing mode is also available using TSYNC, SYNC and DV as input control signals. These timing control signals have to be programmed by the user.
0
0 -> 1
0 or 1
0 -> 1
0 or 1
0
1 1
0 or 1 0 or 1
0 -> 1 1 -> 0
CLK SYNC TSYNC DV SET MR06 = 1 HORIZONTAL SYNC ACTIVE VIDEO ANALOG OUTPUT PROGRAMMABLE INPUT TIMING
81 A 66 B
66 C
243 D
1920 E
Figure 48. Async Timing Mode--Programming Input Control Signals for SMPTE295M Compatibility
525 VIDEO OUTPUT
1
12
13
42
43
HSYNC VSYNC DV
Figure 49. DV Input Control Signal in Relation to Video Output Signal
-26-
REV. A
ADV7195
MODE REGISTER 1 MR1 (MR17-MR10) (Address (SR4-SR0) = 01H) Test Pattern Hatch/Frame (MR13)
Figure 51 shows the various operations under the control of Mode Register 1.
MR1 BIT DESCRIPTION Pixel Data Enable (MR10)
If this bit is set to "0," a crosshatch test pattern is output from the ADV7195. The crosshatch test pattern can be used to test monitor convergence. If this bit is set to "1," a uniform colored frame/field test pattern is output from the ADV7195. The color of the lines or the frame/field is white by default but can be programmed to be any color using the Color Y, Color Cr, Color Cb registers.
VBI Open (MR14)
When this bit is set to "0," the pixel data input to the ADV7195 is blanked such that a black screen is output from the DACs. When this bit is set to "1," pixel data is accepted at the input pins and the ADV7195 outputs to the standard set in "Output Standard Selection" (MR01-00). This bit also must be set to "1" to enable output of the test pattern signals.
Input Format (MR11)
This bit enables or disables the facility of VBI data insertion during the Vertical Blanking Interval. For this purpose Lines 7-20 in 1080i and Lines 6-25 in 720p can be used for VBI data insertion.
Reserved (MR15-MR17)
It is possible to input data in 4:2:2 format or in 4:4:4 HDTV format.
Test Pattern Enable (MR12)
A "0" must be written to these bits.
Enables or disables the internal test pattern generator.
MR07
MR06
MR05
MR04
MR03
MR02
MR01
MR00
MR07 ZERO MUST BE WRITTEN TO THIS BIT
INPUT STANDARD MR05 0 1 1080I 720P
MR04 ZERO MUST BE WRITTEN TO THIS BIT
INPUT CONTROL SIGNALS MR03 MR02 0 0 1 1 0 1 0 1 HSYNC/VSYNC/DV EAV/SAV TSYNC/SYNC/DV RESERVED
DV POLARITY MR06 0 ACTIVE HIGH 1 ACTIVE LOW OUTPUT STANDARD SELECTION MR01 MR00 0 0 1 1 0 1 0 1 EIA770.3 RESERVED FULL I/P RANGE RESERVED
Figure 50. Mode Register 0
MR17
MR16
MR15
MR14
MR13
MR12
MR11
MR10
MR17-MR15 ZERO MUST BE WRITTEN TO THIS BIT
VBI OPEN MR14 0 DISABLE 1 ENABLE
TEST PATTERN ENABLE MR12 0 DISABLE 1 ENABLE
PIXEL DATA ENABLE MR10 0 DISABLE 1 ENABLE
TEST PATTERN HATCH/FRAME MR13 0 HATCH 1 FIELD/FRAME
INPUT FORMAT MR11 0 4:4:4 Y CR CB 1 4:2:2 Y CR CB
Figure 51. Mode Register 1
REV. A
-27-
ADV7195
MODE REGISTER 2 MR1 (MR27-MR20) (Address (SR4-SR0) = 02H) MODE REGISTER 3 MR3 (MR37-MR30) (Address (SR4-SR0) = 03H)
Figure 53 shows the various operations under the control of Mode Register 2.
MR2 BIT DESCRIPTION Y Delay (MR20-MR22)
Figure 54 shows the various operations under the control of Mode Register 3.
MR3 BIT DESCRIPTION HDTV Enable (MR30)
With these bits it is possible to delay the Y signal with respect to the falling edge of the horizontal sync signal by up to four pixel clock cycles. Figure 52 demonstrates this facility.
Color Delay (MR23-MR25)
When this bit is set to "1," the ADV7195 reverts to HDTV mode. When set to "0" the ADV7195 reverts to Progressive Scan Mode (PS mode).
Reserved (MR31-MR32)
With these bits it is possible to delay the color signals with respect to the falling edge of the horizontal sync signal by up to four pixel clock cycles. Figure 52 demonstrates this facility.
Reserved (MR26-MR27)
A "0" must be written to these bits.
DAC A Control (MR33)
A "0" must be written to these bits.
Setting this bit to "1" enables DAC A, otherwise this DAC is powered down.
DAC B Control (MR34)
NO DELAY Y DELAY Y OUTPUT
Setting this bit to "1" enables DAC B, otherwise this DAC is powered down.
DAC C Control (MR35)
MAX DELAY NO DELAY
Setting this bit to "1" enables DAC C, otherwise this DAC is powered down.
Reserved (MR36-MR37)
A "0" must be written to these bits.
PrPb DELAY PrPb OUTPUT
MAX DELAY
Figure 52. Y and Color Delay
MR27
MR26
MR25
MR24
MR23
MR22
MR21
MR20
MR27-MR26 A ZERO MUST BE WRITTEN TO THESE BITS
COLOR DELAY MR25 MR24 MR23 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 PCLK 1 PCLK 2 PCLK 3 PCLK 4 PCLK
Y DELAY MR22 MR21 MR20 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 PCLK 1 PCLK 2 PCLK 3 PCLK 4 PCLK
Figure 53. Mode Register 2
MR37
MR36
MR35
MR34
MR33
MR32
MR31
MR30
MR37-MR36 ZERO MUST BE WRITTEN TO THESE BITS
DAC B CONTROL MR34 0 POWER-DOWN 1 NORMAL DAC C CONTROL MR35 0 POWER-DOWN 1 NORMAL
MR32-MR31 ZERO MUST BE WRITTEN TO THESE BITS
HDTV ENABLE MR30 0 DISABLE 1 ENABLE
DAC A CONTROL MR33 0 POWER-DOWN 1 NORMAL
Figure 54. Mode Register 3
-28-
REV. A
ADV7195
MODE REGISTER 4 MR4 (MR47-MR40) (Address (SR4-SR0) = 04H) Color Output Swap (MR53)
Figure 55 shows the various operations under the control of Mode Register 4.
MR4 BIT DESCRIPTION Timing Reset (MR40)
By default DAC B is configured as the Pr output and DAC C as the Pb output. In setting this bit to "1," the DAC outputs can be swapped around so that DAC B outputs Pb and DAC C outputs Pr. Table X demonstrates this in more detail.
Reserved (MR54-MR57)
A "0" must be written to these bits.
Table X. Relationship Between Input Pixel Port, MR53 and DAC B, DAC C Outputs In 4:4:4 Input Mode
Toggling MR40 from low to high and low again resets the internal horizontal and vertical timing counters.
Reserved (MR41-MR47)
A "0" must be written to these bits.
MODE REGISTER 5 MR5 (MR57-MR50) (Address (SR4-SR0) = 05H)
Color Data Input on Pins Cr9-0 Cb/Cr9-0 Cr9-0 Cb/Cr9-0
In 4:2:2 Input Mode
MR53 0 0 1 1
Analog Output Signal DAC B DAC C DAC C DAC B
Figure 56 shows the various operations under the control of Mode Register 5.
MR5 BIT DESCRIPTION Reserved (MR50)
This bit is reserved for the revision code.
RGB Mode (MR51)
Color Data Input on Pins Cr9-0 Cb/Cr9-0 Cb/Cr9-0
MR53 0 or 1 0 1
Analog Output Signal Not Operational DAC C (Pb) DAC C (Pr)
When RGB mode is enabled (MR51 = "1"), the ADV7195 accepts unsigned binary RGB data at its input port. This control is also available in Async Timing Mode.
Sync on PrPb (MR52)
By default the color component output signals Pr, Pb do not contain any horizontal sync pulses. If required, they can be inserted when MR52 = "1." This control is not available in RGB Mode.
MR47
MR46
MR45
MR44
MR43
MR42
MR41
MR40
MR47-MR41 ZERO MUST BE WRITTEN TO THESE BITS
TIMING RESET MR40
Figure 55. Mode Register 4
MR57
MR56
MR55
MR54
MR53
MR52
MR51
MR50
MR57-MR54 ZERO MUST BE WRITTEN TO THESE BITS
COLOR OUTPUT SWAP MR53 0 1 DAC B = PR DAC C = R
SYNC ON PrPb MR52 0 DISABLE 1 ENABLE
MR50 RESERVED FOR REVISION CODE
RGB MODE MR51 0 DISABLE 1 ENABLE
Figure 56. Mode Register 5
REV. A
-29-
ADV7195
DAC TERMINATION AND LAYOUT CONSIDERATIONS Voltage Reference PC BOARD LAYOUT CONSIDERATIONS
The ADV7195 contains an onboard voltage reference. The VREF pin is normally terminated to VAA through a 0.1 F capacitor when the internal VREF is used. Alternatively, the ADV7195 can be used with an external VREF (AD589). Resistor RSET is connected between the RSET pin and AGND and is used to control the full-scale output current and therefore the DAC voltage output levels. For full-scale output, RSET must have a value of 2470 ; RLOAD has a value of 300 . When an input range of 0-1023 is selected, the value of RSET must be 2820 . The ADV7195 has three analog outputs, corresponding to Y, Pr, Pb video signals. The DACs must be used with external buffer circuits in order to provide sufficient current to drive an output device. Suitable op amps are the AD8009, AD8002, AD8001, or AD8057. To calculate the output full-scale current and voltage, the following equations should be used: VOUT = IOUT x RLOAD IOUT = [VREF x k]/RSET k = 5.66, for I/P Ranges 64-940, 64-960, O/P Standards EIA-770.1-3 k = 6.46, FCI Input Ranges 0-1023, Output Standard RS-170/343A VREF = 1.235 V
The ADV7195 is optimally designed for lowest noise performance, both radiated and conducted noise. To complement the excellent noise performance of the ADV7195, it is imperative that great care be given to the PC board layout. The layout should be optimized for lowest noise on the ADV7195 power and ground lines. This can be achieved by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and AGND, and VDD and DGND pins, should be kept as short as possible to minimize inductive ringing. It is recommended that a four-layer printed circuit board be used. With power and ground planes separating the layer of the signal carrying traces of the components and solder-side layer. Placement of components should be considered to separate noisy circuits such as crystal clocks, high-speed logic circuitry, and analog circuitry. There should be a separate analog ground plane (AGND) and a separate digital ground plane (GND). Power planes should encompass a digital power plane (VDD) and an analog power plane (VAA). The analog power plane should contain the DACs and all associated circuitry, and the VREF circuitry. The digital power plane should contain all logic circuitry. The analog and digital power planes should be individually connected to the common power plane at one single point through a suitable filtering device such as a ferrite bead.
POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP VAA 10nF 0.1 F VAA VAA 0.1 F 24, 35 COMP VAA 1, 12 VDD DAC A 300 Y OUTPUT 10nF 0.1 F
Cb/Cr0-Cb/Cr9
Cr0-Cr9 DAC B Y0-Y9 UNUSED INPUTS SHOULD BE GROUNDED 300 Pr (V) OUTPUT
ADV7195
HSYNC/SYNC VSYNC/TSYNC DAC C 300 VAA 100 SCL 100 RESET SDA VREF CLKIN ALSB AGND 26, 33 4.7k RSET GND 13, 52 MPU BUS 5k VAA 5k Pb (U) OUTPUT
VAA 4.7k 4.7 F 6.3V 27MHz, 74.25MHz OR 74.1758MHz CLOCK VAA
DV
2.47k 2.82k
OR
Figure 57. Circuit Layout
-30-
REV. A
ADV7195
DAC output traces on a PCB should be treated as transmission lines. It is recommended that the DACs be placed as close as possible to the output connector, with the analog output traces being as short as possible (less than 3 inches). The DAC termination resistors should be placed as close as possible to the DAC outputs and should overlay the PCB's ground plane. As well as minimizing reflections, short analog output traces will reduce noise pickup due to neighboring digital circuitry.
Supply Decoupling
Due to the high clock rates used, long clock lines to the ADV7195 should be avoided to minimize noise pickup. Any active pull-up termination resistors for the digital inputs should be connected to the digital power plane and not the analog power plane.
Analog Signal Interconnect
The ADV7195 should be located as close as possible to the output connectors, thus minimizing noise pickup and reflections due to impedance mismatch. For optimum performance, the analog outputs should be source and load terminated, as shown in Figure 58. The termination resistors should be as close as possible to the ADV7195 to minimize reflections. Any unused inputs should be tied to ground.
Video Output Buffer and Optional Output Filter
Noise on the analog power plane can be further reduced by the use of decoupling capacitors. Optimum performance is achieved by the use of 0.1 F ceramic capacitors. Each of group of VAA or VDD pins should be individually decoupled to ground. This should be done by placing the capacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance.
Digital Signal Interconnect
Output buffering is necessary in order to drive output devices,
such as progressive scan or HDTV monitors.
The digital signal lines should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power plane.
Analog Devices produces a range of suitable op amps for this application. Suitable op amps would be the AD8009, AD8002, AD8001, or AD8057. More information on line driver buffering circuits is given in the relevant op amp data sheets.
+5V 0.1 F 10 F 75 COAX 75
DAC A
LPF
AD8057
75
0.1 F
10 F
ADV7195
-5V +5V 0.1 F 10 F 75 COAX 75
PROGRESSIVE SCAN MONITOR
DAC B
LPF
AD8057
75
0.1 F +5V +5V 0.1 F DAC C LPF 75 10 F
10 F
COAX 75
AD8057
75
0.1 F -5V
10 F
Figure 58. Output Buffer and Optional Filter
REV. A
-31-
ADV7195
An optional analog reconstruction LPF might be required as an antialias filter if the ADV7195 is connected to a device that requires this filtering. The Eval ADV7195/ADV7196/ADV7197 EB evaluation board uses the ML6426 Microlinear IC, which provides buffering and low-pass filtering for HDTV applications. The Eval ADV7195/ADV7196/ADV7197 EB Rev. B and Rev. C evaluation board uses the AD8057 as a buffer and a sixth order filter as a LPF.
6.8 H 600R 6.8pF 10 H 22pF 2.2 H 18pF 600R AD8057
REGISTER SETTINGS Table XI. Register Settings on Power-Up
Address 00hex 01hex 02hex 03hex 04hex 05hex 06hex 07hex 08hex 09hex 10hex 22hex 23hex 24hex 25hex 26hex 27hex Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Color Y Color Cr Color Cb Mode Register 6 Filter Gain Adaptive Filter Gain 1 Adaptive Filter Gain 2 Adaptive Filter Gain 3 Adaptive Filter Threshold A Adaptive Filter Threshold B Adaptive Filter Threshold C
Register Setting 00hex 00hex 00hex 38hex 00hex 00hex A0hex 80hex 80hex 00hex 00hex AChex 9Ahex 88hex 28 hex 3Fhex 64 hex
Figure 59. Example/Cr Output Filter: PS Mode/2x Oversampling
0 -5 -10 GROUP DELAY (SEC) -15 MAGNITUDE (dB)
498 63n 398 54n 298 45n 198 36n 97.6 27n PHASE (DEG) 0 18n -102 9n -202 1
2 3 4 5 6 7 8 9 10 2 3 4 0n
Table XII. Internal Colorbars (Hatch), Progressive Scan Mode
Address 00hex 01hex 02hex 03hex 04hex 05hex 06hex 07hex 08hex 09hex Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Color Y Color Cr Color Cb Mode Register 6
Register Setting 00hex 05hex 00hex 38hex 00hex 00hex xxhex xxhex xxhex 3Ehex
-20 -25
-30
-35
FREQUENCY - MHz
Figure 60. Frequency Response|C1 Filter Circuit in above Figure
Table XIII. Internal Colorbars (Field), HDTV Mode
Address 00hex 01hex 02hex 03hex 04hex 05hex 06hex 07hex 08hex Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Color Y Color Cr Color Cb
Register Setting 00hex 0Dhex 00hex 39hex 00hex 00hex xxhex xxhex xxhex
-32-
REV. A
ADV7195
INPUT CODE EIA-770.2, STANDARD FOR Y OUTPUT VOLTAGE
INPUT CODE
940 700mV
EIA-770.3, STANDARD FOR Y
OUTPUT VOLTAGE 700mV
940
ACTIVE VIDEO
ACTIVE VIDEO 300mV
64
0mV
64
0mV
-300mV
-300mV
EIA-770.3, STANDARD FOR Pr/Pb
EIA-770.2, STANDARD FOR Pr/Pb OUTPUT VOLTAGE 350mV
OUTPUT VOLTAGE 350mV 300mV
960
960
ACTIVE VIDEO
ACTIVE VIDEO 512 0mV
512
0mV
-300mV 64 -350mV
-300mV 64 -350mV
Figure 61. EIA-770.2 Standard Output Signals (525p)
Figure 63. EIA-770.3 Standard Output Signals (1080i, 720p)
INPUT CODE
EIA-770.1, STANDARD FOR Y
OUTPUT VOLTAGE 782mV
INPUT CODE 1023
Y-OUTPUT LEVELS FOR FULL I/P SELECTION
OUTPUT VOLTAGE 700mV
940
714mV
ACTIVE VIDEO
ACTIVE VIDEO
64
64 0mV
0mV
-300mV
-286mV EIA-770.1, STANDARD Pr/Br OUTPUT VOLTAGE
PrPb-OUTPUT LEVELS FOR FULL I/P SELECTION 1023
OUTPUT VOLTAGE 700mV
960
350mV
ACTIVE VIDEO
ACTIVE VIDEO 512 0mV
64
0mV
-300mV 64 -350mV
-300mV
Figure 62. EIA-770.1 Standard Output Signals (525p)
Figure 64. Output Levels for Full I/P Selection
REV. A
-33-
ADV7195
SMPTE293M
ANALOG WAVEFORM EAV CODE F 0 0F F 0 0V H 4 CLOCK SAMPLE NUMBER 719
OHDATUM ANCILLARY DATA (OPTIONAL) SAV CODE F00F F00V H 4 CLOCK 799 854 857 0 719 DIGITAL ACTIVE LINE C C bYr C YrY
INPUT PIXELS
723 736
DIGITAL HORIZONTAL BLANKING FVH = FVH AND PARITY BITS SAV = LINE 43-525 = 200H SAV = LINE 1-42 = 2AC EAV = LINE 43-525 = 274H EAV = LINE 1-42 = 2D8
Figure 65. EAV/SAV Input Data Timing Diagram--SMPTE293M
OHDATUM SMPTE274M
ANALOG WAVEFORM
4T EAV CODE
272T ANCILLARY DATA (OPTIONAL) OR BLANKING CODE
4T SAV CODE
1920T DIGITAL ACTIVE LINE C rY
INPUT PIXELS
F 0 0F F 0 0V H 4 CLOCK
C F00FC F00VbYr H 4 CLOCK 0 2199 44 188 192
SAMPLE NUMBER
2112
2116 2156
2111
FVH = FVH AND PARITY BITS SAV/EAV = LINE 1-562: F = 0 SAV/EAV = LINE 563-1125: F = 1 SAV/EAV = LINE 1-20; 561-583; 1124-1125: V = 1 SAV/EAV = LINE 21-560; 584-1123: V = 0
Figure 66. EAV/SAV Input Data Timing Diagram--SMPTE274M
-34-
REV. A
ADV7195
ACTIVE VIDEO VERTICAL BLANK ACTIVE VIDEO
522
523
524
525
1
2
5
6
7
8
9
12
13
10
11
42
42
43
44
Figure 67. SMPTE293M (525p)
ACTIVE VIDEO VERTICAL BLANK
ACTIVE VIDEO
622
623
624
625
1
2
4
5
6
7
8
9
10
11
12
13
43
44
45
Figure 68. ITU-R.BT1358 (625p)
DISPLAY
VERTICAL BLANKING INTERVAL
747
748
749
750
1
2
3
4
5
6
7
8
25
26
27
744
745
Figure 69. SMPTE296M (720p)
DISPLAY FIELD 1 VERTICAL BLANKING INTERVAL
1124
1125
1
2
3
4
5
6
7
8
20
21
22
560
DISPLAY FIELD 2 VERTICAL BLANKING INTERVAL
561
562
563
564
565
566
567
568
569
570
583
584
585
1123
Figure 70. SMPT274M (1080i)
REV. A
-35-
ADV7195
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
52-Lead Plastic Quad Flatpack (S-52)
0.094 (2.39) 0.084 (2.13) 0.037 (0.95) 0.026 (0.65) SEATING PLANE TOP VIEW
(PINS DOWN)
0.557 (14.15) 0.537 (13.65) 0.398 (10.11) 0.390 (9.91)
52 1 PIN 1 40 39
0.012 (0.30) 0.006 (0.15) 0.008 (0.20) 0.006 (0.15) 0.082 (2.09) 0.078 (1.97)
13 14
27 26
0.0256 (0.65) BSC
0.014 (0.35) 0.010 (0.25)
0.398 (10.11) 0.390 (9.91) 0.557 (14.15) 0.537 (13.65)
-36-
REV. A
PRINTED IN U.S.A.
C00232-0-5/02(A)

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