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| w w a D . w aS t ee h 4U t om .c w w U t W83627EHF 4 e e W83627EHG hLPC I/O WINBOND S ta a .D w .c m o Date: Mar 18 2005 Revision: 0.6 w w w .D a aS t ee h 4U t om .c W83627EHF/W83627EHG Preliminary W83627EHF Data Sheet Revision History Pages 1 2 3 Dates 10/01/2004 11/09/2004 12/07/2004 03/18/2005 Version 0.5 0.51 0.52 0.6 Web Version N/A N/A N/A N/A Main Contents First published preliminary version. Correct typo at 5.11. 1. Correct DC CHARACTERISTICS description 2. Update Demo Circuit 3. Add Pb-free part no:W83627EHG Add SMART FANTM III description Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. W83627EHF/W83627EHG Preliminary TABLE OF CONTENTS 1. GENERAL DESCRIPTION ..................................................................................... 1 2. FEATURES............................................................................................................. 2 3. BLOCK Diagram .................................................................................................... 6 4. PIN CONFIGURATION FOR W83627EHF............................................................. 7 5. PIN DESCRIPTION................................................................................................. 8 5.1 LPC Interface......................................................................................................................8 5.2 FDC Interface .....................................................................................................................9 5.3 Multi-Mode Parallel Port...................................................................................................10 5.4 Serial Port & Infrared Port Interface.................................................................................11 5.5 KBC Interface ...................................................................................................................13 5.6 Serial Flash Interface .......................................................................................................13 5.7 Hardware Monitor Interface .............................................................................................14 5.8 Game Port & MIDI Port ....................................................................................................15 5.9 ACPI Interface ..................................................................................................................16 5.10 General Purpose I/O Port...............................................................................................16 5.10.1 GPIO Power Source................................................................................................................ 16 5.10.2 GPIO-1 Interface ..................................................................................................................... 17 5.10.3 GPIO-2 Interface ..................................................................................................................... 17 5.10.4 GPIO-3 Interface ..................................................................................................................... 17 5.10.5 GPIO-4 Interface ..................................................................................................................... 18 5.10.6 GPIO-5 Interface ..................................................................................................................... 18 5.10.7 GPIO-6 Interface ..................................................................................................................... 18 5.10.8 GPIO-1 and GPIO-4 with WDTO# / SUSLED / PLED multi-function...................................... 18 5.11 POWER PINS ................................................................................................................19 6. Hardware monitor ............................................................................................... 20 6.1 General Description..........................................................................................................20 6.2 Access Interface...............................................................................................................20 6.2.1 LPC interface............................................................................................................................. 20 6.2.2 I2C interface............................................................................................................................... 21 6.2.2.1 Serial bus (I2C) access timing..............................................................................................................22 6.3 Analog Inputs....................................................................................................................22 6.3.1 Monitor over 2.048V voltage ..................................................................................................... 23 6.3.2 CPUVCORE voltage detection method..................................................................................... 24 6.3.3 Temperature Measurement Machine ........................................................................................ 24 7.3.3.1 Monitor temperature from thermistor ....................................................................................................24 TM TM 7.3.3.2 Monitor temperature from Pentium II /Pentium III thermal diode.....................................................25 6.4 FAN Speed Count and FAN Speed Control ....................................................................25 6.4.1 Fan speed count........................................................................................................................ 25 6.4.2 Fan speed control...................................................................................................................... 27 6.4.2.1 PWM Duty Cycle Output.......................................................................................................................27 6.4.2.2 DC Voltage Output ...............................................................................................................................27 6.5 Smart Fan Control ............................................................................................................27 6.5.1 Thermal Cruise mode................................................................................................................ 27 6.5.2 Fan Speed Cruise mode ........................................................................................................... 29 6.5.3 Manual Control Mode ................................................................................................................ 29 6.6 SMI# interrupt mode.........................................................................................................33 6.6.1 Voltage SMI# mode................................................................................................................... 33 W83627EHF/W83627EHG Preliminary 6.6.2 Fan SMI# mode......................................................................................................................... 33 6.6.3 Temperature SMI# mode .......................................................................................................... 34 6.6.3.1 Temperature sensor 1(SYSTIN) SMI# interrupt has 3 modes ..............................................................34 6.6.3.2 Temperature sensor 2(CPUTIN) and sensor 3(AUXTIN) SMI# interrupt has two modes .....................36 6.7 OVT# interrupt mode........................................................................................................37 6.8 REGISTERS AND RAM...................................................................................................38 6.8.1 Address Port (Port x5h)............................................................................................................. 38 6.8.2 Data Port (Port x6h) .................................................................................................................. 38 6.8.3 SYSFANOUT PWM Output Frequency Configuration Register - Index 00h (Bank 0).............. 39 6.8.4 SYSFANOUT Output Value Select Register - Index 01h (Bank 0) ........................................... 40 6.8.5 CPUFANOUT0 PWM Output Frequency Configuration Register - Index 02h (Bank 0) ........... 42 6.8.6 CPUFANOUT0 Output Value Select Register - Index 03h (Bank 0) ........................................ 42 6.8.7 FAN Configuration Register I - Index 04h (Bank 0) .................................................................. 43 6.8.8 SYSTIN Target Temperature Register/ SYSFANIN Target Speed Register - Index 05h (Bank 0) ............................................................................................................................................................ 44 6.8.9 CPUTIN Target Temperature Register/ CPUFANIN0 Target Speed Register - Index 06h (Bank 0) ........................................................................................................................................................ 44 6.8.10 Tolerance of Target Temperature or Target Speed Register - Index 07h (Bank 0)................ 45 6.8.11 SYSFANOUT Stop Value Register - Index 08h (Bank 0) ....................................................... 45 6.8.12 CPUFANOUT0 Stop Value Register - Index 09h (Bank 0) ..................................................... 45 6.8.13 SYSFANOUT Start-up Value Register - Index 0Ah (Bank 0).................................................. 46 6.8.14 CPUFANOUT0 Start-up Value Register - Index 0Bh (Bank 0) ............................................... 46 6.8.15 SYSFANOUT Stop Time Register - Index 0Ch (Bank 0) ........................................................ 47 6.8.16 CPUFANOUT0 Stop Time Register - Index 0Dh (Bank 0)...................................................... 47 6.8.17 Fan Output Step Down Time Register - Index 0Eh (Bank 0) .................................................. 48 6.8.18 Fan Output Step Up Time Register - Index 0Fh (Bank 0)....................................................... 48 6.8.19 AUXFANOUT PWM Output Frequency Configuration Register - Index 10h (Bank 0) ........... 49 6.8.20 AUXFANOUT Output Value Select Register - Index 11h (Bank 0)......................................... 50 6.8.21 FAN Configuration Register II - Index 12h (Bank 0) ............................................................... 50 6.8.22 AUXTIN Target Temperature Register/ AUXFANIN0 Target Speed Register - Index 13h (Bank 0) .............................................................................................................................................. 51 6.8.23 Tolerance of Target Temperature or Target Speed Register - Index 14h (Bank 0)................ 51 6.8.24 AUXFANOUT Stop Value Register - Index 15h (Bank 0) ....................................................... 52 6.8.25 AUXFANOUT Start-up Value Register - Index 16h (Bank 0).................................................. 52 6.8.26 AUXFANOUT Stop Time Register - Index 17h (Bank 0) ........................................................ 53 6.8.27 OVT# Configuration Register - Index 18h (Bank 0) ................................................................ 53 6.8.28 Reserved - Index 19h (Bank 0) ............................................................................................... 54 6.8.29 Reserved - Index 1A-1Bh (Bank 0) ......................................................................................... 54 6.8.30 Reserved - Index 1Ch-1Fh (Bank 0) ....................................................................................... 54 6.8.31 Value RAM Index 20h- 3Fh (Bank 0)................................................................................. 54 6.8.32 Configuration Register - Index 40h (Bank 0).......................................................................... 55 6.8.33 Interrupt Status Register 1 - Index 41h (Bank 0) ................................................................... 56 6.8.34 Interrupt Status Register 2 - Index 42h (Bank 0) ................................................................... 56 6.8.35 SMI# Mask Register 1 - Index 43h (Bank 0) .......................................................................... 57 6.8.36 SMI# Mask Register 2 - Index 44h (Bank 0) .......................................................................... 57 6.8.37 Reserved Register - Index 45h (Bank 0)............................................................................... 58 6.8.38 SMI# Mask Register 3 - Index 46h (Bank 0) ......................................................................... 58 6.8.39 Fan Divisor Register I - Index 47h (Bank 0) ........................................................................... 58 6.8.40 Serial Bus Address Register - Index 48h (Bank 0) ............................................................... 59 6.8.41 Reserved - Index 49h (Bank 0) .............................................................................................. 59 6.8.42 CPUFANOUT1 with Temperature source Select - Index 4Ah (Bank 0)................................. 59 6.8.43 Fan Divisor Register II - Index 4Bh (Bank 0) ......................................................................... 59 6.8.44 SMI#/OVT# Control Register - Index 4Ch (Bank 0) ............................................................... 60 6.8.45 FAN IN/OUT Control Register - Index 4Dh (Bank 0) ............................................................. 61 W83627EHF/W83627EHG Preliminary 6.8.46 Register 50h ~ 5Fh Bank Select Register - Index 4Eh (Bank 0)............................................ 61 6.8.47 Winbond Vendor ID Register - Index 4Fh (Bank 0) ............................................................... 62 6.8.48 Winbond Test Register - Index 50h-55h (Bank 0).................................................................. 62 6.8.49 BEEP Control Register 1 - Index 56h (Bank 0)....................................................................... 62 6.8.50 BEEP Control Register 2 - Index 57h (Bank 0)....................................................................... 63 6.8.51 Chip ID - Index 58h (Bank 0)................................................................................................... 64 6.8.52 Diode Selection Register - Index 59h (Bank 0)....................................................................... 64 6.8.53 Reserved - Index 5Ah-5Ch (Bank 0) ....................................................................................... 65 6.8.54 VBAT Monitor Control Register - Index 5Dh (Bank 0) ............................................................ 65 6.8.55 Reserved Register - Index 5Eh-5Fh (Bank 0)......................................................................... 66 6.8.56 CPUFANOUT1 PWM Output Frequency Configuration Register - Index 60h (Bank 0) ......... 66 6.8.57 CPUFANOUT1 Output Value Select Register - Index 61h (Bank 0) ...................................... 67 6.8.58 FAN Configuration Register III - Index 62h (Bank 0) .............................................................. 67 6.8.59 Target Temperature Register/ CPUFANIN1 Target Speed Register - Index 63h (Bank 0) .... 68 6.8.60 CPUFANOUT1 Stop Value Register - Index 64h (Bank 0) ..................................................... 68 6.8.61 CPUFANOUT1 Start-up Value Register - Index 65h (Bank 0)................................................ 69 6.8.62 CPUFANOUT1 Stop Time Register - Index 66h (Bank 0) ...................................................... 69 6.8.63 CPUFANOUT0 Maximum Output Value Register - Index 67h (Bank 0)................................. 70 6.8.64 CPUFANOUT0 Output Step Value Register - Index 68h (Bank 0) ......................................... 70 6.8.65 CPUFANOUT1 Maximum Output Value Register - Index 69h (Bank 0)................................. 71 6.8.66 CPUFANOUT1 Output Step Value Register - Index 6Ah (Bank 0)......................................... 71 6.8.67 CPUTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 1)........ 72 6.8.68 CPUTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 1) ........ 72 6.8.69 CPUTIN Temperature Sensor Configuration Register - Index 52h (Bank 1) .......................... 73 6.8.70 CPUTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 1) ........... 73 6.8.71 CPUTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 1) ............ 73 6.8.72 CPUTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank1). 74 6.8.73 CPUTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank 1). 74 6.8.74 AUXTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 2)........ 75 6.8.75 AUXTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 2)......... 75 6.8.76 AUXTIN Temperature Sensor Configuration Register - Index 52h (Bank 2) .......................... 76 6.8.77 AUXTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 2)............ 76 6.8.78 AUXTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 2) ............ 76 6.8.79 AUXTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank 2) 77 6.8.80 AUXTIN Temperature Sensor Over-temperature(Low Byte) Register - Index 56h (Bank 2).. 77 6.8.81 Interrupt Status Register 3 - Index 50h (Bank 4) .................................................................... 78 6.8.82 SMI# Mask Register 4 - Index 51h (Bank 4) ........................................................................... 78 6.8.83 Reserved Register - Index 52h (Bank 4)................................................................................. 78 6.8.84 BEEP Control Register 3 - Index 53h (Bank 4)....................................................................... 79 6.8.85 SYSTIN Temperature Sensor Offset Register - Index 54h (Bank 4) ...................................... 79 6.8.86 CPUTIN Temperature Sensor Offset Register - Index 55h (Bank 4)...................................... 79 6.8.87 AUXTIN Temperature Sensor Offset Register - Index 56h (Bank 4) ...................................... 80 6.8.88 Reserved Register - Index 57h-58h (Bank 4) ......................................................................... 80 6.8.89 Real Time Hardware Status Register I - Index 59h (Bank 4).................................................. 81 6.8.90 Real Time Hardware Status Register II - Index 5Ah (Bank 4) ................................................ 81 6.8.91 Real Time Hardware Status Register III - Index 5Bh (Bank 4) ............................................... 82 6.8.92 Reserved Register - Index 5Ch-5Dh (Bank 4) ........................................................................ 83 6.8.93 Value RAM 2 Index 50h-59h (Bank 5)............................................................................... 83 6.8.94 Winbond Test Register - Index 50h-57h (Bank 6)................................................................... 83 7. Configuration Register ...................................................................................... 84 7.1 Chip (Global) Control Register.........................................................................................84 7.2 Logical Device 0 (FDC) ....................................................................................................90 7.3 Logical Device 1 (Parallel Port)........................................................................................93 W83627EHF/W83627EHG Preliminary 7.4 Logical Device 2 (UART A) ..............................................................................................94 7.5 Logical Device 3 (UART B) ..............................................................................................95 7.6 Logical Device 5 (Keyboard Controller) ...........................................................................97 7.6 Logical Device 6 (Serial Flash Interface) .........................................................................98 7.7 Logical Device 7 (GPIO1, GPIO6, Game Port & MIDI Port) ...........................................99 7.8 Logical Device 8 (WDTO# & PLED) ..............................................................................102 7.9 Logical Device 9 (GPIO2,GPIO3, GPIO4, GPIO5 & SUSLED) (VSB Power) ..............104 7.10 Logical Device A (ACPI)...............................................................................................107 7.11 Logical Device B (Hardware Monitor) ..........................................................................113 8. DC Specification................................................................................................ 114 8.1 Absolute Maximum Ratings ...........................................................................................114 8.2 DC CHARACTERISTICS ...............................................................................................114 9. How to READ THE TOP MARKING .................................................................. 121 10. PACKAGE SPECIFICATION............................................................................ 122 Appendix A : Demo Circuit................................................................................... 122 W83627EHF/W83627EHG Preliminary 1. GENERAL DESCRIPTION W83627EHF is an evolving product from Winbond's most popular I/O family. They feature a whole new interface, namely LPC (Low Pin Count) interface, which will be supported in the new generation chip-set. This interface as its name suggests is to provide an economical implementation of I/O's interface with lower pin count and still maintains equivalent performance as its ISA interface counterpart. Approximately 40 pin counts are saved in LPC I/O comparing to ISA implementation. It is fully transparent in terms of software which means no BIOS or device driver update is needed except chip-specific configuration. The disk drive adapter functions of W83627EHF include a floppy disk drive controller compatible with the industry standard 82077/ 765, data separator, write pre-compensation circuit, decode logic, data rate selection, clock generator, drive interface control logic, and interrupt and DMA logic. The wide range of functions integrated onto the W83627EHF greatly reduces the number of components required for interfacing with floppy disk drives. W83627EHF supports four 360K, 720K, 1.2M, 1.44M, or 2.88M disk drives and data transfer rates of 250 Kb/s, 300 Kb/s, 500 Kb/s,1 Mb/s, and 2 Mb/s. W83627EHF provides two high-speed serial communication ports (UARTs), one of which supports serial Infrared communication. Each UART includes a 16-byte send/receive FIFO, a programmable baud rate generator, complete modem control capability, and a processor interrupt system. Both UARTs provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud rates of 230k, 460k, or 921k bps which support higher speed modems. In addition, W83627EHF provides IR functions: IrDA 1.0 (SIR for 1.152K bps) . W83627EHF supports one PC-compatible printer port (SPP), Bi-directional Printer port (BPP) and also Enhanced Parallel Port (EPP) and Extended Capabilities Port (ECP). And W83627EHF contains a Game port and a MIDI port. The game port is designed to support 2 joysticks and can be applied to all standard PC game control devices, they are very important for a entertainment or consumer computer. W83627EHF provides Serial Flash ROM interface. That can support up to 8M bits serial flash ROM. W83627EHF provides flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to provide a predefined alternate function. W83627EHF supports hardware status monitoring for personal computers. It can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stably and properly. Moreover, W83627EHF supports the Smart Fan control system, including the "Thermal CruiseTM" and "Speed CruiseTM" functions. Smart Fan can make system more stable and user friendly. W83627EHF is made to fully comply with Microsoft(c) PC98 and PC99 Hardware Design Guide, and meet the requirements of ACPI. The configuration registers support mode selection, function enable/disable, and power down function selection. Furthermore, the configurable PnP features are compatible with the plug-and-play feature demand of Windows 95/98TM, which makes system resource allocation more efficient than ever. The special characteristic of Super I/O product line is to avoid power rails short. This is especially true to a multi-power system where power partition is much more complex than a single-power one. Special care might be applied during layout stage or the IC will fail even though its intended function is workable. Publication Release Date: Mar 2005 Revision 0.6 -1- W83627EHF/W83627EHG Preliminary 2. FEATURES General * * * * * * * * Meet LPC Spec. 1.01 Support LDRQ#(LPC DMA), SERIRQ (Serial IRQ) Integrated Hardware Monitor functions Compliant with Microsoft PC2000/PC2001 Hardware Design Guide Support DPM (Device Power Management), ACPI Programmable configuration settings Single 24 or 48 MHz clock input It is 3.3V level but 5V tolerance support --- Besides LPC function pins(Pin21 ~ Pin30) and H/W monitor analog pins(Pin95 ~ Pin110) --- Input level can up to 5V and maximum input level can be up to 5V+10% FDC * * * * * * * * * * * * * Compatible with IBM PC AT disk drive systems Variable write pre-compensation with track selectable capability Support vertical recording format DMA enable logic 16-byte data FIFOs Support floppy disk drives and tape drives Detects all overrun and underrun conditions Built-in address mark detection circuit to simplify the read electronics FDD anti-virus functions with software write protect and FDD write enable signal (write data signal was forced to be inactive) Support up to four 3.5-inch or 5.25-inch floppy disk drives Completely compatible with industry standard 82077 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate Support 3-mode FDD, and its Win95/98 driver Publication Release Date: Mar 2005 Revision 0.6 -2- W83627EHF/W83627EHG Preliminary UART * * * Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs MIDI compatible Fully programmable serial-interface characteristics: --- 5, 6, 7 or 8-bit characters --- Even, odd or no parity bit generation/detection --- 1, 1.5 or 2 stop bits generation * Internal diagnostic capabilities: --- Loop-back controls for communications link fault isolation --- Break, parity, overrun, framing error simulation * * Programmable baud rate generator allows division of 1.8461 MHz and 24 MHz by 1 to (216-1) Maximum baud rate up to 921k bps for 14.769 MHz and 1.5M bps for 24 MHz Infrared * * Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps Parallel Port * * * * * Compatible with IBM parallel port Support PS/2 compatible bi-directional parallel port Support Enhanced Parallel Port (EPP) - Compatible with IEEE 1284 specification Support Extended Capabilities Port (ECP) - Compatible with IEEE 1284 specification Enhanced printer port back-drive current protection Game Port * * Support two separate Joysticks Support every Joystick two axis (X, Y) and two button (A, B) controllers MIDI Port * * * The baud rate is 31.25 K baud 16-byte input FIFO 16-byte output FIFO Publication Release Date: Mar 2005 Revision 0.6 -3- W83627EHF/W83627EHG Preliminary Keyboard Controller * 8042 based with optional F/W from AMIKKEYTM-2, Phoenix MultiKey/42TM or customer code with 2K bytes of programmable ROM, and 256 bytes of RAM * * * * * * * * * Asynchronous Access to Two Data Registers and One status Register Software compatibility with the 8042 Support PS/2 mouse Support port 92 Support both interrupt and polling modes Fast Gate A20 and Hardware Keyboard Reset 8 Bit Timer/ Counter Support binary and BCD arithmetic 6 MHz, 8 MHz, 12 MHz, or 16 MHz operating frequency Serial Flash ROM Interface Support up to 8M bits flash ROM General Purpose I/O Ports * * 48 programmable general purpose I/O ports GPIO port 1 and 4 can not only serve as simple I/O ports but also watch dog timer output, Power LED output, Suspend LED output * Functional in power down mode (GP24 ~ GP27, GPIO-3, GPIO-4, GPIO-5) OnNow Functions * * * Keyboard Wake-Up by programmable keys Mouse Wake-Up by programmable buttons On Now Wake-Up from all of the ACPI sleeping states (S1-S5) Publication Release Date: Mar 2005 Revision 0.6 -4- W83627EHF/W83627EHG Preliminary Hardware Monitor Functions Smart Fan control system, support SMART FANTM I - "Thermal CruiseTM" and "Speed CruiseTM" Mode , SMART FANTM III function 3 thermal inputs from optionally remote thermistors or PentiumTM II/III/4 thermal diode output 10 voltage inputs (CPUVCORE, VIN[0..4] and intrinsic 3VCC, AVCC , 3VSB, VBAT) 5 fan speed monitoring inputs 4 fan speed control Dual mode for fan control (PWM & DC) Build in case open detection circuit Programmable hysteresis and setting points for all monitored items Over temperature indicate output Issue SMI#, OVT# to activate system protection Winbond Hardware DoctorTM Support 6 VID inputs / outputs Provide I2C interface to read/write registers Package * 128-pin PQFP Publication Release Date: Mar 2005 Revision 0.6 -5- W83627EHF/W83627EHG Preliminary 3. BLOCK DIAGRAM LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ LPC Interface Joystick interface signals MSI MSO General-purpose I/O pins Hardware monitor channel and Vref Keyboard/Mouse data and clock Game Port FDC Floppy drive interface signals MIDI URA, B Serial port A, B interface signals IRRX GPIO IR IRTX HM PRT Printer port interface signals KBC ACPI Publication Release Date: Mar 2005 Revision 0.6 -6- CPUTIN SYSTIN VID5 VID4 VID3 VID2 VID1 VID0 AUXFANIN0 CPUFANIN0 SYSFANIN AVCC CPUFANOUT0 SYSFANOUT AGND BEEP/SI GP21/CPUFANIN1/MSI GP20/CPUFANOUT1/MSO GP17/GPSA2 GP16/GPSB2 GP15/GPY1 GP14/GPY2 GP13/GPX2 GP12/GPX1 GP11/GPSB1 GP10/GPSA1 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 4. PIN CONFIGURATION FOR W83627EHF W83627EHF -764 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 GP37 KDAT/GP26 KCLK/GP27 3VSB KBRST GA20M SO/AUXFANIN1 RIA#/GP60 DCDA#/GP61 VSS SOUTA/GP62(PENKBC) SINA/GP63 DTRA#/GP64(PENROM) RTSA#/GP65(HEFRAS) DSRA#/GP66 CTSA#/GP67 3VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3 DRVDEN0 GP23/SCK INDEX# MOA# HM_SMI#/OVT# DSA# AUXFANOUT0 DIR# STEP# WD# WE# 3VCC TRAK0# WP# RDATA# HEAD# DSKCHG# IOCLK GP22/SCE# VSS PCICLK LDRQ# SERIRQ LAD3 LAD2 LAD1 LAD0 3VCC LFRAME# LRESET# SLCT PE BUSY ACK# PD7 PD6 PD5 PD4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 AUXTIN VREF CPUVCORE VIN0 VIN1 VIN2 VIN3 VIN4 RSTOUT0# RSTOUT1# GP30 GP31 SCL/GP32/RSTOUT2# SDA/GP33/RSTOUT3# GP34/RSTOUT4# GP35 PME# RIB#/GP40 DCDB#/GP41 SOUTB/IRTX SINB/IRRX DTRB#/GP44 RTSB#/GP45 DSRB#/GP46 CTSB#/GP47 GP50/WDTO#(EN_VRM10) CASEOPEN# RSMRST#/GP51 VBAT SUSB#/GP52 PSON#/GP53 PWROK/GP54 GP55/SUSLED GP36 PSIN/GP56 PSOUT#/GP57 MDAT/GP24 MCLK/GP25 W83627EHF/W83627EHG Publication Release Date: Mar 2005 Revision 0.6 Preliminary W83627EHF/W83627EHG Preliminary 5. PIN DESCRIPTION Note: Please refer to Section 8.2 DC CHARACTERISTICS for details. AOUT AIN INcs INt INtd INts INtsp3 INtu I/O8t I/O12t I/OD12ts I/OD16cs I/OD24t OUT8 OUT12 OUT24 OD8 OD12 OD24 - Analog output pin - Analog input pin - CMOS level Schmitt-triggered input pin - TTL level input pin - TTL level input pin with internal pull down resistor - TTL level Schmitt-triggered input pin - 3.3V TTL level Schmitt-triggered input pin - TTL level input pin with internal pull up resistor - TTL level bi-directional pin with 8 mA source-sink capability -3.3V TTL level bi-directional pin with 12 mA source-sink capability - 3.3V TTL level bi-directional Schmitt-triggered pin. Open-drain output with 12 mA sink capability - CMOS level Schmitt-triggered bi-directional pin. Open-drain output with 16 mA sink capability - TTL level bi-directional pin. Open-drain output with 24 mA sink capability - TTL level output pin with 8 mA source-sink capability -3.3V TTL level output pin with 12 mA source-sink capability - TTL level output pin with 24 mA source-sink capability - Open-drain output pin with 8 mA sink capability - Open-drain output pin with 12 mA sink capability - Open-drain output pin with 24 mA sink capability 5.1 LPC Interface SYMBOL IOCLK PME# PCICLK LDRQ# SERIRQ LAD[3:0] LFRAME# LRESET# PIN 18 86 21 22 23 24-27 29 30 I/O INtp OD12p INtsp O12p I/OD12tp I/O12tp INtsp INtsp FUNCTION System clock input, which is selective by the register according to the input frequency either 24MHz or 48MHz. Default is 48MHz. Generated PME event. PCI clock 33 MHz input. Encoded DMA Request signal. Serial IRQ Input/Output. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral. Indicates start of a new cycle or termination of a broken cycle. Reset signal. It can connect to PCIRST# signal on the host. Publication Release Date: Mar 2005 Revision 0.6 -8- W83627EHF/W83627EHG Preliminary 5.2 FDC Interface SYMBOL DRVDEN0 INDEX# PIN 1 3 I/O OD24 INcsu OD24 OD24 OD24 OD24 OD24 OD24 INcsu FUNCTION Drive Density Select bit 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. This input pin can be pulled up internally by a 1 K(50%). The resistor also can be disabled/enabled by bit 7 of LD0-CRF0(FIPURDWN). Default is disabled. Motor A On. When set to 0, this pin enables disk drive 0. This is an open drain output. Drive Select A. When set to 0, this pin enables disk drive A. This is an open drain output. Direction of the head step motor. An open drain output. Logic 1 = outward motion Logic 0 = inward motion Step output pulses. This active low open drain output produces a pulse to move the head to another track. Write data. This logic low open drain writes pre-compensation serial data to the selected FDD. An open drain output. Write enable. An open drain output. Track 0. This Schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. This input pin can be pulled up internally by a 1 K(50%). The resistor also can be disabled/enabled by bit 7 of LD0-CRF0(FIPURDWN). Default is disabled. Write protected. This active low Schmitt input from the disk drive indicates that the diskette is write-protected. This input pin can be pulled up internally by a 1 K(50%). The resistor also can be disabled/enabled by bit 7 of LD0CRF0(FIPURDWN). Default is disabled. The read data input signal from the FDD. This input pin can be pulled up internally by a 1 K(50%). The resistor also can be disabled/enabled by bit 7 of LD0-CRF0(FIPURDWN). Default is disabled. Head select. This open drain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side 1 Diskette change. This signal is active low at power on and whenever the diskette is removed. This input pin can be pulled up internally by a 1 K(50%) . The resistor also can be disabled/enabled by bit 7 of LD0-CRF0 (FIPURDWN). Default is disabled. MOA# DSA# DIR# STEP# WD# WE# TRAK0# 4 6 8 9 10 11 13 WP# 14 INcsu RDATA# 15 INcsu OD24 HEAD# 16 DSKCHG# 17 INcsu Publication Release Date: Mar 2005 Revision 0.6 -9- W83627EHF/W83627EHG Preliminary 5.3 Multi-Mode Parallel Port SYMBOL PIN I/O FUNCTION PRINTER MODE: An active high input on this pin indicates that the printer is selected. This pin is pulled high internally. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. PRINTER MODE: An active high input on this pin indicates that the printer has detected the end of the paper. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: An active high input indicates that the printer is not ready to receive data. This pin is pulled high internally. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. PRINTER MODE: ACK# An active low input on this pin indicates that the printer has received data and is ready to accept more data. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: ERR# An active low input on this pin indicates that the printer has encountered an error condition. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: SLIN# Output line for detection of printer selection. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: INIT# Output line for the printer initialization. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: AFD# An activtput from this pin causes the printer to auto feed a line after a line is printed. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: STB# An active low output is used to latch the parallel data into the printer. This pin is pulled high internally. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD0 Parallel port data bus bit 0. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. Publication Release Date: Mar 2005 Revision 0.6 - 10 - SLCT 31 INts PE 32 INts BUSY 33 INts ACK# 34 INts ERR# 45 INts OD12 SLIN# 43 /OUT12 INIT# 44 OD12 /OUT12 AFD# 46 OD12 /OUT12 STB# 47 OD12 /OUT12 PD0 42 I/O12ts W83627EHF/W83627EHG Preliminary SYMBOL PD1 PIN 41 I/O I/O12ts I/O12ts I/O12ts I/O12ts I/O12ts I/O12ts I/O12ts FUNCTION PRINTER MODE: PD1 Parallel port data bus bit 1. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD2 Parallel port data bus bit 2. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD3 Parallel port data bus bit 3. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD4 Parallel port data bus bit 4. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD5 Parallel port data bus bit 5. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD6 Parallel port data bus bit 6. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: PD7 Parallel port data bus bit 7. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PD2 40 PD3 39 PD4 38 PD5 37 PD6 36 PD7 35 5.4 Serial Port & Infrared Port Interface SYMBOL CTSA# GP67 CTSB# GP47*** DSRA# GP66 DSRB# 79 50 78 PIN 49 I/O INt I/OD12t INt I/OD12t INt I/OD12t INt FUNCTION Clear To Send. It is the modem control input. The function of these pins can be tested by reading bit 4 of the handshake status register. General purpose I/O port 6 bit 7. Clear To Send. It is the modem control input. The function of these pins can be tested by reading bit 4 of the handshake status register. General purpose I/O port 4 bit 7. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. General purpose I/O port 6 bit 6. Data Set Ready. An active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the UART. Publication Release Date: Mar 2005 Revision 0.6 - 11 - W83627EHF/W83627EHG Preliminary SYMBOL GP46* RTSA# PIN I/O I/OD12t OUT8 FUNCTION General purpose I/O port 4 bit 6. UART A Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. During power-on reset, this pin is pulled down internally(20K 30%) and is defined as HEFRAS, which provides the power-on value for CR26 bit 6 (HEFRAS). A 1 k is reserved to pull down and a 1 k is recommended if intends to pull up. (select 4EH as configuration I/O ports address) General purpose I/O port 6 bit 5. UART B Request To Send. An active low signal informs the modem or data set that the controller is ready to send data. General purpose I/O port 4 bit 5. UART A Data Terminal Ready. An active low signal informs the modem or data set that the controller is ready to communicate. During power-on reset, this pin is pulled down internally(20K 30%)and is defined as PENROM disable, which provides the power-on value for CR24 bit 1 (ENROM). A 1 k is reserved to pull down and a 1 k resistor is recommended if intends to pullup to enable ROM. General purpose I/O port 6 bit 4. UART B Data Terminal Ready. An active low signal informs the modem or data set that controller is ready to communicate. General purpose I/O port 4 bit 4. Serial Input. It is used to receive serial data through the communication link. General purpose I/O port 6 bit 3. Serial Input. It is used to receive serial data through the communication link. IR Receiver input. General purpose I/O port 4 bit 3. UART A Serial Output. It is used to transmit serial data out to the communication link. During power on reset, this pin is pulled down internally(20K 30%)and is defined as PENKBC, which provides the power on value for CR24 bit 2. A 1 k is reserved to pull down and a 1 k is recommended if intends to pull up. General purpose I/O port 6 bit 2. UART B Serial Output. It is used to transmit serial data out to the communication link. IR Transmitter output. General purpose I/O port 4 bit 2. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. Publication Release Date: Mar 2005 Revision 0.6 - 12 - HEFRAS 51 INt GP65 RTSB# GP45*** DTRA# I/O8 OUT8 I/OD8t OUT8 80 52 PENROM GP64 DTRB# GP44* SINA GP63 SINB IRRX GP43*** SOUTA 54 82 53 81 INt I/O8 OUT8 I/OD8t INt I/OD8 INt I/OD12 OUT8 PENKBC GP62 SOUTB IRTX GP42* DCDA# INt I/O8 83 OUT8 I/OD8 56 INt W83627EHF/W83627EHG Preliminary SYMBOL GP61 DCDB# GP41*** RIA# GP60 RIB# GP40* 57 57 85 84 PIN I/O I/OD12 INt I/OD12 INt I/OD12 INt I/OD12 FUNCTION General purpose I/O port 6 bit 1. Data Carrier Detect. An active low signal indicates the modem or data set has detected a data carrier. General purpose I/O port 4 bit 1. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. General purpose I/O port 6 bit 0. Ring Indicator. An active low signal indicates that a ring signal is being received from the modem or data set. General purpose I/O port 4 bit 0. Note. The * sign see 5.10.8 GPIO-1 and GPIO-4 with WDTO# / SUSLED / PLED multi-function 5.5 KBC Interface SYMBOL GA20M KBRST KCLK GP27 KDAT GP26 MCLK GP25 MDAT GP24 PIN 59 60 62 63 65 66 I/O OUT12 OUT12 I/OD16ts I/OD16t I/OD16ts I/OD16t I/OD16ts I/OD16t I/OD16ts I/OD16t FUNCTION Gate A20 output. This pin is high after system reset. (KBC P21) Keyboard reset. This pin is high after system reset. (KBC P20) Keyboard Clock. General purpose I/O port 2 bit 7. Keyboard Data. General purpose I/O port 2 bit 6. PS2 Mouse Clock. General purpose I/O port 2 bit 5. PS2 Mouse Data. General purpose I/O port 2 bit 4. 5.6 Serial Flash Interface SYMBOL SCE# GP22 SCK GP23 SI 118 BEEP SO 58 OD8 INts PIN 19 I/O OUT12 I/OD12t OUT12 I/OD12t OUT8 FUNCTION Serial Flash ROM interface chip select. General purpose I/O port 2 bit 2. Clock output for Serial Flash. (33MHz) General purpose I/O port 2 bit 3. Transfer commands, address or data to Serial Flash. It is connected to SI of Serial Flash. Beep function for hardware monitor. This pin is low after system reset. Receive data from Serial Flash. It is connected to SO of Serial Flash. Publication Release Date: Mar 2005 Revision 0.6 - 13 - 2 W83627EHF/W83627EHG Preliminary AUXFANIN1 I/O12ts 0 to +3V amplitude fan tachometer input. 5.7 Hardware Monitor Interface SYMBOL BEEP 118 SI CASEOPEN# VIN4 VIN3 VIN2 VIN1 VIN0 CPUVCORE VREF AUXTIN CPUTIN SYSTIN OVT# 5 HM_SMI# VID5 VID4 VID3 VID2 VID1 VID0 AUXFANIN1 SO AUXFANIN0 CPUFANIN0 SYSFANIN CPUFANIN1 MSI GP21 105 106 107 108 109 110 58 111 112 113 119 OD12 76 95 96 97 98 99 100 101 102 103 104 OUT8 INt AIN AIN AIN AIN AIN AIN AOUT AIN AIN AIN OD12 PIN I/O OD8 FUNCTION Beep function for hardware monitor. This pin is low after system reset. Transfer commands, address or data to Serial Flash. It is connected to SI of Serial Flash. CASE OPEN. An active low input from an external device when case is opened. This signal can be latched if pin VBAT is connect to battery, even W83627EHF is power off. 0V to 2.048V FSR Analog Inputs. (FSR: Full Scale Register) 0V to 2.048V FSR Analog Inputs. 0V to 2.048V FSR Analog Inputs. 0V to 2.048V FSR Analog Inputs. 0V to 2.048V FSR Analog Inputs. 0V to 2.048V FSR Analog Inputs. Reference Voltage (2.048V) for temperature maturation. Temperature sensor 3 inputs. It is used for temperature maturation. Temperature sensor 2 inputs. It is used for CPU temperature maturation. Temperature sensor 1 input. It is used for system temperature maturation. Over temperature Shutdown Output. It indicated the temperature is over temperature limit. System Management Interrupt channel output. (Default after PCIRST) I/O12 VID input detect, also with output control. I/O12ts INts I/O12ts I/O12ts INcs I/OD12t 0V to +3.3V amplitude fan tachometer input. Receive data from Serial Flash. It is connected to SO of Serial Flash. 0V to +3.3V amplitude fan tachometer input. 0V to +3.3V amplitude fan tachometer input. (Default) MIDI serial data input. General purpose I/O port 2 bit 1. Publication Release Date: Mar 2005 Revision 0.6 - 14 - W83627EHF/W83627EHG Preliminary AUXFANOUT CPUFANOUT0 SYSFANOUT 7 115 116 AOUT/ OUT12 DC/PWM fan output control. CPUFANOUT0 & AUXFANOUT are default PWM Mode, CPUFANOUT1 & SYSFANOUT are default DC Mode. DC/PWM fan output control. CPUFANOUT0 & AUXFANOUT are default PWM Mode, CPUFANOUT1 & SYSFANOUT are default DC Mode. MIDI serial data output. General purpose I/O port 2 bit 0. CPUFANOUT1 MSO GP20 120 AOUT/ OUT12 OUT12 I/OD12t 5.8 Game Port & MIDI Port SYMBOL GPSA1 GP10* GPSB1 GP11** GPX1 126 GP12* GPX2 GP13** GPY2 124 GP14* GPY1 123 GP15** GPSB2 122 GP16* GPSA2 121 I/OD12cs INcs General purpose I/O port 1 bit 6. Active-low, Joystick I switch input 2. This pin has an internal pull-up resistor. (Default) Publication Release Date: Mar 2005 Revision 0.6 - 15 INcs I/OD12cs I/OD12cs I/OD12cs PIN 128 127 I/O INcs I/OD12cs INcs I/OD12cs FUNCTION Active-low, Joystick I switch input 1. (Default) General purpose I/O port 1 bit 0. Active-low, Joystick II switch input 1. (Default) General purpose I/O port 1 bit 1. Joystick II timer pin. this pin connects to X positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 2. Joystick II timer pin. this pin connects to X positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 3. Joystick II timer pin. this pin connects to Y positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 4. Joystick I timer pin. this pin connects to Y positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 5. Active-low, Joystick II switch input 2. This pin has an internal pull-up resistor. (Default) 125 I/OD12cs W83627EHF/W83627EHG Preliminary GP17** MSI CPUFANIN1 GP21 MSO CPUFANOUT1 119 I/OD12cs INcs I/O12ts I/OD12t OUT12 AOUT/ OUT12 I/OD12t General purpose I/O port 1 bit 7. MIDI serial data input. (Default) 0V to +3.3V amplitude fan tachometer input. General purpose I/O port 2 bit 1. MIDI serial data output. (Default) DC/PWM fan output control. CPUFANOUT0 & AUXFANOUT are default PWM Mode, CPUFANOUT1 & SYSFANOUT are default DC Mode. General purpose I/O port 2 bit 0. 120 GP20 Note. The * sign see 5.10.8 GPIO-1 and GPIO-4 with WDTO# / SUSLED / PLED multi-function 5.9 ACPI Interface SYMBOL PSIN GP56 PSOUT# GP57 VBAT RSTOUT0# RSTOUT1# RSTOUT2# GP32 SCL RSTOUT3# GP33 SDA RSTOUT4# GP34 88 89 90 74 94 93 67 PIN 68 I/O INtd I/OD12t OD12 I/OD12t PWR OD12 OUT12 OUT12 I/OD12t INts OUT12 I/OD12t I/OD12ts OUT12 I/OD12t FUNCTION Panel Switch Input. This pin is high active with an internal pull down resistor. General purpose I/O port 5 bit 6. Panel Switch Output. This signal is used for Wake-Up system from S5c o l d state. This pin is pulse output, active low. General purpose I/O port 5 bit 7. +3.3V on-board battery for the digital circuitry. Secondary LRESET# output 0. Secondary LRESET# output 1. Secondary LRESET# output 2. General purpose I/O port 3 bit 2. Serial Bus clock. Secondary LRESET# output 3. General purpose I/O port 3 bit 3. Serial bus bi-directional Data. Secondary LRESET# output 4. General purpose I/O port 3 bit 4. 5.10 General Purpose I/O Port 5.10.1 GPIO Power Source SYMBOL GPIO port 1 POWER SOURCE VCC Publication Release Date: Mar 2005 Revision 0.6 - 16 - W83627EHF/W83627EHG Preliminary GPIO port 2 (Bit0-3) GPIO port 2 (Bit4-7) GPIO port 3 GPIO port 4 GPIO port 5 GPIO port 6 5.10.2 GPIO-1 Interface see 5.8 Game Port VCC VSB VSB VSB VSB VCC 5.10.3 GPIO-2 Interface SYMBOL GP20 CPUFANOUT1 MSO GP21 CPUFANIN1 MSI GP22 SCE# GP23 SCK GP24 MDAT GP25 MCLK GP26 KDAT GP27 KCLK PIN I/O I/OD12t AOUT/ OUT12 OUT12 I/OD12t I/O12ts INcs I/OD12t OUT12 I/OD12t OUT12 I/OD16t I/OD16ts I/OD16t I/OD16ts I/OD16t I/OD16ts I/OD16t I/OD16ts FUNCTION General purpose I/O port 2 bit 0. DC/PWM fan output control. CPUFANOUT0 & AUXFANOUT are default PWM Mode, CPUFANOUT1 & SYSFANOUT are default DC Mode. MIDI serial data output. (Default) General purpose I/O port 2 bit 1. 0V to +3.3V amplitude fan tachometer input. MIDI serial data input. (Default) General purpose I/O port 2 bit 2. Serial Flash ROM interface chip select. General purpose I/O port 2 bit 3. Clock output for Serial Flash. (33MHz) General purpose I/O port 2 bit 4. PS2 Mouse Data. General purpose I/O port 2 bit 5. PS2 Mouse Clock. General purpose I/O port 2 bit 6. Keyboard Data. General purpose I/O port 2 bit 7. Keyboard Clock. 120 119 19 2 66 65 63 62 5.10.4 GPIO-3 Interface SYMBOL GP30 GP31 GP32 RSTOUT2# SCL GP33 RSTOUT3# PIN 92 91 90 89 I/O I/OD12t I/OD12t I/OD12t OUT12 INts I/OD12t OUT12 FUNCTION General purpose I/O port 3 bit 0. General purpose I/O port 3 bit 1 General purpose I/O port 3 bit 2. Secondary LRESET# output 2. Serial Bus clock. General purpose I/O port 3 bit 3. Secondary LRESET# output 3. Publication Release Date: Mar 2005 Revision 0.6 - 17 - W83627EHF/W83627EHG Preliminary SDA GP34 RSTOUT4# GP35 GP36 GP37 88 87 69 64 I/OD12ts I/OD12t OUT12 I/OD12t I/OD12t I/OD12t Serial bus bi-directional Data. General purpose I/O port 3 bit 4. Secondary LRESET# output 4. General purpose I/O port 3 bit 5 General purpose I/O port 3 bit 6 General purpose I/O port 3 bit 7 5.10.5 GPIO-4 Interface see 5.4 Serial Port B 5.10.6 GPIO-5 Interface SYMBOL GP50 EN_VRM10 WDTO# GP51 RSMRST# GP52 SUSB# GP53 PSON# GP54 PWROK GP55 SUSLED GP56 PSIN GP57 PSOUT# 67 PIN I/O I/O12t INcd OUT12 I/OD12t OD12 I/OD12t INt I/OD12t OD12 I/OD12t OD12 I/O12t OUT12 I/OD12t INtd I/OD12t OD12 FUNCTION General purpose I/O port 5 bit 0. During VSB power reset (RSMRST), this pin is pulled down internally and is defined as VID transition voltage level, which provides the value for CR2C bit 3. A 1 k is reserved to pull down and a 1 k is recommended if intends to pull up. Watchdog timer output signal. General purpose I/O port 5 bit 1. Resume reset signal output. General purpose I/O port 5 bit 2. System S3 states input. General purpose I/O port 5 bit 3. This pin generates the PWRCTL# signal while the power failure. General purpose I/O port 5 bit 4. This pin generates the PWROK signal while the VCC come in. General purpose I/O port 5 bit 5. Suspended LED output. General purpose I/O port 5 bit 6. Panel Switch Input. This pin is high active with an internal pull down resistor. General purpose I/O port 5 bit 7. Panel Switch Output. This signal is used for Wake-Up system from S5c o l d state. This pin is pulse output, active low. 77 75 73 72 71 70 68 5.10.7 GPIO-6 Interface see 5.4 Serial Port A 5.10.8 GPIO-1 and GPIO-4 with WDTO# / SUSLED / PLED multi-function Publication Release Date: Mar 2005 Revision 0.6 - 18 - W83627EHF/W83627EHG Preliminary SYMBOL GPxx* WDTO# GPxx** PLED GPxx*** SUSLED PIN ------I/O I/OD12t OD12 I/OD12t OD12 I/OD12t OD12 FUNCTION This GPxx* can be served GPIO or Watchdog timer output signal. This GPxx** can be served GPIO or Power LED output signal. This GPxx*** can be served GPIO or Suspend LED output signal. 5.11 POWER PINS SYMBOL 3VSB VBAT 3VCC AVCC AGND GND PIN 61 74 12,28,48 114 117 20,55 FUNCTION +3.3V stand-by power supply for the digital circuitry. +3V on-board battery for the digital circuitry. +3.3V power supply for driving 3V on host interface. Analog +3.3V power input. Internally supplier to all analog circuitry. Internally connected to all analog circuitry. The ground reference for all analog inputs. Ground. Publication Release Date: Mar 2005 Revision 0.6 - 19 - W83627EHF/W83627EHG Preliminary 6. Hardware monitor 6.1 General Description The W83627EHF can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stable and properly. W83627EHF provides LPC interface to access hardware. An 8-bit analog-to-digital converter (ADC) was built inside W83627EHF. The W83627EHF can simultaneously monitor 6 analog voltage inputs (intrinsic monitor VBAT,3VSB, 3VCC,& AVCC power), 5 fan tachometer inputs, 3 remote temperature, one case-open detection signal. The remote temperature sensing can be performed by thermistors or directly from IntelTM Deschutes CPU thermal diode output. Also the W83627EHF provides: 4 PWM (pulse width modulation) outputs for the fan speed control or 4 DCFAN outputs for the fan speed control; beep tone output for warning; HM_SMI#(through SERIRQ or OVT# pin) , OVT# signals for system protection events. Through the application software or BIOS, the users can read all the monitored parameters of system from time to time. And a pop-up warning can be also activated when the monitored item was out of the proper/preset range. The application software could be Winbond's Hardware DoctorTM or other management application software. Also the users can set up the upper and lower limits (alarm thresholds) of these monitored parameters and to activate one programmable and masked interrupts. An optional beep tone could be used as warning signals when the monitored parameters are out of the preset range. 6.2 Access Interface W83627EHF provides two interface for microprocessor to read/write hardware monitor internal registers. 6.2.1 LPC interface The first interface uses LPC Bus to access which the ports of low byte (bit2~bit0) are defined in the port 5h and 6h. The other higher bits of these ports is set by W83627EHF itself. The general decoded address is set to port 295h and port 296h. These two ports are described as following: Port 295h: Index port. Port 296h: Data port. The register structure is showed as the Figure 6.1 Publication Release Date: Mar 2005 Revision 0.6 - 20 - W83627EHF/W83627EHG Preliminary Smart Fan Configuration Registers 00h-1Fh Configuration Register 40h Interrupt Status Registers 41h, 42h SMI# Mask Registers 43h-44h Fan Divisor Register I 47h Serial Bus Address 48h LPC Bus Monitor Value Registers 20h~3Fh Port 5h BANK 1 CPUTIN Temperature Control/Staus Registers 50h~56h BANK 2 AUXTIN Temperature Control/Staus Registers 50h~56h BANK 4 Interrupt Status & HM_SMI Mask Registers 50h~51h BANK 4 Beep Control Registers 53h Index Register FAN4 Source Select Register 4Ah BANK 4 Temperature Offset Registers 54h~56h Fan Divisor Register I 4Bh HM_SMI#/OVT# Control Register 4Ch Fan IN /OUT Control Register 4Dh Port 6h Data Register Bank Select for 50h~5Fh Registers. 4Eh Winbond Vendor ID 4Fh BANK 4 Read Time Status Registers 59h~5Bh BANK 5 Monitor Value Registers 59h~5Bh BANK 0 BEEP Control Registers 56h~57h BANK 0 Chip ID Register 58h BANK 0 Temperature Sensor Type Configuration & Fan Divisor Bit2 Registers 59h,5Dh Figure 6.1 : LPC interface access diagram 6.2.2 I2C interface Publication Release Date: Mar 2005 Revision 0.6 - 21 - W83627EHF/W83627EHG Preliminary The second interface uses I2C Serial Bus. W83627EHF has a programmable serial bus address. It defined at Index 48h. 6.2.2.1 Serial bus (I C) access timing 2 (a) Serial bus write to internal address register followed by the data byte 0 SCL SDA Start By Master 7 8 0 7 8 0 1 0 1 1 0 1 R/W Ack by 627EHF D7 D6 D5 D4 D3 D2 D1 D0 Ack by 627EHF Frame 1 Serial Bus Address Byte 0 Frame 2 Internal Index Register Byte 7 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0 8 Ack Ack by by 784R 627EHF Stop by Master Frame 3 Data Byte Figure 1. Serial Bus Write to Internal Address Register followed by the Data Byte (b) Serial bus read from a register 0 SCL SDA Start By Master 7 8 0 7 8 0 1 0 1 1 0 1 R/W Ack by 627EHF D7 D6 D5 D4 D3 D2 D1 D0 Ack by 627EHF Frame 1 Serial Bus Address Byte 0 Frame 2 Internal Index Register Byte 0 7 8 0 7 8 0 Repeat start by Master 1 0 1 1 0 1 R/W Ack by 627EHF D7 D6 D5 D4 D3 D2 D1 D0 Ack by Master Stop by Master Frame 3 Serial Bus Address Byte 0 Frame 4 Data Byte Figure 2. Serial Bus Read from Internal Address Register 6.3 Analog Inputs The maximum input voltage of the analog pin is 2.048V because the 8-bit ADC has a 8mV LSB. Really, the application of the PC monitoring would most often be connected to power suppliers. The CPU Vcore voltage , battery(pin 74), 3VSB(pin 61), 3VCC(pin 12) , AVCC(pin 114) voltage can directly connected to these analog inputs. The +12V voltage inputs should be reduced a factor with external resistors so as to obtain the input range. As Figure 6.2 shows. Publication Release Date: Mar 2005 Revision 0.6 - 22 - W83627EHF/W83627EHG Preliminary AVCC Power Inputs VBAT VSB 3VCC CPUVCORE Pin 114 Pin 74 Pin 61 Pin 12 Pin 64 V0 R1 R2 VIN0 Pin 99 Positive Voltage Input VIN2 VIN3 VIN4 R3 Negative Voltage Input V1 Pin 97 Pin 96 Pin 95 8-bit ADC with 8mV LSB VIN1 Pin 98 R4 THM 10K@25 C, beta=3435K R R 10K, 1% VREF R 15K, 1% AUXTIN CPUTIN SYSTIN CPUD+ CAP,2200p CPUDAGND Pin 117 Pin 102 Pin 103 Pin 104 Pin 101 Figure 6.2 6.3.1 Monitor over 2.048V voltage The +12V input voltage can be expressed as following equation. VIN 0 = V 0 x R2 R1 + R2 The value of R1 and R2 can be selected to 56K Ohms and 10K Ohms, respectively, when the input voltage V0 is 12V. The node voltage of VIN0 can be subject to less than 2.048V for the maximum input range of the 8-bit ADC. The -12V input voltage can be expressed as following equation. VIN1 = (V 1 - 2.048) x R4 + 2.048, whereV 1 = -12 R3 + R 4 The value of R3 and R4 can be selected to 232K Ohms and 10K Ohms, respectively, when the input voltage V1 is -12V. The node voltage of VIN1 can be subject to less than 2.048V for the maximum input range of the 8-bit ADC. Both of pin 12 and pin 114 are connected to the power supply VCC with +3.3V. There are two functions in these 2 pins with 3.3V. The first function is to supply internal (digital/analog) power in the W83627EHF and Publication Release Date: Mar 2005 Revision 0.6 - 23 - W83627EHF/W83627EHG Preliminary the second function is that this voltage with 3.3V is connected to internal serial resistors to monitor the +3.3V voltage. The W83627EHF internal two serial resistors are 34 K and 34 K so that input voltage to ADC is 1.65V which is less than 2.048V of ADC maximum input voltage. The express equation can represent as follows. Vin = VCC x 34 K 1.65V , where VCC is set to 3.3V. 34 K + 34 K The Pin 61 is connected to 3.3 VSB voltage. W83627EHF monitors this voltage and the internal two serial resistors are 34 K and 34 K so that input voltage to ADC is 1.65V which less than 2.048V of ADC maximum input voltage. 6.3.2 CPUVCORE voltage detection method W83627EHF provides one detection methods for CPUVCORE(pin 100). The LSB of this mode is 8mV. This means that the detected voltage equals to the reading of this voltage register multiplies 8mV. The formula is as the following: Detected Voltage = Reading 0.008 V 6.3.3 Temperature Measurement Machine The temperature data format is 8-bit two's-complement for sensor SYSTIN and 9-bit two's-complement for sensor CPUTIN and AUXTIN. The 8-bit temperature data can be obtained by reading the CR[27h]. The 9-bit temperature data can be obtained by reading the 8 MSBs from the Bank1/Bank2 CR[50h] and the LSB from the Bank1/Bank2 CR[51h] bit 7. The format of the temperature data is show in Table 6.1. Temperature +125C +25C +1C +0.5C +0C -0.5C -1C -25C -55C 8-Bit Digital Output 8-Bit Binary 0111,1101 0001,1001 0000,0001 0000,0000 1111,1111 1110,0111 1100,1001 8-Bit Hex 7Dh 19h 01h 00h FFh E7h C9h Table 6.1 9-Bit Digital Output 9-Bit Binary 0,1111,1010 0,0011,0010 0,0000,0010 0,0000,0001 0,0000,0000 1,1111,1111 1,1111,1110 1,1100,1110 1,1001,0010 9-Bit Hex 0FAh 032h 002h 001h 000h 1FFh 1FFh 1CEh 192h 7.3.3.1 Monitor temperature from thermistor The W83627EHF can connect three thermistors to measure three different environment temperature. The specification of thermistor should be considered to (1) value is 3435K, (2) resistor value is 10K ohms at 25C. In the Figure 6.2, the themistor is connected by a serial resistor with 10K Ohms, then connect to VREF (pin 101). Publication Release Date: Mar 2005 Revision 0.6 - 24 - W83627EHF/W83627EHG Preliminary 7.3.3.2 Monitor temperature from Pentium II /Pentium III TM TM thermal diode The W83627EHF can alternate the thermistor to Pentium IITM/Pentium IIITM thermal diode and the circuit connection is shown as Figure 6.3. The pin of Pentium IITM/ Pentium IIITM D- is connected to AGND(pin 117) and the pin D+ is connected to temperature sensor pin in the W83627EHF. The resistor R=15K ohms should be connected to VREF to supply the diode bias current and the bypass capacitor C=3300pF should be added to filter the high frequency noise. VREF R=15K,1% W83627EHF Pentium II/III/IV CPU Therminal Diode D+ C=2200pF D- CPUTIN AGND AGND Figure 6.3 6.4 FAN Speed Count and FAN Speed Control 6.4.1 Fan speed count Inputs are provides for signals from fans equipped with tachometer outputs. The level of these signals should be set to TTL level, and maximum input voltage can not be over +3.3V. If the input signals from the tachometer outputs are over the +3.3V, the external trimming circuit should be added to reduce the voltage to obtain the input specification. The normal circuit and trimming circuits are shown as Figure 6.4. Determine the fan counter according to: Count = 1.35 x 10 6 RPM x Divisor 1.35 x 10 6 Count x Divisor In other words, the fan speed counter has been read from register Bank0 Index 28h, 29h, 2Ah ,3Fh and Bank5 53h, the fan speed can be evaluated by the following equation. RPM = The default divisor is 2 and defined at Bank0 Index 47h.bit7~4, Index 4Bh.bit7~6, Index 4Ch.bit7, Index 59h.bit7.bit3~2 and Index 5Dh.bit5~7 which are three bits for divisor. That provides very low speed fan counter such as power supply fan. The followed table is an example for the relation of divisor, RPM, and count. Publication Release Date: Mar 2005 Revision 0.6 - 25 - W83627EHF/W83627EHG Preliminary Divisor 1 2 (default) 4 8 16 32 64 128 Nominal RPM 8800 4400 2200 1100 550 275 137 68 Time per Revolution 6.82 ms 13.64 ms 27.27 ms 54.54 ms 109.08 ms 218.16 ms 436.32 ms 872.64 ms Counts 153 153 153 153 153 153 153 153 Table 6.2 70% RPM 6160 3080 1540 770 385 192 96 48 Time for 70% 9.84 ms 19.48 ms 38.96 ms 77.92 ms 155.84 ms 311.68 ms 623.36 ms 1246.72 ms Publication Release Date: Mar 2005 Revision 0.6 - 26 - W83627EHF/W83627EHG Preliminary 6.4.2 Fan speed control W83627EHF provides two controllable methods for Fan speed control. One is PWM duty cycle output and the other is DC voltage output. Either PWM or DC output can be programmed at Bank0 Index 04h.bit1~0 , Index 12h.bit0 and Index 62h.bit6. 6.4.2.1 PWM Duty Cycle Output The W83627EHF provides maximum 4 sets for fan PWM speed control. The duty cycle of PWM can be programmed by a 8-bit registers which are defined in the Bank0 Index 01h, Index 03h, Index 11h and Index 61h. The default duty cycle is set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be represented as follows. Dutycycle(%) = Programmed 8 - bit Register Value x 100% 255 The PWM clock frequency also can be program and defined in the Bank0 Index 00h, Index 02h, Index 10h and Index 60h. 6.4.2.2 DC Voltage Output The W83627EHF has a 6 bit DAC which produces 0 to 3.3 volts DC output that provides maximum 4 sets for fan speed control. The analog output can be programmed in the Bank0 Index 01h, Index 03h, Index 11h and Index 61h. The default value is 111111YY,YY is reserved 2 bits, that is default output value is nearly 3.3 V. The expression of output voltage can be represented as follow , Output Voltage (V) = 3VCC x Programmed 6 - bit Register Value 64 6.5 Smart Fan Control SMART FANTM I Smart Fan Control provides two mechanisms. One is Thermal Cruise mode and the other is Fan Speed Cruise mode. When enable Smart Fan, the Fan output will start from previous setting of Bank0 Index 01h, Index 03h, Index 11h and Index 61h to increase or decrease. 6.5.1 Thermal Cruise mode There are maximum 4 pairs of Temperature/Fan output control at this mode: SYSTIN with SYSFANOUT, CPUTIN with CPUFANOUT0, AUXTIN with AUXFANOUT and CPUFANOUT1 depends on Bank0 Index 4Ah.bit7~6 setting that is temperature source selection. W83627EHF provides the Smart Fan system which can control the fan speed automatically depend on current temperature to keep it with in a specific range. At first a wanted temperature and interval must be set (ex. 55 C 3 C) by BIOS, as long as the real temperature remains below the setting value, the fan will be off. Once the temperature exceeds the setting high limit temperature ( 58C), the fan will be turned on with a specific speed set by BIOS (ex: 20% output) and automatically controlled its output with the temperature varying. Three conditions may occur : Publication Release Date: Mar 2005 Revision 0.6 - 27 - W83627EHF/W83627EHG Preliminary (1) If the temperature still exceeds the high limit (ex: 58C), Fan output will increase slowly. If the fan has been operating in its fully speed but the temperature still exceeds the high limit(ex: 58C), a warning message will be issued to protect the system. (2) If the temperature goes below the high limit (ex: 58C), but above the low limit (ex: 52C), the fan speed will be fixed at the current speed because the temperature is in the target area(ex: 52 C ~ 58C). (3) If the temperature goes below the low limit (ex: 52C), Fan output will decrease slowly to 0 until the temperature exceeds the low limit. In other words, If "current temperature" > "High Limit", increase fan speed; If "current temperature" < "Low Limit", decrease fan speed; Otherwise, keep the fan speed. Figure 6.6 and 6.7 give the illustration for Thermal Cruise Mode . A Tolerance Target Temperature Tolerance B C D 58C 55C 52C (%) 100 50 0 Fan Start = 20% Fan output Figure 6.6 A Tolerance Target Temperature Tolerance B C D 58C 55C 52C (%) 100 Fan Start = 20% 50 0 Figure 6.7 Publication Release Date: Mar 2005 Revision 0.6 - 28 Fan Start = 20% Fan Stop = 10% Fan output W83627EHF/W83627EHG Preliminary One more protection is provided that Fan output will not be decreased to 0 in the above (3) situation in order to keep the fans running with a minimum speed. By setting Bank0 Index12h.bit3~5 to 1, Fan output will be decreased to the "Stop Output Value" which are defined at Bank0 Index08h, Index09h and Index17h. 6.5.2 Fan Speed Cruise mode There are 4 pairs of Fan input/Fan output control at this mode: SYSFANIN with SYSFANOUT, CPUFANIN0 with CPUFANOUT0, AUXFANIN with AUXFANOUT and CPUFANIN1 with CPUFANOUT1. At this mode, W83627EHF provides the Smart Fan system which can control the fan speed automatically depend on current fan speed to keep it with in a specific range. A wanted fan speed count and interval must be set (ex. 160 10 ) by BIOS. As long as the fan speed count is the specific range, Fan output will keep the current value. If current fan speed count is higher than the high limit (ex. 160+10), Fan output will be increased to keep the count less than the high limit. Otherwise, if current fan speed is less than the low limit(ex. 160-10), Fan output will be decreased to keep the count higher than the low limit. See Figure 6.8 example. Count 170 160 150 (%) 100 50 0 A C Fan output Figure 6.8 6.5.3 Manual Control Mode Smart Fan control system can be disabled and the fan speed control algorithm can be programmed by BIOS or application software. The programming method is just as section 6.4.2. SMART FANTM III SMART FANTM III mode sets a target temperature through BIOS or application software and W83627EHF controls the fan speed so that the temperature could meet the target temperature set in the BIOS or software. Only Pin115 (CPUFANOUT0) and Pin120 (CPUFANOUT1) in W83627EHF support SMART FANTM III. Pin115 (CPUFANOUT0) pairs with Pin103 (CPUTIN); while Pin120 (CPUFANOUT1) pairs with Pin104 (SYSTIN), Pin103 (CPUTIN), or Pin102 (AUXTIN), which is defined in Bank0 Index 4Ah.bit7~6. Figure 6.9, 6.10, and 6.11 illustrate SMART FANTM III mode, and the algorithm of fan speed control is described as follows: (1) Figure 6.9 shows the initial condition of SMART FANTM III. Target Temperature, Temperature Publication Release Date: Mar 2005 Revision 0.6 - 29 - W83627EHF/W83627EHG Preliminary Tolerance, Maximum Fan Output and Minimum Fan Output must be set first. If the currently measured temperature is within the (Target Temperature Temperature Tolerance), the fan speed remains constant. In the case that currently measured temperature goes beyond (Target Temperature Temperature Tolerance), which is shown in Figure 6.10, fan speed jumps up to the next step. "Step" here refers to the value in the CPUFANOUT Output Value Select Register, Bank0 Index03h or Index61h. Meanwhile, original Target Temperature dynamically shifts to (Target Temperature Temperature Tolerance), and new Target Temperature, named Target Temperature 1, is formed. In other words, Target Temperature 1 equals original Target Temperature plus Temperature Tolerance. If the currently measured temperature is within the (Target Temperature 1 Temperature Tolerance) then, the fan speed remains constant. Otherwise, fan speed jumps up to the next step again. Target Temperature then dynamically shifts to (Target Temperature 1 Temperature Tolerance), and new Target Temperature again, named Target Temperature 2, is formed. The fan-speed-up and Target Temperature comparison-then-shift process continue until currently measured temperature locates within (Target Temperature X Temperature Tolerance), or fan output speed reaches its maximum speed. Please be noted that "Speed-up Slope" shown in the Figure 6.10 must be an integer. In other words, Max.FanOutput - InitialOutput must be an integer; otherwise, it may lead to register overflow. Steps (2) (3) (4) (5) (6) (7) In the case that currently measured temperature goes below (Target Temperature Temperature Tolerance), which is shown in Figure 6.11, fan speed slows down by one step. "Step" here refers to the value in the CPUFANOUT Output Value Select Register, Bank0 Index03h or Index61h. (8) Meanwhile, original Target Temperature dynamically shifts to (Target Temperature Temperature Tolerance), and new Target Temperature, named Target Temperature 1, is formed. In other words, Target Temperature 1 equals original Target Temperature minus Temperature Tolerance. (9) If the currently measured temperature is within the (Target Temperature 1 Temperature Tolerance) then, the fan speed remains constant. Otherwise, fan speed slows down by one step again. Target Temperature then dynamically shifts to (Target Temperature 1 Temperature Tolerance), and new Target Temperature again, named Target Temperature 2, is formed. (10) The fan-slow-down and Target Temperature comparison-then-shift process continue until currently measured temperature locates within (Target Temperature X Temperature Tolerance), or fan output speed hits its minimum speed. (11) Please be noted that "Speed-down Slope" shown in the Figure 6.11 must be an integer. In other words, InitialOutput - Min.FanOutput must be an integer; otherwise, it may lead to register overflow. Step (12) In the case that the temperature is always lower than (Target Temperature X Temperature Tolerance), and, for some reason, the fan speed would like to be kept at the minimum speed, Stop Value, instead of being stopped, set register Bank0 12h.bit 4. Set bit 4 to 1, fan speed will always keep at the value set in Bank0 Index09h when temperature is always below (Target Temperature X Temperature Tolerance). Set bit 4 to 0, fan speed will decrease to 0 after a time period set in Bank0 Index0Dh. Publication Release Date: Mar 2005 Revision 0.6 - 30 - W83627EHF/W83627EHG Preliminary Setting Fan output (DC / PWM) Max. Fan Output Tolerance Min. Fan Output Tar. - Tol. Tar. + Tol. Temperature Figure 6.9 Current Temp. > Target Temp. + Tol. Fan output (DC / PWM) Max. Fan Output Tolerance Step Fan Initial Output Value Speed-up Slope Min. Fan Output = Step = Integer (Max. Fan output - Initial output) Tar Tar 1 Tar 3 Tar 2 Tar 4 Tar 5 Temperature Figure 6.10 Publication Release Date: Mar 2005 Revision 0.6 - 31 - W83627EHF/W83627EHG Preliminary Current Temp. < Target Temp. - Tol. Fan output (DC / PWM) Max. Fan Output Tolerance Fan Initial Output Value Step = Speed-down Slope (Initial Value - Min. Fan output) Step = Integer Min. Fan Output Tar 3 Tar 2 Tar 1 Tar Temperature Figure 6.11 Publication Release Date: Mar 2005 Revision 0.6 - 32 - W83627EHF/W83627EHG Preliminary 6.6 SMI# interrupt mode The HM_SMI#/OVT# pin is a multi-function pin. The function is selected at Configuration Register CR[29h] bit 6. 6.6.1 Voltage SMI# mode SMI# interrupt for voltage is Two-Times Interrupt Mode. Voltage exceeding high limit or going below low limit will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. (Figure 6.12 ) 6.6.2 Fan SMI# mode SMI# interrupt for fan is Two-Times Interrupt Mode. Fan count exceeding the limit, or exceeding and then going below the limit, will causes an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. (Figure 6.13 ) High limit Low limit Fan Count limit SMI# * * * * SMI# * * *Interrupt Reset when Interrupt Status Registers are read Figure 6.12 Figure 6.13 Publication Release Date: Mar 2005 Revision 0.6 - 33 - W83627EHF/W83627EHG Preliminary 6.6.3 Temperature SMI# mode 6.6.3.1 Temperature sensor 1(SYSTIN) SMI# interrupt has 3 modes (1) Comparator Interrupt Mode Setting the THYST (Temperature Hysteresis) limit to 127C will set temperature sensor 1 SMI# to the Comparator Interrupt Mode. Temperature exceeds TO (Over Temperature) Limit causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the TO , the interrupt will occur again when the next conversion has completed. If an interrupt event has occurred by exceeding TO and not reset, the interrupts will not occur again. The interrupts will continue to occur in this manner until the temperature goes below TO. (Figure 6.14 ) Setting the THYST lower than TO will set temperature sensor 1 SMI# to the Interrupt Mode. The following are two kinds of interrupt modes, which are selected by Bank0 Index 4Ch bit5 : (2) Two-Times Interrupt Mode Temperature exceeding TO causes an interrupt and then temperature going below THYST will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO , then reset, if the temperature remains above the THYST , the interrupt will not occur. (Figure 6.15 ) (3) One-Time Interrupt Mode Temperature exceeding TO causes an interrupt and then temperature going below THYST will not cause an interrupt. Once an interrupt event has occurred by exceeding TO , then going below THYST, an interrupt will not occur again until the temperature exceeding TO. (Figure 6.16 ) T HYST 127'C T OI T OI T HYST SMI# * * * * SMI# * * * *Interrupt Reset when Interrupt Status Registers are read Figure 6.14 Figure 6.15 Publication Release Date: Mar 2005 Revision 0.6 - 34 - W83627EHF/W83627EHG Preliminary T OI T HYST SMI# * * *Interrupt Reset when Interrupt Status Registers are read Figure 6.16 Publication Release Date: Mar 2005 Revision 0.6 - 35 - W83627EHF/W83627EHG Preliminary 6.6.3.2 Temperature sensor 2(CPUTIN) and sensor 3(AUXTIN) SMI# interrupt has two modes It is programmed at Bank0 Index 4Ch.bit 6. (1) Comparator Interrupt Mode Temperature exceeding TO causes an interrupt and this interrupt will be reset by reading all the Interrupt Status Register. Once an interrupt event has occurred by exceeding TO, then reset, if the temperature remains above the THYST, the interrupt will occur again when the next conversion has completed. If an interrupt event has occurred by exceeding TO and not reset, the interrupts will not occur again. The interrupts will continue to occur in this manner until the temperature goes below THYST. ( Figure 6.17 ) (2) Two-Times Interrupt Mode Temperature exceeding TO causes an interrupt and then temperature going below THYST will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt Status Register. Once an interrupt event has occurred by exceeding TO , then reset, if the temperature remains above the THYST , the interrupt will not occur. (Figure 6.18 ) T OI T OI T HYST T HYST SMI# * * * * * SMI# * * * *Interrupt Reset when Interrupt Status Registers are read Figure 6.17 Figure 6.18 Publication Release Date: Mar 2005 Revision 0.6 - 36 - W83627EHF/W83627EHG Preliminary 6.7 OVT# interrupt mode The HM_SMI#/OVT# pin (pin 5) is a multi-function pin. The function is selected at Configuration Register CR[29h] bit 6. The OVT# mode selection bits are at Bank0 Index18h bit4, Bank1 Index 52h bit1 and Bank2 Index 52h bit1. (1) Comparator Mode : Temperature exceeding TO causes the OVT# output activated until the temperature is less than THYST. ( Figure 6.19) (2) Interrupt Mode: Temperature exceeding TO causes the OVT# output activated indefinitely until reset by reading temperature sensor registers. Temperature exceeding TO , then OVT# reset, and then temperature going below THYST will also cause the OVT# activated indefinitely until reset by reading temperature sensor registers. Once the OVT# is activated by exceeding TO , then reset, if the temperature remains above THYST , the OVT# will not be activated again.( Figure 6.19) To T HYST OVT# (Comparator Mode; default) OVT# (Interrupt Mode) * * * *Interrupt Reset when Temperature sensor registers are read Figure 6.19 Publication Release Date: Mar 2005 Revision 0.6 - 37 - W83627EHF/W83627EHG Preliminary 6.8 REGISTERS AND RAM Address Port and Data Port are set in the register CR60 and CR61 of Device B which is Hardware Monitor Device. The value in CR60 is high byte and that in CR61 is low byte. For example, setting CR60 to 02 and CR61 to 90 causes the Address Port to be 0x295 and Data Port to be 0x296. 6.8.1 Address Port (Port x5h) Address Port: Power on Default Value Attribute: Size: Port x5h 00h Bit 6:0 Read/write , Bit 7: Reserved 8 bits 7 6 5 4 3 2 1 0 Data Bit7: Reserved Bit 6-0: Read/Write Bit 7 Reserved (Power On default 0) Bit 6 A6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Address Pointer (Power On default 00h) A5 A4 A3 A2 A1 Bit 0 A0 6.8.2 Data Port (Port x6h) Data Port: Power on Default Value Attribute: Size: Port x6h 00h Read/write 8 bits 7 6 5 4 3 2 1 0 Data Bit 7-0: Data to be read from or to be written to RAM and Register. Publication Release Date: Mar 2005 Revision 0.6 - 38 - W83627EHF/W83627EHG Preliminary 6.8.3 SYSFANOUT PWM Output Frequency Configuration Register - Index 00h (Bank 0) Register Location: 00h Power on Default Value: 04h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 PWM_SCALE1 PWM_CLK_SEL1 The register is meaningful when SYSFANOUT be programmed as PWM output. Bit 7: SYSFANOUT PWM Input Clock Source Select. This bit selects the clock source of PWM output frequency. Set to 0, select 24 MHz. Set to 1, select 180 KHz. Bit 6-0: SYSFANOUT PWM Pre-Scale divider. This is the divider of clock source of PWM output frequency. The maximum divider is 128 (7Fh). This divider should not be set to 0. 01h : divider is 1 02h : divider is 2 03h : divider is 3 : : the formula is PWM output frequency = Input Clock 1 Pre_Scale Divider 256 Publication Release Date: Mar 2005 Revision 0.6 - 39 - W83627EHF/W83627EHG Preliminary 6.8.4 SYSFANOUT Output Value Select Register - Index 01h (Bank 0) Register Location: 01h Power on Default Value: FFh Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 SYSFANOUT Value (1)If SYSFANOUT be programmed as PWM output (Bank0 Index 04h.bit0 is 0) Bit 7-0: SYSFANOUT PWM Duty Cycle. Write FFh, SYSFANOUT is always logical High which means duty cycle is 100%. Write 00h, SYSFANOUT is always logical Low which means duty cycle is 0%. Note. XXh: PWM Duty Cycle output percentage is (XX/256*100%) during one cycle. (2)If SYSFANOUT be programmed as DC Voltage output (Bank0 Index 04h.bit0 is 1) Bit 7-2: SYSFANOUT voltage control. Bit 1-0: Reserved. OUTPUT Voltage = AVCC * FANOUT 64 BIT 7 0 0 0 0 0 0 BIT 6 0 0 0 0 0 0 BIT 5 0 0 0 0 0 0 BIT 4 0 0 0 0 1 1 BIT 3 0 0 1 1 0 0 If AVCC= 3.3V , output voltage table is OUTPUT BIT 7 BIT 6 BIT 5 BIT 4 BIT 2 VOLTAGE 0 0 1 0 0 0 1 0 1 0 1 0.05 0.10 0.15 0.21 0.26 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 BIT 3 0 0 1 1 0 0 BIT 2 0 1 0 1 0 1 OUTPUT VOLTAGE 1.65 1.70 1.75 1.80 1.86 1.91 Publication Release Date: Mar 2005 Revision 0.6 - 40 - W83627EHF/W83627EHG Preliminary 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0.31 0.36 0.41 0.46 0.52 0.57 0.62 0.67 0.72 0.77 0.83 0.88 0.93 0.98 1.03 1.08 1.13 1.19 1.24 1.29 1.34 1.39 1.44 1.50 1.55 1.60 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.96 2.01 2.06 2.11 2.17 2.22 2.27 2.32 2.37 2.42 2.48 2.53 2.58 2.63 2.68 2.73 2.78 2.84 2.89 2.94 2.99 3.04 3.09 3.15 3.20 3.25 Table 6.4 . Publication Release Date: Mar 2005 Revision 0.6 - 41 - W83627EHF/W83627EHG Preliminary 6.8.5 CPUFANOUT0 PWM Output Frequency Configuration Register - Index 02h (Bank 0) Register Location: 02h Power on Default Value: 04h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 PWM_SCALE2 PWM_CLK_SEL2 The register is meaningful when CPUFANOUT0 be programmed as PWM output. Bit 7: CPUFANOUT0 PWM Input Clock Source Select. This bit selects the clock source of PWM output frequency. Set to 0, select 24 MHz. Set to 1, select 180 KHz. Bit 6-0: CPUFANOUT0 PWM Pre-Scale divider. This is the divider of clock source of PWM output frequency. The maximum divider is 128 (7Fh). This divider should not be set to 0. 01h : divider is 1 02h : divider is 2 03h : divider is 3 : : the formula is PWM output frequency = Input Clock 1 Pre_Scale Divider 256 6.8.6 CPUFANOUT0 Output Value Select Register - Index 03h (Bank 0) Register Location: 03h Power on Default Value: FFh Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 CPUFANOUT0 Value Publication Release Date: Mar 2005 Revision 0.6 - 42 - W83627EHF/W83627EHG Preliminary (1)If CPUFANOUT0 be programmed as PWM output (Bank0 Index 04h.bit1 is 0) Bit 7-0: CPUFANOUT0 PWM Duty Cycle. Write FFh, CPUFANOUT0 duty cycle is 100%. Write 00h, CPUFANOUT duty cycle is 0%. Note. XXh: PWM Duty Cycle output percentage is (XX/256*100%) during one cycle. (2)If CPUFANOUT0 be programmed as DC Voltage output (Bank0 Index 04h.bit1 is 1) Bit 7-2: CPUFANOUT0 voltage control. Bit 1-0: Reserved. OUTPUT Voltage = AVCC * Note. See the Table 6.4 FANOUT 64 6.8.7 FAN Configuration Register I - Index 04h (Bank 0) Register Location: 04h Power on Default Value: 01h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 SYSFANOUT_SEL CPUFANOUT0_SEL SYSFANOUT_Mode SYSFANOUT_Mode CPUFANOUT0_Mode CPUFANOUT0_Mode Reserved Reserved Bit 7-6: Reserved Bit 5-4: CPUFANOUT0 mode control. Set 00, CPUFANOUT0 is as Manual Mode. (Default). Set 01, CPUFANOUT0 is as Thermal Cruise Mode. Set 10, CPUFANOUT0 is as Fan Speed Cruise Mode. Set 11, reserved and no function. Bit 3-2: SYSFANOUT mode control. Set 00, SYSFANOUT is as Manual Mode. (Default). Set 01, SYSFANOUT is as Thermal Cruise Mode. Set 10, SYSFANOUT is as Fan Speed Cruise Mode. Set 11, CPUFANOUT0 is SMART FANTM III Mode. Bit 1: CPUFANOUT0 output mode selection. Set to 0, CPUFANOUT0 pin is as PWM output duty cycle so that it can drive a logical high or low signal. Set to 1, CPUFANOUT0 pin is as DC voltage output which can provide analog voltage output . (Default 0) Publication Release Date: Mar 2005 Revision 0.6 - 43 - W83627EHF/W83627EHG Preliminary Bit 0: SYSFANOUT output mode selection. Set to 0, SYSFANOUT pin is as PWM duty cycle output so that it can drive a logical high or low signal. Set to 1, SYSFANOUT pin is as DC voltage output which can provide analog voltage output . (Default 1) 6.8.8 SYSTIN Target Temperature Register/ SYSFANIN Target Speed Register - Index 05h (Bank 0) Register Location: 05h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 Target Temperature / Target Speed (1)When at Thermal Cruise mode: Bit 7: Reserved. Bit 6-0: SYSTIN Target Temperature. (2)When at Fan Speed Cruise mode: Bit 7-0: SYSFANIN Target Speed. 6.8.9 CPUTIN Target Temperature Register/ CPUFANIN0 Target Speed Register - Index 06h (Bank 0) Register Location: 06h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 Target Temperature / Target Speed (1)When at Thermal Cruise mode or SMARTFAN III mode: Bit 7: Reserved. Bit 6-0: CPUTIN Target Temperature. (2)When at Fan Speed Cruise mode: Bit 7-0: CPUFANIN0 Target Speed. Publication Release Date: Mar 2005 Revision 0.6 - 44 - W83627EHF/W83627EHG Preliminary 6.8.10 Tolerance of Target Temperature or Target Speed Register - Index 07h (Bank 0) Register Location: 07h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 SYSTIN Target Temperature Tolerance / SYSFANIN Target Speed Tolerance CPUTIN Target Temperature Tolerance / CPUFANIN0 Target Speed Tolerance (1)When at Thermal Cruise mode or SMARTFAN III mode: Bit 7-4: Tolerance of CPUTIN Target Temperature. Bit 3-0: Tolerance of SYSTIN Target Temperature. (2)When at Fan Speed Cruise mode: Bit 7-4: Tolerance of CPUFANIN0 Target Speed. Bit 3-0: Tolerance of SYSFANIN Target Speed. 6.8.11 SYSFANOUT Stop Value Register - Index 08h (Bank 0) Register Location: 08h Power on Default Value: 01h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 SYSFANOUT Stop Value When at Thermal Cruise mode, SYSFANOUT value will decrease to this value. This register should be written a non-zero minimum stop value. Please note that Stop Value does not mean that fan really stops. It means that if the temperature keeps below low temperature limit, then the fan speed keeps on decreasing until reaching a minimam value, and this is Stop Value. 6.8.12 CPUFANOUT0 Stop Value Register - Index 09h (Bank 0) Register Location: 09h Power on Default Value: 01h Attribute: Read/Write Size: 8 bits Publication Release Date: Mar 2005 Revision 0.6 - 45 - W83627EHF/W83627EHG Preliminary 7 6 5 4 3 2 1 0 CPUFANOUT0 Stop Value When at Thermal Cruise mode or SMARTFAN III mode, CPUFANOUT0 value will decrease to this value. This register should be written a non-zero minimum stop value. Please note that Stop Value does not mean that fan really stops. It means that if the temperature keeps below low temperature limit, then the fan speed keeps on decreasing until reaching a minimam value, and this is Stop Value. 6.8.13 SYSFANOUT Start-up Value Register - Index 0Ah (Bank 0) Register Location: 0Ah Power on Default Value: 01h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 SYSFANOUT Start-up Value When at Thermal Cruise mode, SYSFANOUT value will increase from 0 to this register value to provide a minimum value to turn on the fan. 6.8.14 CPUFANOUT0 Start-up Value Register - Index 0Bh (Bank 0) Register Location: 0Bh Power on Default Value: 01h Attribute: Read/Write Size: 8 bits Publication Release Date: Mar 2005 Revision 0.6 - 46 - W83627EHF/W83627EHG Preliminary 7 6 5 4 3 2 1 0 CPUFANOUT0 Start-up Value When at Thermal Cruise mode, CPUFANOUT0 value will increase from 0 to this register value to provide a minimum value to turn on the fan. 6.8.15 SYSFANOUT Stop Time Register - Index 0Ch (Bank 0) Register Location: 0Ch Power on Default Value: 3Ch Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 SYSFANOUT Stop Time When at Thermal Cruise mode, this register determines the time of which SYSFANOUT value is from stop value to 0. (1)When at PWM output: The unit of this register is 0.1 second. The default time is 6 seconds. (2)When at DC Voltage output: The unit of this register is 0.4 second. The default time is 24 seconds. 6.8.16 CPUFANOUT0 Stop Time Register - Index 0Dh (Bank 0) Register Location: 0Dh Power on Default Value: 3Ch Attribute: Read/Write Size: 8 bits Publication Release Date: Mar 2005 Revision 0.6 - 47 - W83627EHF/W83627EHG Preliminary 7 6 5 4 3 2 1 0 CPUFANOUT0 Stop Time When at Thermal Cruise mode or SMARTFAN III mode, this register determines the time of which CPUFANOUT0 value is from stop value to 0. (1)When at PWM output: The unit of this register is 0.1 second. The default time is 6 seconds. (2)When at DC Voltage output: The unit of this register is 0.4 second. The default time is 24 seconds. 6.8.17 Fan Output Step Down Time Register - Index 0Eh (Bank 0) Register Location: 0Eh Power on Default Value: 0Ah Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 FANOUT Value Step Down Time This register determines the speed of FANOUT decreasing its value in Smart Fan Control mode. (1)When at PWM output: The unit of this register is 0.1 second. The default time is 1 seconds. (2)When at DC Voltage output: The unit of this register is 0.4 second. The default time is 4 seconds. 6.8.18 Fan Output Step Up Time Register - Index 0Fh (Bank 0) Register Location: 0Fh Power on Default Value: 0Ah Attribute: Read/Write Size: 8 bits Publication Release Date: Mar 2005 Revision 0.6 - 48 - W83627EHF/W83627EHG Preliminary 7 6 5 4 3 2 1 0 FANOUT Value Step Up Time This register determines the speed of FANOUT increasing the its value in Smart Fan Control mode. (1)When at PWM output: The unit of this register is 0.1 second. The default time is 1 seconds. (2)When at DC Voltage output: The unit of this register is 0.4 second. The default time is 4 seconds. 6.8.19 AUXFANOUT PWM Output Frequency Configuration Register - Index 10h (Bank 0) Register Location: 10h Power on Default Value: 04h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 PWM_SCALE3 PWM_CLK_SEL3 The register is meaningful when AUXFANOUT be programmed as PWM output. Bit 7: AUXFANOUT PWM Input Clock Source Select. This bit selects the clock source of PWM output frequency. Set to 0, select 24 MHz. Set to 1, select 180 KHz. Bit 6-0: AUXFANOUT PWM Pre-Scale divider. This is the divider of clock source of PWM output frequency. The maximum divider is 128 (7Fh). This divider should not be set to 0. 01h : divider is 1 02h : divider is 2 03h : divider is 3 : : the formula is PWM output frequency = Input Clock 1 Pre_Scale Divider 256 Publication Release Date: Mar 2005 Revision 0.6 - 49 - W83627EHF/W83627EHG Preliminary 6.8.20 AUXFANOUT Output Value Select Register - Index 11h (Bank 0) Register Location: 11h Power on Default Value: FFh Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 AUXFANOUT Value (1)If AUXFANOUT be programmed as PWM output (Bank0 Index 12h.bit0 is 0) Bit 7-0: AUXFANOUT PWM Duty Cycle. Write FFh, AUXFANOUT duty cycle is 100%. Write 00h, AUXFANOUT duty cycle is 0%. Note. XXh: PWM Duty Cycle output percentage is (XX/256*100%) during one cycle. (2)If AUXFANOUT be programmed as DC Voltage output (Bank0 Index 12h.bit0 is 1) Bit 7-2: AUXFANOUT voltage control. Bit 1-0: Reserved. OUTPUT Voltage = AVCC * Note. See the Table 6.4 6.8.21 FAN Configuration Register II - Index 12h (Bank 0) Register Location: 12h Power on Default Value: 01h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 FANOUT 16 AUXFANOUT_SEL AUXFANOUT_Mode AUXFANOUT_Mode AUXFANOUT_MIN_Value CPUFANOUT0_MIN_Value SYSFANOUT_MIN_Value CPUFANOUT1_MIN_Value Reserved Bit 7: Reserved Bit 6: Set 1, CPUFANOUT1 value will decrease to and keep the value set in Index 64h when temperature goes below target range. This is to maintain the fan speed in a minimum value. Publication Release Date: Mar 2005 Revision 0.6 - 50 - W83627EHF/W83627EHG Preliminary Set 0, CPUFANOUT1 value will decrease to 0 when temperature goes below target range. Bit 5: Set 1, SYSFANOUT value will decrease to and keep the value set in Index 08h when temperature goes below target range. This is to maintain the fan speed in a minimum value. Set 0, SYSFANOUT value will decrease to 0 when temperature goes below target range. Bit 4: Set 1, CPUFANOUT0 value will decrease to and keep the value set in Index 09h when temperature goes below target range. This is to maintain the fan speed in a minimum value. Set 0, CPUFANOUT0 value will decrease to 0 when temperature goes below target range. Bit 3: Set 1, AUXFANOUT value will decrease to and keep the value set in Index 17h when temperature goes below target range. This is to maintain the fan speed in a minimum value. Set 0, AUXFANOUT value will decrease to 0 when temperature goes below target range. Bit 2-1: AUXFANOUT mode control. Set 00, AUXFANOUT is as Manual Mode. (Default). Set 01, AUXFANOUT is as Thermal Cruise Mode. Set 10, AUXFANOUT is as Fan Speed Cruise Mode. Set 11, reserved and no function. Bit 0: AUXFANOUT output mode selection. Set to 0, AUXFANOUT pin is as PWM output duty cycle so that it can drive a logical high or low signal. Set to 1, AUXFANOUT pin is as DC voltage output which can provide analog voltage output. (Default 0) 6.8.22 AUXTIN Target Temperature Register/ AUXFANIN0 Target Speed Register - Index 13h (Bank 0) Register Location: 13h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 Target Temperature / Target Speed (1)When at Thermal Cruise mode: Bit 7: Reserved. Bit 6-0: AUXTIN Target Temperature. (2)When at Fan Speed Cruise mode: Bit 7-0: AUXFANIN0 Target Speed. 6.8.23 Tolerance of Target Temperature or Target Speed Register - Index 14h (Bank 0) Register Location: 14h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits Publication Release Date: Mar 2005 Revision 0.6 - 51 - W83627EHF/W83627EHG Preliminary 7 6 5 4 3 2 1 0 AUXTIN Target Temperature Tolerance / AUXFANIN Target Speed Tolerance Reserved (1)When at Thermal Cruise mode: Bit 3-0: Tolerance of AUXTIN Target Temperature. (2)When at Fan Speed Cruise mode: Bit 3-0: Tolerance of AUXFANIN0 Target Speed. 6.8.24 AUXFANOUT Stop Value Register - Index 15h (Bank 0) Register Location: 15h Power on Default Value: 01h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 AUXFANOUT Stop Value When at Thermal Cruise mode, AUXFANOUT value will decrease to this value. This register should be written a non-zero minimum output value. Please note that Stop Value does not mean that fan really stops. It means that if the temperature keeps below low temperature limit, then the fan speed keeps on decreasing until reaching a minimam value, and this is Stop Value. 6.8.25 AUXFANOUT Start-up Value Register - Index 16h (Bank 0) Register Location: 16h Power on Default Value: 01h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 AUXFANOUT Start-up Value Publication Release Date: Mar 2005 Revision 0.6 - 52 - W83627EHF/W83627EHG Preliminary When at Thermal Cruise mode, AUXFANOUT value will increase from 0 to this register value to provide a minimum value to turn on the fan. 6.8.26 AUXFANOUT Stop Time Register - Index 17h (Bank 0) Register Location: 17h Power on Default Value: 3Ch Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 AUXFANOUT Stop Time When at Thermal Cruise mode, this register determines the time of which AUXFANOUT value is from stop value to 0. (1)When at PWM output: The unit of this register is 0.1 second. The default time is 6 seconds. (2)When at DC Voltage output: The unit of this register is 0.4 second. The default time is 24 seconds. 6.8.27 OVT# Configuration Register - Index 18h (Bank 0) Register Location: 18h Power on Default Value: 43h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved OVT1_Mode Reserved DIS_OVT1 Reserved Bit 7: Reserved. Bit 6: Set to 1, disable temperature sensor SYSTIN over-temperature (OVT#) output. Set to 0, enable the SYSTIN OVT# output. Publication Release Date: Mar 2005 Revision 0.6 - 53 - W83627EHF/W83627EHG Preliminary Bit 5: Reserved. Bit 4: SYSTIN OVT# mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected. Bit 3-1: Reserved. Bit 0: Reserved. 6.8.28 Reserved - Index 19h (Bank 0) 6.8.29 Reserved - Index 1A-1Bh (Bank 0) 6.8.30 Reserved - Index 1Ch-1Fh (Bank 0) 6.8.31 Value RAM Index 20h- 3Fh (Bank 0) Address A6-A0 Description 20h CPUVCORE reading 21h VIN0 reading 22h AVCC reading 23h 3VCC reading 24h VIN1 reading 25h VIN2 reading 26h VIN3 reading 27h SYSTIN temperature sensor reading 28h SYSFANIN reading Note: This location stores the number of counts of the internal clock per revolution. 29h CPUFANIN0 reading Note: This location stores the number of counts of the internal clock per revolution. 2Ah AUXFANIN0 reading Note: This location stores the number of counts of the internal clock per revolution. 2Bh CPUVCORE High Limit 2Ch CPUVCORE Low Limit 2Dh VIN0 High Limit 2Eh VIN0 Low Limit 2Fh AVCC High Limit 30h AVCC Low Limit 31h 3VCC High Limit 32h 3VCC Low Limit 33h VIN1 High Limit 34h VIN1 Low Limit 35h VIN2 High Limit 36h VIN2 Low Limit 37h VIN3 High Limit 38h VIN3 Low Limit 39h SYSTIN temperature sensor High Limit 3Ah SYSTIN temperature sensor Hysteresis Limit Publication Release Date: Mar 2005 Revision 0.6 - 54 - W83627EHF/W83627EHG Preliminary 3Bh SYSFANIN Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. CPUFANIN0 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. AUXFANIN0 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. CPUFANIN1 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. CPUFANIN1 reading Note: This location stores the number of counts of the internal clock per revolution. 3Ch 3Dh 3Eh 3Fh 6.8.32 Configuration Register - Index 40h (Bank 0) Register Location: 40h Power on Default Value: 03h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 START SMI#Enable Reserved INT_Clear Reserved Reserved Reserved INITIALIZATION Bit 7: A one restores power on default value to some registers. This bit clears itself since the power on default is zero. Bit 6: Reserved Bit 5: Reserved Bit 4: Reserved Bit 3: A one disables the SMI# output without affecting the contents of Interrupt Status Registers. The device will stop monitoring. It will resume upon clearing of this bit. Bit 2: Reserved Bit 1: A one enables the SMI# Interrupt output. Bit 0: A one enables startup of monitoring operations, a zero puts the part in standby mode. Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "INT_Clear'' bit. Publication Release Date: Mar 2005 Revision 0.6 - 55 - W83627EHF/W83627EHG Preliminary 6.8.33 Interrupt Status Register 1 - Index 41h (Bank 0) Register Location: 41h Power on Default Value: 00h Attribute: Read Only Size: 8 bits 7 6 5 4 3 2 1 0 CPUVCORE VIN0 AVCC(Pin114) 3VCC SYSTIN CPUTIN SYSFANIN CPUFANIN0 Bit 7: A one indicates the fan count limit of CPUFANIN0 has been exceeded. Bit 6: A one indicates the fan count limit of SYSFANIN has been exceeded. Bit 5: A one indicates a High limit of CPUTIN temperature has been exceeded. Bit 4: A one indicates a High limit of SYSTIN temperature has been exceeded . Bit 3: A one indicates a High or Low limit of 3VCC has been exceeded. Bit 2: A one indicates a High or Low limit of AVCC has been exceeded. Bit 1: A one indicates a High or Low limit of VIN0 has been exceeded. Bit 0: A one indicates a High or Low limit of CPUVCORE has been exceeded. 6.8.34 Interrupt Status Register 2 - Index 42h (Bank 0) Register Location: 42h Power on Default Value: 00h Attribute: Read Only Size: 8 bits 7 6 5 4 3 2 1 0 VIN1 VIN3 VIN2 AUXFANIN0 CASEOPEN AUXTIN TAR1 TAR2 Publication Release Date: Mar 2005 Revision 0.6 - 56 - W83627EHF/W83627EHG Preliminary Bit 7: A one indicates that the CPUTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFanTM. Bit 6: A one indicates that the SYSTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFanTM. Bit 5: A one indicates a High limit of AUXTIN temperature has been exceeded. Bit 4: A one indicates case has been opened. Bit 3: A one indicates the fan count limit of AUXFANIN0 has been exceeded . Bit 2: A one indicates a High or Low limit of VIN2 has been exceeded. Bit 1: A one indicates a High or Low limit of VIN3 has been exceeded. Bit 0: A one indicates a High or Low limit of VIN1 has been exceeded. 6.8.35 SMI# Mask Register 1 - Index 43h (Bank 0) Register Location: 43h Power on Default Value: DEh Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 CPUVCORE VIN0 AVCC(Pin114) 3VCC SYSTIN CPUTIN SYSFANIN CPUFANIN0 Bit 7-0: A one disables the corresponding interrupt status bit for SMI interrupt. 6.8.36 SMI# Mask Register 2 - Index 44h (Bank 0) Register Location: 44h Power on Default Value: FFh Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 VIN1 VIN3 VIN2 AUXFANIN0 CASEOPEN AUXTIN TAR1 TAR2 Bit 7-0: A one disables the corresponding interrupt status bit for SMI interrupt. Publication Release Date: Mar 2005 Revision 0.6 - 57 - W83627EHF/W83627EHG Preliminary 6.8.37 Reserved Register - Index 45h (Bank 0) 6.8.38 SMI# Mask Register 3 - Index 46h (Bank 0) Register Location: 46h Power on Default Value: 07h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 VIN4 CPUFANIN1 AUXFANIN1 Reserved Reserved Reserved Reserved Reserved Bit 7-3: Reserved. Bit 2-0: A one disables the corresponding interrupt status bit for SMI interrupt. 6.8.39 Fan Divisor Register I - Index 47h (Bank 0) Register Location: 47h Power on Default Value: 55h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 FANINC5 FANOPV5 FANINC4 FANOPV4 SYSFANIN DIV_B0 SYSFANIN DIV_B1 CPUFANIN0 DIV_B0 CPUFANIN0 DIV_B1 Bit 7-6: CPUFANIN0 Divisor bit1:0. Bit 5-4: SYSFANIN Divisor bit1:0. Bit 3: CPUFANIN1 output value if bit 0 sets to 0. Write 1, pin119(CPUFANIN1) always generates a logic high signal. Write 0, pin119 always generates a logic low signal. This bit is default 0. Bit 2: CPUFANIN1 Input Control. Set to 1, pin119 (CPUFANIN1) acts as FAN tachometer input, which is default value. Set to 0, this pin119 acts as FAN control signal and the output value of FAN control is set by this register bit 1. Bit 1: AUXFANIN1 output value if bit 0 sets to 0. Write 1, pin58(AUXFANIN1) always generates a logic high signal. Write 0, pin58 always generates a logic low signal. This bit is default 0. Bit 0: AUXFANIN1 Input Control. Set to 1, pin58 (AUXFANIN1) acts as FAN tachometer input, which is default value. Set to 0, this pin58 acts as FAN control signal and the output value of FAN control is set by this register bit 1. Publication Release Date: Mar 2005 Revision 0.6 - 58 - W83627EHF/W83627EHG Preliminary Note : Please refer to Bank0 Index 5Dh , Fan divisor table. 6.8.40 Serial Bus Address Register - Index 48h (Bank 0) Register Location: 48h Power on Default Value: 2Dh Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 Serial Bus Addr. Reserved Bit 7: Reserved (Read Only). Bit 6-0: Serial Bus address <7:1>. 6.8.41 Reserved - Index 49h (Bank 0) 6.8.42 CPUFANOUT1 with Temperature source Select - Index 4Ah (Bank 0) Register Location: 4Ah Power on Default Value: 40h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved CPUFANOUT1 SRC Bit 7-2: Reserved. Bit 1-0: Select Temperature source for CPUFANOUT1 at Thermal Cruise mode. <1:0> = 00 - SYSTIN. <1:0> = 01 - CPUTIN.(Default) <1:0> = 10 - AUXTIN. <1:0> = 11 - Reserved. 6.8.43 Fan Divisor Register II - Index 4Bh (Bank 0) Register Location: 4Bh Power on Default Value: 44h Attribute: Read/Write Size: 8 bits Publication Release Date: Mar 2005 Revision 0.6 - 59 - W83627EHF/W83627EHG Preliminary 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved ADCOVSEL ADCOVSEL AUXFANIN0 DIV_B0 AUXFANIN0 DIV_B1 Bit 7-6: AUXFANIN0 Divisor bit1:0. Note : Please refer to Bank0 Index 5Dh , Fan divisor table. Bit 5-4: Select A/D Converter Clock Input. <5:4> = 00 - default. ADC clock select 22.5 Khz. <5:4> = 01- ADC clock select 5.6 Khz. (22.5K/4) <5:4> = 10 - ADC clock select 1.4Khz. (22.5K/16) <5:4> = 11 - ADC clock select 0.35 Khz. (22.5K/64) Bit 3-2: These two bits should be set to 01h. The default value is 01h. Bit 1-0: Reserved. 6.8.44 SMI#/OVT# Control Register - Index 4Ch (Bank 0) Register Location: 4Ch Power on Default Value: 10h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 Reserved Reserved OVTPOL DIS_OVT2 DIS_OVT3 EN_T1_ONE T2T3_INTMode CPUFANIN1 DIV_B2 Bit 7: CPUFANIN1 Divisor bit2. Bit 6: Set to 1, the SMI# output type of Temperature CPUTIN/AUXTIN is set to Comparator Interrupt mode. Set to 0, the SMI# output type is set to Two-Times Interrupt mode. (default 0) Bit 5: Set to 1, the SMI# output type of temperature SYSTIN is One-Time interrupt mode. Set to 0, the SMI# output type is Two-Times interrupt mode. Bit 4: Disable temperature sensor AUXTIN over-temperature (OVT) output if set to 1. Set to 0, enable AUXTIN OVT output through pin OVT#. (default 1) Bit 3: Disable temperature sensor CPUTIN over-temperature (OVT) output if set to 1. Set to 0, enable CPUTIN OVT output through pin OVT#. (default 0) Bit 2: Over-temperature polarity. Write 1, OVT# active high. Write 0, OVT# active low. (default 0) Publication Release Date: Mar 2005 Revision 0.6 - 60 - W83627EHF/W83627EHG Preliminary Bit 1-0: Reserved. 6.8.45 FAN IN/OUT Control Register - Index 4Dh (Bank 0) Register Location: 4Dh Power on Default Value: 15h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 FANINC1 FANOPV1 FANINC2 FANOPV2 FANINC3 FANOPV3 Reserved Reserved Bit 7-6: Reserved. Bit 5: AUXFANIN0 output value if bit 4 sets to 0. Write 1, pin111(AUXFANIN0) always generates a logic high signal. Write 0, pin111 always generates a logic low signal. This bit is default 0. Bit 4: AUXFANIN0 Input Control. Set to 1, pin111(AUXFANIN) acts as FAN tachometer input, which is default value. Set to 0, this pin111 acts as FAN control signal and the output value of FAN control is set by this register bit 5. Bit 3: CPUFANIN0 output value if bit 2 sets to 0. Write 1, pin112(CPUFANIN0) always generates a logic high signal. Write 0, pin112 always generates a logic low signal. This bit is default 0. Bit 2: CPUFANIN0 Input Control. Set to 1, pin112(CPUFANIN0) acts as FAN tachometer input, which is default value. Set to 0, this pin112 acts as FAN control signal and the output value of FAN control is set by this register bit 3. Bit 1: SYSFANIN output value if bit 0 sets to 0. Write 1, pin113(SYSFANIN) always generates a logic high signal. Write 0, pin113 always generates a logic low signal. This bit is default 0. Bit 0: SYSFANIN Input Control. Set to 1, pin113(SYSFANIN) acts as FAN tachometer input, which is default value. Set to 0, this pin113 acts as FAN control signal and the output value of FAN control is set by this register bit 1. 6.8.46 Register 50h ~ 5Fh Bank Select Register - Index 4Eh (Bank 0) Register Location: 4Eh Power on Default Value: 80h Attribute: Read/Write Size: 8 bits Publication Release Date: Mar 2005 Revision 0.6 - 61 - W83627EHF/W83627EHG Preliminary 7 6 5 4 3 2 1 0 BANKSEL0 BANKSEL1 BANKSEL2 Reserved EN_CPUFANIN1_BP EN_AUXFANIN1_BP Reserved HBACS Bit 7: HBACS - High byte access. Set to 1, access Index 4Fh high byte register. Set to 0, access Index 4Fh low byte register. (default 1) Bit 6: Reserved. This bit should be set to 0. Bit 5: BEEP output control for AUXFANIN1 if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 4: BEEP output control for CPUFANIN1 if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 3: Reserved. This bit should be set to 0. Bit 2-0: Index ports 0x50~0x5F Bank select. Set to 0, select Bank0. Set to 1, select Bank1. Set to 2, select Bank2. 6.8.47 Winbond Vendor ID Register - Index 4Fh (Bank 0) Register Location: 4Fh Power on Default Value: <15:0> = 5CA3h Attribute: Read Only Size: 16 bits 15 8 7 0 VIDH VIDL Bit 15-8: Vendor ID High Byte if Index 4Eh.bit7=1. Default 5Ch. Bit 7-0: Vendor ID Low Byte if Index 4Eh.bit7=0. Default A3h. 6.8.48 Winbond Test Register - Index 50h-55h (Bank 0) 6.8.49 BEEP Control Register 1 - Index 56h (Bank 0) Register Location: 56h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits Publication Release Date: Mar 2005 Revision 0.6 - 62 - W83627EHF/W83627EHG Preliminary 7 6 5 4 3 2 1 0 EN_CPUVCORE_BP EN_VIN0_BP EN_AVCC_BP EN_3VCC_BP EN_SYSTIN_BP EN_CPUTIN_BP EN_SYSFANIN_BP EN_CPUFANIN0_BP Bit 7: BEEP output control for CPUFANIN0 if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 6: BEEP output control for SYSFANIN if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 5: BEEP output control for temperature CPUTIN if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 4: BEEP output control for temperature SYSTIN if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 3: BEEP output control for 3VCC if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 2: BEEP output control for AVCC if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 1: BEEP output control for VIN0 if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 0: BEEP output control for CPUVCORE if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. 6.8.50 BEEP Control Register 2 - Index 57h (Bank 0) Register Location: 57h Power on Default Value: 80h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 EN_VIN1_BP EN_VIN2_BP EN_VIN3_BP EN_AUXFANIN0_BP EN_CASEOPEN_BP EN_AUXTIN_BP Reserved EN_GBP Bit 7: Global BEEP Control. Write 1, enable global BEEP output, which is default value. Write 0, disable all BEEP output. Bit 6: Reserved. Publication Release Date: Mar 2005 Revision 0.6 - 63 - W83627EHF/W83627EHG Preliminary Bit 5: BEEP output control for temperature AUXTIN if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 4: BEEP output control for CASEOPEN if case has been opened. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 3: BEEP output control for AUXFANIN0 if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 2: BEEP output control for VIN3 if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 1: BEEP output control for VIN2 if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 0: BEEP output control for VIN1 if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. 6.8.51 Chip ID - Index 58h (Bank 0) Register Location: 58h Power on Default Value: A1h Attribute: Read Only Size: 8 bits 7 6 5 4 3 2 1 0 CHIPID Bit 7-0: Winbond Chip ID number. Read this register will return A1h. 6.8.52 Diode Selection Register - Index 59h (Bank 0) Register Location: 59h Power on Default Value: 70h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 CPUFANIN1 DIV_B0 CPUFANIN1 DIV_B1 AUXFANIN1 DIV_B0 AUXFANIN1 DIV_B1 SELPIIV1 SELPIIV2 SELPIIV3 AUXFANIN1 DIV_B2 Publication Release Date: Mar 2005 Revision 0.6 - 64 - W83627EHF/W83627EHG Preliminary Bit 7: AUXFANIN1 Divisor bit2. Bit 6: Diode mode selection of temperature AUXTIN if Index 5Dh bit3 is 1. Set this bit to 1, select Pentium II CPU compatible thermal diode. Set this bit to 0, select 2N3904 bipolar diode. Bit 5: Diode mode selection of temperature CPUTIN if Index 5Dh bit2 is 1. Set this bit to 1, select Pentium II CPU compatible thermal diode. Set this bit to 0, select 2N3904 bipolar diode. Bit 4: Diode mode selection of temperature SYSTIN if Index 5Dh bit1 is 1. Set this bit to 1, select Pentium II CPU compatible thermal diode. Set this bit to 0, select 2N3904 bipolar diode. Bit 3-2: AUXFANIN1 Divisor bit 1:0. Bit 1-0: CPUFANIN1 Divisor bit 1:0. 6.8.53 Reserved - Index 5Ah-5Ch (Bank 0) 6.8.54 VBAT Monitor Control Register - Index 5Dh (Bank 0) Register Location: 5Dh Power on Default Value: 00h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 EN_VBAT_MNT DIODES1 DIODES2 DIODES3 Reserved SYSFANIN DIV_B2 CPUFANIN0 DIV_B2 AUXFANIN0 DIV_B2 Bit 7: AUXFANIN0 Divisor bit2. Bit 6: CPUFANIN0 Divisor bit2. Bit 5: SYSFANIN Divisor bit2. Bit 4: Reserved. Bit 3: Sensor type selection of AUXTIN. Set to 1, select diode sensor. Set to 0, select thermistor sensor. Bit 2: Sensor type selection of CPUTIN. Set to 1, select diode sensor. Set to 0, select thermistor sensor. Bit 1: Sensor type selection of SYSTIN. Set to 1, select diode sensor. Set to 0, select thermistor sensor. Bit 0: Set to 1, enable battery voltage monitor. Set to 0, disable battery voltage monitor. After set this bit from 0 to 1, the monitored value will be updated to the VBAT reading value register after one monitor cycle time. Publication Release Date: Mar 2005 Revision 0.6 - 65 - W83627EHF/W83627EHG Preliminary Fan divisor table : Bit 2 0 0 0 0 Bit 1 0 0 1 1 Bit 0 0 1 0 1 Fan Divisor 1 2 4 8 Bit 2 1 1 1 Bit 1 0 0 1 Bit 0 0 1 0 1 Fan Divisor 16 32 64 128 1 1 Table 6.3 6.8.55 Reserved Register - Index 5Eh-5Fh (Bank 0) 6.8.56 CPUFANOUT1 PWM Output Frequency Configuration Register - Index 60h (Bank 0) Register Location: 60h Power on Default Value: 04h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 PWM_SCALE4 PWM_CLK_SEL4 The register is meaningful when CPUFANOUT1 be programmed as PWM output. Bit 7: CPUFANOUT1 PWM Input Clock Source Select. This bit selects the clock source of PWM output frequency. Set to 0, select 24 MHz. Set to 1, select 180 KHz. Bit 6-0: CPUFANOUT1 PWM Pre-Scale divider. This is the divider of clock source of PWM output frequency. The maximum divider is 128 (7Fh). This divider should not be set to 0. 01h : divider is 1 02h : divider is 2 03h : divider is 3 : : the formula is PWM output frequency = Input Clock 1 Pre_Scale Divider 256 Publication Release Date: Mar 2005 Revision 0.6 - 66 - W83627EHF/W83627EHG Preliminary 6.8.57 CPUFANOUT1 Output Value Select Register - Index 61h (Bank 0) Register Location: 61h Power on Default Value: FFh Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 CPUFANOUT1 Value (1)If CPUFANOUT1 be programmed as PWM output (Bank0 Index 62h.bit6 is 0) Bit 7-0: CPUFANOUT1 PWM Duty Cycle. Write FFh, CPUFANOUT1 duty cycle is 100%. Write 00h, CPUFANOUT1 duty cycle is 0%. Note. XXh: PWM Duty Cycle output percentage is (XX/256*100%) during one cycle. (2)If CPUFANOUT1 be programmed as DC Voltage output (Bank0 Index 62h.bit6 is 1) Bit 7-2: CPUFANOUT1 voltage control. Bit 1-0: Reserved. OUTPUT Voltage = AVCC * Note. See the Table 6.4 6.8.58 FAN Configuration Register III - Index 62h (Bank 0) Register Location: 62h Power on Default Value: 40h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 FANOUT 64 Target Temperature Tolerance / CPUFANIN1 Target Speed Tolerance CPUFANOUT1_Mode CPUFANOUT1_Mode CPUFANOUT1_SEL Reserved Bit7 : Reserved. Publication Release Date: Mar 2005 Revision 0.6 - 67 - W83627EHF/W83627EHG Preliminary Bit 6: CPUFANOUT1 output mode selection. Set to 0, CPUFANOUT1 pin is as PWM output duty cycle so that it can drive a logical high or low signal. Set to 1, CPUFANOUT1 pin is as DC voltage output which can provide analog voltage output. (Default 1) Bit 5-4: CPUFANOUT1 mode control. Set 00, CPUFANOUT1 is as Manual Mode. (Default). Set 01, CPUFANOUT1 is as Thermal Cruise Mode. Set 10, CPUFANOUT1 is as Fan Speed Cruise Mode. Set 11, CPUFANOUT1 is SMART FANTM III Mode. (1)When at Thermal Cruise mode or SMART FANTM III mode: Bit3-0: Tolerance of select temperature source Target Temperature. (2)When at Fan Speed Cruise mode: Bit3-0: Tolerance of CPUFANIN1 Target Speed. 6.8.59 Target Temperature Register/ CPUFANIN1 Target Speed Register - Index 63h (Bank 0) Register Location: 63h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 Target Temperature / Target Speed (1)When at Thermal Cruise mode or SMART FANTM III mode: Bit 7: Reserved. Bit 6-0: Target Temperature of select temperature source. (2)When at Fan Speed Cruise mode: Bit 7-0: CPUFANIN1 Target Speed. 6.8.60 CPUFANOUT1 Stop Value Register - Index 64h (Bank 0) Register Location: 64h Power on Default Value: 01h Attribute: Read/Write Size: 8 bits Publication Release Date: Mar 2005 Revision 0.6 - 68 - W83627EHF/W83627EHG Preliminary 7 6 5 4 3 2 1 0 CPUFANOUT1 Stop Value When at Thermal Cruise mode or SMART FANTM III mode, CPUFANOUT1 value will decrease to this value. This register should be written a non-zero minimum stop value. Please note that Stop Value does not mean that fan really stops. It means that if the temperature keeps below low temperature limit, then the fan speed keeps on decreasing until reaching a minimam value, and this is Stop Value. 6.8.61 CPUFANOUT1 Start-up Value Register - Index 65h (Bank 0) Register Location: 65h Power on Default Value: 01h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 CPUFANOUT1 Start-up Value When at Thermal Cruise mode, CPUFANOUT1 value will increase from 0 to this register value to provide a minimum value to turn on the fan. 6.8.62 CPUFANOUT1 Stop Time Register - Index 66h (Bank 0) Register Location: 66h Power on Default Value: 3Ch Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 CPUFANOUT1 Stop Time Publication Release Date: Mar 2005 Revision 0.6 - 69 - W83627EHF/W83627EHG Preliminary When at Thermal Cruise mode or SMART FANTM III mode, this register determines the time of which CPUFANOUT1 value is from stop value to 0. (1)When at PWM output: The unit of this register is 0.1 second. The default time is 6 seconds. (2)When at DC Voltage output: The unit of this register is 0.4 second. The default time is 24 seconds. 6.8.63 CPUFANOUT0 Maximum Output Value Register - Index 67h (Bank 0) Register Location: 67h Power on Default Value: FFh Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 CPUFANOUT0 Max. Value When at SMART FANTM III mode, CPUFANOUT0 value will increase to this value. This register should be written a non-zero value that cannot lower than Stop value. 6.8.64 CPUFANOUT0 Output Step Value Register - Index 68h (Bank 0) Register Location: 68h Power on Default Value: 01h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 CPUFANOUT0 Step This register determines the value that CPUFANOUT0 in SMART FANTM III mode decreased or increased to the next speed. Publication Release Date: Mar 2005 Revision 0.6 - 70 - W83627EHF/W83627EHG Preliminary 6.8.65 CPUFANOUT1 Maximum Output Value Register - Index 69h (Bank 0) Register Location: 69h Power on Default Value: FFh Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 CPUFANOUT1 Max. Value When at SMART FANTM III mode, CPUFANOUT1 value will increase to this value. This register should be written a non-zero value that cannot lower than Stop value. 6.8.66 CPUFANOUT1 Output Step Value Register - Index 6Ah (Bank 0) Register Location: 6Ah Power on Default Value: 01h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 CPUFANOUT1 Step This register determines the value that CPUFANOUT1 in SMART FANTM III mode decreased or increased to the next speed. Publication Release Date: Mar 2005 Revision 0.6 - 71 - W83627EHF/W83627EHG Preliminary 6.8.67 CPUTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 1) Register Location: 50h Attribute: Read Only Size: 8 bits 7 6 5 4 3 2 1 0 TEMP<8:1> Bit 7-0: Temperature <8:1> of CPUTIN sensor, which is high byte, means 1C. 6.8.68 CPUTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 1) Register Location: 51h Attribute: Read Only Size: 8 bits 7 6 5 4 3 2 1 0 Reserved TEMP<0> Bit 7: Temperature <0> of CPUTIN sensor, which is low byte, means 0.5C. Bit 6-0: Reserved. Publication Release Date: Mar 2005 Revision 0.6 - 72 - W83627EHF/W83627EHG Preliminary 6.8.69 CPUTIN Temperature Sensor Configuration Register - Index 52h (Bank 1) Register Location: 52h Power on Default Value: 00h Size: 8 bits 7 6 5 4 3 2 1 0 STOP OVTMOD Reserved FAULT FAULT Reserved Reserved Reserved Bit 7-5: Read Only - Reserved. This bit should be set to 0. Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Bit 2: Read - Reserved. This bit should be set to 0. Bit 1: Read/Write - OVT# mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected. Bit 0: Read/Write - When set to 1 the sensor will stop monitor. 6.8.70 CPUTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 1) Register Location: 53h Power on Default Value: 4Bh Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 THYST<8:1> Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. 6.8.71 CPUTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 1) Register Location: 54h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits Publication Release Date: Mar 2005 Revision 0.6 - 73 - W83627EHF/W83627EHG Preliminary 7 6 5 4 3 2 1 0 Reserved THYST<0> Bit 7: Hysteresis temperature bit 0, which is low Byte. Bit 6-0: Reserved. 6.8.72 CPUTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank1) Register Location: 55h Power on Default Value: 50h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 TOVF<8:1> Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C. 6.8.73 CPUTIN Temperature Sensor Over-temperature (Low Byte) Register - Index 56h (Bank 1) Register Location: 56h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 Reserved TOVF<0> Bit 7: Over-temperature bit 0, which is low Byte. Bit 6-0: Reserved. Publication Release Date: Mar 2005 Revision 0.6 - 74 - W83627EHF/W83627EHG Preliminary 6.8.74 AUXTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 2) Register Location: 50h Attribute: Read Only Size: 8 bits 7 6 5 4 3 2 1 0 TEMP<8:1> Bit 7: Temperature <8:1> of AUXTIN sensor, which is high byte, means 1C. 6.8.75 AUXTIN Temperature Sensor Temperature (Low Byte) Register - Index 51h (Bank 2) Register Location: 51h Attribute: Read Only Size: 8 bits 7 6 5 4 3 2 1 0 Reserved TEMP<0> Bit 7: Temperature <0> of AUXTIN sensor, which is low byte, means 0.5C. Bit 6-0: Reserved. Publication Release Date: Mar 2005 Revision 0.6 - 75 - W83627EHF/W83627EHG Preliminary 6.8.76 AUXTIN Temperature Sensor Configuration Register - Index 52h (Bank 2) Register Location: 52h Power on Default Value: 00h Size: 8 bits 7 6 5 4 3 2 1 0 STOP OVTMOD Reserved FAULT FAULT Reserved Reserved Reserved Bit 7-5: Read - Reserved. This bit should be set to 0. Bit 4-3: Read/Write - Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Bit 2: Read - Reserved. This bit should be set to 0. Bit 1: Read/Write - OVT# mode select. This bit default is set to 0, which is compared mode. When set to 1, interrupt mode will be selected. Bit 0: Read/Write - When set to 1 the sensor will stop monitor. 6.8.77 AUXTIN Temperature Sensor Hysteresis (High Byte) Register - Index 53h (Bank 2) Register Location: 53h Power on Default Value 4Bh Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 THYST<8:1> Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. 6.8.78 AUXTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 2) Register Location: 54h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits Publication Release Date: Mar 2005 Revision 0.6 - 76 - W83627EHF/W83627EHG Preliminary 7 6 5 4 3 2 1 0 Reserved THYST<0> Bit 7: Hysteresis temperature bit 0, which is low Byte. Bit 6-0: Reserved. 6.8.79 AUXTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank 2) Register Location: 55h Power on Default Value: 50h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 TOVF<8:1> Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C. 6.8.80 AUXTIN Temperature Sensor Over-temperature(Low Byte) Register - Index 56h (Bank 2) Register Location: 56h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 Reserved TOVF<0> Bit 7: Over-temperature bit 0, which is low Byte. Bit 6-0: Reserved. Publication Release Date: Mar 2005 Revision 0.6 - 77 - W83627EHF/W83627EHG Preliminary 6.8.81 Interrupt Status Register 3 - Index 50h (Bank 4) Register Location: 50h Power on Default Value: 00h Attribute: Read Only Size: 8 bits 7 6 5 4 3 2 1 0 VSB VBAT TAR3 VIN4 CPUFANIN1 AUXFANIN1 Reserved Reserved Bit 7-6: Reserved. Bit 5: A one indicates the fan count limit of AUXFANIN1 has been exceeded . Bit 4: A one indicates the fan count limit of CPUFANIN1 has been exceeded . Bit 3: A one indicates a High or Low limit of VIN4 has been exceeded. Bit 2: A one indicates that the AUXTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFanTM. Bit 1: A one indicates a High or Low limit of VBAT has been exceeded. Bit 0: A one indicates a High or Low limit of VSB has been exceeded. 6.8.82 SMI# Mask Register 4 - Index 51h (Bank 4) Register Location: 51h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 VSB VBAT Reserved Reserved TAR3 Reserved Reserved Reserved Bit 7-5: Reserved. Bit 4: A one disables the corresponding interrupt status bit for SMI interrupt. Bit 3-2: Reserved. Bit 1: A one disables the corresponding interrupt status bit for SMI interrupt. Bit 0: A one disables the corresponding interrupt status bit for SMI interrupt. 6.8.83 Reserved Register - Index 52h (Bank 4) Publication Release Date: Mar 2005 Revision 0.6 - 78 - W83627EHF/W83627EHG Preliminary 6.8.84 BEEP Control Register 3 - Index 53h (Bank 4) Register Location: 53h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 EN_VSB_BP EN_VBAT_BP Reserved Reserved Reserved EN_USER_BP Reserved Reserved Bit 7-6: Reserved. Bit 5: User define BEEP output function. Write 1, the BEEP is always active. Write 0, this function is inactive. (Default 0) Bit 4-2: Reserved. Bit 1: BEEP output control for VBAT if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 0: BEEP output control for VSB if the monitor value exceed the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. 6.8.85 SYSTIN Temperature Sensor Offset Register - Index 54h (Bank 4) Register Location: 54h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 OFFSET<7:0> Bit 7-0: SYSTIN temperature offset value. The value in this register will be added to the monitored value so that the reading value will be the sum of the monitored value and the offset value. 6.8.86 CPUTIN Temperature Sensor Offset Register - Index 55h (Bank 4) Register Location: 55h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits Publication Release Date: Mar 2005 Revision 0.6 - 79 - W83627EHF/W83627EHG Preliminary 7 6 5 4 3 2 1 0 OFFSET<7:0> Bit 7-0: CPUTIN temperature offset value. The value in this register will be added to the monitored value so that the reading value will be the sum of the monitored value and the offset value. 6.8.87 AUXTIN Temperature Sensor Offset Register - Index 56h (Bank 4) Register Location: 56h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits 7 6 5 4 3 2 1 0 OFFSET<7:0> Bit 7-0: AUXTIN temperature offset value. The value in this register will be added to the monitored value so that the reading value will be the sum of the monitored value and the offset value. 6.8.88 Reserved Register - Index 57h-58h (Bank 4) Publication Release Date: Mar 2005 Revision 0.6 - 80 - W83627EHF/W83627EHG Preliminary 6.8.89 Real Time Hardware Status Register I - Index 59h (Bank 4) Register Location: 59h Power on Default Value: 00h Attribute: Read Only Size: 8 bits 7 6 5 4 3 2 1 0 CPUVCORE_STS VIN0_STS AVCC_STS 3VCC_STS SYSTIN_STS CPUTIN_STS SYSFANIN_STS CPUFANIN0_STS Bit 7: CPUFANIN0 status. Read 1, the fan speed count is over the limit value. Read 0, the fan speed count is in the limit range. Bit 6: SYSFANIN status. Read 1, the fan speed count is over the limit value. Read 0, the fan speed count is in the limit range. Bit 5: CPUTIN temperature sensor status. Read 1, the temperature exceeds the over-temperature limit value. Read 0, the temperature is in under the hysteresis value. Bit 4: SYSTIN temperature sensor status. Read 1, the temperature exceeds the over-temperature limit value. Read 0, the temperature is in under the hysteresis value. Bit 3: 3VCC Voltage status. Read 1, the voltage of 3VCC is over/under the limit value. Read 0, the voltage of 3VCC is in the limit range. Bit 2: AVCC Voltage status. Set 1, the voltage of AVCC is over/under the limit value. Read 0, the voltage of AVCC is in the limit range. Bit 1: VIN0 Voltage status. Set 1, the voltage of VIN0 is over/under the limit value. Read 0, the voltage of VIN0 is in the limit range. Bit 0: CPUVCORE Voltage status. Read 1, the voltage of CPUVCORE is over/under the limit value. Read 0, the voltage of CPUVCORE is in the limit range. 6.8.90 Real Time Hardware Status Register II - Index 5Ah (Bank 4) Register Location: 5Ah Power on Default Value: 00h Attribute: Read Only Size: 8 bits 7 6 5 4 3 2 1 0 VIN1_STS TAR4_STS CPUFANIN1_STS AUXFANIN0_STS CASEOPEN_STS AUXTIN_STS TAR1_STS TAR2_STS Publication Release Date: Mar 2005 Revision 0.6 - 81 - W83627EHF/W83627EHG Preliminary Bit 7: Smart Fan of CPUFANIN0 warning status. Read 1, the CPUTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFanTM. Read 0, the temperature does not reach the warning range yet. Bit 6: Smart Fan of SYSFANIN warning status. Read 1, the SYSTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFanTM. Read 0, the temperature does not reach the warning range yet. Bit 5: AUXTIN temperature sensor status. Read 1, the temperature exceeds the over-temperature limit value. Read 0, the temperature is in under the hysteresis value. Bit 4: Case Open status. Read 1, the case open is detected and latched. Read 0, the case is not latched open. Bit 3: AUXFANIN0 status. Read 1, the fan speed count is over the limit value. Read 0, the fan speed count is in the limit range. Bit 2: CPUFANIN1 status. Read 1, the fan speed count is over the limit value. Read 0, the fan speed count is in the limit range. Bit 1: Smart Fan of CPUFANIN1 warning status. Read 1, the select temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFanTM. Read 0, the temperature does not reach the warning range yet. Bit 0: VIN1 Voltage status. Read 1, the voltage of VIN1 is over/under the limit value. Read 0, the voltage of VIN1 is in the limit range. 6.8.91 Real Time Hardware Status Register III - Index 5Bh (Bank 4) Register Location: 5Bh Power on Default Value: 00h Attribute: Read Only Size: 8 bits 7 6 5 4 3 2 1 0 VSB_STS VBAT_STS TAR3_STS VIN4_STS VIN3_STS VIN2_STS Reserved AUXFANIN1_STS Bit 7: AUXFANIN1 status. Read 1, the fan speed count is over the limit value. Read 0, the fan speed count is in the limit range. Bit 6: Reserved. Bit 5: VIN2 Voltage status. Read 1, the voltage of VIN2 is over/under the limit value. Read 0, the voltage of VIN21 is in the limit range. Bit 4: VIN3 Voltage status. Read 1, the voltage of VIN3 is over/under the limit value. Read 0, the voltage of VIN3 is in the limit range. Bit 3: VIN4 Voltage status. Read 1, the voltage of VIN4 is over/under the limit value. Read 0, the voltage of VIN4 is in the limit range. Bit 2: Smart Fan of AUXFANIN warning status. Read 1, the AUXTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFanTM. Read 0, the temperature does not reach the warning range yet. Publication Release Date: Mar 2005 Revision 0.6 - 82 - W83627EHF/W83627EHG Preliminary Bit 1: VBAT Voltage status. Read 1, the voltage of VBAT is over/under the limit value. Read 0, the voltage of VBAT is in the limit range. Bit 0: VSB Voltage status. Read 1, the voltage of VSB is over/under the limit value. Read 0, the voltage of VSB is in the limit range. 6.8.92 Reserved Register - Index 5Ch-5Dh (Bank 4) 6.8.93 Value RAM 2 Index 50h-59h (Bank 5) Address A6-A0 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch Description VSB reading VBAT reading. The reading is meaningless if EN_VBAT_MNT bit(Bank0 Index 5Dh.bit0) is not set. VIN4 reading AUXFANIN1 reading Note: This location stores the number of counts of the internal clock per revolution. 3VSB High Limit 3VSB Low Limit VBAT High Limit VBAT Low Limit VIN4 High Limit VIN4 Low Limit Reserved Reserved AUXFANIN1 Fan Count Limit Note: It is the number of counts of the internal clock for the Low Limit of the fan speed. 6.8.94 Winbond Test Register - Index 50h-57h (Bank 6) Publication Release Date: Mar 2005 Revision 0.6 - 83 - W83627EHF/W83627EHG Preliminary 7. Configuration Register 7.1 Chip (Global) Control Register CR 02h. (Software Reset; Write Only) Bit Read / Write 7~1 Reserved. 0 Write "1" Only Software RESET. CR 07h. (Logic Device; Default 00h) Bit Read / Write 7~0 R/W Logical Device Number. Description Description CR 20h. (Chip ID, MSB; Read Only) Bit Read / Write Description 7~0 Read Only Chip ID number = 88h (higher byte). CR 21h. (Chip ID, LSB; Read Only) Bit Read / Write Description 7~0 Read Only Chip ID number = 6Xh (lower byte). X for IC version CR 22h. (Device Power Down; Default FFh) Bit Read / Write 7 Reserved. 6 R/W HM Power Down. 5 R/W URB Power Down. 4 R/W URA Power Down. 3 R/W PRT Power Down. 2 Reserved. 1 Reserved. 0 R/W FDC Power Down. Description 0: Power down. 0: Power down. 0: Power down. 0: Power down. 1: No power down. 1: No power down. 1: No power down. 1: No power down. 0: Power down. 1: No power down. CR 23h. (IPD; Default 00h) Bit Read / Write Description 7~1 Reserved. IPD (Immediate Power Down). When set to 1, whole chip is put into power 0 R/W down mode immediately. CR 24h. (Global Option; Default 0100_0ss0b) s: value by strapping Bit Read / Write Description 7 Reserved. CLKSEL => Input clock rate selection 6 R/W =0 The clock input on pin18 is 24MHz. =1 The clock input on pin18 is 48MHz. (Default) 5~3 Reserved. Publication Release Date: Mar 2005 Revision 0.6 - 84 - W83627EHF/W83627EHG Preliminary 2 Read Only ENKBC => Enable keyboard controller =0 KBC is disabled after hardware reset. =1 KBC is enabled after hardware reset. This bit is read only, and set/reset by power-on strapping pin (PIN54; SOUTA). ENROM => Enable Serial FHW =0 ROM is disabled after hardware reset. =1 ROM is enabled after hardware reset. This bit set/reset by power-on strapping pin (PIN52; DTRA). PNPCVS => =0 The compatible PNP address select registers have default values. =1 The compatible PNP address select registers have no default value. 1 R/W 0 R/W CR 25h. (Interface tri-state Enable; Default 00h) Bit Read / Write 7~6 Reserved. 5 R/W URBTRI 4 R/W URATRI 3 R/W PRTTRI 2~1 Reserved. 0 R/W FDCTRI. Description s: value by strapping CR 26h. (Global Option; Default 0s000000b) Bit Read / Write Description SEL4FDD => 7 R/W =0 Select two FDD mode. =1 Select four FDD mode. HEFRAS => =0 Write 87h to location 2E twice. 6 R/W =1 Write 87h to location 4E twice. The corresponding power-on strapping pin is RTSA# (pin 51). LOCKREG => 5 R/W =0 Enable R/W configuration registers. =1 Disable R/W configuration registers. 4 Reserved. DSFDLGRQ => =0 Enable FDC legacy mode on IRQ and DRQ selection, then DO 3 R/W register (base address + 2) bit 3 is effective on selecting IRQ. =1 Disable FDC legacy mode on IRQ and DRQ selection, then DO register (base address + 2) bit 3 is not effective on selecting IRQ. DSPRLGRQ => =0 Enable PRT legacy mode on IRQ and DRQ selection, then DCR 2 R/W register (base address + 2) bit 4 is effective on selecting IRQ. =1 Disable PRT legacy mode on IRQ and DRQ selection, then DCR register (base address + 2) bit 4 is not effective on selecting IRQ. Publication Release Date: Mar 2005 Revision 0.6 - 85 - W83627EHF/W83627EHG Preliminary Bit Read / Write Description DSUALGRQ => =0 Enable UART A legacy mode on IRQ selection, then HCR register (base address + 4) bit 3 is effective on selecting IRQ. =1 Disable UART A legacy mode on IRQ selection, then HCR register (base address + 4) bit 3 is not effective on selecting IRQ. DSUBLGRQ => =0 Enable UART B legacy mode on IRQ selection, then HCR register (base address + 4) bit 3 is effective on selecting IRQ. =1 Disable UART B legacy mode on IRQ selection, then HCR register (base address + 4) bit 3 is not effective on selecting IRQ. 1 R/W 0 R/W CR 27h. (Reserved) CR 28h. (Global Option; Default 50h) Bit Read / Write Description 7 Reserved. Flash ROM size select = 00 1M = 01 2M 6~5 R/W = 10 4M (Default) = 11 8M Select to enable/disable decoding of BIOS ROM range 000E xxxxh. 4 R/W =0 Enable decoding of BIOS ROM range at 000E xxxxh. =1 Disable decoding of BIOS ROM range at 000E xxxxh. Select to enable/disable decoding of BIOS ROM range FFFE xxxxh. 3 R/W =0 Enable decoding of BIOS ROM range at FFFE xxxxh. =1 Disable decoding of BIOS ROM range at FFFE xxxxh. PRTMODS2 ~ 0 => 2~0 R/W = 0xx Parallel Port Mode. = 1xx Reserved. CR 29h. (OVT#/HM_SMI#, UART A, Game port & MIDI pin select; Default 04h) Bit Read / Write Description 7 Reserved. PIN5 function select 6 R/W =0 PIN5 OVT# HM_SMI#. =1 PIN5 5~4 Reserved. PIN49~54,56~57 function select 3 R/W UART A. =0 PIN49~54,56~57 GPIO6. =1 PIN49~54,56~57 Publication Release Date: Mar 2005 Revision 0.6 - 86 - W83627EHF/W83627EHG Preliminary PIN119~120 function select Bit-2 Bit-1 PIN119~PIN120 function 0 0 PIN 119~120 CPUFANIN1, CPUFANOUT1 0 1 PIN 119~120 GP21, GP20 1 x PIN 119~120 MSI, MSO (Default) PIN121~128 function select Game Port. =0 PIN121~128 =1 PIN121~128 GPIO1. 2~1 R/W 0 R/W CR 2Ah. (I2C pin select; Default 00h) Bit Read / Write Description 7~6 Reserved. Serial flash interface configuration register.(VBAT) =0 Normal mode. 5 R/W =1 Extend dummy cycle mode. Note: The bit will be ignored while CR24 bit-1 is low. (VSB Power) 4 3~2 1 R/W Reserved. R/W Serial flash interface configuration register.(VBAT) =0 Normal mode. =1 Fast mode. Note: The bit will be ignored while CR24 bit-1 is low. 0 R/W PIN89, PIN90 function select (I2C interafce) =0 {PIN89, PIN90} set by CR2C[6:5]. =1 {PIN89, PIN90} SDA, SCL. KB, MS pin function select =0 KB, MS function. =1 GPIO function. CR 2Bh. (Reserved) CR 2Ch. (GPIO3, GPIO4 multi-function selection; Default 00h) Bit Read / Write Description PIN88 Select 7 R/W =0 PIN88 GP34 =1 PIN88 RSTOUT4# PIN89 Select =0 PIN89 GP33 6 R/W =1 PIN89 RSTOUT3# Note: The bit will be ignored while CR2A bit-1 is High. (VSB Power) 5 4 R/W Reserved PIN90 Select =0 PIN90 =1 PIN90 GP32 RSTOUT2# Note: The bit will be ignored while CR2A bit-1 is High. Publication Release Date: Mar 2005 Revision 0.6 - 87 - W83627EHF/W83627EHG Preliminary Bit 3 Read / Write R/W 2 R/W Description EN_VRM10 Configure bit =0 VID input voltage is TTL. =1 VID input voltage is VRM10. The bit is strapping by PIN77 (GP50).--- Pull high to 3VSB. EN_PWRDN. (VBAT) =0 Thermal shutdown function is disabled. =1 Enable thermal shutdown function. PIN78~85 function select Bit-1 Bit-0 PIN78~PIN85 function Reserved PIN82 0 0 Reserved PIN83 GPIO4 Others IRRX PIN82 0 1 IRTX PIN83 GPIO4 Others 1 0 PIN 78~85 GPIO4 1 1 PIN 78~85 UART B 1~0 R/W CR 2Dh. (GPIO5 and power control signals multi-function selection; default 21h) (VSB Power) Bit Read / Write Description PIN67 Select (reset by RSMRST#) 7 R/W =0 PIN67 PSOUT# =1 PIN67 GPIO57 PIN68 Select (reset by RSMRST#) 6 R/W =0 PIN68 PSIN =1 PIN68 GPIO56 PIN70 Select (reset by RSMRST#) 5 R/W =0 PIN70 SUSLED =1 PIN70 GPIO55 PIN71 Select (reset by RSMRST#) 4 R/W =0 PIN71 PWROK =1 PIN71 GPIO54 PIN72 Select (reset by RSMRST#) 3 R/W =0 PIN72 PSON# =1 PIN72 GPIO53 PIN73 Select (reset by RSMRST#) 2 R/W =0 PIN73 SUSB# =1 PIN73 GPIO52 PIN75 Select (reset by RSMRST#) 1 R/W =0 PIN75 RSMRST# =1 PIN75 GPIO51 Publication Release Date: Mar 2005 Revision 0.6 - 88 - W83627EHF/W83627EHG Preliminary 0 R/W PIN77 Select (reset by RSMRST#) =0 PIN77 WDTO# =1 PIN77 GPIO50 CR 2Eh. (Default 00h) Bit Read / Write 7~0 R/W Description Test Mode Bits: Reserved for Winbond. CR 2Fh. (Default 00h) Bit Read / Write 7~0 R/W Description Test Mode Bits: Reserved for Winbond. Publication Release Date: Mar 2005 Revision 0.6 - 89 - W83627EHF/W83627EHG Preliminary 7.2 Logical Device 0 (FDC) CR 30h. (Default 01h) Bit Read / Write 7~1 Reserved. 0 R/W 0: Logical device is inactive. 1: Activate the logical device. Description CR 60h, 61h. (Default 03h,F0h) Bit Read / Write Description These two registers select FDC I/O base address <100h : FF8h> on 8 7~0 R/W bytes boundary. CR 70h. (Default 06h) Bit Read / Write 7~4 Reserved. 3~0 R/W CR 74h. (Default 02h) Bit Read / Write 7~3 Reserved. 2~0 R/W Description These bits select IRQ resource for FDC. Description These bits select DRQ resource for FDC. 000: DMA0. 001: DMA1. 010: DMA2. 1xx: No DMA active. 011: DMA3. CR F0h. (Default 8Eh) Bit Read / Write 7 R/W 6 5 4 3~2 1 0 R/W R/W R/W R/W R/W R/W Description This bit controls the internal pull-up resistors of the FDC input pins RDATA#, INDEX#, TRAK0#, DSKCHG# and WP#. 0: The internal pull-up resistors of FDC are turned on. 1: The internal pull-up resistors of FDC are turned off. (Default) This bit determines the polarity of all FDD interface signals. 0: FDD interface signals are active low. 1: FDD interface signals are active high. When this bit is logic 0, indicates a second drive is installed and is reflected in status register A. (PS2 mode only) Swap Drive 0, 1 Mode => 0: No Swap. 1: Drive and Motor select 0 and 1 are swapped. Interface Mode. 00: Model 30. 01: PS/2. 10: Reserved. 11: AT Mode FDC DMA Mode. 0: Burst Mode is enabled 1: Non-Burst Mode. Floppy Mode. 0: Normal Floppy Mode. 1: Enhanced 3-mode FDD. Publication Release Date: Mar 2005 Revision 0.6 - 90 - W83627EHF/W83627EHG Preliminary CR F1h. (Default 00h) Bit Read / Write 7~6 5~4 3~2 R/W R/W R/W 1 R/W 0 R/W Description 00: FDD A. 01: FDD B. 10: FDD C. 11: FDD D. Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7, 6. Density Select. 00: Normal. 01 Normal. 10: 1 (Forced to logic 1). 11: 0 (Forced to logic 0). DISFDDWR => 0: Enable FDD write. 1: Disable FDD write (forces pins WE, WD stay high). SWWP => 0: Normal, use WP to determine whether the FDD is write protected or not. 1: FDD is always write-protected. Boot Floppy. CR F2h. (Default FFh) Bit Read / Write 7~6 R/W 5~4 R/W 3~2 R/W 1~0 R/W CR F4h. (Default 00h) Bit Read / Write 7 Reserved. 6 5 4~3 2 1~0 R/W Reserved. R/W Reserved. R/W Description FDD D Drive Type. FDD C Drive Type. FDD B Drive Type. FDD A Drive Type. Description 0: Enable FDC Pre-compensation. 1: Disable FDC Pre-compensation. Data Rate Table selection (Refer to TABLE A). 00: Select regular drives and 2.88 format. 01: 3-mode drive. 10: 2 Meg Tape. 11: Reserved. Drive Type selection (Refer to TABLE B). CR F5h. (Default 00h) Bit Read / Write 7~0 R/W Description Same as FDD0 of CR F5h. Publication Release Date: Mar 2005 Revision 0.6 - 91 - W83627EHF/W83627EHG Preliminary TABLE A Drive Rate Table Select DRTS1 DRTS0 Data Rate DRATE1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 2Meg 250K --125K 0 0 1 0 1 0 500K 250K 1Meg 500K 250K 125K --250K 0 0 1 1 1 0 1 0 300K 250K 1Meg 500K 150K 125K --250K 0 0 1 1 Selected Data Rate SELDEN MFM 1Meg 500K DRATE0 1 0 FM --250K 1 1 TABLE B DTYPE0 DTYPE1 DRVDEN0 (pin 2) DRVDEN1 (pin 3) DRIVE TYPE 4/2/1 MB 3.5"" 0 0 SELDEN DRATE0 2/1 MB 5.25" 2/1.6/1 MB 3.5" (3-MODE) 0 1 1 1 0 1 DRATE1 SELDEN DRATE0 DRATE0 DRATE0 DRATE1 Publication Release Date: Mar 2005 Revision 0.6 - 92 - W83627EHF/W83627EHG Preliminary 7.3 Logical Device 1 (Parallel Port) CR 30h. (Default 01h) Bit Read / Write 7~1 Reserved. 0 R/W 0: Logical device is inactive. 1: Activate the logical device. Description CR 60h, 61h. (Default 03h, 78h) Bit Read / Write Description These two registers select PRT I/O base address. <100h : FFCh> on 4 bytes boundary (EPP not supported) or 7~0 R/W <100h : FF8h> on 8 bytes boundary (all modes supported, EPP is only available when the base address is on 8 byte boundary). CR 70h. (Default 07h) Bit Read / Write 7~4 Reserved. 3~0 R/W CR 74h. (Default 04h) Bit Read / Write 7~3 Reserved. 2~0 R/W Description These bits select IRQ resource for PRT. Description These bits select DRQ resource for PRT. 000: DMA0. 001: DMA1. 010: DMA2. 1xx: No DMA active. 011: DMA3. CR F0h. (Default 3Fh) Bit Read / Write 7 Reserved. 6~3 R/W Description ECP FIFO Threshold. Parallel Port Mode selection (CR28 bit2 PRTMODS2 = 0). 000: Standard and Bi-direction (SPP) mode. 001: EPP - 1.9 and SPP mode. 010: ECP mode. 011: ECP and EPP - 1.9 mode. 100: Printer Mode. 101: EPP - 1.7 and SPP mode. 110: Reserved. 111: ECP and EPP - 1.7 mode. 2~0 R/W Publication Release Date: Mar 2005 Revision 0.6 - 93 - W83627EHF/W83627EHG Preliminary 7.4 Logical Device 2 (UART A) CR 30h. (Default 01h) Bit Read / Write 7~1 Reserved. 0 R/W 0: Logical device is inactive. 1: Activate the logical device. Description CR 60h, 61h. (Default 03h, F8h) Bit Read / Write Description These two registers select Serial Port 1 I/O base address <100h : FF8h> 7~0 R/W on 8 bytes boundary. CR 70h. (Default 04h) Bit Read / Write 7~4 Reserved. 3~0 R/W CR F0h. (Default 00h) Bit Read / Write 7~2 Reserved. 1~0 R/W Description These bits select IRQ resource for Serial Port 1. Description 00: UART A clock source is 1.8462 MHz (24 MHz / 13). 01: UART A clock source is 2 MHz (24 MHz / 12). 00: UART A clock source is 24 MHz (24 MHz / 1). 00: UART A clock source is 14.769 MHz (24 MHz / 1.625). Publication Release Date: Mar 2005 Revision 0.6 - 94 - W83627EHF/W83627EHG Preliminary 7.5 Logical Device 3 (UART B) CR 30h. (Default 01h) Bit Read / Write 7~1 Reserved. 0 R/W 0: Logical device is inactive. 1: Activate the logical device. Description CR 60h, 61h. (Default 02h, F8h) Bit Read / Write Description These two registers select Serial Port 2 I/O base address <100h : FF8h> 7~0 R/W on 8 bytes boundary. CR 70h. (Default 03h) Bit Read / Write 7~4 Reserved. 3~0 R/W CR F0h. (Default 00h) Bit Read / Write 7~4 Reserved. 3 R/W Description These bits select IRQ resource for Serial Port 2. Description 0: No reception delay when SIR is changed from TX mode to RX mode. 1: Reception delay 4 characters-time (40 bit-time) when SIR is changed from TX mode to RX mode. 0: No transmission delay when SIR is changed from RX mode to TX mode. 1: Transmission delay 4 characters-time (40 bit-time) when SIR is changed from RX mode to TX mode. 00: UART B clock source is 1.8462 MHz (24 MHz / 13). 01: UART B clock source is 2 MHz (24 MHz / 12). 00: UART B clock source is 24 MHz (24 MHz / 1). 00: UART B clock source is 14.769 MHz (24 MHz / 1.625). 2 R/W 1~0 R/W Publication Release Date: Mar 2005 Revision 0.6 - 95 - W83627EHF/W83627EHG Preliminary CR F1h. (Default 00h) Bit Read / Write 7 R/W 6 5~3 2 R/W R/W R/W 1 R/W 0 R/W Description Reserved. IRLOCSEL => IR I/O pins' location selection. 0: Through SINB / SOUTB. 1: Through IRRX / IRTX. IRMODE => IR function mode selection. See below table. IR half / full duplex function selection. 0: IR function is Full Duplex. 1: IR function is Half Duplex. 0: SOUTB pin of UART B function or IRTX pin of IR function in normal condition. 1: Inverse SOUTB pin of UART B function or IRTX pin of IR function. 0: SINB pin of UART B function or IRRX pin of IR function in normal condition. 1: Inverse SINB pin of UART B function or IRRX pin of IR function. IR MODE 00X 010* 011* 100 101 110 111* IR FUNCTION Disable IrDA IrDA ASK-IR ASK-IR ASK-IR ASK-IR IRTX Tri-state Active pulse 1.6 S Active pulse 3/16 bit time Inverting IRTX/SOUTB pin Inverting IRTX/SOUTB & 500 KHZ clock Inverting IRTX/SOUTB Inverting IRTX/SOUTB & 500 KHZ clock IRRX High Demodulation into SINB/IRRX Demodulation into SINB/IRRX Routed to SINB/IRRX Routed to SINB/IRRX Demodulation into SINB/IRRX Demodulation into SINB/IRRX Note: The notation is normal mode in the IR function. Publication Release Date: Mar 2005 Revision 0.6 - 96 - W83627EHF/W83627EHG Preliminary 7.6 Logical Device 5 (Keyboard Controller) CR 30h. (Default 01h) Bit Read / Write 7~1 Reserved. 0 R/W 0: Logical device is inactive. 1: Activate the logical device. Description CR 60h, 61h. (Default 00h,60h) Bit Read / Write Description These two registers select the first KBC I/O base address <100h : FFFh> 7~0 R/W on 1 byte boundary. CR 62h, 63h. (Default 00h,64h) Bit Read / Write Description These two registers select the second KBC I/O base address <100h : 7~0 R/W FFFh> on 1 byte boundary. CR 70h. (Default 01h) Bit Read / Write 7~4 Reserved. 3~0 R/W CR 72h. (Default 0Ch) Bit Read / Write 7~4 Reserved. 3~0 R/W CR F0h. (Default83h) Bit Read / Write KBC clock rate selection 00: 6MHz 01: 8MHz 10: 12MHz 11: 16MHz 0: Port 92 disable. 1: Port 92 enable. 0: Gate A20 software control. 1: Gate A20 hardware speed up. 0: KBRST software control. 1: KBRST hardware speed up. Description These bits select IRQ resource for KINT. (Keyboard interrupt) Description These bits select IRQ resource for MINT. (PS/2 Mouse interrupt) Description 7~6 R/W 5~3 2 1 0 Reserved. R/W R/W R/W Publication Release Date: Mar 2005 Revision 0.6 - 97 - W83627EHF/W83627EHG Preliminary 7.6 Logical Device 6 (Serial Flash Interface) CR 30h. (Default 00h) Bit Read / Write 7~1 Reserved. 1 0 R/W Reserved. Description 0: Serial Flash Interface is inactive. 1: Activate Serial Flash Interface. CR 62h, 63h. (Default 00h) Bit Read / Write Description These two registers select Serial Flash Interface I/O base address <100h : 7~0 R/W FF8h> on 1 byte boundary. Publication Release Date: Mar 2005 Revision 0.6 - 98 - W83627EHF/W83627EHG Preliminary 7.7 Logical Device 7 (GPIO1, GPIO6, Game Port & MIDI Port) CR 30h. (Default 00h) Bit Read / Write 7~4 Reserved. 3 R/W 2 R/W 1 R/W 0 R/W Description 0: GPIO6 is inactive. 0: MIDI Port is inactive. 0: Game Port is inactive. 0: GPIO1 is inactive. 1: Activate GPIO6. 1: Activate MIDI Port. 1: Activate Game Port. 1: Activate GPIO1. CR 60h, 61h. (Default 02h, 01h) Bit Read / Write Description These two registers select Game Port base address <100h : FFFh> on 1 7~0 R/W byte boundary. CR 62h, 63h. (Default 03h, 30h) Bit Read / Write Description These two registers select MIDI Port base address <100h : FFEh> on 2 7~0 R/W bytes boundary. CR 70h. (Default 09h) Bit Read / Write 7~4 Reserved. 3~0 R/W Description These bits select IRQ resource for MIDI Port. CR F0h. (GPIO1 I/O register; Default FFh) Bit Read / Write Description GPIO1 I/O register 7~0 R/W 0: The respective GPIO1 PIN is programmed as an Output port 1: The respective GPIO1 PIN is programmed as an Input port. CR F1h. (GPIO1 Data register; Default 00h) Bit Read / Write Description GPIO1 Data register R/W For Output ports, the respective bits can be read/written and produced to 7~0 pins. For Input ports, the respective bits can be read only from pins. Write Read Only accesses will be ignored. CR F2h. (GPIO1 Inversion register; Default 00h) Bit Read / Write Description GPIO1 Inversion register 0: The respective bit and the port value are the same. 7~0 R/W 1: The respective bit and the port value are inverted. (Both Input & Output ports) Publication Release Date: Mar 2005 Revision 0.6 - 99 - W83627EHF/W83627EHG Preliminary CR F3h. (GPIO1 I/O register; Default 00h) Bit Read / Write 0: GPIO17 7 R/W 1: GPIO17 PLED 0: GPIO16 6 R/W 1: GPIO16 WDTO# 0: GPIO15 5 R/W 1: GPIO15 PLED 0: GPIO14 4 R/W 1: GPIO14 WDTO# 0: GPIO13 3 R/W 1: GPIO13 PLED 0: GPIO12 2 R/W 1: GPIO12 WDTO# 0: GPIO11 1 R/W PLED 1: GPIO11 0: GPIO10 0 R/W WDTO# 1: GPIO10 Description CR F4h. (GPIO6 I/O register; Default FFh) Bit Read / Write Description GPIO6 I/O register 7~0 R/W 0: The respective GPIO6 PIN is programmed as an Output port 1: The respective GPIO6 PIN is programmed as an Input port. CR F5h. (GPIO6 Data register; Default 00h) Bit Read / Write Description GPIO6 Data register R/W For Output ports, the respective bits can be read/written and produced to 7~0 pins. For Input ports, the respective bits can be read only from pins. Write Read Only accesses will be ignored. CR F6h. (GPIO6 Inversion register; Default 00h) Bit Read / Write Description GPIO6 Inversion register 0: The respective bit and the port value are the same. 7~0 R/W 1: The respective bit and the port value are inverted. (Both Input & Output ports) CR F7h. (Game Port PAD control register; Default 00h) Bit Read / Write Description 7~1 Reserved. Publication Release Date: Mar 2005 Revision 0.6 - 100 - W83627EHF/W83627EHG Preliminary 0 R/W Joystick Power Down 0: Joystick Power Down Disable. 1: Joystick Power Down Enable. Publication Release Date: Mar 2005 Revision 0.6 - 101 - W83627EHF/W83627EHG Preliminary 7.8 Logical Device 8 (WDTO# & PLED) CR 30h. (Default 00h) Bit Read / Write 7~1 Reserved. 0 R/W Description 0: WDTO# is inactive. 1: Activate WDTO#. CR F5h. (WDTO#, PLED and KBC P20 control mode register; Default 00h) Bit Read / Write Description Select Power LED mode. 00: Power LED pin is tri-stated. 01: Power LED pin is driven low. 7~6 R/W 10: Power LED pin outputs 1Hz pulse with 50% duty cycle. 11: Power LED pin outputs 1/4Hz pulse with 50% duty cycle. 5 Reserved. Faster 1000 times for WDTO# count mode. 0: Disable. 4 R/W 1: Enable. (If bit-3 is Second Mode , the count mode be 1/1000 Sec.) (If bit-3 is Minute Mode , the count mode be 1/1000 Min.) Select WDTO# count mode. 3 R/W 0: Second Mode. 1: Minute Mode. Enable the rising edge of KBC reset (P20) to issue time-out event. 2 R/W 0: Disable. 1: Enable. Disable / Enable the WDTO# output low pulse to the KBRST# pin (PIN60) 1 R/W 0: Disable. 1: Enable. 0 Reserved. CR F6h. (WDTO# counter register; Default 00h) Bit Read / Write Description Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load the value to Watch Dog Counter and start counting down. If the bit 7 and 6 of CR F7h are set, any Mouse Interrupt or Keyboard Interrupt event will also cause the reload of previously-loaded non-zero value to Watch Dog Counter and start counting down. Reading this register returns current value 7~0 R/W in Watch Dog Counter instead of Watch Dog Timer Time-out value. 00h: Time-out Disable 01h: Time-out occurs after 1 second/minute 02h: Time-out occurs after 2 second/minutes 03h: Time-out occurs after 3 second/minutes .................................................................. FFh: Time-out occurs after 255 second/minutes Publication Release Date: Mar 2005 Revision 0.6 - 102 - W83627EHF/W83627EHG Preliminary CR F7h. (WDTO# control & status register; Default 00h) Bit Read / Write Description Mouse interrupt reset watch-dog timer enable 7 R/W 0: Watchdog timer is not affected by mouse interrupt. 1: Watchdog timer is reset by mouse interrupt. Keyboard interrupt reset watch-dog timer enable 6 R/W 0: Watchdog timer is not affected by keyboard interrupt. 1: Watchdog timer is reset by keyboard interrupt. 5 Write "1" Only Trigger WDTO# event. This bit is self-clearing. WDTO# status bit 4 R/W 0: Watchdog timer is running. 1: Watchdog timer issues time-out event. 3~0 R/W These bits select IRQ resource for WDTO#. (02h for SMI# event.) Publication Release Date: Mar 2005 Revision 0.6 - 103 - W83627EHF/W83627EHG Preliminary 7.9 Logical Device 9 (GPIO2,GPIO3, GPIO4, GPIO5 & SUSLED) (VSB Power) CR 30h. (Default 00h) Bit Read / Write 7~4 Reserved. 3 R/W 2 R/W 1 R/W 0 R/W Description 0: GPIO5 is inactive. 0: GPIO4 is inactive. 0: GPIO3 is inactive. 0: GPIO2 is inactive. 1: Activate GPIO5 1: Activate GPIO4. 1: Activate GPIO3. 1: Activate GPIO2. CR E0h. (GPIO5 I/O register; Default FFh) Bit Read / Write Description GPIO5 I/O register 7~0 R/W 0: The respective GPIO5 PIN is programmed as an Output port 1: The respective GPIO5 PIN is programmed as an Input port. CR E1h. (GPIO5 Data register; Default 00h) Bit Read / Write Description GPIO5 Data register R/W For Output ports, the respective bits can be read/written and produced to pins. 7~0 For Input ports, the respective bits can be read only from pins. Write Read Only accesses will be ignored. CR E2h. (GPIO5 Inversion register; Default 00h) Bit Read / Write Description GPIO5 Inversion register 0: The respective bit and the port value are the same. 7~0 R/W 1: The respective bit and the port value are inverted. (Both Input & Output ports) CR E3h. (GPIO2 register; Default FFh) Bit Read / Write Description GPIO2 I/O register 7~0 R/W 0: The respective GPIO2 PIN is programmed as an Output port 1: The respective GPIO2 PIN is programmed as an Input port CR E4h. (GPIO2 Data register; Default 00h) Bit Read / Write Description GPIO2 Data register R/W For Output ports, the respective bits can be read/written and produced to 7~0 pins. For Input ports, the respective bits can be read only from pins. Write Read Only accesses will be ignored. Publication Release Date: Mar 2005 Revision 0.6 - 104 - W83627EHF/W83627EHG Preliminary CR E5h. (GPIO2 Inversion register; Default 00h) Bit Read / Write Description GPIO2 Inversion register 0: The respective bit and the port value are the same. 7~0 R/W 1: The respective bit and the port value are inverted. (Both Input & Output ports) CR F0h. (GPIO3 I/O register; Default FFh) Bit Read / Write Description GPIO3 I/O register 7~0 R/W 0: The respective GPIO3 PIN is programmed as an Output port 1: The respective GPIO3 PIN is programmed as an Input port. CR F1h. (GPIO3 Data register; Default 00h) Bit Read / Write Description GPIO3 Data register R/W For Output ports, the respective bits can be read/written and produced to 7~0 pins. For Input ports, the respective bits can be read only from pins. Write Read Only accesses will be ignored. CR F2h. (GPIO3 Inversion register; Default 00h) Bit Read / Write Description GPIO3 Inversion register 0: The respective bit and the port value are the same. 7~0 R/W 1: The respective bit and the port value are inverted. (Both Input & Output ports) CR F3h. (Suspend LED mode register; Default 00h) (VBAT power) Bit Read / Write Description Select Suspend LED mode. 00: Suspend LED pin is tri-stated. 7~6 R/W 01: Suspend LED pin is driven low. 10: Suspend LED pin outputs 1Hz pulse with 50% duty cycle. 11: Suspend LED pin outputs 1/4Hz pulse with 50% duty cycle. 5~0 Reserved. CR F4h. (GPIO4 I/O register; Default FFh) Bit Read / Write Description GPIO4 I/O register 7~0 R/W 0: The respective GPIO4 PIN is programmed as an Output port 1: The respective GPIO4 PIN is programmed as an Input port. CR F5h. (GPIO4 Data register; Default 00h) Bit Read / Write Description GPIO4 Data register 7~0 R/W For Output ports, the respective bits can be read/written and produced to pins. Publication Release Date: Mar 2005 Revision 0.6 - 105 - W83627EHF/W83627EHG Preliminary For Input ports, the respective bits can be read only from pins. Write accesses will be ignored. CR F6h. (GPIO4 Inversion register; Default 00h) Bit Read / Write Description GPIO4 Inversion register 0: The respective bit and the port value are the same. 7~0 R/W 1: The respective bit and the port value are inverted. (Both Input & Output ports) Read Only CR F7h. (GPIO4 multi-function select register; Default 00h) Bit Read / Write Description 0: GPIO47 7 R/W 1: GPIO47 SUSLED 0: GPIO46 6 R/W 1: GPIO46 WDTO# 0: GPIO45 5 R/W 1: GPIO45 SUSLED 0: GPIO44 4 R/W WDTO# 1: GPIO44 0: GPIO43 3 R/W SUSLED 1: GPIO43 0: GPIO42 2 R/W 1: GPIO42 WDTO# 0: GPIO41 1 R/W 1: GPIO41 SUSLED 0: GPIO40 0 R/W 1: GPIO40 WDTO# Publication Release Date: Mar 2005 Revision 0.6 - 106 - W83627EHF/W83627EHG Preliminary 7.10 Logical Device A (ACPI) (CR30, CR70 are VCC powered; CRE0~F7 are VRTC powered) CR 30h. (Default 00h) Bit Read / Write 7~1 Reserved. 0 R/W 0: Logical device is inactive. 1: Activate the logical device. Description CR 70h. (Default 00h) Bit Read / Write 7~4 Reserved. 3~0 R/W Description These bits select IRQ resource for PME#. CR E0h. (Default 01h) (VBAT power) Bit Read / Write Description DIS_PSIN => Disable panel switch input to turn system power supply on. 7 R/W 0: PSIN is wire-AND and connected to PSOUT#. 1: PSIN is blocked and cannot affect PSOUT#. Enable KBC wake-up 6 R/W 0: Disable keyboard wake-up function via PSOUT#. 1: Enable keyboard wake-up function via PSOUT#. Enable Mouse wake-up 5 R/W 0: Disable mouse wake-up function via PSOUT#. 1: Enable mouse wake-up function via PSOUT#. MSRKEY => 3 keys (ENMDAT_UP, CRE6[7]; MSRKEY, CRE0[4]; MSXKEY, CRE0[1]) define the combinations of the mouse wake-up events. Please check out the following table for the detailed. ENMDAT_UP MSRKEY MSXKEY Wake-up event 1 4 R/W 1 0 0 0 0 3 2 Reserved. R/W x x 0 1 0 1 1 0 1 1 0 0 Any button clicked or movement. One click of either left or right MS button. One click of the MS left button. One click of the MS right button. Two clicks of the MS left button. Two clicks of the MS right button. Keyboard / Mouse swap enable 0: Normal mode. 1: Keyboard / Mouse ports are swapped. Publication Release Date: Mar 2005 Revision 0.6 - 107 - W83627EHF/W83627EHG Preliminary 1 R/W MSXKEY => 3 keys (ENMDAT_UP, CRE6[7]; MSRKEY, CRE0[4]; MSXKEY, CRE0[1]) define the combinations of the mouse wake-up events. Please check out the table in CRE0[4] for the detailed. KBXKEY => 0: Only the pre-determined key combination in sequence can wake up the system. 1: Any character received from keyboard can wake up the system. 0 R/W CR E1h. (KBC Wake-Up Index Register; Default 00h) (VSB power) Bit Read / Write Description Keyboard wake-up index register. It is the index register of CRE2, which is the access window of keyboard pre-determined key combination characters. The first set of wake up key 7~0 R/W combination is in the range of 0x00 - 0x0E, the second set 0x30 - 0x3E, and the third set 0x40 - 0x4E. Incoming key combination can be read through 0x10 - 0x1E. CR E2h. (KBC Wake-Up Data Register; Default ffh) (VSB power) Bit Read / Write Description Keyboard wake-up data register. 7~0 R/W It is the data register of the keyboard pre-determined key combination characters, which is indexed by CRE1. CR E3h. (Event Status Register; Default 08h) Bit Read / Write Description 7~6 Reserved. Read Only 5 This event status is caused by VSB power off/on. Read-Clear If E4[7] is 1 => This bit is 0: When power-loss occurs and VSB power is on, indicate that Read Only turn on system power. 4 This bit is 1: When power-loss occurs and VSB power is on, indicate that Read-Clear turn off system power. If E4[7] is 0 => This bit is always 0. Thermal shutdown status. Read Only 0: No thermal shutdown event issued. 3 Read-Clear 1: The thermal shutdown event issued. PSIN_STS Read Only 2 0: No PSIN event issued. Read-Clear 1: The PSIN event issued. MSWAKEUP_STS => The bit is latched by the mouse wake-up event. Read Only 1 0: No mouse wake-up event issued. Read-Clear 1: The mouse wake-up event issued. KBWAKEUP_STS => The bit is latched by the keyboard wake-up event. Read Only 0 0: No keyboard wake-up event issued. Read-Clear 1: The keyboard wake-up event issued. Publication Release Date: Mar 2005 Revision 0.6 - 108 - W83627EHF/W83627EHG Preliminary CR E4h. (Default 00h) Bit Read / Write 7 R/W 6~5 R/W Description Disable / Enable power loss control function (LDA: CRE4[6:5]) for Intel chipset. (VBAT) 0: Disable. 1: Enable. Power loss control bits => (VBAT) 00: System always turns off when come back from power loss state. 01: System always turns on when come back from power loss state. 10: System turns off / on when come back from power loss state depend on the state before power loss. 11: User define the state before power loss.(The last state set at CRE6[4]) Keyboard wake-up options. (LRESET#) 0: Password or sequence hot keys programmed in the registers. 1: Any key. Enable the hunting mode for all wake-up events set in CRE0. This bit is cleared when any wake-up events is captured. (LRESET#) 0: Disable. 1: Enable. 4 3 Reserved R/W 2 1~0 R/W Reserved. CR E5h. (Reserved) Bit Read / Write 7~0 Reserved. CR E6h. (Default 00h) Bit Read / Write 7 6 5 4 R/W Reserved. R/W R/W Description Description ENMDAT => (VSB) 3 keys (ENMDAT_UP, CRE6[7]; MSRKEY, CRE0[4]; MSXKEY, CRE0[1]) define the combinations of the mouse wake-up events. Please check out the table in CRE0[4] for the detailed. CASEOPEN Clear Control. (VSB) Write 1 to this bit will clear CASEOPEN status. Powerloss Last State Flag. (VBAT) 0: ON 1: OFF. PWROK_DEL (first stage) (VSB) Set the delay rising time from PWROK_LP to PWROK_ST. 0: 300 ~ 600 ms. 1: 200 ~ 300 ms. PWROK_DEL (VSB) Set the delay rising time from PWROK_ST to POWEROK. 00: No delay time. 01: Delay 32 ms 10: 96 ms 11: Delay 250 ms 3 R/W 2~1 0 R/W Reserved. Publication Release Date: Mar 2005 Revision 0.6 - 109 - W83627EHF/W83627EHG Preliminary CR E7h. (Default 00h) Bit Read / Write Description ENKD3 => (VSB) Enable the third set of keyboard wake-up key combination. Its values are accessed through keyboard wake-up index register (CRE1) and keyboard wake-up data register (CRE2) at the index from 40h to 4eh. 0: Disable the third set of the key combinations. 1: Enable the third set of the key combinations. ENKD2 => (VSB) Enable the second set of keyboard wake-up key combination. Its values are accessed through keyboard wake-up index register (CRE1) and keyboard wake-up data register (CRE2) at the index from 30h to 3eh. 0: Disable the second set of the key combinations. 1: Enable the second set of the key combinations. ENWIN98KEY => (VSB) Enable Win98 keyboard dedicated key to wake-up system via PSOUT# when keyboard wake-up function is enabled. 0: Disable Win98 keyboard wake-up. 1: Enable Win98 keyboard wake-up. EN_ONPSOUT (VBAT) Disable/Enable to issue a 0.5s long PSOUT# pulse when system returns from power loss state and is supposed to be on as described in CRE4[6:5], logic device A. (for SiS & VIA chipsets) 0: Disable. 1: Enable. Select WDTO# reset source (VSB) 0: Watchdog timer is reset by LRESET#. 1: Watchdog timer is reset by POWEROK Hardware Monitor RESET source select (VBAT) 0: POWEROK 1: LRESET# 7 R/W 6 R/W 5 R/W 4 R/W 3 2~1 0 R/W Reserved. R/W CR E8h. (Reserved) CR F2h. (Default 7Ch) (VSB power) Bit Read / Write 7 Reserved. Enable RSTOUT4# function. 6 R/W 0: Disable RSTOUT4#. 1: Enable RSTOUT4#. Enable RSTOUT3# function. 5 R/W 0: Disable RSTOUT3#. 1: Enable RSTOUT3#. Enable RSTOUT2# function. 4 R/W 0: Disable RSTOUT2#. 1: Enable RSTOUT2#. Description Publication Release Date: Mar 2005 Revision 0.6 - 110 - W83627EHF/W83627EHG Preliminary 3 R/W Enable RSTOUT1# function. 0: Disable RSTOUT1#. 1: Enable RSTOUT1#. Enable RSTOUT0# function. 0: Disable RSTOUT0#. 1: Enable RSTOUT0#. EN_PME => 0: Disable PME. 1: Enable PME. 2 1 0 R/W Reserved. R/W CR F3h. (Default 00h) Bit Read / Write 7~6 Reserved. 5 4 3 2 1 0 R / W-Clear R / W-Clear R / W-Clear R / W-Clear R / W-Clear R / W-Clear Description PME status of the Mouse IRQ event. Write 1 to clear this status. PME status of the KBC IRQ event. Write 1 to clear this status. PME status of the PRT IRQ event. Write 1 to clear this status. PME status of the FDC IRQ event. Write 1 to clear this status. PME status of the URA IRQ event. Write 1 to clear this status. PME status of the URB IRQ event. Write 1 to clear this status. CR F4h. (Default 00h) Bit Read / Write 7~4 Reserved. 3 2 1 0 R / W-Clear R / W-Clear R / W-Clear R / W-Clear Description PME status of the HM IRQ event. Write 1 to clear this status. PME status of the WDTO# event. Write 1 to clear this status. PME status of the MIDI IRQ event. Write 1 to clear this status. PME status of the RIB event. Write 1 to clear this status. CR F6h. (Default 00h) (VSB power) Bit Read / Write Description 7~6 Reserved. 0: Disable PME interrupt of the Mouse IRQ event. 5 R/W 1: Enable PME interrupt of the Mouse IRQ event. 0: Disable PME interrupt of the KBC IRQ event. 4 R/W 1: Enable PME interrupt of the KBC IRQ event. 0: Disable PME interrupt of the PRT IRQ event. 3 R/W 1: Enable PME interrupt of the PRT IRQ event. 0: Disable PME interrupt of the FDC IRQ event. 2 R/W 1: Enable PME interrupt of the FDC IRQ event. Publication Release Date: Mar 2005 Revision 0.6 - 111 - W83627EHF/W83627EHG Preliminary 1 0 R/W R/W 0: Disable PME interrupt of the URA IRQ event. 1: Enable PME interrupt of the URA IRQ event. 0: Disable PME interrupt of the URB IRQ event. 1: Enable PME interrupt of the URB IRQ event. CR F7h. (Default 00h) (VSB power) Bit Read / Write Description 7~4 Reserved. 0: Disable PME interrupt of the HM IRQ event. 3 R/W 1: Enable PME interrupt of the HM IRQ event. 0: Disable PME interrupt of the WDTO# event. 2 R/W 1: Enable PME interrupt of the WDTO# event. 0: Disable PME interrupt of the MIDI IRQ event. 1 R/W 1: Enable PME interrupt of the MIDI IRQ event. 0: Disable PME interrupt of the RIB event. 0 R/W 1: Enable PME interrupt of the RIB event. Publication Release Date: Mar 2005 Revision 0.6 - 112 - W83627EHF/W83627EHG Preliminary 7.11 Logical Device B (Hardware Monitor) CR 30h. (Default 00h) Bit Read / Write 7~1 Reserved. 0 R/W 0: Logical device is inactive. 1: Activate the logical device. Description CR 60h, 61h. (Default 00h, 00h) Bit Read / Write Description These two registers select HM base address <100h : FFEh> on 2 bytes 7~0 R/W boundary. CR 70h. (Default 00h) Bit Read / Write 7~4 Reserved. 3~0 R/W Description These bits select IRQ resource for HM. CR F0h. (VID Control register; Default C1h) Bit Read / Write VID I/O Control (CRF1[5:0]) 7 R/W 0: VID output mode. 1: VID input mode. 6-0 Reserved. Description CR F1h. (VID Data Register; Default 00h) Bit Read / Write 7~6 Reserved. 5~0 R/W VID[5:0] Data Register. Description Publication Release Date: Mar 2005 Revision 0.6 - 113 - W83627EHF/W83627EHG Preliminary 8. DC SPECIFICATION 8.1 Absolute Maximum Ratings PARAMETER Power Supply Voltage (3.3V) Input Voltage RTC Battery Voltage VBAT Operating Temperature Storage Temperature RATING -0.5 to 6.5 -0.5 to VDD+0.5 2.2 to 4.0 0 to +70 -55 to +150 UNIT V V V C C of Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability the device. 8.2 DC CHARACTERISTICS (Ta = 0C to 70C, VDD = 3.3V 10%, VSS = 0V, VDD is 5V 10% tolerance) PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS RTC Battery Quiescent Current ACPI Stand-by Power Supply Quiescent Current IBAT IBAT 2.4 2.0 A mA VBAT = 2.5 V VSB = 3.3 V, All ACPI pins are not connected. I/O8t - TTL level bi-directional pin with 8mA source-sink capability Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V IOL = 8 mA IOH = - 8 mA VIN = 3.3V VIN = 0V A A I/O12t - TTL level bi-directional pin with 12mA source-sink capability Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V IOL = 12 mA IOH = -12 mA VIN = 3.3V VIN = 0V A A I/O24t - TTL level bi-directional pin with 24mA source-sink capability Input Low Voltage VIL 0.8 V Publication Release Date: Mar 2005 Revision 0.6 - 114 - W83627EHF/W83627EHG Preliminary Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 V V V IOL = 24 mA IOH = -24 mA VIN = 3.3V VIN = 0V A A I/O12tp3 - 3.3V TTL level bi-directional pin with 12mA source-sink capability Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V IOL = 12 mA IOH = -12 mA VIN = 3.3V VIN = 0V A A I/O12ts - TTL level Schmitt-trigger bi-directional pin with 12mA source-sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL VOH ILIH ILIL 2.4 +10 -10 0.5 1.6 0.5 0.8 2.0 1.2 0.4 1.1 2.4 V V V V V VDD=3.3V IOL = 12 mA IOH = -12 mA VIN = 3.3V VIN = 0V A A I/O24ts - TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL VOH ILIH ILIL 2.4 +10 -10 0.5 1.6 0.5 0.8 2.0 1.2 0.4 1.1 2.4 V V V V V VDD= 3.3V IOL = 24 mA IOH = -24 mA VIN = 3.3V VIN = 0V A A I/O24tsp3 - 3.3V TTL level Schmitt-trigger bi-directional pin with 24mA source-sink capability Input Low Threshold Voltage Vt0.5 0.8 1.1 V Publication Release Date: Mar 2005 Revision 0.6 - 115 - W83627EHF/W83627EHG Preliminary Input High Threshold Voltage Hystersis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage Vt+ VTH VOL VOH ILIH ILIL 2.4 +10 -10 1.6 0.5 2.0 1.2 0.4 2.4 V V V V VDD=3.3V IOL = 24 mA IOH = -24 mA VIN = 3.3V VIN = 0V A A I/OD12t - TTL level bi-directional pin and open-drain output with 12mA sink capability Input Low Voltage Input High Voltage Output Low Voltage Input High Leakage Input Low Leakage VIL VIH VOL ILIH ILIL 2.0 0.4 +10 -10 0.8 V V V IOL = 12 mA VIN = 3.3V VIN = 0V A A I/OD24t - TTL level bi-directional pin and open-drain output with 24mA sink capability Input Low Voltage Input High Voltage Output Low Voltage Input High Leakage Input Low Leakage VIL VIH VOL ILIH ILIL 2.0 0.4 +10 -10 0.8 V V V IOL = 24 mA VIN = 3.3V VIN = 0V A A I/OD12ts - TTL level Schmitt-trigger bi-directional pin and open drain output with 12mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 0.4 +10 -10 1.1 2.4 V V V V VDD=3.3V IOL = 12 mA VIN = 3.3V VIN = 0V A A I/OD24ts - TTL level Schmitt-trigger bi-directional pin and open drain output with 24mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis VtVt+ VTH 0.5 1.6 0.5 0.8 2.0 1.2 1.1 2.4 V V V VDD=3.3V Publication Release Date: Mar 2005 Revision 0.6 - 116 - W83627EHF/W83627EHG Preliminary Output Low Voltage Input High Leakage Input Low Leakage VOL ILIH ILIL 0.4 +10 -10 V IOL = 24 mA VIN = 3.3V VIN = 0V A A I/OD12cs - CMOS level Schmitt-trigger bi-directional pin and open drain output with 12mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 0.4 +10 -10 1.1 2.4 V V V V VDD = 3.3 V VDD = 3.3 V VDD = 3.3 V IOL = 12 mA VIN = 3.3 V VIN = 0 V A A I/OD16cs - CMOS level Schmitt-trigger bi-directional pin and open drain output with 16mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 0.4 +10 -10 1.1 2.4 V V V V VDD = 3.3 V VDD = 3.3 V VDD = 3.3 V IOL = 16 mA VIN = 3.3 V VIN = 0 V A A I/OD12csd - CMOS level Schmitt-trigger bi-directional pin with internal pull down resistor and open drain output with 12mA sink capability Input Low Threshold Voltage Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 0.4 +10 -10 1.1 2.4 V V V V VDD = 3.3 V VDD = 3.3 V VDD = 3.3 V IOL = 12 mA VIN = 3.3 V VIN = 0 V A A I/OD12csu - CMOS level Schmitt-trigger bi-directional pin with internal pull up resistor and open drain output with 12mA sink capability Input Low Threshold Voltage Vt0.5 0.8 1.1 V VDD = 3.3 V Publication Release Date: Mar 2005 Revision 0.6 - 117 - W83627EHF/W83627EHG Preliminary Input High Threshold Voltage Hystersis Output Low Voltage Input High Leakage Input Low Leakage Vt+ VTH VOL ILIH ILIL 1.6 0.5 2.0 1.2 0.4 +10 -10 2.4 V V V VDD = 3.3 V VDD = 3.3 V IOL = 12 mA VIN = 3.3 V VIN = 0 V IOL = 4 mA IOH = -4 mA IOL = 8 mA IOH = -8 mA IOL = 12 mA IOH = -12 mA IOL = 16 mA IOH = -16 mA IOL = 24 mA IOH = -24 mA A A V V O4 - Output pin with 4mA source-sink capability Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage VOL VOH VOL VOH VOL VOH VOL VOH VOL VOH 2.4 2.4 0.4 V V 2.4 0.4 2.4 0.4 2.4 0.4 0.4 O8 - Output pin with 8mA source-sink capability V V V V V V O12 - Output pin with 12mA source-sink capability O16 - Output pin with 16mA source-sink capability O24 - Output pin with 24mA source-sink capability O12p3 - 3.3V output pin with 12mA source-sink capability Output Low Voltage VOL 0.4 V IOL = 12 mA O24p3 - 3.3V output pin with 24mA source-sink capability Output Low Voltage Output Low Voltage Output Low Voltage Output Low Voltage VOL VOL VOL VOL 0.4 0.4 0.4 0.4 V V V V IOL = 24 mA IOL = 12 mA IOL = 24 mA IOL = 12 mA OD12 - Open drain output pin with 12mA sink capability OD24 - Open drain output pin with 24mA sink capability OD12p3 - 3.3V open drain output pin with 12mA sink capability INt - TTL level input pin Input Low Voltage Input High Voltage VIL VIH 2.0 0.8 V V Publication Release Date: Mar 2005 Revision 0.6 - 118 - W83627EHF/W83627EHG Preliminary Input High Leakage Input Low Leakage ILIH ILIL +10 -10 A A VIN = 3.3 V VIN = 0 V INtp3 - 3.3V TTL level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 2.0 +10 -10 0.8 V V A A VIN = 3.3V VIN = 0 V INtd - TTL level input pin with internal pull down resistor Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 2.0 +10 -10 0.8 V V A A VIN = 3.3 V VIN = 0 V INtu - TTL level input pin with internal pull up resistor Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage VIL VIH ILIH ILIL 2.0 +10 -10 0.8 V V A A VIN = 3.3 V VIN = 0 V INts - TTL level Schmitt-trigger input pin VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 +10 -10 1.1 2.4 V V V VDD = 3.3 V VDD = 3.3 V VDD = 3.3 V VIN = 3.3 V VIN = 0 V Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage A A INtsp3 - 3.3 V TTL level Schmitt-trigger input pin Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 +10 -10 1.1 2.4 V V V VDD = 3.3 V VDD = 3.3 V VDD = 3.3 V VIN = 3.3 V VIN = 0 V A A INc - CMOS level input pin VIL 1.5 V Publication Release Date: Mar 2005 Revision 0.6 Input Low Voltage - 119 - W83627EHF/W83627EHG Preliminary Input High Voltage Input High Leakage Input Low Leakage VIH ILIH ILIL 3.5 +10 -10 V A A VIN = 3.3V VIN = 0 V INcd - CMOS level input pin with internal pull down resistor VIL VIH ILIH ILIL 3.5 +10 -10 1.5 V V Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage A A VIN = 3.3V VIN = 0 V INcs - CMOS level Schmitt-trigger input pin VtVTH ILIH ILIL 1.3 1.5 1.5 2 +10 -10 1.7 V V VDD = 3.3V VDD = 3.3V VIN = 3.3V VIN = 0 V Input Low Threshold Voltage Hystersis Input High Leakage Input Low Leakage A A INcsu - CMOS level Schmitt-trigger input pin with internal pull up resistor VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 +10 -10 1.1 2.4 V V V VDD = 3.3V VDD = 3.3V VDD = 3.3V VIN = 3.3V VIN = 0 V Input Low Threshold Voltage Input High Threshold Voltage Hystersis Input High Leakage Input Low Leakage A A Publication Release Date: Mar 2005 Revision 0.6 - 120 - W83627EHF/W83627EHG Preliminary 9. HOW TO READ THE TOP MARKING Example: The top marking of W83627EHF/W83627EHG inbond W83627EHF 330G9A282012345UB inbond 330G9A282012345UB W83627EHG 1st line: Winbond logo 2nd line: the type number: W83627EHF, W83627EHG (Pb-free package) 3rd line: the tracking code 030A7C282012345UA 330: packages made in '03, week 30 G: assembly house ID; G means GR, A means ASE ... etc. 9: code version; 9 means code 009 A: IC revision; A means version A, B means version B 282012345: wafer production series lot number UB: Winbond internal use. Publication Release Date: Mar 2005 Revision 0.6 - 121 - W83627EHF/W83627EHG Preliminary 10. PACKAGE SPECIFICATION (128-pin PQFP) HE E 102 65 Symbol Min Dimension in mm Dimension in inch Nom 0.35 2.72 0.20 0.15 14.00 20.00 0.50 Max 0.45 2.87 0.30 0.20 14.10 20.10 Min 0.010 0.101 0.004 0.004 0.547 0.783 Nom 0.014 0.107 0.008 0.006 0.551 0.787 0.020 Max 0.018 0.113 0.012 0.008 0.555 0.791 103 64 D HD 128 39 1 e b 38 A1 A2 b c D E e HD HE L L1 y 0 c 0.25 2.57 0.10 0.10 13.90 19.90 17.00 23.00 0.65 17.20 23.20 0.80 1.60 17.40 23.40 0.95 0.669 0.905 0.025 0.677 0.913 0.031 0.063 0.685 0.921 0.037 0.08 0 7 0 0.003 7 Note: 1.Dimension D & E do not include interlead flash. 2.Dimension b does not include dambar protrusion/intrusion . 3.Controlling dimension : Millimeter 4.General appearance spec. should be based on final visual inspection spec. A A2 See Detail F Seating Plane A1 y L L1 Detail F 5. PCB layout please use the "mm". Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ Winbond Electronics Corporation America 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office 9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. APPENDIX A : DEMO CIRCUIT Publication Release Date: Mar 2005 Revision 0.6 - 122 - W83627EHF/W83627EHG Preliminary R89 IO3V R90 R91 4.7K 4.7K 4.7K SDA SCL GP31 GP30 RSTOUT1# RSTOUT0# VIN4 VIN3 VIN2 VIN1 VIN0 CPUVCORE VREF AUXTIN CPUTIN SYSTIN RSTOUT4# GP35 PME# RIB# DCDB# SOUTB SINB DTRB# RTSB# DSRB# CTSB# GP50 CASEOPEN# RSMRST# IOBAT SLP_S3# PWRCTL# PWROK SUSLED GP36 PSIN PSOUT# MDAT MCLK 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 L1 FB 2 2 2 2 3 3 2 4 4 4 4 4 4 4 4 2 7 2 7 7 7 7 7 7 7 7 7 IO3V U1 5,6 5,6 5,6 VID5 VID4 VID3 VID2 VID1 VID0 AUXFANIN0 CPUFANIN0 SYSFANIN AVCC AGND L2 FB AGND 7 R1 4.7K IO3V DRVDEN0 SCK/GP23 INDEX# MOA# OVT#/HM_SMI# DSA# AUXFANOUT DIR# STEP# WD# WE# 3VCC TRAK0# WP# RDATA# HEAD# DSKCHG# IOCLK SCE#/GP22 VSS PCICLK LDRQ# SERIRQ LAD3 LAD2 LAD1 LAD0 3VCC LFRAME# LRESET# SLCT PE BUSY ACK# PD7 PD6 PD5 PD4 5,6 CPUFANOUT0 5,6 SYSFANOUT 7 AGND 2 SI 3 MSI 3 MSO 3 GPSA2 3 GPSB2 3 GPY1 3 GPY2 3 GPX2 3 GPX1 3 GPSB1 3 GPSA1 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 AUXTIN0 VREF CPUVCORE VIN0 VIN1 VIN2 VIN3 VIN4 RSTOUT0# RSTOUT1# GP30 GP31 RSTOUT2#/GP32/SCL RSTOUT3#/GP33/SDA RSTOUT4#/GP34 GP35 PME# GP40/RIB# GP41/DCDB# GP42/IRTX/SOUTB GP43/IRRX/SINB GP44/DTRB# GP45/RTSB# GP46/DSRB# GP47/CTSB# WDTO#/GP50(EN_VRM10) CASEOPEN# GP51/RSMRST# VBAT GP52/SUSB# GP53/PSON# GP54/PWROK SUSLED/GP55 GP36 GP56/PSIN GP57/PSOUT# GP24/MDAT GP25/MCLK C1 0.1U CPUTIN SYSTIN VID5 VID4 VID3 VID2 VID1 VID0 AUXFANIN0 CPUFANIN0 SYSFANIN AVCC CPUFANOUT0 SYSFANOUT AGND BEEP/SI MSI/CPUFANIN1/GP21 MSO/CPUFANOUT1/GP20 GPSA2/GP17 GPSB2/GP16 GPY1/GP15 GPY2/GP14 GPX2/GP13 GPX1/GP12 GPSB1/GP11 GPSA1/GP10 W83627EHF GP37 GP26/KDAT GP27/KCLK 3VSB KBRST GA20M AUXFANIN1/SO GP60/RIA# GP61/DCDA# VSS GP62/SOUTA(PENKBC) GP63/SINA GP64/DTRA#(PENROM) GP65/RTSA#(HEFRAS) GP66/DSRA# GP67/CTSA# 3VCC STB# AFD# ERR# INIT# SLIN# PD0 PD1 PD2 PD3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 GP37 KDAT KCLK KBRST GA20M SO RIA# DCDA# SOUTA SINA DTRA# RTSA# DSRA# CTSA# STB# AFD# ERR# INIT# SLIN# 3 3 C2 2 4 4 2,4 4 2,4 2,4 4 4 4 4 4 4 4 0.1U IO3VSB IO3V C3 0.1U 3 DRVDEN0 2 SCK 3 INDEX# 3 MOA# OVT# 3 DSA# 5,6 AUXFANOUT 3 DIR# 3 STEP# 3 WD# 3 WE# 3 TRAK0# 2,3 WP# 3 RDATA# 3 HEAD# 3 DSKCHG# 2 SCE# U2 IO5V 14 VCC OSC48M 2 2 LPC INTERFACE O/P GND 8 7 PCICLK LDRQ# SERIRQ LAD[0..3] 2 LFRAME# LRESET# LAD[0..3] IO3V PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 PD[0..7] 4 ACK# BUSY PE SLCT 4 4 4 4 IO3V C4 0.1U 0.1U C5 LAD3 LAD2 LAD1 LAD0 Winbond Electronic Corp. Title W83627EHF CIRCUIT (LPC I/O + HW) Size B Date: Document Number W83627EHF MAIN Thursday, December 02, 2004 Sheet 1 of 8 Rev 0.3 Publication Release Date: Mar 2005 Revision 0.6 - 123 - W83627EHF/W83627EHG Preliminary SUSPEND LED CIRCUIT PANEL SWITCH R4 100 IO3VSB 1 PSIN R5 10K JP1 1 2 HEADER 2 SUSLED IOVSB R2 150 D1 Q1 2N3904 R3 4.7K PIN 70 doesn't need pull-up resistor POWER LED CIRCUIT R6 IO5V 150 D2 Q2 2N3904 R7 4.7K Serial Flash IO3V PLED U3 1 1 1,3 SCE# SO SWP# 1 2 3 4 CE# VCC SO HOLD# WP# SCK GND SI PM25LV512 8 7 6 5 HOLD# SCK SI POWER ON STRAPPING PIN 1 1 FOR W83627EHF RP1 HEFRAS 1,4 PENROM 1,4 PENKBC 1,4 EN_VRM10 1 IO3VSB 8 7 6 5 1K/OPTION 8 7 6 5 4.7K 1 2 3 4 RP2 RTSA# DTRA# SOUTA GP50 1 2 3 4 8 7 6 5 4.7K /OPTION IO3V IO3VSB RP2 1 1 1 1 PME# PSOUT# RSMRST# PWRCTL# 1 2 3 4 IO3V RP3 1 1 1 1 LDRQ# LFRAME# SERIRQ PWROK 1 2 3 4 4.7K 8 7 6 5 0 RTSA# DTRA# SOUTA IO3V 1 4E ENABLE SPI KBC ENABLE VRM10 LEVEL I/O CONFIGURATION ADDRESS ENABLE SPI KBC FUNCTION ENABLE VID LEVEL SELECTION Winbond Electronic Corp. Title W83627EHF CIRCUIT (LPC I/O + HW) Size B Date: Document Number SPI & STRAPPING Function Thursday , December 02, 2004 Sheet 2 of 8 Rev 0.3 2E DISABLE SPI KBC DISABLE TTL LEVEL GP50 RP4 LAD[0..3] 1 2 3 4 4.7K 8 7 6 5 1 LAD[0..3] Publication Release Date: Mar 2005 Revision 0.6 - 124 - W83627EHF/W83627EHG Preliminary F1 BATTERY CIRCUIT IOBAT BT1 BATTERY 3V R10 1K D3 1N4148 C6 0.1U JP5:1-2 Clear CMOS 2-3 Enable ONNOW f unctions 3 2 1 1 1 VWAKE FUSE R8 4.7K R9 4.7K L3 MDAT FB L4 MCLK C7 47P JP2 HEAD3 C8 47P FB J1 1 2 3 4 5 6 HEADER 6 PS2 MOUSE VWAKE OnNow or Wake_up function power R11 4.7K R12 4.7K L5 J2 1 2 3 4 5 6 C12 0.1U HEADER 6 1 D4 IO5V 2 1N4148 VWAKE 1 KDAT FB L6 KCLK C10 47P C11 47P FB C9 0.1U 2 KEYBOARD JP3 KB/MS D5 IO5VSB 1N4148 VWAKE CIRCUIT 1 1 IO5V GAME & MIDI PORT CIRCUIT IO5V IO5V IO5V IO5V IO5V FDC R13 1K L7 FB 8 7 6 5 RP5 1K J3 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 1 2 3 4 R14 2.2K R15 2.2K R16 2.2K R17 2.2K P1 R18 2.2K 1 1 1 1 1 1 1 1 1 1 MSI GPSA2 GPSB2 GPY 1 GPY 2 MSO GPX2 GPX1 GPSB1 GPSA1 R22 2.2K R23 2.2K R19 2.2K R20 2.2K R21 2.2K 8 15 7 14 6 13 5 12 4 11 3 10 2 9 1 GAMEPORT C14 0.01U C15 0.01U C16 0.01U C17 0.01U 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 DRVDEN0 INDEX# MOA# DSA# DIR# STEP# WD# WE# TRAK0# WP# RDATA# HEAD# DSKCHG# 1 1 1 1 1 1 1 1 1 1,2 1 1 1 FDC CONNECTOR C13 0.01U C18 0.01U C19 0.01U C20 0.01U C21 0.01U WINBOND ELECTRONICS CORP. Title W83627EHF CIRCUIT (LPC I/O + HW) Size B Date: Document Number GAME & MIDI & KBC & FDC Thursday , December 02, 2004 Sheet 3 of 8 Rev 0.3 Publication Release Date: Mar 2005 Revision 0.6 - 125 - W83627EHF/W83627EHG Preliminary IO5V D6 DIODE SCHOTTKY PRT PORT RP8 1 1 1 1 1 STB# AFD# INIT# SLIN# PD[0..7] PD[0..7] PD0 PD1 PD2 PD3 1 2 3 4 22 RP10 PD4 PD5 PD6 PD7 1 2 3 4 22 1 1 1 1 1 ERR# ACK# BUSY PE SLCT C22 180 C31 180 C23 180 C32 180 C24 180 C33 180 8 7 6 5 1 2 3 4 22 RP9 8 7 6 5 8 7 6 5 1 RP6 10P9R-2K 1 RP7 10P9R-2K 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 J4 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 DB25 C25 180 C34 180 C26 180 C35 180 C27 180 C36 180 C28 180 C37 180 C29 180 C38 180 C30 180 IR CONNECTOR COM PORT IO5V U4 IO5V 1,2 1,2 1,2 1 1 1 1 1 RTSA# DTRA# SOUTA RIA# CTSA# DSRA# SINA DCDA# 20 16 15 13 19 18 17 14 12 11 VCC DA1 DA2 DA3 RY 1 RY 2 RY 3 RY 4 RY 5 GND W83778 (SOP20) +12V DY 1 DY 2 DY 3 RA1 RA2 RA3 RA4 RA9 -12V 1 5 6 8 2 3 4 7 9 10 IO+12V NRTSA NDTRA NSOUTA NRIA NCTSA NDSRA NSINA NDCDA IO-12V GND NRIA NDTRA NCTSA NSOUTA NRTSA NSINA NDSRA NDCDA 5 9 4 8 3 7 2 6 1 UART A P2 1 SINB J5 1 2 3 4 5 CN2X5 1 SOUTB 6 7 8 9 10 COMA 1 5 6 8 2 3 4 7 9 10 IO+12V NRTSB NDTRB NSOUTB NRIB NCTSB NDSRB NSINB NDCDB IO-12V GND NRIB NDTRB NCTSB NSOUTB NRTSB NSINB NDSRB NDCDB (UARTA) P3 5 9 4 8 3 7 2 6 1 UART B WINBOND Electronics Corp. U5 IO5V 1 1 1 1 1 1 1 1 RTSB# DTRB# SOUTB RIB# CTSB# DSRB# SINB DCDB# 20 16 15 13 19 18 17 14 12 11 VCC DA1 DA2 DA3 RY 1 RY 2 RY 3 RY 4 RY 5 GND W83778 (SOP20) +12V DY 1 DY 2 DY 3 RA1 RA2 RA3 RA4 RA9 -12V COMB (UARTB) Title W83627EHF CIRCUIT (LPC I/O + HW) Size B Date: Document Number PRINT & COM Port Thursday , December 02, 2004 Sheet 4 of 8 Rev 0.3 Publication Release Date: Mar 2005 Revision 0.6 - 126 - W83627EHF/W83627EHG Preliminary Circuit For PWM Fan Control Only IO+12V R24 IO+12V R25 R28 4.7K 1K Q4 PNP 3906 R26 1K Q3 PNP 3906 D7 1N4148 R27 4.7K R30 27K R32 10K 4.7K D8 1N4148 R29 4.7K R31 510 1,6 AUXFANOUT R33 27K R35 10K SY SFANIN 1,6 R34 1,6 SY SFANOUT 510 Q6 MOSFET N 2N7002 C40 10u JP5 + 3 2 1 HEADER 3 Q5 MOSFET N 2N7002 C39 10u JP4 + 3 2 1 HEADER 3 AUXFANIN0 1,6 IO+12V IO+12V D9 1N4148 IO3V R37 4.7K R41 1,6 CPUFANOUT0 510 D10 1N4148 R39 4.7K R40 27K R42 10K JP6 3 2 1 HEADER 3 CPUFANIN0 1,6 AUXFANIN1 6 JP15 4 3 2 1 PWM FANOUT +12V GND HEADER 4 IO+12V R43 R44 4.7K 1K Q9 PNP 3906 D11 1N4148 R45 4.7K R46 27K R48 10K R47 6 CPUFANOUT1 510 Q10 MOSFET N 2N7002 C42 10u JP8 + 3 2 1 HEADER 3 CPUFANIN1 6 Winbond Electronic Corp. Title W83627EHF CIRCUIT (LPC I/O + HW) Size Document Number Custom FAN Control (PWM) Date: Thursday , December 02, 2004 Sheet 5 of 8 Rev 0.3 Publication Release Date: Mar 2005 Revision 0.6 - 127 - W83627EHF/W83627EHG Preliminary Circuit for DC / PWM Fan Control (USE W83391QS) IO+12V 1 IO+12V Q11 N DGS 20N03L 3 R50 10K R53 3.48K/EHF FAN1_DRV FAN1_SEN FAN2_DRV FAN2_SEN FAN3_DRV FAN3_SEN FAN4_DRV FAN4_SEN W83391QS 16 15 14 13 12 11 R56 10K 10 9 R58 3.48K/EHF IO+12V 1 C51 470u 1N4148 D15 R57 4.7K JP10 3 2 1 Q13 N DGS 20N03L 3 HEADER 3 IO+12V R59 CPUFANIN0 27K R60 10K 1,5 2 C48 10n 3 1 Q12 N DGS 20N03L C44 470u 1N4148 D12 R51 4.7K U6 IO+12V C45 0.1U C46 0.1U 1 2 3 D13 4 D14 DIODE C49 0.1U DIODE C47 0.1U 5 6 7 C50 0.1U 8 FAN1_IN FAN2_IN VCC12 CIN CHRPMP GND FAN3_IN FAN4_IN IO+12V JP9 3 2 1 HEADER 3 IO+12V R54 SY SFANIN 27K R55 10K 1,5 2 R49 100K R52 100K C43 10n 1,5 SY SFANOUT 1,5 CPUFANOUT0 2 5 AUXFANOUT0 1,5 CPUFANOUT1 R61 100K R62 100K R63 10K C53 0.1U C54 0.1U C52 10n 1N4148 C55 470u IO+12V 1 D16 R64 4.7K R65 3.48K/EHF JP11 3 2 1 R66 AUXFANIN0 27K R67 10K 5 2 C56 10n R68 10K 3 Q14 N DGS 20N03L HEADER 3 IO+12V 1N4148 C57 470u D17 R69 4.7K R70 3.48K/EHF JP12 3 2 1 HEADER 3 R71 CPUFANIN1 27K R72 10K 1,5 IO+12V IO3V D18 1N4148 R73 4.7K JP13 3 2 1 HEADER 3 AUXFANIN1 5 Winbond Electronic Corp. Title W83627EHF CIRCUIT (LPC I/O + HW) Size Document Number Custom FAN Control (DC / PWM) Date: Thursday , December 02, 2004 Sheet 6 of 8 Rev 0.3 Publication Release Date: Mar 2005 Revision 0.6 - 128 - W83627EHF/W83627EHG Preliminary Temperature Sensing RT1 R74 10K 1% RT2 R77 AUXTIN R78 1 CPUTIN C58 2200P CPUDAGND 15K 1% /EHF CPUD+ 1 FROM CPU'S THERM DIODE 1 1 10K 1% THERMISTOR R76 4.7K IO3V t VREF THERMISTOR R75 100 1 SY STIN t LS1 W83627EHF VREF=2.048V BEEP SPEAKER Q15 NPN R79 IOBAT CASEOPEN# 2M R80 R81 1.5V CPUVCORE 10K R83 IO+12V R82 56K 1% /EHF 10K 1% VIN0 1 VIN2 R86 IO-12V 232K 1% R87 10K 1% /EHF VREF 1 +5V 22K 1% R88 10K 1% R85 VIN3 1 1 IO-5V 120K 1% R87 10K 1% /EHF R86 VREF 1 1 1 10K 1% 1 VIN1 1 2 1 Voltage Sensing JP14 CASEOPEN FROM CPU VCORE W83627EHF VREF=2.048V VIN4 1 Winbond Electronic Corp. Title W83627EHF CIRCUIT (LPC I/O + HW) Size Document Number Custom Voltage & Temperature Sensing Date: Thursday , December 02, 2004 Sheet 7 of 8 Rev 0.3 Publication Release Date: Mar 2005 Revision 0.6 - 129 - 2 W83627EHF/W83627EHG Preliminary Temperature Sensing RT1 R74 10K 1% RT2 R77 AUXTIN R78 1 CPUTIN C58 2200P CPUDAGND 15K 1% /EHF CPUD+ 1 FROM CPU'S THERM DIODE 1 1 10K 1% THERMISTOR R76 4.7K IO3V t VREF THERMISTOR R75 100 1 SYSTIN t LS1 W83627EHF VREF=2.048V BEEP SPEAKER Q15 NPN R79 IOBAT CASEOPEN# 2M R80 R81 1.5V CPUVCORE 10K R83 IO+12V R82 56K 1% /EHF 10K 1% VIN0 1 R85 R86 IO-12V 232K 1% R87 10K 1% /EHF 10K 1% VREF 1 +5V 22K 1% R88 VIN3 1 +1.8V 10K 1% R84 VIN2 1 1 1 10K 1% 1 VIN1 1 2 1 Voltage Sensing JP14 CASEOPEN FROM CPU VCORE W83627EHF VREF=2.048V VIN4 1 Winbond Electronic Corp. Title W83627EHF CIRCUIT (LPC I/O + HW) Size Document Number Custom Voltage & Temperature Sensing Date: Tuesday, November 09, 2004 Sheet 7 of 8 Rev 0.2 Publication Release Date: Mar 2005 Revision 0.6 - 130 - 2 W83627EHF/W83627EHG Preliminary Revision History 0.1 First Publication 0.2 1. Add reserved pull down resistors at strapping pins 2. Revise the print port pull register from 2.7K to 2K ohm, and replcae D6 to schottky diode. 0.3 1. Modify PWM circuit to control 4 pins Fan 2. Add -5VIN Application circuit Winbond Electronic Corp. Title W83627EHF CIRCUIT (LPC I/O + HW) Size A Date: Document Number Rev ision History Thursday , December 02, 2004 Sheet 8 of 8 Rev 0.3 Publication Release Date: Mar 2005 Revision 0.6 - 131 - |
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