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| SM5907AF NIPPON PRECISION CIRCUITS INC. compression and non compression type shock-proof memory controller Overview The SM5907AF is a compression and non compression type shock-proof memory controller LSI for compact disc players. The compression level can be set in 4 levels, and external memory can be selected from 4 options (4M, 4Mx 2, 16M, 16Mx 2). It operates from a 2.4 to 3.6 V supply voltage range. Features - 2-channel processing - Serial data input 2s complement, 16-bit/MSB first, right-justified format Wide capture function (up to 3 x speed input rate) - System clock input 384fs (16.9344 MHz) - Shock-proof memory controller ADPCM compression method 4-bit compression mode 2.78 s/Mbit 5-bit compression mode 2.22 s/Mbit 6-bit compression mode 1.85 s/Mbit Full-bit non compression mode 0.74 s/Mbit 4 external DRAM configurations selectable 1 or 2 x 16M DRAM (4M x 4 bits, refresh cycle = 2048 cycle) 1 or 2 x 4M DRAM (1M x 4 bits) lim 44-pin QFP 4-level compression mode selectable pre Ordering Information SM5907AF NIPPON PRECISION CIRCUITS-1 ina ry Data residual detector: 15-bit operation, 16-bit output Forced mute - Microcontroller interface Serial command write and status read-out - Extension I/O Microcontroller interface for external control using 5 extension I/O pins - +2.4 to +3.6 V operating voltage range - Schmitt inputs All input pins (including I/O pins) except CLK (system clock) - Reset signal noise elimination Approximately 3.8 s or longer (65 system clock pulses) continuous LOW-level reset - 44-pin QFP package (0.8 mm pin pitch) SM5907AF Package dimensions (Unit: mm) 44-pin QFP 12.80 0.30 10.00 0.30 0.80 0.35 0.10 Pinout (Top View) lim A3 A2 A1 A0 A4 A5 A6 44 43 42 41 40 39 38 A7 A8 37 36 35 A9 VDD2 UC1 UC2 UC3 UC4 UC5 34 NRAS 1 2 3 4 5 6 7 8 9 pre NCAS3 CLK NTEST VSS 10 11 YSRDATA 12 13 14 15 16 17 18 19 20 21 ZSRDATA ZLRCK YLRCK ZSCK YBLKCK NRESET ZSENSE YFLAG YSCK YFCLK VDD1 22 ina ry 0.17 0.05 (1.40) 4 12.80 0.30 10.00 0.30 0 to 10 0.20 1.50 0.10 (1.40) 0.15 0.20MAX 0.15 0.05 C0 .7 0.60 0.20 33 32 31 30 29 28 27 26 25 24 23 NWE D1 D0 D3 D2 NCAS A10/ NCAS2 YMCLK YMDATA YMLD YDMUTE SM5 9 0 7 A F NIPPON PRECISION CIRCUITS-2 SM5907AF Pin description Pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Pin name VDD2 UC1 UC2 UC3 UC4 UC5 NCAS3 NTEST CLK VSS YSRDATA YLRCK YSCK ZSCK ZLRCK ZSRDATA YFLAG YFCLK YBLKCK NRESET ZSENSE VDD1 I/O Ip/O Ip/O Ip/O Ip/O Ip/O O Ip I I I I O O O I I I I O I I Function H VDD supply pin Microcontroller interface extension I/O 1 Microcontroller interface extension I/O 2 Microcontroller interface extension I/O 3 Microcontroller interface extension I/O 4 Microcontroller interface extension I/O 5 Test pin Ground Setting L ina ry DRAM2 CAS control (with two 16M DRAMs) 16.9344 MHz clock input Audio serial input data Audio serial input LR clock Audio serial input bit clock Left channel Audio serial output bit clock Audio serial output data Audio serial output LR clock Left channel Signal processor IC RAM overflow flag Crystal-controlled frame clock Subcode block clock signal System reset pin Microcontroller interface status output VDD supply pin Forced mute pin Mute Microcontroller interface latch clock Microcontroller interface serial data DRAM address 10 Microcontroller interface shift clock DRAM2 CAS control (with two 4M DRAMs) DRAM CAS control DRAM data input/output 2 DRAM data input/output 3 DRAM data input/output 0 DRAM data input/output 1 DRAM WE control DRAM address 9 DRAM address 8 DRAM address 7 DRAM address 6 DRAM address 5 DRAM address 4 DRAM address 0 DRAM address 1 DRAM address 2 DRAM address 3 DRAM RAS control Test Right channel Right channel Overflow pre lim YDMUTE YMLD YMDATA YMCLK A10 I I O O (NCAS2) NCAS D2 D3 D0 D1 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 O Ip/O Ip/O Ip/O Ip/O O O NWE A9 A8 A7 A6 A5 A4 A0 A1 A2 A3 NRAS O O O O O O O O O O Ip : Input pin with pull-up resistor Reset Ip/O : Input/Output pin (With pull-up resistor when in input mode) NIPPON PRECISION CIRCUITS-3 SM5907AF Absolute maximum ratings (VSS = 0V, VDD1, VDD2 pin voltage = VDD) Parameter Supply voltage Input voltage Storage temperature Power dissipation Symbol VDD VI TSTG PD Rating - 0.3 to 4.6 VSS - 0.3 to VDD + 0.3 - 55 to 125 350 Unit V V C mW Note. Refer to pin summary on the next page. Values also apply for supply inrush and switch-off. Electrical characteristics Recommended operating conditions Parameter Supply voltage Operating temperature Symbol VDD TOPR (VSS = 0V, VDD1, VDD2 pin voltage = VDD) Rating Unit V C 2.4 to 3.6 Standard voltage:(VDD1 = VDD2 = 3.0 to 3.6 V, VSS = 0 V, Ta = - 40 to 85 C) Parameter Pin Symbol IDD Condition Min Rating Typ 4.5 1.8 0.7VDD 0.3VDD 1.0 0.7VDD 0.3VDD IOH = - 0.5 mA IOL = 0.5 mA VIN = VDD VIN = 0V VIN = 0V VIN = VDD VIN = 0V 5 5 1 25 25 4 VDD - 0.4 0.4 115 115 15 1.0 1.0 Max 8.0 3.0 mA mA V V VP-P V V V V A A A A A Unit Current consumption Input voltage pre L level Output voltage Input current (*4,5) CLK H level L level IIH1 IIL1 IIL2 ILH ILL (*3,4) (*2) Input leakage current (*2,3,4) (*A) VDD1 = VDD2 = 3 V, CLK input frequency fXTI= 384fs = 16.9344 MHz, all outputs unloaded, SHPRF: Shock-proof, typical values are for VDD1 = VDD2 = 3 V. lim VDD CLK H level L level VIH1 VIL1 VINAC VIH2 VIL2 VOH1 VOL1 (*2,3,4) H level DC characteristics ina ry - 40 to 85 (*A)SHPRF ON (*A)Through mode AC coupling NIPPON PRECISION CIRCUITS-4 SM5907AF Low-voltage:(VDD1 = VDD2 = 2.4 to 3.0 V, VSS = 0 V, Ta = - 20 to 70 C) Parameter Current consumption Input voltage Pin VDD CLK H level L level (*2,3,4) Output voltage Input current (*4,5) CLK (*3,4) Input leakage current (*2,3,4) (*2) Symbol IDD VIH1 VIL1 Condition Min (*B)SHPRF ON (*B)Through mode 0.7VDD 1.0 Rating Typ 4.5 1.8 Max 8.0 3.0 0.3VDD mA mA V V VP-P V V V V A A A A A Unit H level L level L level H level (*B) VDD1 = VDD2 = 3 V, CLK input frequency fXTI= 384fs = 16.9344 MHz, all outputs unloaded, SHPRF: Shock-proof, typical values are for VDD1 = VDD2 = 3 V. pre lim (*1) (*2) Pin function Pin name Pin name Pin function (*3) (*4) (*5) Pin function Pin name Pin name Pin name Pin function Pin function YSRDATA, YLRCK, YSCK, YFLAG, YFCLK, NRESET, YBLKCK, YDMUTE, YMLD, YMDATA, YMCLK Schmitt input pin with pull-up NTEST ZSCK, ZLRCK, ZSRDATA, ZSENSE, NCAS, NCAS2, NCAS3, NWE, NRAS, A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10 ina ry VINAC VIH2 VIL2 AC coupling 0.7VDD VOH1 VOL1 IOH = - 0.5 mA IOL = 0.5 mA VIN = VDD VIN = 0V VIN = 0V VDD - 0.4 5 0.4 IIH1 IIL1 IIL2 ILH ILL 25 4 115 15 5 25 115 1.0 1 VIN = VDD VIN = 0V 1.0 Clock input pin (AC input) CLK Schmitt input pins I/O pins (Schmitt input with pull-up in input state) UC1, UC2, UC3, UC4, UC5, D0, D1, D2, D3 Outputs 0.3VDD NIPPON PRECISION CIRCUITS-5 SM5907AF AC characteristics Standard voltage: VDD1 = VDD2 = 3.0 to 3.6 V, VSS = 0 V, Ta = -40 to 85 C Low-voltage: VDD1 = VDD2 = 2.4 to 3.0 V, VSS = 0 V, Ta = -20 to 70 C (*) Typical values are for fs = 44.1 kHz System clock (CLK pin) Parameter Clock pulsewidth (HIGH level) Clock pulsewidth (LOW level) Clock pulse cycle Symbol ina ry Condition Rating Typ 29.5 29.5 59 System clock Min 26 26 Max 125 125 384fs 58 250 Unit ns ns ns tCWH tCWL tCY System clock input CLK t CWH 0.5VDD t CWL t CY Serial input (YSRDATA, YLRCK, YSCK pins) Parameter lim Symbol Min 75 75 Rating Typ Max Unit ns ns ns ns ns ns ns 3fs fs Condition YSCK pulsewidth (HIGH level) YSCK pulsewidth (LOW level) YSCK pulse cycle YSRDATA setup time YSRDATA hold time Last YSCK rising edge to YLRCK edge YLRCK edge to first YSCK rising edge YLRCK pulse frequency See note below. tBCWH tBCWL tBCY tDS tDH tBL tLB 150 50 50 50 0 50 Memory system ON (MSON=H) Memory system OFF (MSON=L) pre operation. fs Note. When the memory system is OFF (through mode), the input data rate is synchronized to the system clock input (384fs), so input data needs to be at 1/384 of this frequency. But, this IC can tolerate a certain amount of jitter. For details, refer to Through-mode t BCWH t BCY t BCWL 0.5VDD YSCK t DS t DH 0.5VDD t BL t LB 0.5VDD YSRDATA YLRCK NIPPON PRECISION CIRCUITS-6 SM5907AF Microcontroller interface (YMCLK, YMDATA, YMLD, ZSENSE pins) Parameter YMCLK LOW-level pulsewidth YMCLK HIGH-level pulsewidth YMDATA setup time YMDATA hold time YMLD LOW-level pulsewidth YMLD setup time YMLD hold time Rise time Fall time ZSENSE output delay Symbol Min Rating Typ Max ns ns ns ns ns ns ns ns ns 30 + 2tCY 30 + 2tCY 30 + tCY 30 + tCY 30 + tCY 30 + tCY Unit Note. tCY is the system clock cycle time (59ns typ). YMDATA t MDS YMCLK t MCWL YMLD t MLS pre lim t MLWL ZSENSE tf YMCLK YMDATA YMLD 0.7 VDD 0.3 VDD Reset input (NRESET pin) Parameter First HIGH-level after supply voltage rising edge NRESET pulsewidth Note. tCY is the system clock (CLK) input (384fs) cycle time. tCY = 59 ns, tNRST (min) = 3.8 s when fs = 44.1 kHz VDD1,VDD2 NRESET t HNRST t NRST ina ry 30 + 2tCY 100 100 100 + 3tCY tMCWL tMCWH tMDS tMDH tMLWL tMLS tMLH tr tf tPZS ns 0.5VDD t MDH 0.5VDD t MCWH t MLH 0.5VDD t PZS 0.5VDD tr 0.7 VDD 0.3 VDD 0.5VDD Symbol Min 0 64 Rating Typ Max Unit tHNRST tNRST tCY (Note) tCY (Note) NIPPON PRECISION CIRCUITS-7 SM5907AF Serial output (ZSRDATA, ZLRCK, ZSCK pins) Parameter ZSCK pulsewidth ZSCK pulse cycle ZSRDATA and ZLRCK output delay time Symbol Condition Min 15 pF load 15 pF load 15 pF load 15 pF load 0 0 Rating Typ 1/96fs 1/48fs 60 60 ns ns Max Unit ZSCK ZSRDATA ZLRCK t DHL DRAM access timing (NRAS, NCAS, NCAS2, NCAS3, NWE, A0 to A10, D0 to D3) Parameter NRAS pulsewidth Symbol Condition Rating Typ 5 2 5 3 1 1 1 5 3 3 40 0 15 pF load 15 pF load Non compression 4M 6-bit compression ina ry 0.5VDD t SCOW t SCOW t SCOY 0.5VDD t DLH Min 3 Max 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 15 pF load 6 3 3.0 7.3 8.8 10.9 5.9 14.6 17.5 21.8 DRAM 5-bit compression x 1 or x 2 4-bit compression tSCOW tSCOY tDHL tDLH Unit NRAS falling edge to NCAS falling edge NCAS pulsewidth NRAS NCAS NCAS NCAS Setup time Hold time Hold time falling edge to address falling edge to address Setup time Setup time Hold time falling edge to data write rising edge to data read pre Input setup Input hold NWE pulsewidth NWE falling edge to NCAS falling edge Refresh cycle (fs = 44.1 kHz playback) Memory system ON (RDEN=H) Decode sequence operation tRASL tRASH tRCD tCASH tCASL tRADS tRADH tCADS tCADH tCWDS tCWDH tCRDS tCRDH tWEL tWCS lim tREF 16M tCY(note) tCY tCY tCY tCY tCY tCY tCY tCY tCY tCY ns ns tCY tCY ms ms ms ms ms ms ms ms Non compression 6-bit compression DRAM 5-bit compression x 1 or x 2 4-bit compression Note. tCY is the system clock (CLK) input (384fs) cycle time. tCY = 59 ns when fs = 44.1 kHz NIPPON PRECISION CIRCUITS-8 SM5907AF DRAM access timing (with single DRAM) t RASL 5 tCY NRAS tRCD 2tCY NCAS tCASL 3 tCY t CASH 5tCY t RASH 3 tCY A0 to A10 ;;;;;;; ;;;;;;; ;;;;;;; ;;;;;;; t RADS 1tCY t RADH 1tCY t CWDS 3tCY D0 to D3 (WRITE) D0 to D3 (READ) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; t WCS 3tCY t WEL 6tCY NWE (WRITE) The NWE terminal output is fixed HIGH during read timing. pre lim DRAM access timing (with double DRAMs) t RASL 5 tCY NRAS t RCD 2tCY NCAS (DRAM1 SELECT) t RDC 2 tCY NCAS2, NCAS3 (DRAM2 SELECT) A0 to A10 ;;;;;;; 1tCY ;;;;;;; ;;;;;;; ;;;;;;; tRADS t RADH 1tCY t CWDS 3tCY D0 to D3 (WRITE) D0 to D3 (READ) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; t WCS 3 tCY t WCS t WEL 6tCY NWE (WRITE) The NWE terminal output is fixed HIGH during read timing. NCAS terminal output is fixed HIGH when selecting "DRAM2". NCAS2/NCAS3 terminal outputs are fixed HIGH when selecting "DRAM1". ina ry t CADS 1tCY t CADH 5tCY t CWDH 3tCY t CRDS t CRDH t RASH 3tCY tCASL 3tCY t CASH 5tCY tCASL 3tCY t CASH 5tCY t CADS 1tCY t CADH 5tCY t CWDH 3tCY t CRDS t CRDH ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; NIPPON PRECISION CIRCUITS-9 SM5907AF Block diagram SM5907 YBLKCK YFCLK YFLAG Control Input 1 YMDATA YMCLK YMLD ZSENSE Microcontroller Interface lim Compression Mode UC1 to UC5 General Port YDMUTE NRESET NTEST pre Control Input 2 CLK A0 to A10 NIPPON PRECISION CIRCUITS-10 D0 to D3 NRAS NCAS NCAS3 NCAS2 NWE ina ry Output Interface Input Interface Input Buffer Through Mode Decoder Encoder DRAM Interface YSRDATA ZSRDATA YLRCK ZLRCK ZSCK YSCK SM5907AF Functional description SM5907AF has two modes of operation; shockproof mode and through mode. The operating sequences are controlled using commands from a microcontroller. Microcontroller interface Commands from the microcontroller are input using 3-wire serial interface inputs; data (YMDATA), bit clock (YMCLK) and load signal (YMLD). Write command format (Commands 80 to 85) DATA 8bit YMDATA D7 D6 D5 D4 D3 YMCLK YMLD pre lim Read command format (Commands 90, 91, 93) COMMAND 8bit B4 B3 YMDATA B7 B6 B5 B2 B1 B0 YMCLK YMLD ZSENSE COMMAND 8bit B4 B3 YMDATA B7 B6 B5 B2 B1 B0 YMCLK YMLD ZSENSE Read command format (Command 92 (memory residual read)) ina ry COMMAND 8bit B4 B3 D2 D1 D0 B7 B6 B5 B2 B1 B0 STATUS 8bit S6 S5 S4 S3 S2 S1 S0 S7 RESIDUAL DATA 16bit S7 S6 S1 S0 M1 M2 M7 M8 Command format In the case of a read command from the microcontroller, bit serial data is output (ZSENSE) synchronized to the bit clock input (YMCLK). NIPPON PRECISION CIRCUITS-11 SM5907AF Command table Write command summary MS command 80 B7 B6 B5 B4 Shock-proof memory system settings Bit D7 D6 D5 D4 D3 D2 D1 D0 Name MSWREN MSWACL MSRDEN MSRACL MSDCN2 MSDCN1 WAQV MSON Function Encode sequence start/stop Write address reset Read address reset 80hex = 1000 0000 ina ry Start Reset Start Reset Decode sequence start/stop Q data valid Valid ON Memory system ON Function Output Output Output Output Output Function H output H output H output H output H output H operation Reset level MSDCN2=H, MSDCN1=H: 3-pair comparison start MSDCN2=H, MSDCN1=L: 2-pair comparison start MSDCN2=L, MSDCN1=H: Direct-connect start MSDCN2=L, MSDCN1=L: Connect operation stop Extension I/O settings 81 B7 B6 B5 B4 Extension I/O port input/output settings Bit D7 D6 D5 D4 D3 D2 D1 D0 UC5OE UC4OE UC3OE UC2OE UC1OE Name 81hex = 1000 0001 H operation Reset level lim Extension I/O port UC5 input/output setting Extension I/O port UC4 input/output setting Extension I/O port UC3 input/output setting Extension I/O port UC2 input/output setting Extension I/O port UC1 input/output setting pre Extension I/O output data settings 82 Bit Name D7 D6 D5 D4 D3 D2 D1 D0 UC5WD UC4WD UC3WD UC2WD UC1WD Extension port HIGH/LOW output level B7 B6 B5 B4 A port setting is invalid if that port has already been defined as an input using the 81H command above. 82hex = 1000 0010 H operation Reset level Extension I/O port UC5 output data setting Extension I/O port UC4 output data setting Extension I/O port UC3 output data setting Extension I/O port UC2 output data setting Extension I/O port UC1 output data setting NIPPON PRECISION CIRCUITS-12 B3 B2 B1 B0 B3 B2 B1 B0 B3 B2 B1 B0 L L L L L L L L L L L L L L L L L L SM5907AF MUTE, CMP12 settings 83 B7 B6 B5 B4 83hex = 1000 0011 Bit D7 D6 D5 D4 D3 D2 D1 D0 CMP12 MUTE Forced muting (changes instantaneously) Mute ON L Name Function H operation Reset level ina ry Function DRAM type setting Full-bit compression mode 6-bit compression mode 5-bit compression mode 4-bit compression mode 12-bit comparison connect/ 16-bit comparison connect 12-bit comparison Refer to "Force mute", "12-bit comparison connection". Option settings 85 B7 B6 B5 B4 85hex = 1000 0101 H operation Reset level Bit D7 Name RAMS1 RAMS1=0 RAMS2=0 when 16M DRAM(4M x 4bit) x double RAMS1=1 RAMS2=0 when 4M DRAM(1M x 4bit) x single D6 D5 RAMS2 YFLGS RAMS1=0 RAMS2=1 when 4M DRAM(1M x 4bit) x double FLAG6 set conditions (reset using status read command 90H) pre lim D4 YFCKP D3 D2 D1 D0 COMPFB COMP6B COMP5B COMP4B RAMS1=1 RAMS2=1 when 16M DRAM(4M x 4bit) x single - When YFLGS=0, YFCKP=0, YFCLK input falling edge, YFLAG=L - When YFLGS=0, YFCKP=1, YFCLK input rising edge, YFLAG=L - When YFLGS=1, YFCKP=0, YFLAG=L L L H L L - When YFLGS=1, YFCKP=1, YFLAG=H When the number of compression bits is set incorrectly (2 or more bits in D0 to D3 are set to 1 or all bits are set to 0), 6-bit compression mode is selected. NIPPON PRECISION CIRCUITS-13 B3 B2 B1 B0 B3 B2 B1 B0 L L L L SM5907AF Read command summary Shock-proof memory status (1) 90 B7 B6 B5 B4 90hex = 1001 0000 Bit S7 S6 S5 S4 S3 S2 S1 S0 DCOMP MSWIH MSRIH Name FLAG6 MSOVF BOVF Function Signal processor IC jitter margin exceeded Input buffer memory overflow Write overflow (Read once only when RA exceeds WA) because sampling rate of input data is too fast Data compare-connect sequence operating HIGH-level state Exceeded DRAM overflow Encode sequence stop due to internal factors Decode sequence stop due to internal factors Shock-proof memory status (2) 91 ina ry Encoding stopped Decoding stopped HIGH-level state No valid data Memory full Encoding Decoding Input buffer memory overflow Compare-connect sequence operating Refer to "Status flag operation summary". B7 B6 B5 B4 91hex = 1001 0001 Bit S7 S6 S5 S4 S3 S2 S1 S0 Name MSEMP OVFL ENCOD DECOD Function lim Encode sequence operating state Decode sequence operating state Valid data empty state (Always HIGH when RA exceeds VWA) Write overflow state (Always HIGH when WA exceeds RA) Refer to "Status flag operation summary". pre NIPPON PRECISION CIRCUITS-14 B3 B2 B1 B0 B3 B2 B1 B0 SM5907AF Shock-proof memory valid data residual 92 B7 B6 B5 B4 B3 B2 B1 B0 92hex = 1001 0010 Bit S7 S6 S5 S4 S3 S2 S1 S0 M1 M2 M3 M4 M5 M6 M7 M8 Name AM21 AM20 AM19 AM18 AM17 AM16 AM15 AM14 AM13 AM12 AM11 AM10 AM09 AM08 AM07 AM06 Function Valid data accumulated VWA-RA (MSB) 4Mx1, 4Mx2, 16Mx1 8M bits 4M bits 2M bits 16Mx2 16M bits 8M bits 4M bits 2M bits Note. The time conversion factor varies depending on the compression bit mode.(M = 1,048,576 K= 1,024) Residual time (sec) = Valid data residual (Mbits) x Time conversion value K where the Time conversion value K (sec/Mbit) 2.78(4 bits), 2.22 (5 bits), 1.85 (6 bits) and 0.74 (Full bits). pre lim Extension I/O inputs 93 Bit S7 S6 S5 S4 S3 S2 S1 S0 Name Function UC5RD UC4RD UC3RD UC2RD UC1RD Input data entering (or output data from) an extension port terminal is echoed to the microcontroller. (That is, the input data entering an I/O port configured as an input port using the 81H command, OR the output data from a pin configured as an output port using the 82H command.) B7 B6 B5 B4 ina ry 1M bits 512k bits 256k bits 128k bits 64k bits 32k bits 16k bits 8k bits 4k bits 2k bits 1k bits 512 bits 256 bits HIGH-level state 1M bits 512k bits 256k bits 128k bits 64k bits 32k bits 16k bits 8k bits 4k bits 2k bits 1k bits 512 bits 93hex = 1001 0011 NIPPON PRECISION CIRCUITS-15 B3 B2 B1 B0 SM5907AF Status flag operation summary Flag name FLAG6 Read method READ 90H bit 7 Set Meaning - Indicates to the CD signal processor DSP (used for error correction, de-interleaving) that a disturbance has exceeded the RAM jitter margin. FLAG6 set conditions - Set according to the YFLAG input and the operating state of YFCKP and YFLGS. Reset MSOVF READ 90H bit 6 Meaning Set Reset - Indicates once only that a write to external DRAM has caused an overflow. (When reset by the 90H status read command, this flag is reset even if the overflow condition continues.) - When the write address (WA) exceeds the read address (RA) - By 90H status read - When a read address clear (MSRACL) or write address clear (MSWACL) command is issued - After external reset BOVF READ 90H bit 5 Meaning Set Reset - Indicates input data rate was too fast causing buffer overflow and loss of data - When inputs a data during a buffer memory overflow - By 90H status read - After external reset DCOMP READ 90H bit 3 pre MSWIH READ 90H bit 2 Meaning Set Reset MSRIH READ 90H bit 1 Set Reset Meaning lim Meaning Set Reset - When a read address clear (MSRACL) or write address clear (MSWACL) command is issued - Indicates that a compare-connect sequence is operating - When a (3-pair or 2-pair) compare-connect start command is received (MSDCN2=1) - When a direct connect command is received (MSDCN2=0, MSDCN1=1) - When a (3-pair or 2-pair) comparison detects conforming data - When the connect has been performed after receiving a direct connect command - When a compare-connect stop command (MSDCN2=0, MSDCN1=0) is received received at the same time, the compare-connect command has priority.) - After external reset (not microcontroller commands) - When FLAG6 (above) is set - When BOVF (above) is set - When MSOVF (above) is set - Indicates that the encode sequence has stopped due to internal factors - When a MSWREN=1 command is received (However, if a compare-connect command is - When conforming data is detected after receiving a compare-connect start command - When the connect has been performed after receiving a direct connect command - After external reset (not microcontroller commands) - When the valid data residual becomes 0 - By 90H status read - When a read address clear (MSRACL) or write address clear (MSWACL) command is received - Indicates that the decode sequence has stopped due to internal factors - When a read address clear (MSRACL) or write address clear (MSWACL) command is issued - After external reset ina ry When YFLGS=0, YFCKP=0, YFCLK input falling edge, YFLAG=L When YFLGS=0, YFCKP=1, YFCLK input rising edge, YFLAG=L When YFLGS=1, YFCKP=0, YFLAG=L When YFLGS=1, YFCKP=1, YFLAG=H - By 90H status read - By 80H command when MSON=ON - After external reset NIPPON PRECISION CIRCUITS-16 SM5907AF Flag name MSEMP Read method READ 91H bit 7 Reset Meaning Set - Indicates that the valid data residual has become 0 - When the VWA (final valid data's next address) = RA (address from which the next read would take place) - Whenever the above does not apply - Indicates a write to external DRAM overflow state OVFL READ 91H bit 6 Meaning Set Reset (Note: This flag is not set when WA=RA through an address initialize or reset operation.) - When the read address (RA) is advanced by the decode sequence - After external reset - When a read address clear (MSRACL) or write address clear (MSWACL) command is issued ENCOD READ 91H bit 5 Meaning Set - Indicates that the encode sequence (input data entry, encoding, DRAM write) is operating - By the 80H command when MSWREN=1 - When conforming data is detected during compare-connect operation - When the FLAG6 flag=1 (above) - When the OVFL flag=1 (above) - When the connect has been performed after receiving a direct connect command Reset - By the 80H command when MSDCN1=1 or MSDCN2=1 (compare-connect start command) - By the 80H command when MSON=0 - After external reset pre lim DECOD READ 91H bit 4 Meaning Set Reset Note. Reset conditions have priority over set conditions. For example, if the 80H command has - Indicates that the decode sequence (read from DRAM, decoding, attenuation, data output) is operating - Whenever the above does not apply MSWREN=1 and MSDCN1=1, the ENCOD flag is reset and compare-connect operation starts. - By a new 80H command when MSRDEN=1 and the MSEMP flag=0 (above) ina ry - When the write address (WA) exceeds the read address (RA). - By the 80H command when MSWREN=0 NIPPON PRECISION CIRCUITS-17 SM5907AF Write command supplementary information 80H (MS command) - MSWREN When 1: Encode sequence starts Invalid when MSON is not 1 within the same 80H command Invalid when FLAG6=1 Invalid when OVFL=1 Invalid when a compare-connect start command (MSDCN2=1 or MSDCN1=1) occurs simultaneously Direct connect if a compare-connect sequence is already operating When 0: Encode sequence stops - MSWACL -MSRACL When 1: Initializes the read address (RA) When 0: No operation - MSDCN2, MSDCN1 When 1: Initializes the write address (WA) When 0: No operation - MSRDEN When 0: Decode sequence stops 81H (Extension I/O port settings) 82H (Extension I/O port output data settings) pre NIPPON PRECISION CIRCUITS-18 lim When 1: Decode sequence starts Does not perform decode sequence if MSON=1.If there is no valid data, decode sequence temporarily stops. But, because the MSRDEN flag setting is maintained as is, the sequence automatically re-starts when valid data appears. ina ry When 0: No operation - MSON When 1 and 1: 3-pair compare-connect sequence starts When 1 and 0: 2-pair compare-connect sequence starts When 0 and 1: Direct connect sequence starts When 0 and 0: Compare-connect sequence stops. No operation if a compare-connect sequence is not operating. - WAQV When 1: The immediately preceding YBLKCK falling-edge timing WA (write address) becomes the VWA (valid write address). When 1: Memory system turns ON and shockproof operation starts When 0: Memory system turns OFF and throughmode playback starts. (In this mode, the attenuator is still active.) SM5907AF 83H ( MUTE, 12-bit comparison connection settings) - MUTE (forced muting) When 1: Outputs are instantaneously muted to 0.(note 1) Same effect as taking the YDMUTE pin HIGH. When 0: No muting(note 1) (note1) Effective at the start left-channel output data. - MUTE, YDMUTE relationship When all mute inputs are 0, mute is released. - CMP12 (12-bit comparison connection) When 1: Performs comparison connection using only the most significant 12 bits of input data. When 0: Performs comparison connection using all 16 bits of input data. 85H (option settings) - RAMS1, RAMS2 When 0 and 0 : 16M DRAM (4Mx4 bits)xdouble When 1 and 0 : 4M DRAM (1Mx4 bits)xsingle When 0 and 1 : 4M DRAM (1Mx4 bits)xdouble When 1 and 1 : 16M DRAM (4Mx4 bits)xsingle - YFLGS, YFCKP When 0 and 0: Sets FLAG6 on the falling edge of YFCLK when YFLAG=0 When 0 and 1: Sets FLAG6 on the rising edge of YFCLK when YFLAG=0 When 1 and 0: Sets FLAG6 when YFLAG=0 When 1 and 1: Sets FLAG6 when YFLAG=1 pre lim ina ry - COMPFB, COMP6B, COMP5B, COMP4B When 0, 0, 0 and 1: Selects 4-bit compression mode When 0, 0, 1 and 0: Selects 5-bit compression mode When 1, 0, 0 and 0: Selects full-bit compression mode In all other cases: Selects 6-bit compression mode Changing mode without initializing during operation is possible. NIPPON PRECISION CIRCUITS-19 SM5907AF Shock-proof operation overview Shock-proof mode is the mode that realizes shockproof operation using external DRAM. Shock-proof mode is invoked by setting MSON=H in microcontroller command 80H. This mode comprises the following 3 sequences. 1. Input data from a signal processor IC is stored in internal buffers. 2. Encoder starts after a fixed number of data have been received. - Decode sequence 1. Reads compressed data stored in external buffer RAM at rate fs. 2. Decoder starts, using the predicting filter type and quantization levels used when encoded. - Compare-connect sequence pre NIPPON PRECISION CIRCUITS-20 lim 1. Encoding immediately stops when either external buffer RAM overflows or when a CD read error occurs due to shock vibrations. 2. Then, using microcontroller command 80H, the compare-connect start command is executed and compare-connect sequence starts. ina ry 3. Outputs the result. - Encode sequence 3. The encoder, after the most suitable predicting filter type and quantization steps have been determined, performs ADPCM encoding and then writes to external DRAM. 3. Compares data re-read from the CD with the processed final valid data stored in RAM (confirms its correctness). 4. As soon as the comparison detects conforming data, compare-connect sequence stops and encode sequence re-starts, connecting the data directly behind previous valid data. SM5907AF RAM addresses The SM5907AF uses either 1 or 2 external 4M or 16M DRAMs as external buffers. Three kinds of addresses are used for external RAM control. WA (write address) RA (read address) VWA (valid write address) Among these, VWA is the write address for conforming data whose validity has been confirmed. Determination of the correctness of data read from the CD is delayed relative to the encode write processing, so VWA is always delayed relative to WA. Connect data work area The region available for valid data is the area between VWA-RA. - Connect data work area This is an area of memory reserved for connect data. This area is 4k bits if using 4M DRAMs or 8k bits if using 16M DRAMs. VWA (valid write address) pre lim The VWA is determined according to the YBLKCK pin and WAQV command. Refer to the timing chart below. 1.YBLKCK is a 75 Hz clock(HIGH for 136 s) when used for normal read mode and it is a 150 Hz clock when used for double-speed read mode, synchronized to the CD format block end timing. When this clock goes LOW, WA which is the write address of internal encode sequence, is stored (see note 2). YBLKCK Microcontroller data set Refer to Microcontroller interface VWA Fig 2. YBLKCK and VWA relationship ina ry WA VWA Valid data area Fig 1. RAM addresses 2.The microcontroller checks the subcode and, if confirmed to be correct, generates a WAQV command (80H). 3.When the WAQV command is received, the previously latched WA is stored as the VWA. (note 2) Actually, there is a small time difference, or gap, between the input data and YBLKCK. This gap serves to preserves the preceding WA to protect against incorrect operation. 13.3ms VWA latch set WAQV set VWA(x) VWA(x + 1) Values shown are for rate fs. The values are 1/2 those shown at rate 2fs. RA NIPPON PRECISION CIRCUITS-21 SM5907AF YFLAG, YFCLK, FLAG6 Correct data demodulation becomes impossible for the CD signal processor IC when a disturbance exceeding the RAM jitter margin occurs. The YFLAG signal input pin is used to indicate when such a condition has occurred. The YFCLK is a 7.35 kHz clock synchronized to the CD format frame 1. The IC checks the YFLAG input and stops the encode sequence when such a disturbance has occurred, and then makes FLAG6 active. The YFLAG check method used changes depending on the YFLGS flag and YFCKP flag (85H command). See table1. If YFLAGS is set to 1, then YFCLK should be tied either High or Low. 85H command YFLGS 1 2 3 4 1 0 YFCKP 0 1 0 1 When YFLAG=LOW on YFCLK input falling edge When YFLAG=LOW on YFCLK input rising edge When YFLAG=LOW When YFLAG=HIGH Table 1. YFLAG signal check method pre NIPPON PRECISION CIRCUITS-22 lim ina ry FLAG6 set conditions YFCLK be tied either High or Low - After system reset FLAG6 reset conditions - When MSON=LOW - By status read (90H command) SM5907AF Compare-connect sequence The SM5907AF supports three kinds of connect modes; 3-pair compare-connect, 2-pair compareconnect and direct connect. Note that the SM5907AF can also operate in 12-bit comparison connect mode using only the most significant 12 bits of data for connection operation. In 3-pair compare-connect mode, the final 6 valid data (3 pairs of left- and right-channel data input before encode processing) and the most recently input data are compared until three continuous data pairs all conform. At this point, the encode sequence is re-started and data is written to VWA. In 2-pair compare-connect mode, comparison occurs just as for 3-pair comparison except that only 2 pairs from the three compared need to conform with the valid data. At this point, the encode sequence is re-started and data is written to VWA. In direct-connect mode, comparison is not performed at all, and encode sequence starts and data is written to the VWA. This mode is for systems that cannot perform compare-connect operation. - Compare-connect preparation time pre lim - Compare-connect sequence stop If a compare-connect stop command (80H with MSDCN1= 1, MSDCN2= 0) is input from the microcontroller, compare-connect sequence stops. 1. Comparison data preparation time Internally, when the compare-connect start command is issued, a sequence starts to restore the data for comparison. The time required for this preparation after receiving the command is approximately 2.5 x (1/fs). (approximately 60 s when fs = 44.1 kHz) 2. After the above preparation is finished, data is input beginning from the left-channel data and comparison starts. ina ry 3. If the compare-connect command is issued again, the preparation time above is not necessary and operation starts from step 2. 4. The same sequence takes place in direct-connect mode also. However, at the point when 3 words have been input, all data is directly connected as if comparison and conformance had taken place. If compare-connect sequence was not operating, the compare-connect stop command performs no operation. However, make sure that the other bit settings within the same 80H command are valid. NIPPON PRECISION CIRCUITS-23 SM5907AF Encode sequence temporary stop - When RAM becomes full, MSWREN is set LOW using the 80H command and encode sequence stops. (For details of the stop conditions, refer to the description of the ENCOD flag.) - Then, if MSWREN is set HIGH without issuing a compare-connect start command, the encode sequence re-starts. At this time, new input data is written not to VWA, but to WA. In this way, the data already written to the region between VWA and WA is not lost. - But if the MSWREN is set HIGH (80H command) after using the compare-connect start command even only once, data is written to VWA. If data is input before comparison and conformance is detected, the same operation as direct-connect mode takes place when the command is issued. After comparison and conformance are detected, no operation is performed because the encode sequence has already been started. However, make sure that the other bit settings within the same 80H command are valid. DRAM refresh pre Data compression mode 4 bit 5 bit 6 bit Full bit lim 4M (1Mx4 bits) 10.88 ms 8.71 ms 7.26 ms 2.72 ms - DRAM initialization refresh A 15-cycle RAS-only refresh is carried out for DRAM initialization under the following conditions. When MSON changes from 0 to 1 using command 80H. When from MSON=1, MSRDEN=0 and MSWREN=0 states only MSWREN changes to 1. In this case, encode sequence immediately starts and initial data is written (at 2fs rate input) after a delay of 0.7ms. - Refresh during Shock-proof mode operation In this IC, a data access operation to any address also serves as a data refresh. Accordingly, there are no specific refresh cycles other than the initialization refresh cycle (described above). This has the resulting effect of saving on DRAM power dissipation. Table 2. Decode sequence refresh rate ina ry DRAMs used (same for 1 or 2 DRAMs) 16M(4Mx4 bits) 21.77ms 17.42ms 14.52ms 5.81ms A data access to DRAM can occur in an encode sequence write operation or in a decode sequence read operation. Write sequence write operation stops during a connect operation whereas a read sequence read operation always continues while data is output to the D/A. The refresh rate for each DRAM during decode sequence is shown in the table below. The decode sequence, set by MSON=1 and MSRDEN=1, operates when valid data is in DRAM (when MSEMP=0). - When MSON=0, DRAM is not refreshed because no data is being accessed. Although MSON=1, DRAM is not refreshed if ENCOD=0 and DECOD=0 (both encode and decode sequence are stopped). NIPPON PRECISION CIRCUITS-24 SM5907AF Through-mode operation If MSON is set LOW (80H command), an operating mode that does not perform shock-proof functions becomes active. In this case, input data is passed as-is (except Force mute operation) to the output. External DRAM is not accessed. - In this case, input data needs to be at a rate fs and the input word clock must be synchronized to the CLK input (384fs). However, short-range jitter can be tolerated (jitter-free system). - Jitter-free system timing starts from the first YLRCK rising edge after either (A) a reset (NRESET= 0) release by taking the reset input from LOW to HIGH or (B) by taking MSON from HIGH to LOW. Accordingly, to provide for the largest possible jitter margin, it is necessary that the YLRCK clock be at rate fs by the time jitter-free timing starts. The jitter margin is 0.2/ fs (80 clock cycles). This jitter margin is the allowable difference between the system clock (CLK) divided by 384 (fs rate clock) and the YLRCK input clock. If the timing difference exceeds the jitter margin, irregular operation like data being output twice or, conversely, incomplete data output may occur. In the worst case, a click noise may also be generated. When switching from shock-proof mode to through mode, an output noise may be generated, and it is therefore recommended to use the YDMUTE setting to mute ZSRDATA until just before data output. Force mute Serial output data is muted by setting the YDMUTE pin input HIGH or by setting the MUTE flag to 1. Mute starts and finishes on the leading left-channel bit. pre lim 12-bit comparison connection When the CMP12 flag is set to 1, the least significant 4 bits of the 16-bit comparison connection input data are discarded and comparison connection is performed using the remaining 12 bits. ina ry When MSON is HIGH and valid data is empty (MSEMP=H), the output is automatically forced into the mute state. Note that if the CMP12 flag is set to 1 during a comparison connection operation, only the most significant 12 bits are used for comparison connection from that point on. NIPPON PRECISION CIRCUITS-25 SM5907AF Timing charts Input timing (YSCK, YSRDATA, YLRCK) 16 16 YSCK LSB ina ry L ch R ch MSB LSB MSB LSB YSRDATA YLRCK 1/(3fs ) Output timing (ZSCK, ZSRDATA, ZLRCK) 1 9 24 33 48 lim L ch MSB LSB ZSCK ZSRDATA ZLRCK R ch MSB LSB pre NIPPON PRECISION CIRCUITS-26 LSB 1/fs SM5907AF DRAM write timing (NRAS, NCAS, NCAS2, NCAS3, NWE, A0 to A10, D0 to D3) Write timing (with single DRAM) t RASL NRAS t RASH t RDC NCAS tRADS A0 to A10 t RADH ;;;;;;;; ;;;;;;;; ;;;;;;;; ;;;;;;;; t CWDS D0 to D3 (WRITE) NWE pre lim t RASL NRAS t RDC NCAS1 (DRAM1 SELECT) t RDC NCAS2, NCAS3 (DRAM2 SELECT) A0 to A10 Write timing (with double DRAMs) ;;;;;;; ;;;;;;; ;;;;;;; ;;;;;;; ;;;;;;; t RADS t RADH t CWDS D0 to D3 (WRITE) NWE ina ry tCASL t CASH t CADS t CADH t CWDH t WEL t RASH tCASL t CASH tCASL t CASH t CADS tCADH t CWDH t WEL ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;; ;;;;;;;;;;;;; ;;;;;;;; ;;;;;;;;;;;;; ;;;;;;;; ;;;;;;;;;;;;; ;;;;;;;; ;;;;;;;;;;;;; ;;;;;;;; ;;;;;;;;;;;;; ;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;;; NIPPON PRECISION CIRCUITS-27 SM5907AF DRAM read timing (NRAS, NCAS, NCAS2, NCAS3, NWE, A0 to A10, D0 to D3) Read timing (with single DRAM) t RASL NRAS t RCD NCAS t RASH ;;;;;;; ;;;;;;; A0 to A10 ;;;;;;; ;;;;;;; ;;;;;;; t RADS tRADH t CADS ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; D0 to D3 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (READ) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; t OEL NWE Read timing (with double DRAMs) lim t RASL t RCD tCASL t RCD tCASL t RADS t RADH t CADS NRAS NCAS1 (DRAM1 SELECT) NCAS2, NCAS3 (DRAM2 SELECT) pre A0 to A10 D0 to D3 (READ) NWE ;;;;;;; ;;;;;;; ;;;;;;; ;;;;;;; ;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ina ry tCASL t CASH t CADH t CRDS t CRDH t RASH t CASH t CASH t CADH t CRDS t CRDH ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;; NIPPON PRECISION CIRCUITS-28 SM5907AF Connection example 4M DRAM x 1 or 2 typical connection SM5907 Microcontroller YMDATA YMCLK YMLD ZSENSE UC1 to UC5 YBLKCK CD DSP YFLAG YSCK YLRCK YSRDATA ZSCK ZLRCK ZSRDATA CLK NRESET YDMUTE D/A converter pre lim SM5907 Microcontroller YMDATA YMCLK YMLD ZSENSE YBLKCK YFCLK CD DSP YFLAG YSCK YLRCK YSRDATA D/A converter ZSCK ZLRCK ZSRDATA CLK NRESET YDMUTE 16M DRAM x 1 or 2 typical connection DRAM OE pin is tied LOW. In response to the YFLAG input, the 85H command (option settings) should be: D5: YFLGS =1, D4: YFCKP set to the YFLAG active level. If YFLAG is active LOW, set YFCKP=0. If YFLAG is active HIGH, set YFCKP=1. If 4M DRAM x 2 are used, use A10/NCAS2 pin. If 16M DRAM x 2 are used, use NCAS3 pin. NIPPON PRECISION CIRCUITS-29 ina ry 4M DRAM 1 RAS WE A0 to A9 D0 to D3 CAS OE YFCLK NRAS NWE A0 to A9 D0 to D3 NCAS 4M DRAM 2 NRAS RAS NWE WE A0 to A9 A0 to A9 D0 to D3 D0 to D3 CAS OE NCAS2 UC1 to UC5 16M DRAM 1 RAS WE A0 to A10 D0 to D3 CAS OE NRAS NWE A0 to A10 D0 to D3 NCAS 16M DRAM 2 NRAS RAS NWE WE A0 to A10 A0 to A10 D0 to D3 D0 to D3 CAS OE NCAS3 SM5907AF Device comparison with SM5903BF Pin No. 7 pin SM5903BF N.C. SM5907AF NCAS3 Microcontroller interface functions 85H (RAMS1=0, RAMS2=0) SM5903BF: 1M DRAM x 1 SM5907AF: 16M DRAM x 2 NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. pre l NIPPON PRECISION CIRCUITS INC. 4-3, FUKUZUMI 2 CHOME, KOTO-KU TOKYO,135-8430, JAPAN Telephon: +81-3-3642-6661 Facsimile: +81-3-3642-6698 NIPPON PRECISION CIRCUITS INC. im 92H (valid residual) In the SM5907AF, if 16M DRAM x 2 configuration is selected using the 85H command (85H RAMS1=0, RAMS2=0), the residual data is 1-bit shifted in order to represent the maximum 32Mbits. ina As pin 7 on the SM5903BF is not connected internally, the possible DRAM configurations are 4M x 1, 4M x 2, and 16M x 1, all of which are completely compatible with the SM5907AF. Note that the chip process is different, and hence some DC characteristics are different. When 16M x 2 configuration is used, the microcontroller interface valid residual memory is different (92H status read). See "Read command summary". ry http://www.npc.co.jp/ Email: sales@npc.co.jp NP0018AE 2000.10 Pin difference NIPPON PRECISION CIRCUITS-30 |
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