View M5M4V4265CJ-5_401831.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MITSUBISHI LSIs MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
DESCRIPTION
This is a family of 262144-word by 16-bit dynamic RAMs with EDO mode fuction, fabricated with the high performance CMOS process, and is ideal for the buffer memory systems of personal computer graphics and HDD where high speed, low power dissipation, and low costs are essential. The use of double-layer metalization process technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. The lower supply (3.3V) operation, due to the optimization of transistor structure, provides low power dissipation while maintaining high speed operation. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. Self or extended refresh current is low enough for battery back-up application. This device has 2CAS and 1W terminals with a refresh cycle of 512 cycles every 8.2ms.
PIN CONFIGURATION (TOP VIEW)
(3.3V)VCC DQ1 DQ2 DQ3 DQ4 (3.3V)VCC DQ5 DQ6 DQ7
1 2 3 4 5 6 7 8 9
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VSS(0V) DQ16 DQ15 DQ14 DQ13 VSS(0V) DQ12 DQ11 DQ10 DQ9 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS(0V)
DQ8 10
FEATURES
Type name
M5M4V4265CXX-5,-5S M5M4V4265CXX-6,-6S M5M4V4265CXX-7,-7S RAS CAS Address access access access time time time (max.ns) (max.ns) (max.ns) Power OE Cycle dissipaaccess time tion time (max.ns) (min.ns) (typ.mW)
NC 11 NC 12 W 13 RAS 14 NC 15 A0 16 A1 17 A2 18 A3 19 (3.3V)VCC 20
50 60 70
13 15 20
25 30 35
13 15 20
90 110 130
408 363 333
XX=TP,J
Standard 40 pin SOJ, 44 pin TSOP (II) Single 3.30.3V supply Low stand-by power dissipation CMOS Input level 1.8mW (Max) CMOS Input level 360W (Max) * Operating power dissipation M5M4V4265CXX-5,-5S 486mW (Max) M5M4V4265CXX-6,-6S 432mW (Max) M5M4V4265CXX-7,-7S 396mW (Max) Self refresh capability * Self refresh current 100A (Max) Extended refresh capability Extended refresh current 100A (Max) EDO mode (512-column random access), Read-modify-write, RASonly refresh, CAS before RAS refresh, Hidden refresh capabilities. Early-write mode, OE and W to control output buffer impedance 512 refresh cycles every 8.2ms (A0~A8) 512 refresh cycles every 128ms (A0~A8) * Byte or word control for Read/Write operation (2CAS, 1W type) * : Applicable to self refresh version (M5M4V4265CJ,TP-5S,-6S, -7S : option) only
Outline 40P0K (400mil SOJ)
(3.3V)VCC DQ1 DQ2 DQ3 DQ4 (3.3V)VCC DQ5 DQ6 DQ7
1 2 3 4 5 6 7 8 9
44 43 42 41 40 39 38 37 36 35
VSS(0V) DQ16 DQ15 DQ14 DQ13 VSS(0V) DQ12 DQ11 DQ10 DQ9
DQ8 10
APPLICATION
Microcomputer memory, Refresh memory for CRT, Frame buffer memory for CRT
NC 13 NC 14
32 31 30 29 28 27 26 25 24 23
NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS(0V)
PIN DESCRIPTION
Pin name A0~A8 DQ1~DQ16 RAS LCAS UCAS W OE VCC VSS 1 Function Address inputs Data inputs / outputs Row address strobe input Lower byte control column address strobe input Upper byte control column address strobe input Write control input Output enable input Power supply (+3.3V) Ground (0V)
W 15 RAS
16
NC 17 A0 18 A1 19 A2 20 A3 21 (3.3V)VCC 22
Outline 44P3W-R (400mil TSOP Nomal Bend)
NC : NO CONNECTION
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
FUNCTION
In addition to EDO Mode, normal read, write and read-modifywrite operations the M5M4V4265CXX provides a number of other functions, e.g., RAS-only refresh, and delayed-write. The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Operation Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write RAS only refresh Hidden refresh
CAS before RAS (Extended *) refresh
Inputs RAS ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT NAC LCAS ACT NAC ACT ACT NAC ACT NAC ACT ACT ACT DNC UCAS NAC ACT ACT NAC ACT ACT NAC ACT ACT ACT DNC W NAC NAC NAC ACT ACT ACT DNC NAC DNC DNC DNC OE ACT ACT ACT NAC NAC NAC DNC ACT DNC DNC DNC DQ1~DQ8 DOUT OPN DOUT DIN DNC DIN OPN DOUT OPN OPN OPN
Input/Output DQ9~DQ16 OPN DOUT DOUT DNC DIN DIN OPN DOUT OPN OPN OPN
Self refresh * Stand-by
Note : ACT : active, NAC : nonactive, DNC : don' t care, OPN : open
BLOCK DIAGRAM
ROW ADDRESS STROBE INPUT RAS LOWER BYTE CONTROL COLUMN ADDRESS LCAS STROBE INPUT UPPER BYTE CONTROL UCAS COLUMN ADDRESS STROBE INPUT WRITE CONTROL INPUT
VCC (3.3V) CLOCK GENERATOR CIRCUIT LOWER UPPER
(8)LOWER DATA IN BUFFER
VSS (0V)
DQ1 DQ2 DQ8
W
(8)LOWER DATA OUT BUFFER
LOWER DATA INPUTS / OUTPUTS
VCC (3.3V) VSS (0V)
A0~A8 COLUMN DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8
(8)UPPER DATA IN BUFFER
SENSE REFRESH AMPLIFIER & I /O CONTROL
DQ9 DQ10 DQ16
ADDRESS INPUTS
ROW & COLUMN ADDRESS BUFFER
UPPER DATA INPUTS / OUTPUTS
ROW A0~ A8 DECODER
MEMORY CELL (4,194,304 BITS)
(8)UPPER DATA OUT BUFFER
VCC (3.3V) VSS (0V)
OE
OUTPUT ENABLE INPUT
2
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IO Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Conditions With respect to VSS Ratings -0.5~4.6 -0.5~4.6 -0.5~4.6 50 1000 0~70 -65~150 Unit V V V mA mW C C
Ta=25C
RECOMMENDED OPERATING CONDITIONS (Ta=0~70C, unless otherwise noted)
Symbol VCC VSS VIH VIL Parameter Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage, all inputs Min 3.0 0 2.0 -0.3 Limits Nom 3.3 0 Max 3.6 0
VCC+0.3
(Note 1)
Unit V V V V
0.8
Note 1 : All voltage values are with respect to VSS.
ELECTRICAL CHARACTERISTICS (Ta=0~70C, VCC=3.30.3V, VSS=0V, unless otherwise noted) (Note 2)
Symbol VOH VOL IOZ II ICC1(AV) Parameter High-level output voltage Low-level output voltage Off-state output current Input current Average supply current from Vcc, operating (Note 3,4,5)
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Test conditions IOH=-2mA IOL=2mA Q floating 0VVOUTVCC
0VVINVCC+0.3V, Other inputs pins=0V
Min 2.4 0 -5 -5
Limits Typ
RAS, CAS cycling tRC=tWC=min. output open RAS= CAS =VIH, output open
Max VCC 0.4 5 5 135 120 110 2 0.5 0.1 * 125 110 95 125 110 95 115 100 85
Unit V V A A mA
ICC2
Supply current from VCC, stand-by
(Note 6) RAS= CASVCC -0.2V output open RAS cycling, CAS=VIH tRC=min. output open RAS=VIL, CAS cycling tPC=min. output open CAS before RAS refresh cycling tRC=min. output open RAS cycling CAS0.2V or CAS before RAS refresh cycling RAS0.2V or VCC-0.2V CAS0.2V or VCC-0.2V W0.2V orVCC-0.2V OE0.2V or VCC-0.2V A0~A8 0.2V or VCC-0.2V, DQ=open tRC=250s, tRAS=tRAS min~1s RAS=CAS0.2V output open
mA
ICC3(AV)
Average supply current M5M4V4265C-6,-6S from Vcc, RAS only refresh mode (Note 3,5) M5M4V4265C-7,-7S Average supply current from Vcc EDO mode (Note 3,4,5) Average supply current from Vcc CAS before RAS refresh mode (Note 3,5)
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
M5M4V4265C-5,-5S
mA
ICC4(AV)
mA
ICC6(AV)
mA
ICC8(AV) *
Average supply current from VCC Extended-refresh mode
100
A
(Note 6)
ICC9(AV) *
Average supply current from VCC Self-refresh mode
(Note 6)
100
A
Note 2 : Current flowing into an IC is positive, out is negative. 3 : ICC1(AV), ICC3(AV), ICC4(AV), and ICC6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4 : ICC1(AV) and ICC4(AV) are dependent on output loading. Specified values are obtained with the output open. 5 : Column Address can be changed once or less while RAS=VIL and CAS=VIH.
3
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
CAPACITANCE (Ta=0~70C, VCC=3.30.3V, VSS=0V, unless otherwise noted)
Symbol CI (A) CI (CLK) CI / O Parameter Input capacitance, address inputs Input capacitance, clock inputs Input/Output capacitance, data ports Test conditions VI=VSS f=1MHz VI=25mVrms Min Limits Typ Max 5 7 7 Unit pF pF pF
SWITCHING CHARACTERISTICS (Ta=0~70C, VCC=3.30.3V, Vss=0V, unless otherwise noted, see notes 6,14,15)
Limits Symbol tCAC tRAC tAA tCPA tOEA tOHC tOHR tCLZ tOEZ tWEZ tOFF tREZ Parameter Access time from CAS Access time from RAS Columu address access time Access time from CAS precharge Access time from OE Output hold time from CAS Output hold time from RAS Output low impedance time from CAS low Output disable time after OE high Output disable time after WE high Output disable time after CAS high Output disable time after RAS high (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7) (Note 13) (Note 13) (Note 7) (Note 12) (Note 12) (Note 12,13) (Note 12,13)
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Unit ns ns ns ns ns ns ns ns ns ns ns ns
Min
Max 13 50 25 28 13
Min
Max 15 60 30 33 15
Min
Max 20 70 35 38 20
5 5 5 13 13 13 13
5 5 5 15 15 15 15
5 5 5 20 20 20 20
Note 6 : An initial pause of 500s is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh cycles). Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 8.2ms) of RAS inactivity before proper device operation is achieved. 7 : Measured with a load circuit equivalent to 50pF, VOH (IOH=-2mA) and VOL(IOL=2mA). The reference levels for measuring of output signals are 2.0V(VOH) and 0.8V(VOL). 8 : Assumes that tRCDtRCD(max) and tASCtASC(max) and tCPtCP(max). 9 : Assumes that tRCDtRCD(max) and tRADtRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10 : Assumes that tRADtRAD(max) and tASCtASC(max). 11 : Assumes that tCPtCP(max) and tASCtASC(max). 12 : tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT 5A ) and is not reference to VOH(min) or VOL(max). 13 : Output is disabled after both RAS and CAS go to high.
4
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh and EDO Mode Cycles)
(Ta=0~70C, VCC=3.30.3V, VSS=0V, unless otherwise noted, see notes 14,15) Limits Symbol tREF tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tRDD tCDD tODD tT Parameter
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Unit ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Min Refresh cycle time Refresh cycle time * RAS high pulse width Delay time, RAS low to CAS low Delay time, CAS high to RAS low Delay time, RAS high to CAS low CAS high pulse width Column address delay time from RAS low Row address setup time before RAS low Column address setup time before CAS low Row address hold time after RAS low Column address hold time after CAS low Delay time, data to CAS low Delay time, data to OE low Delay time, RAS high to data Delay time, CAS high to data Delay time, OE high to data Transition time Note 14 : The timing requirements are assumed tT=2ns.
Max 8.2 128 32
Min
Max 8.2 128 45
Min
Max 8.2 128 50
(Note 16)
(Note 17) (Note 18)
(Note 19) (Note 19) (Note 20) (Note 20) (Note 20) (Note 21)
30 18 5 0 8 13 0 0 8 8 0 0 13 13 13 1
25 10
50
40 20 5 0 10 15 0 0 10 10 0 0 15 15 15 1
30 13
50
50 20 5 0 10 15 0 0 10 10 0 0 20 20 20 1
35 13
50
Note 15 : VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Note 16 : tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. Note 17 : tRAD(max) is specified as a reference point only. If tRADtRAD(max) and tASCtASC(max), access time is controlled exclusively by tAA. Note 18 : tASC(max) is specified as a reference point only. If tRCDtRCD(max) and tASCtASC(max), access time is controlled exclusively by tCAC. Note 19 : Either tDZC or tDZO must be satisfied. Note 20 : Either tRDD or tCDD or tODD must be satisfied. Note 21 : tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Limits Symbol tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tCAL tORH tOCH Read cycle time Parameter
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Unit ns ns ns ns ns ns ns ns ns ns ns ns
RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Read setup time before CAS low Read hold time after CAS high Read hold time after RAS high Column address to RAS hold time Column address to CAS hold time RAS hold time after OE low CAS hold time after OE low Note 22 : Either tRCH or tRRH must be satisfied for a read cycle.
(Note 22) (Note 22)
Min 90 50 8 40 13 0 0 0 25 13 13 13
Max 10000 10000
Min 110 60 10 48 15 0 0 0 30 18 15 15
Max 10000 10000
Min 130 70 13 55 20 0 0 0 35 23 20 20
Max 10000 10000
5
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Limits Symbol tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH Parameter Write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Write setup time before CAS low Write hold time after CAS low CAS hold time after W low RAS hold time after W low Write pulse width Data setup time before CAS low or W low Data hold time after CAS low or W low
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Unit ns ns ns ns ns ns ns ns ns ns ns ns
(Note 24)
Min 90 50 8 40 13 0 8 8 8 8 0 8
Max 10000 10000
Min 110 60 10 48 15 0 10 10 10 10 0 10
Max 10000 10000
Min 130 70 10 55 20 0 13 13 13 13 0 13
Max 10000 10000
Read-Write and Read-Modify-Write Cycles
Limits Symbol tRWC tRAS Parameter Read write/read modify write cycle time
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Unit
ns (Note 23) ns 10000 10000 10000 RAS low pulse width ns tCAS 10000 10000 10000 CAS low pulse width ns tCSH CAS hold time after RAS low tRSH ns RAS hold time after CAS low ns tRCS Read setup time before CAS low ns tCWD (Note 24) Delay time, CAS low to W low tRWD ns (Note 24) Delay time, RAS low to W low tAWD ns (Note 24) Delay time, address to W low tOEH ns OE hold time after W low Note 23 : tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. Note 24 : tWCS, tCWD, tRWD and tAWD and tCPWD are specified as reference points only. If tWCStWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWDtCWD(min), tRWDtRWD(min), tAWDtAWD(min) and tCPWDtCPWD(min)
(for EDO mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH) is indeterminate.
Min 109 75 38 70 38 0 28 65 40 13
Max
Min 133 89 44 82 44 0 32 77 47 15
Max
Min 161 107 57 99 57 0 42 92 57 20
Max
6
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Mix Cycle, Hi-Z control by OE or W)
Limits Symbol tHPC tHPRWC tDOH tRAS tCP tCPRH tCPWD tCHOL tOEPE tWPE tHCWD tHAWD tHPWD tHCOD tHAOD tHPOD Parameter (Note 26) Hyper page mode read/write cycle time Hyper page mode read write/read modify write cycle time Output hold time from CAS low (Note 27) RAS low pulse width for read or write cycle (Note 28) CAS high pulse width RAS hold time after CAS precharge (Note 24) Delay time, CAS precharge to W low Hold time to maintain the data Hi-Z until CAS access OE pulse width (Hi-Z control) W pulse width (Hi-Z control) Delay time, CAS low to W low after read Delay time, Address to W low after read Delay time, CAS precharge to W low after read Delay time, CAS low to OE high after read Delay time, Address to OE high after read Delay time, CAS precharge to OE high after read
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
(Note 25)
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Min 20 57 5 65 8 28 43 7 7 7 28 40 43 13 25 28
Max
100000 13
Min 25 66 5 77 10 33 50 7 7 7 32 47 50 15 30 33
Max
100000 16
Min 30 79 5 92 10 38 60 7 7 7 42 57 60 20 35 38
Max
100000 16
Note 25 : All previously specified timing requirements and switching characteristics are applicable to their respective EDO mode cycle. Note 26 : tHPC(min) is specified in the case of read-only and early write-only in EDO mode. Note 27 : tRAS(min) is specified as two cycles of CAS input are performed. Note 28 : tCP(max) is specified as a reference point only.
CAS before RAS Refresh Cycle
Symbol tCSR tCHR tCAS
(Note 29)
Limits Parameter CAS setup time before RAS low CAS hold time after RAS low CAS low pulse width
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Unit ns ns ns
Min 5 10 17
Max
Min 5 10 17
Max
Min 5 15 22
Max
Note 29 : Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
Self Refresh Cycle *
Symbol tRASS tRPS tCHS
(Note 30)
Limits Parameter CBR self refresh RAS low pulse width CBR self refresh RAS high precharge time CBR self refresh CAS hold time
M5M4V4265C-5,-5S M5M4V4265C-6,-6S M5M4V4265C-7,-7S
Unit s ns ns
Min 100 90 -50
Max
Min 100 110 -50
Max
Min 100 130 -50
Max
7
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Timing Diagrams Read Cycle
(Note 31)
tRC tRAS VIH VIL tCSH tCRP VIH LCAS/UCAS VIL tRAD tASR VIH VIL tRAH tASC tCAH tRAL tCAL tASR
ROW ADDRESS
tRP
RAS
tRPC tRCD tRSH tCAS tCRP
A0~A8
ROW ADDRESS
COLUMN ADDRESS
tRCS VIH VIL tDZC
tRRH tRCH
W
tCDD DQ1~DQ16 (INPUTS) VIH VIL tCAC tAA tCLZ DQ1~DQ16 (OUTPUTS) VOL VOH
Hi-Z Hi-Z
tREZ tOHR
tWEZ tOFF tOHC
Hi-Z
tOEA tRAC tDZO tOEA tOCH
DATA VALID
tOEZ tODD
OE
VIH VIL tORH
Note 31
Indicates the don't care input. VIH(min)VINVIH(max) or VIL(min)VINVIL(max) Indicates the invalid output.
8
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Byte Read Cycle
tRC tRAS VIH VIL tCSH tCRP VIH VIL tCAS UCAS (or LCAS) VIH VIL tRAD tASR VIH VIL tRAH tASC tCAH tRAL tCAL tASR
ROW ADDRESS
tRP
RAS
tRPC tRCD tRSH tCRP
LCAS (or UCAS)
tCPN
A0~A8
ROW ADDRESS
COLUMN ADDRESS
tRRH tRCS VIH VIL tRCH
W
DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS)
DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL tDZC DQ9~DQ16 VIH (or DQ1~DQ8) VIL (INPUTS)
Hi-Z
tCDD
Hi-Z
tCAC tAA tCLZ DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL
Hi-Z
tREZ tOHR tOFF tOHC
Hi-Z DATA VALID
tWEZ
tRAC tDZO VIH VIL tORH tOEA tOCH OE tOEZ tODD
9
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Early Write Cycle
tWC tRAS VIH VIL tCSH tCRP VIH LCAS/UCAS VIL tASR VIH VIL tRAH tASC tCAH tASR tRCD tRSH tCAS tCRP tRPC tRP
RAS
A0~A8
ROW ADDRESS
COLUMN ADDRESS
ROW ADDRESS
tWCS VIH VIL tDS
tWCH
W
tDH
DQ1~DQ16 (INPUTS)
VIH VIL
DATA VALID
DQ1~DQ16 VOH (OUTPUTS) VOL
Hi-Z
OE
VIH VIL
10
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Byte Early Write Cycle
tWC tRAS VIH VIL tCRP VIH VIL tCAS UCAS (or LCAS) VIH VIL tASR VIH VIL tRAH tASC tCAH
COLUMN ADDRESS
tRP
RAS
tCSH tRCD tRSH
tRPC tCRP
LCAS (or UCAS)
tASR
A0~A8
ROW ADDRESS
ROW ADDRESS
tWCS W VIH VIL
tWCH
DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS)
DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL tDS DQ9~DQ16 VIH (or DQ1~DQ8) VIL (INPUTS)
Hi-Z
tDH
DATA VALID
DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL
Hi-Z
OE
VIH VIL
11
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Delayed Write Cycle
tWC tRAS VIH VIL tCRP VIH LCAS/UCAS VIL tASR tRAH tASC tCAH tASR
COLUMN ADDRESS ROW ADDRESS
tRP
RAS
tCSH tRCD tRSH tCAS
tRPC tCRP
A0~A8
VIH VIL
ROW ADDRESS
tRCS VIH VIL tWCH tDZC DQ1~DQ16 (INPUTS) VIH VIL tCLZ
Hi-Z
tCWL tRWL tWP
W
tDS
tDH
DATA VALID
DQ1~DQ16 VOH (OUTPUTS) VOL
Hi-Z
Hi-Z
tDZO VIH VIL
tOEH tOEZ tODD
OE
12
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Byte Delayed Write Cycle
tWC tRAS RAS VIH VIL tCSH tCRP VIH VIL tCAS UCAS (or LCAS) VIH VIL tASR VIH VIL tRAH tASC tCAH tASR
COLUMN ADDRESS ROW ADDRESS
tRP
tRPC tRSH tCRP
tRCD
LCAS (or UCAS)
A0~A8
ROW ADDRESS
tRCS VIH VIL
tCWL tRWL tWP
W
DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS)
DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL tDZC DQ9~DQ16 VIH (or DQ1~DQ8) (INPUTS) VIL
Hi-Z
tWCH tDS
Hi-Z
tDH
DATA VALID
tCLZ
DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL
Hi-Z
Hi-Z
tDZO VIH VIL
tOEZ tODD
tOEH
OE
13
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC tRAS VIH VIL tCRP VIH LCAS/UCAS VIL tASR tRAH tRAD tASC tCAH tASR tCSH tRCD tRSH tCAS tRPC tCRP tRP
RAS
A0~A8
VIH VIL
ROW ADDRESS
COLUMN ADDRESS
ROW ADDRESS
tRCS VIH VIL tDZC DQ1~DQ16 (INPUTS) VIH VIL
Hi-Z
tAWD tCWD tRWD
tCWL tRWL tWP
W
tDS
tDH
DATA VALID
tCAC tAA tCLZ
DQ1~DQ16 VOH (OUTPUTS) VOL
Hi-Z
DATA VALID
Hi-Z
tRAC tDZO VIH VIL tOEA
tODD tOEZ
tOEH
OE
14
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Byte Read-Write, Read-Modify-Write Cycle
tRWC tRAS VIH VIL tCSH tRCD tCRP LCAS (or UCAS) VIH VIL tCAS UCAS (or LCAS) VIH VIL tASR VIH VIL tRAH tRAD tASC tCAH tASR tRSH tCRP tRPC tRP
RAS
A0~A8
ROW ADDRESS
COLUMN ADDRESS
ROW ADDRESS
tRCS VIH VIL
tAWD tCWD tRWD
tCWL tRWL tWP
W
DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS)
DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL
Hi-Z
tDZC DQ9~DQ16 VIH (or DQ1~DQ8) VIL (INPUTS)
Hi-Z
tDS
tDH
DATA VALID
tCAC tAA tCLZ
DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL
Hi-Z
DATA VALID
Hi-Z
tRAC tDZO tOEA
tODD tOEZ tOEH
OE
VIH VIL
15
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle
tRAS VIH VIL tCSH tCRP VIH LCAS/UCAS VIL tRAD tASR VIH VIL tRAH tASC tCAH tASC tCAH tASC tCPRH tCAH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS
tRP
RAS
tASR
A0~A8
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tRCS tCAL VIH VIL tCAL
tRAL tCAL
tRRH tRCH
W
tWEZ tDZC tRDD tCDD
Hi-Z
DQ1~DQ16 (INPUTS)
VIH VIL tCAC tAA tCLZ tCAC tAA tDOH
DATA VALID-1
tCAC tAA tDOH
DATA VALID-2
tREZ tOHR tOFF tOHC
DATA VALID-3
DQ1~DQ16 VOH (OUTPUTS) VOL
Hi-Z
tRAC tDZO
tOEA tOCH
tCPA
tCPA tOEZ
OE
VIH VIL tODD
16
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Byte Read Cycle
tRAS RAS VIH VIL tCSH tCRP tRCD tCP tHPC tCAS tCP tRSH tRP
LCAS (or UCAS)
VIH VIL
tCAS VIH VIL tRAD tASR VIH VIL tRAH tASC tCAH tASC tCAH tASC
tCAS
tCRP
UCAS (or LCAS)
tCPRH tCAH tASR
A0~A8
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tRCS tCAL VIH VIL tDZC tCAL
tRAL tCAL
tRRH tRCH
W
DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS) tCAC tAA DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL
Hi-Z
Hi-Z
tREZ tOHR
DATA VALID-2
tCLZ tDZC DQ9~DQ16 VIH (or DQ1~DQ8) (INPUTS) VIL tCPA
tRDD tCDD
Hi-Z
tCAC tAA tCLZ
tCAC tAA tDOH
tWEZ tOFF tOHC
DATA VALID-3
DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL
Hi-Z
DATA VALID-1
tRAC tDZO
tOEA tOCH
tCPA tOEZ
OE
VIH VIL tODD
17
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Early Write Cycle
tRAS VIH VIL tCSH tCRP VIH LCAS/UCAS VIL tCAL tASR VIH VIL tRAH tASC tCAH tASC tCAH tASC tCAL tCAH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS
tRP
RAS
tCRP
tASR
ROW ADDRESS
A0~A8
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
tWCS VIH VIL tDS
tWCH
tWCS
tWCH
tWCS
tWCH
W
tDH
tDS
tDH
tDS
tDH
DQ1~DQ16 (INPUTS)
VIH VIL
DATA VALID-1
DATA VALID-2
DATA VALID-3
DQ1~DQ16 VOH (OUTPUTS) VOL
Hi-Z
OE
VIH VIL
18
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Byte Early Write Cycle
tRAS RAS VIH VIL tCSH tCRP VIH VIL tRCD VIH VIL tCAL tASR VIH VIL tRAH tASC tCAH tASC tCAH tASC tCAL tCAH tASR
ROW ADDRESS
tRP
tHPC
tRSH
LCAS (or UCAS)
tCAS
tCP
tCAS
tCP
tCAS
tCRP
UCAS (or LCAS)
A0~A8
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
tWCS VIH VIL tDS DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS)
tWCH
tWCS
tWCH
tWCS
tWCH
W
tDH
tDS
tDH
DATA VALID-1
DATA VALID-3
DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL tDS DQ9~DQ16 VIH (or DQ1~DQ8) VIL (INPUTS)
Hi-Z
tDH
DATA VALID-2
DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL
Hi-Z
OE
VIH VIL
19
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read-Write, Read-Modify-Write Cycle
tRAS VIH VIL tCSH tCRP VIH LCAS/UCAS VIL tASR VIH VIL tRAH tRAD tASC tCAH tASC tCAH tCWL tRCD tCAS tCP tHPRWC tCAS
tRP
RAS
tRWL
tCRP
tASR
ROW ADDRESS
A0~A8
ROW ADDRESS
COLUMN-1
COLUMN-2
tRCS VIH VIL
tAWD tCWD
tCWL tWP tRCS
tAWD tCWD
tWP
W
tRWD tDZC DQ1~DQ16 (INPUTS) VIH VIL
Hi-Z
tCPWD tDS tDH
DATA VALID-1
tDZC
Hi-Z
tDS
tDH
DATA VALID-2
tCAC tAA tCLZ
tCAC tAA tCLZ
DATA VALID-1
DQ1~DQ16 VOH (OUTPUTS) VOL
Hi-Z
Hi-Z
DATA VALID-2
Hi-Z
tRAC tDZO tOEA
tODD tOEZ tDZO
tCPA tOEA
tODD tOEH tOEZ
OE
VIH VIL
20
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Byte Read-Write, Read-Modify-Write Cycle
tRAS VIH VIL tCSH tCRP VIH VIL tRCD tCAS tCP UCAS (or LCAS) VIH VIL tASR VIH VIL tRAH tRAD tASC tCAH tASC tCAH tCWL tHPRWC tCAS
tRP
RAS
tRWL
LCAS (or UCAS)
tCRP
tASR
ROW ADDRESS
A0~A8
ROW ADDRESS
COLUMN-1
COLUMN-2
tRCS W VIH VIL
tAWD tCWD
tCWL tWP tRCS
tAWD tCWD
tWP
tRWD
tCPWD
DQ1~DQ8 VIH (or DQ9~DQ16) VIL (INPUTS)
DQ1~DQ8 VOH (or DQ9~DQ16) (OUTPUTS) VOL tDZC DQ9~DQ16 VIH (or DQ1~DQ8) VIL (INPUTS)
Hi-Z
Hi-Z
tDS
tDH
DATA VALID-1
tDZC
Hi-Z
tDS
tDH
DATA VALID-2
tCAC tAA tCLZ
tCAC tAA tCLZ
DQ9~DQ16 VOH (or DQ1~DQ8) (OUTPUTS) VOL
Hi-Z
DATA VALID-1
Hi-Z
DATA VALID-2
Hi-Z
tRAC tDZO tOEA
tODD tOEZ tDZO
tCPA tOEA
tODD tOEH tOEZ
OE
VIH VIL
21
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Mix Cycle (1)
tRAS tRWL RAS VIH VIL tCSH tCRP VIH LCAS/UCAS VIL tRAD tASR VIH VIL tRAH tASC tCAH tASC tCAH tASC tCAH tRCD tCAS tCP tHPC tCAS tCP tHPRWC tCAS tCWL
tRP
tCRP
tASR
ROW ADDRESS
A0~A8
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
tRCS tCAL W VIH VIL tDZC
tWCS
tWCH tCAL
tCPWD tAWD tCWD
tWP
tDS DQ1~DQ16 (INPUTS) VIH VIL tCAC tAA tCLZ DQ1~DQ16 VOH (OUTPUTS) VOL
Hi-Z
DATA VALID-1
tDH
tDZC
tDS
tDH
DATA VALID-2
tAA tCAC tCLZ
DATA VALID-3
DATA VALID-3
tWEZ
tRAC tDZO VIH VIL tODD tOEA tOEZ tOCH OE tDZO
tCPA tOEA tOEZ tOEH
tODD
22
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Mix Cycle (2)
RAS
VIH VIL
VIH LCAS/UCAS VIL tCP tASC VIH VIL tCAL tRCH tWCS W VIH VIL tHCWD tHAWD tHPWD DQ1~DQ16 (INPUTS) VIH VIL
Hi-Z
tCAS tCAH
COLUMN-1
tCAS tASC tCAH tASC tCAH
A0~A8
COLUMN-2
COLUMN-3
tCAL tWCH
tDH tDS
DATA VALID-2
tDZC
Hi-Z
tCAC tAA tCPA tWEZ
DATA VALID-1
tCAC tAA tCPA tCLZ
Hi-Z
DQ1~DQ16 VOH (OUTPUTS) VOL tHCOD tHAOD tHPOD OE VIH VIL
DATA VALID-3
tOEZ tODD
tDZC
tOEA
23
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle (Hi-Z control by OE)
tRAS VIH VIL tCSH tCRP VIH LCAS/UCAS VIL tRAD tASR VIH VIL tRAH tASC tCAH tASC tCAH tCPRH tASC tCAH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS
tRP
RAS
tCRP
tASR
A0~A8
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tRCS VIH VIL
tRAL
tRRH tRCH
W
tWEZ tDZC tRDD tCDD
Hi-Z
DQ1~DQ16 (INPUTS)
VIH VIL tCAC tAA tCLZ tCAC tAA tDOH
DATA VALID-1 DATA VALID-1
tCAC tAA tCLZ
DATA VALID-2 Hi-Z
tREZ tOHR tOFF tOHC
DATA VALID-3
DQ1~DQ16 VOH (OUTPUTS) VOL
Hi-Z
tRAC tDZO VIH VIL tOEA
tOEZ tOCH tOEA
tCPA tCHOL
tCPA tOEZ tOEZ
OE
tOEPE
tOEPE
tODD
24 M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
EDO Mode Read Cycle (Hi-Z control by W)
tRAS VIH VIL tCSH tCRP VIH LCAS/UCAS VIL tRAD tASR VIH VIL tRAH tASC tCAH tASC tCAH tCPRH tASC tCAH tRCD tCAS tCP tHPC tCAS tCP tRSH tCAS
tRP
RAS
tCRP
tASR
A0~A8
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ROW ADDRESS
tRAL tRCS VIH VIL tDZC tWPE tRCH tRCS
tRRH tRCH
W
tWEZ tRDD tCDD
DQ1~DQ16 (INPUTS)
VIH VIL tCAC tAA tCLZ tCAC tAA tDOH
DATA VALID-1
Hi-Z
tCAC tAA tWEZ
DATA VALID-2
tCLZ
Hi-Z
tREZ tOHR tOFF tOHC
DATA VALID-3
DQ1~DQ16 VOH (OUTPUTS) VOL
Hi-Z
tRAC tDZO VIH VIL tOEA tOCH OE
tCPA
tCPA tOEZ
tODD
25
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
RAS-only Refresh Cycle
tRC tRAS RAS VIH VIL tRPC tCRP VIH LCAS/UCAS VIL tASR tRAH tASR tCRP tRP
A0~A8
VIH VIL
ROW ADDRESS
ROW ADDRESS
W
VIH VIL
DQ1~DQ16 (INPUTS)
VIH VIL
DQ1~DQ16 VOH (OUTPUTS) VOL
Hi-Z
OE
VIH VIL
26
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
CAS before RAS Refresh Cycle, Extended Refresh Cycle *
tRC tRP RAS VIH VIL tRPC tCSR tCHR tRAS tRAS
tRC tRP
tRPC tCSR VIH LCAS/UCAS VIL tCPN
tCHR
tRPC
tCRP
tASR A0~A8 VIH VIL tRRH tRCH W VIH VIL
ROW ADDRESS COLUMN ADDRESS
tRCS
DQ1~DQ16 (INPUTS)
VIH VIL tREZ tOHR tOFF tOHC
DQ1~DQ16 VOH (OUTPUTS) VOL tOEZ OE VIH VIL
Hi-Z
27
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Hidden Refresh Cycle (Read)
(Note 32)
tRC tRAS RAS VIH VIL tCRP VIH LCAS/UCAS VIL tASR VIH VIL tRAD tRAH
ROW ADDRESS
tRC tRP tRAS tRP
tRCD
tRSH
tCHR
tASC
tCAH
COLUMN ADDRESS
tASR
A0~A8
ROW ADDRESS
tRCS tRAL VIH W VIL tDZC DQ1~DQ16 (INPUTS) VIH VIL tCAC tAA tCLZ
Hi-Z DATA VALID Hi-Z
tRRH
tCDD tRDD
tREZ tOHR tOFF tOHC
Hi-Z
DQ1~DQ16 VOH (OUTPUTS) VOL
tRAC tDZO VIH VIL
tOEA tORH
tOEZ tODD
OE
Note 32 : Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above.
28
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Self Refresh Cycle * (Note 30)
tRP RAS VIH VIL
tRASS
tRPS
tRPC tRPC VIH LCAS/UCAS VIL tCPN tASR A0~A8 VIH VIL tRRH tRCH W VIH VIL tRDD tCDD DQ1~DQ16 (INPUTS) VIH VIL
Hi-Z ROW ADDRESS
tCSR
tCHS
tCRP
tRCS
tREZ tOHR tOFF tOHC
Hi-Z
DQ1~DQ16 VOH (OUTPUTS) VOL tOEZ tODD OE VIH VIL
29
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
Note 30 : Self refresh sequence Two refreshing methods should be used properly depending on the low pulse width (tRASS) of RAS signal during self refresh period. 1. Distributed refresh during Read/Write operation (A) Timing Diagram
Read / Write Cycle Self Refresh Cycle Read / Write Cycle
tNSD RAS
tRASS100s
tSND
last refresh cycle
first refresh cycle
Table 2
Read / Write Cycle CBR distributed refresh RAS only distributed refresh Read / Write Self Refresh tNSD250s tNSD16s Self Refresh Read / Write tSND250s tSND16s
(B) Definition of distributed refresh tREF tREF / 512 tREF / 512
RAS
refresh cycle read/write cycles refresh cycle refresh cycle read/write cycles
Definition of CBR distributed refresh (Including extended refresh) The CBR distributed refresh performs more than 512 constant period (250s max.) CBR cycles within 128 ms. Definition of RAS only distributed refresh All combinations of nine row address signals (A0 ~ A8) are selected during 512 constant period (16s max.) RAS only refresh cycles within 8.2 ms. Note: Hidden refresh may be used instead of CBR refresh. RAS/CAS refresh may be used instead of RAS only refresh. 1.1 CBR distributed refresh Switching from read/write operation to self refresh operation. The time interval from the falling edge of RAS signal in the last CBR refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tNSD (shown in table 2).
Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period should be set within tSND (shown in table 2). 1.2 RAS only distributed refresh Switching from read/write operation to self refresh operation. The time interval t NSD from the falling edge of RAS signal in the last RAS only refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 16s. Switching from self refresh operation to read/write operation. The time interval tSND from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period should be set within 16s.
30
M5M4V4265CJ,TP-5,-5S:under development
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
2. Burst refresh during Read/Write operation (A) Timing diagram
Read / Write Self Refresh Read / Write
tNSB
tRASS100s
tSNB
RAS
first refresh cycles
refresh cycles 511 cycles
refresh cycles 511 cycles
last refresh cycles
Table 3
Read / Write Cycle CBR burst refresh RAS only burst refresh Read / Write Self Refresh tNSB8.2ms Self Refresh Read / Write tSNB8.2ms
tNSB+tSNB8.2ms
(B) Definition of burst refresh
8.2ms
RAS
refresh cycles 512 cycles
read/write cycles
Definition of CBR burst refresh The CBR burst refresh performs more than 512 continuous CBR cycles within 8.2 ms. Definition of RAS only burst refresh All combination of nine row address signals (A0~A8) are selected during 512 continuous RAS only refresh cycles within 8.2 ms. 2.1 CBR burst refresh Switching from read/write operation to self refresh operation. The time interval tNSB from the falling edge of RAS signal in the first CBR refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within 8.2 ms. Switching from self refresh operation to read/write operation. The time interval tSNB from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last CBR refresh cycle during read/write operation period should be set within 8.2 ms. 2.2 RAS only burst refresh Switching from read/write operation to self refresh operation. The time interval from the falling edge of RAS signal in the first RAS only refresh cycle during read/write operation period to the falling edge of RAS signal at the start of self refresh operation should be set within tNSB (shown in table 3). Switching from self refresh operation to read/write operation. The time interval from the rising edge of RAS signal at the end of self refresh operation to the falling edge of RAS signal in the last RAS only refresh cycle during read/write operation period should be set within tSNB (shown in table 3).
31
M5M4V4265CJ,TP-5,-5S:under development

▲Up To Search▲

Price & Availability of M5M4V4265CJ-5

	To Download M5M4V4265CJ-5 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .