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Integrated Circuit Systems, Inc.
ICS9DB306
PCI EXPRESS, JITTER ATTENUATOR
Features
* Six differential LVPECL output pairs * 1 differential clock input * CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Maximum output frequency: 140MHz * Output skew: 135ps (maximum) * Cycle-to-Cycle jitter: 25ps (maximum) * RMS phase jitter @ 100MHz, (1.5MHz - 22MHz): 3ps (typical) * 3.3V operating supply * 0C to 70C ambient operating temperature * Lead-Free package fully RoHS compliant * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS9DB306 is a high performance 1-to-6 ICS Differential-to LVPECL Jitter Attenuator designed HiPerClockSTM for use in PCI ExpressTM systems. In some PCI ExpressTM systems, such as those found in desktop PCs, the PCI ExpressTM clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a zero delay buffer may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS9DB306 has 2 PLL bandwidth modes. In low bandwidth mode, the PLL loop BW is about 500kHz and this setting will attenuate much of the jitter from the reference clock input while being high enough to pass a triangular input spread spectrum profile. There is also a high bandwidth mode which sets the PLL bandwidth at 1MHz which will pass more spread spectrum modulation. For serdes which have x30 reference multipliers instead of x25 multipliers, 5 of the 6 PCI ExpressTM outputs (PCIEX1:5) can be set for 125MHz instead of 100MHz by configuring the appropriate frequency select pins (FS0:1). Output PCIEX0 will always run at the reference clock frequency (usually 100MHz) in desktop PC PCI ExpressTM Applications.
BLOCK DIAGRAM
nOE0
1 Disabled 0 Enabled /5 Buffer
0 1
PIN ASSIGNMENT
PCIEXT0 nPCIEXC0
VEE PCIEXT1 PCIEXC1 PCIEXT2 PCIEXC2 VCC nOE0 nOE1 VCC PCIEXC3 PCIEXT3 PCIEXC4 PCIEXT4 VEE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC PCIEXC0 PCIEXT0 FS0 nCLK CLK PLL_BW VCCA VEE BYPASS FS1 PCIEXT5 PCIEXC5 VCC
CLK nCLK
Phase Detector
Loop Filter
VCO
0 /4 1 /5
0
PCIEXT1 nPCIEXC1 PCIEXT2 nPCIEXC2
1
FS0 /5 Internal Feedback 0 /5 1 /4
0
ICS9DB306
PCIEXT3 nPCIEXC3 PCIEXT4 nPCIEXC4
1
28-Lead TSSOP, 173-MIL 4.4mm x 9.7mm x 0.92mm body package L Package Top View
PCIEXT5 nPCIEXC5
ICS9DB306
28-Lead, 209-MIL SSOP 5.3mm x 10.2mm x 1.75mm body package F Package Top View
FS1
BYPASS nOE1
1 Disabled 0 Enabled
9DB306BL
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REV. A APRIL 7, 2005
Integrated Circuit Systems, Inc.
ICS9DB306
PCI EXPRESS, JITTER ATTENUATOR
Type Power Output Output Power Input Output Output Output Description Negative supply pins. Differential output pairs. LVPECL interface levels. Differential output pairs. LVPECL interface levels. Core supply pins. Output enable. When HIGH, forces true outputs (PCIEXTx) to go Pulldown LOW and the inver ted outputs (PCIEXCx) to go HIGH. When LOW, outputs are enabled. LVCMOS/LVTTL interface levels. Differential output pairs. LVPECL interface levels. Differential output pairs. LVPECL interface levels. Differential output pairs. LVPECL interface levels. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. Bypass select pin. When HIGH, the PLL is in bypass mode, and the Pulldown device can function as a 1:6 buffer. LVCMOS/LVTTL interface levels. Analog supply pin. Requires 24 series resistor. Pullup Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. VCC/2 default when left floating. Pulldown Pullup Frequency select pin. LVCMOS/LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 14, 20 2, 3 4, 5 6, 9, 15, 28 7, 8 10, 11 12, 13 16, 17 18 19 21 22 23 24 25 Name VEE PCIEXT1, PCIEXC1 PCIEXT2, PCIEXC2 VCC nOE0, nOE1 PCIEXC3, PCIEXT3 PCIEXC4, PCIEXT4 PCIEXC5, PCIEXT5 FS1 BYPASS VCCA PLL_BW CL K nCLK FS0
Input Power Input Input Input Input
PCIEXT0, 26, 27 Output Differential output pairs. LVPECL interface levels. PCIEXC0 NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor
TO
Test Conditions
Minimum
Typical 4 51 51
Maximum
Units pF K K
TABLE 3A. RATIO OF OUTPUT FREQUENCY INPUT FREQUENCY FUNCTION TABLE, FS0
Inputs FS0 0 1 PCIEX0 1 1 Outputs PCIEX1 5/4 1
TABLE 3B. RATIO OF OUTPUT FREQUENCY INPUT FREQUENCY FUNCTION TABLE, FS1
Inputs Outputs PCIEX3 1 5/4 PCIEX4 1 5/4 FS1 0 1
TO
PCIEX2 5/4 1
PCIEX5 1 5/4
TABLE 3C. OUTPUT ENABLE FUNCTION TABLE, nOE0
Inputs nOE0 0 1
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TABLE 3D. OUTPUT ENABLE FUNCTION TABLE, nOE1
Inputs nOE1 0 1 Outputs PCIEX3:5 Enabled Disabled
TABLE 3E. PLL BANDWIDTH FUNCTION TABLE
Inputs PLL_BW 0 1 Bandwidth 500kHz 1MHz
TABLE 3F. PLL MODE FUNCTION TABLE
Inputs BYPASS 1 0 PLL Mode Disabled Enabled
REV. A APRIL 7, 2005
Outputs PCIEX0:2 Enabled Disabled
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Integrated Circuit Systems, Inc.
ICS9DB306
PCI EXPRESS, JITTER ATTENUATOR
4.6V -0.5V to VCC + 0.5V 50mA 100mA 49.8C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCA ICC ICCA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical 3. 3 3. 3 Maximum 3.465 3.465 135 25 Units V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current nOE0, nOE1, FS1, BYPASS FS0, PLL_BW nOE0, nOE1, FS1, BYPASS FS0, PLL_BW VCC = VIN = 3.465V Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 5 VCC = 3.465V, VIN = 0V -5 -150 Units mV mV A A A A
IIL
Input Low Current
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current CLK, nCLK CLK, nCLK Test Conditions VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V 0.15 Minimum Typical Maximum 150 150 1.3 VCC - 0.85 Units A A V V
Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
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REV. A APRIL 7, 2005
Integrated Circuit Systems, Inc.
ICS9DB306
PCI EXPRESS, JITTER ATTENUATOR
Test Conditions Minimum VCC - 1.4 VCC - 2.0 0.6 Typical Maximum VCC - 0.9 VCC - 1.7 1.0 Units V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol Parameter VOH VOL VSWING Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V5%, TA = 0C TO 70C
Symbol fMAX Parameter Output Frequency Output Skew; NOTE 1, 2 Cycle-to-Cycle Jitter, NOTE 2 RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time Integration Range: 1.5MHz - 22MHz 20% to 80% 55 Test Conditions Minimum Typical Maximum 140 135 25 3 200 700 52 Units MHz ps ps ps ps %
tsk(o) tjit(cc) tjit(O)
tR / tF
odc Output Duty Cycle 48 NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot following this section.
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REV. A APRIL 7, 2005
Integrated Circuit Systems, Inc.
ICS9DB306
PCI EXPRESS, JITTER ATTENUATOR
TYPICAL PHASE NOISE AT 100MHZ
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k
PCI ExpressTM Filter 100MHz
RMS Phase Jitter (Random) 1.5MHz to 22MHz = 3ps (typical)
0
NOISE POWER dBc Hz
Raw Phase Noise Data
Phase Noise Result by adding PCI ExpressTM Filter to raw data
1M 10M 100M
The illustrated phase noise plot was taken using a low phase noise signal generator, the noise floor of the signal generator is less than that of the device under test. Using this configuration allows one to see the true spectral purity or phase noise performance of the PLL in the device under
OFFSET FREQUENCY (HZ)
test. Due to the tracking ability of a PLL, it will track the input signal up to its loop bandwidth. Therefore, if the input phase noise is greater than that of the VCO, it will increase the output phase noise performance of the device. It is recommended that the phase noise performance of the input is verified in order to achieve the above phase noise performance.
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REV. A APRIL 7, 2005
Integrated Circuit Systems, Inc.
ICS9DB306
PCI EXPRESS, JITTER ATTENUATOR
PARAMETER MEASUREMENT INFORMATION
2V
VCC
VCC
Qx
SCOPE
nCLK
V
PP
Cross Points
V
CMR
LVPECL
nQx VEE
CLK
V EE
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PCIEXC0:5x PCIEXT0:5x PCIEXC0:5y PCIEXT0:5y
PCIEXC0:5 PCIEXT0:5
tcycle
n
tjit(cc) = tcycle n -tcycle n+1
tsk(o)
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
PCIEXC0:5
80% Clock Outputs
80% VSW I N G
PCIEXT0:5
Pulse Width t
PERIOD
20% tR tF
20%
odc =
t PW t PERIOD
OUTPUT RISE/FALL TIME
9DB306BL
OUTPUT DUTY CYCLE/PULSE WIDTH PERIOD
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REV. A APRIL 7, 2005
tcycle n+1
Integrated Circuit Systems, Inc.
ICS9DB306
PCI EXPRESS, JITTER ATTENUATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS9DB306 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC and VCCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 24 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin.
3.3V VCC .01F V CCA .01F 10F 24
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1 1K Single Ended Clock Input
CLKx
V_REF
nCLKx
C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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REV. A APRIL 7, 2005
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ICS9DB306
PCI EXPRESS, JITTER ATTENUATOR
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
TERMINATION
FOR
LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
RTT =
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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REV. A APRIL 7, 2005
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ICS9DB306
PCI EXPRESS, JITTER ATTENUATOR
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
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REV. A APRIL 7, 2005
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ICS9DB306
PCI EXPRESS, JITTER ATTENUATOR
LVPECL output drivers, one of terminations approaches is shown in this schematic. For additional termination approaches, please refer to the LVPECL Termination Application Note.
SCHEMATIC EXAMPLE
Figure 5 shows an example of ICS9DB306 application schematic. In this example, the device is operated at VCC = 3.3V. The decoupling capacitor should be located as close as possible to the power pin. The input is driven by a HCSL driver. For
Zo = 50 VCC R11 1K R7 24 VCCA U1 VCC C16 10uF C11 0.1uF 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VCC PCIEXC5 PCIEXT5 FS1 BY PASS VEE VCCA PLL_BW CLK nCLK FS0 PCIEXT0 PCIEXC0 VCC VEE PCIEXT4 PCIEXC4 PCIEXT3 PCIEXC3 VCC nOE1 nOE0 VCC PCIEXC2 PCIEXT2 PCIEXC1 PCIEXT1 VEE 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ICS9DB306 VCC R4 50 R5 50 +
VCC
Zo = 50
LVPECL
R6 50
VCC R12 33 Zo = 50
Zo = 50 HCSL R13 33 R1 50 R2 50 R10 1K
R8 1K
R9 1K
Zo = 50 +
Zo = 50
LVPECL R14 50 R15 50
(U1-15)
VCC
(U1-28)
(U1-6)
(U1-9)
VCC=3.3V
C1 0.1uF
C2 0.1uF
C3 0.1uF
C3 0.1uF R16 50
FIGURE 5. EXAMPLE
OF
ICS9DB306 SCHEMATIC
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REV. A APRIL 7, 2005
Integrated Circuit Systems, Inc.
ICS9DB306
PCI EXPRESS, JITTER ATTENUATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS9DB306. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS9DB306 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 135mA = 467.8mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 6 * 30mW = 180mW
Total Power_MAX (3.465V, with all outputs switching) = 467.8mW + 180mW = 647.8mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43.9C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.648W * 43.9C/W = 98.4C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
28-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 82.9C/W 49.8C/W
200
68.7C/W 43.9C/W
500
60.5C/W 41.2C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5.
ICS9DB306
PCI EXPRESS, JITTER ATTENUATOR
VCCO
Q1
VOUT RL 50 VCCO - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CCO
*
For logic high, VOUT = V (V
CCO_MAX
OH_MAX
=V
CCO_MAX
- 0.9V
-V
OH_MAX
) = 0.9V =V - 1.7V
*
For logic low, VOUT = V (V
CCO_MAX
OL_MAX
CCO_MAX
-V
OL_MAX
) = 1.7V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CCO_MAX
CCO_MAX
-V
OH_MAX
) = [(2V - (V
CCO_MAX
-V
OH_MAX
))/R ] * (V
L
CCO_MAX
-V
OH_MAX
)=
[(2V - 0.9V)/50] * 0.9V = 19.8mW ))/R ] * (V
L
Pd_L = [(V
OL_MAX
- (V
CCO_MAX
- 2V))/R ] * (V
L
CCO_MAX
-V
OL_MAX
) = [(2V - (V
CCO_MAX
-V
OL_MAX
CCO_MAX
-V
OL_MAX
)=
[(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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REV. A APRIL 7, 2005
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ICS9DB306
PCI EXPRESS, JITTER ATTENUATOR RELIABILITY INFORMATION
TABLE 7A.
JAVS. AIR FLOW TABLE FOR 28 LEAD TSSOP PACKAGE
JA by Velocity (Linear Feet per Minute)
0 200
68.7C/W 43.9C/W
500
60.5C/W 41.2C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
82.9C/W 49.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7B.
JAVS. AIR FLOW TABLE FOR 28 LEAD SSOP PACKAGE
JA by Velocity (Linear Feet per Minute)
0 200
36C/W
500
30C/W
Multi-Layer PCB, JEDEC Standard Test Boards
49C/W
TRANSISTOR COUNT
The transistor count for ICS9DB306 is: 2190
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REV. A APRIL 7, 2005
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ICS9DB306
PCI EXPRESS, JITTER ATTENUATOR
28 LEAD TSSOP PACKAGE OUTLINE - F SUFFIX
FOR
PACKAGE OUTLINE - L SUFFIX
FOR
28 LEAD SSOP
TABLE 8A. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 9.60 6.40 BASIC 4.50 Millimeters Minimum 28 1.20 0.15 1.05 0.30 0.20 9.80 Maximum
TABLE 8B. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L 0.55 0 0.05 1.65 0.22 0.09 9.90 7.40 5.00 0.65 BASIC 0.95 8 1.85 0.38 0.25 10.50 8.20 5.60 Millimeters Minimum 28 2.00 Maximum
Reference Document: JEDEC Publication 95, MO-150
Reference Document: JEDEC Publication 95, MO-153
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REV. A APRIL 7, 2005
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ICS9DB306
PCI EXPRESS, JITTER ATTENUATOR
Marking ICS9DB306BL ICS9DB306BL Package 28 Lead TSSOP 28 Lead TSSOP on Tape and Reel 28 Lead "Lead-Free" TSSOP 28 Lead "Lead-Free" TSSOP on Tape and Reel 28 Lead SSOP Count 48 per Tube 100 0 48 per Tube 1000 46 per Tube Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS9DB306BL ICS9DB306BLT ICS9DB306BLLF ICS9DB306BLLFT ICS9DB306BF
ICS9DB306BLLF ICS9DB306BLLF ICS9DB306BF
ICS9DB306BFT ICS9DB306BF 28 Lead SSOP on Tape and Reel 1000 0C to 70C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 9DB306BL
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REV. A APRIL 7, 2005
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ICS9DB306
PCI EXPRESS, JITTER ATTENUATOR
REVISION HISTORY SHEET Description of Change Added PLL Mode Function Table. Date 4/7/05
Rev A
Table 3F
Page 2
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