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DATA SHEET
MOS INTEGRATED CIRCUIT
PD30181A, 30181AY
VR4181A 64-/32-BIT MICROPROCESSOR
TM
DESCRIPTION
The PD30181A and 30181AY (VR4181A), which are high-performance 64-/32-bit microprocessors employing the TM TM RISC (reduced instruction set computer) architecture developed by MIPS , are products in the VR Series of microprocessors manufactured by NEC. The VR4181A includes as its CPU the VR4120TM core, an ultra-low-power-consumption core featuring cache memory, a high-speed product-sum operation unit, and a memory management unit. Other on-chip components include an LCD controller, CompactFlash controller, USB host/function controller, DMA controller, SDRAM controller, 2 2 PWM controller, AC97/I S audio interface, full-duplex asynchronous serial interface, IrDA interface, I C serial interface, keyboard interface, touch panel interface, real-time clock, A/D converter, D/A converter, and other controllers and interfaces required for battery-driven mobile information devices, fixed compact information devices, car navigation systems, and compact embedded devices. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. * VR4181A Hardware User's Manual (U16049E) TM * VR4100 Series Architecture User's Manual (U15509E)
FEATURES
VR4120 core (64-bit RISC core) on chip as CPU Pipeline clock: 131 MHz Conforms to MIPS III (except for FPU, LL and SC instructions) and MIPS16 instruction sets Supports MACC and DMACC high-speed product-sum operation instructions On-chip cache memory Capacity includes 8 KB instruction cache and 8 KB data cache Employs a writeback cache Physical addresses: 32 bits Virtual addresses: 40 bits On-chip 32 double-entry TLB Effective power management using four modes: Fullspeed, Standby, Suspend, and Hibernate Employs a high-performance internal system bus (Tbus) DRAM controller supporting 64 Mb, 128 Mb, and 256 Mb SDRAMs External system bus interface supporting ROM, page ROM, flash memory, SRAM, ISA devices, IDE (ATA) devices, and SyncFlashTM memory UMA type LCD controller (supports STN and TFT panels) ExCA register-compatible CompactFlash interface (2 slots) USB host controller (Rev1.1, OHCI Rev1.0) controller USB function (Rev1.1) controller 2 AC97 and I S audio interfaces (1 channel each) Clocked serial interface (1 channel) NS16550-compatible serial interface (3 channels) IrDA (SIR) interface (1 channel) 2 I C bus interfaces (2 channels, PD30181AY only) PWM controller (3 channels) DMA controller supporting chain mode (4 channels) Keyboard scan interface (supports 8 x 12 key matrix) X-Y coordinate auto scan touch panel interface On-chip A/D converter and D/A converter On-chip watchdog timer unit RTC unit (total of 3 timer and counter channels) On-chip PLL and clock generators Power supplies: 2.5 V for core, 3.3 V for I/O block Package: 240-pin plastic FBGA
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U16277EJ1V0DS00 (1st edition) Date Published October 2002 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
(c)
2002
1997
PD30181A, 30181AY
APPLICATIONS
Car navigation systems Digital consumer devices (digital information home equipment) Battery-driven mobile information devices Controllers for embedded devices
ORDERING INFORMATION
Part Number Package 240-pin plastic FBGA (16 x 16)
Note
I C Bus Interface None None On chip On chip
2
Internal Maximum Operating Frequency 131 MHz 131 MHz 131 MHz 131 MHz
PD30181AF1-131-GA3 PD30181AF1-131-GA3-A PD30181AYF1-131-GA3 PD30181AYF1-131-GA3-A
Note Lead-free product
Note
240-pin plastic FBGA (16 x 16) 240-pin plastic FBGA (16 x 16) 240-pin plastic FBGA (16 x 16)
PIN CONFIGURATION
* 240-pin plastic FBGA (16 x 16)
Bottom view
Top view
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
VUTRPNML K J HGF EDCBA
ABCDE FGH J K LMNPRTUV Index mark
2
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(1/3)
No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 C1 C2 C3 C4 Power Supply 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V D6 D5 D3 D1 D8 D10 D12 D14 D16 D17 UDP CLK48 SDCS2# SDCS3# MEMWR# PCS4# PCS1# IORD# D7 DQM1/LBE1# D4 D2 D0 D9 D11 D13 D15 UDN UHDN UPON DQM3/LBE3# PCS3# ROMCS# PCS2# SYSDIR IOWR# DQM0/LBE0# WE# D28 D27 Name No. C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 E1 E2 E3 E4 E8 E9 E10 E11 Power Supply 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 3.3 V 2.5 V 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 2.5 V D26 D24 D23 D22 D20 D18 UHDP UOC NMI# DQM2/LBE2# PCS0# SYSEN# IORDY UBE# CAS# RAS# D29 VDD2 D25 GND2 VDD2 D21 D19 GNDU VDDU GND3 VDD3 GND2 MEMRD# PWM1/KSCAN6/GPIO9 IOCS16# PWM0/KSCAN7/GPIO8 SDCLK SDCS1# D30 VDD3 VDD3 GND3 GND2 VDD2 Name
Remark # indicates active low.
Data Sheet U16277EJ1V0DS
3
PD30181A, 30181AY
(2/3)
No. E15 E16 E17 E18 F1 F2 F3 F4 F15 F16 F17 F18 G1 G2 G3 G4 G15 G16 G17 G18 H1 H2 H3 H4 H5 H14 H15 H16 H17 H18 J1 J2 J3 J4 J5 J14 J15 J16 J17 J18 K1 Power Supply 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V VDD3 KPORT0/GPIO4 PWM2/KSCAN5/GPIO10 KPORT1/GPIO5 SDCS0# CKE0 D31 GND3 GNDP CF1_DIR/KPORT4/GPIO39 KPORT2/GPIO6 CLKX1 A13 A14 TC0#/GPIO52 TC1#/GPIO53 VDDP KPORT3/GPIO7 CF1_EN#/KPORT5/GPIO38 CLKX2 SA10 A0 A23/RP# A24/CKE1 GND2 VDDO GNDO KSCAN0/GPIO0 KSCAN3/GPIO3 RTCX2 A1 A2 A21/GPIO60 A22/GPIO61 GND3 VDD2 GND3 KSCAN1/GPIO1 KSCAN2/GPIO2 RTCX1 A3 Name No. K2 K3 K4 K5 K14 K15 K16 K17 K18 L1 L2 L3 L4 L5 L14 L15 L16 L17 L18 M1 M2 M3 M4 M15 M16 M17 M18 N1 N2 N3 N4 N15 N16 N17 N18 P1 P2 P3 P4 P8 P9 Power Supply 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 2.5 V A12 A19/GPIO58 A20/GPIO59 VDD3 VDD3 SO/KSCAN9/GPIO21 SCK/KSCAN11/GPIO23 FRM/KSCAN8/GPIO20 CF1_VCCEN#/KSCAN4/GPIO37 A11 A9 A17/GPIO56 A18/GPIO57 VDD2 GND2 JTMS JTDO SI/KSCAN10/GPIO22 JTCK A8 A7 A15/GPIO54 A16/GPIO55 JTRST# CF0_IOIS16#/GPIO34 JTDI/RMODE# BKTGIO# A6 A5 A10 GND2 VDD2 CF0_CD2#/GPIO36 CF0_CD1#/GPIO35 CF_WAIT#/GPIO33 A4 DAK1# DRQ1# GNDAD VDD2 GND2 Name
Remark # indicates active low.
4
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(3/3)
No. P10 P11 P15 P16 P17 P18 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 Power Supply 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3V GND2 GND3 CF0_CE2#/GPIO32 CF0_DIR/GPIO27 CF0_READY/GPIO29 CF0_CE1#/GPIO31 DRQ0# POWER RSTSW# GNDTP VDDTP VDDAD VDD3 GND3 DCD2#/SDATAIN/SDI SDA0/KPORT6/GPIO11 VPBIAS/GPO63 VPLCD/GPO62 VDD3 VDD2 GND3 CF_REG#/GPIO25 CF0_RESET/GPIO28 CF0_STSCHG#/GPIO30 RTCRST# POWERON DAK0# TPX1 AIN2 DCD0#/GPIO16 DSR0#/CTS1#/GPIO15 RTS2#/SYNC/WS/DIVMODE1Note 1 DTR2#/SDATAOUT/SDO/DIVMODE0 TxD1/SDA1/GPIO13 ENAB/M/BMODE0Note 1 FPD14/CF1_STSCHG#/GPIO50 FPD13/CF1_CE2#/GPIO49 FPD8/GPIO44 FPD0
Note 1
Name
No. T16 T17 T18 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18
Power Supply 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V FPD2 I.C. (GND3)Note 2 CF0_EN#/GPIO26 MPOWER AIN0 TPX0 TPY0
Name
TxD0/CLKSEL2Note 1 RTS0#/GPIO19/CLKSEL1Note 1 RxD2/IRDIN CTS2#/BITCLK/SCLK I.C. (GND3)Note 2 SCL0/KPORT7/GPIO12 VSYNC/FLM/BMODE1Note 1 FPD15/CF1_READY/GPIO51 FPD12/CF1_CE1#/GPIO48 FPD10/CF1_CD1#/GPIO46 FPD6/GPIO42 FPD4/GPIO40 CF1_RESET/DBUS32Note 1 CF0_VCCEN#/GPIO24 TPY1 AIN1 AIN3 AOUT RxD0 CTS0#/GPIO18 DTR0#/RTS1#/GPIO17/CLKSEL0Note 1 TxD2/IRDOUT/MIPS16ENNote 1 DSR2#/SRESET# RxD1/SCL1/GPIO14 DCLK/SHCLK HSYNC/LOCLK/NWIREENNote 1 FPD11/CF1_CD2#/GPIO47 FPD9/GPIO45 FPD7/GPIO43 FPD5/GPIO41 FPD3 FPD1
Notes 1. These pins are used for mode settings. A mode setting is made according to the status of these pins at the rising edge of the RTCRST# signal. Use pull-up/pull-down resistors to set the pin statuses. 2. Be sure to connect these pins to GND3. Remark # indicates active low.
Data Sheet U16277EJ1V0DS
5
PD30181A, 30181AY
PIN INDENTIFICATION (1/2) A(24:0): AIN(3:0): AOUT: BITCLK: BKTGIO#: BMODE(1:0): CAS#: CF_REG#: CF_WAIT#: CF0_CD(2:1)#: CF0_CE(2:1)#: CF0_DIR: CF0_EN#: CF0_IOIS16#: CF0_READY: CF0_RESET: CF0_STSCHG#: CF0_VCCEN#: CF1_CD(2:1)#: CF1_CE(2:1)#: CF1_DIR: CF1_EN#: CF1_READY: CF1_RESET: CF1_STSCHG#: CF1_VCCEN#: CKE0: CKE1: CLK48: CLKSEL(2:0): CLKX(2:1): D(31:0): DAK(1:0)#: DBUS32: DCD0#, DCD2#: DCLK: DIVMODE(1:0): DQM(3:0): Address bus Analog data Input Analog data output AC97 bit clock N-wire break trigger I/O Boot mode SDRAM column address strobe CompactFlash register memory access CompactFlash wait input CompactFlash card detect CompactFlash card enable CompactFlash data direction CompactFlash buffer enable CompactFlash I/O is 16 bits CompactFlash ready CompactFlash reset CompactFlash status change CompactFlash VCC enable CompactFlash card detect CompactFlash card enable CompactFlash data direction CompactFlash buffer enable CompactFlash ready CompactFlash reset CompactFlash status change CompactFlash VCC enable SDRAM Clock enable SyncFlash memory clock enable USB clock input Pipeline clock select Clock input Data bus DMA acknowledge ROM data bus mode 16550 data carrier detect TFT dot clock Divide-by mode SDRAM byte enable DRQ(1:0)#: DMA request
DSR0#, DSR2#: 16550 data set ready DTR0#, DTR2#: 16550 data terminal ready ENAB: FLM: FPD(15:0): FRM: GND2: GND3: GNDAD: GNDO: GNDP: GNDTP: GNDU: GPIO(61:0): GPO(63:62): HSYNC: I.C.: IOCS16#: IORD#: IORDY: IOWR#: IRDIN: IRDOUT: JTCK: JTDI: JTDO: JTMS: JTRST#: KPORT(7:0): KSCAN(11:0): LOCLK: LBE(3:0)#: M: MEMRD#: MEMWR#: MIPS16EN: MPOWER: NMI#: TFT display enable STN first line clock LCD display data CSI frame input Internal ground I/O ground A/D and D/A converter ground Oscillator ground PLL ground Touch panel ground USB transceiver ground General-purpose I/O General-purpose output TFT horizontal sync Internally connected I/O 16-bit bus sizing I/O read I/O ready I/O write IrDA data input IrDA data output N-wire clock N-wire data input N-wire data output N-wire mode select N-wire reset Key Scan input Key Scan output STN load clock System bus byte enable STN modulation clock Memory read Memory write MIPS16 enable Main power control Non maskable interrupt
CTS0#, CTS1#, CTS2#: 16550 clear to send
Remark # indicates active low.
6
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
PIN INDENTIFICATION (2/2) NWIREEN: PCS(4:0)#: POWER: POWERON: PWM(2:0): RAS#: RMODE#: ROMCS#: RP#: RSTSW#: RTCRST#: RTCX(2:1): RxD0, RxD1, RxD2: SA10: SCLK: SCL1, SCL0: SCK: SDA1, SDA0: SDATAIN: SDATAOUT: SDCLK: SDCS(3:2)#: SDCS(1:0)#: SDI: SDO: SHCLK: SI: N-Wire enable Programmable chip select Power switch Power on state Pulse width modulation SDRAM row address strobe N-wire reset mode select Chip select for ROM SyncFlash memory reset/power-down Reset switch Real-time clock reset Real-time clock input 16550 receive data SDRAM address 10-bit I S continuous clock I C clock CSI serial clock I C data AC97 serial codec data input AC97 serial codec data output SDRAM clock SyncFlash memory chip select SDRAM chip select I S serial codec data input I S serial codec data output STN shift clock CSI data input Remark # indicates active low.
2 2 2 2 2
SO: SRESET#: SYNC: SYSDIR: SYSEN#: TC(1:0)#: TPX(1:0): TPY(1:0): UBE#: UDN: UDP: UHDN: UHDP: UOC: UPON: VDD2: VDD3: VDDAD: VDDO: VDDP: VDDTP: VDDU: VPBIAS: VPLCD: VSYNC: WE#: WS:
CSI data output AC97 reset AC97 synchronous clock System data direction System data enable Terminal counter Touch panel X coordinate data Touch panel Y coordinate data Upper byte enable for system bus USB function negative data USB function positive data USB host negative data USB host positive data USB host root hub port over current USB host root hub port power control Internal power supply I/O power supply A/D and D/A converter power supply Oscillator power supply PLL power supply Touch panel power supply USB transceiver power supply Bias power control Logic power control TFT vertical sync SDRAM write enable I S word select
2
TxD0, TxD1, TxD2: 16550 transmit data
RTS0#, RTS1#, RTS2#: 16550 data request to send
Data Sheet U16277EJ1V0DS
7
PD30181A, 30181AY
INTERNAL BLOCK DIAGRAM AND EXAMPLE OF CONNECTION OF EXTERNAL BLOCKS
PC CompactFlash/ Communication PC Card STN/TFT LCD Panel Color/Monochrome SDRAM/ SyncFlash ROM/Flash memory ISA I/O Devices HDD, CD-ROM Mouse Printer
32/16-bit Bus Buf
Buf
BluetoothTM Baseband USB Func. Control USB Host Control AC97 Control PCM Sound Stereo CODEC RTC/ Timer Power Management I2S Control
LCD Control
SDRAM Control
Bus Control
DMA
Card/IDE Control 2 slots
In-circuit emulator N-Wire
Debug I/F
VR4120 CPU Core
CPU I/F
Bridge
Interrupt Watchdog Control Timer
Bridge
Audio Input
32.768 kHz 18.432 MHz
Clock Generator
Key Scan I/F
PWM Control 3ch
GPIO 64 MAX.
Serial (UART) 3ch
Serial (I2C) 2ch
Serial (CSI)
Touch Panel Control
D/A Analog Control A/D Touch Panel
VR4181A
Port Control LED LCD Backlight Contrast
IrDA/ RS-232-C Driver, Bluetooth Baseband, etc.
CCD Module, Serial EEPROMTM etc.
MCU, CODEC Control, etc.
Battery Monitor
CPU CORE INTERNAL BLOCK DIAGRAM
Virtual address bus Internal data bus
Control (o) Control (i) Address/Data (o) Address/Data (i)
Bus interface
Data cache (8 KB)
Instruction cache (8 KB)
CP0
CPU
TLB
Clock generator Internal clock
8
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
CONTENTS
1. PIN FUNCTIONS .................................................................................................................................. 10
1.1 1.2 1.3 1.4 Pin Functions ......................................................................................................................................... 10 Pin Status in Specific Status ................................................................................................................ 26 Pin I/O Circuit Types and Recommended Connection of Unused Pins............................................ 33 Pin I/O Circuits ....................................................................................................................................... 36
2. ELECTRICAL SPECIFICATIONS ........................................................................................................ 37 3. PACKAGE DRAWING .......................................................................................................................... 68 4. RECOMMENDED SOLDERING CONDITIONS .................................................................................. 69
Data Sheet U16277EJ1V0DS
9
PD30181A, 30181AY
1. PIN FUNCTIONS
Remark # indicates active low.
1.1 Pin Functions
(1) System bus interface signals (1/3)
Signal Name A24 A23 A(22:15) SA10 I/O O O O O Function Address bus These pins are used to specify system bus addresses. They are used to access ROM, flash memory, SRAM, ISA devices, PC Cards, IDE (ATA) devices, and general-purpose devices. Address bit 10 for SDRAM or SyncFlash memory Instead of connecting to A10, connect this pin (SA10) to address bit 10 in SDRAM or SyncFlash memory. Address bus These pins are used to specify system bus addresses. They are used to access SDRAM, SyncFlash memory, ROM, flash memory, SRAM, ISA devices, CompactFlash/PC Cards, IDE (ATA) devices, and general-purpose devices. Data bus These pins are used to transfer data to the VR4181A and SDRAM, SyncFlash memory, ROM, flash memory, SRAM, ISA devices, CompactFlash/PC Cards, IDE (ATA) devices, and general-purpose devices. Programmable chip select These pins can be set as active when the VR4181A accesses ROM, flash memory, SRAM, and general-purpose devices. They can be connected only to devices that are not subject to bus sizing via the IOCS16# pin. Boot ROM chip select This pin can be set as active when the VR4181A accesses boot ROM or flash memory. When the BMODE(1:0) pin status is 01 and the RTCRST# signal has been cleared, the VR4181A fetches the boot code from a device connected to the ROMCS# pin to activate this pin. System bus memory read This pin becomes active when the VR4181A reads data from any of the following devices. * ROM, flash memory, SRAM, or general-purpose devices controlled by the ROMCS# pin or PCS# pin * External ISA bus memory space devices and CompactFlash/PC Card memory space devices Alternate Function CKE1 RP# GPIO(61:54) -
A(14:0)
O
-
D(31:0)
I/O
-
PCS(4:0)#
O
-
ROMCS#
O
-
MEMRD#
O
-
10
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(2/3)
Signal Name MEMWR# I/O O Function System bus memory write This pin becomes active when the VR4181A writes to any of the following devices. * ROM, flash memory, SRAM, or general-purpose devices controlled by the ROMCS# pin or PCS# pin * External ISA bus memory space devices and CompactFlash/PC Card memory space devices System bus I/O read This pin becomes active when the VR4181A reads data from the external ISA bus I/O space devices or CompactFlash/PC Card I/O ports. It is valid only when accessing the external ISA bus I/O space. System bus I/O write This pin becomes active when the VR4181A writes data to external ISA bus I/O space devices or CompactFlash/PC Card I/O ports. It is valid only when accessing the external ISA bus I/O space. System bus I/O channel ready This pin (IORDY) is set as inactive in relation to read/write strobes from the VR4181A in order to extend the access time for a device connected to the system bus. It is set as active once the device is in a mode that supports access from the VR4181A. It can be used to access a device connected to the ROMCS# pin or PCS# pin or a device connected to the external ISA space. System bus sizing request Set this signal as active when an ISA device connected to the system bus accesses data in 16-bit width. Bus sizing that uses this pin IOCS16# is enabled only when accessing the external ISA space. System bus higher byte enable This pin becomes active during system bus access if the higher bytes of the 16-bit data bus are valid. It can be used if a device connected to the ROMCS# or PCS# pin or a device connected to the external ISA space uses 16-bit width. System bus byte enable The LBE(3:0)# signal pins used for 32-bit general-purpose devices are shared as the DQM(3:0) signal pins for SDRAM and SyncFlash memory, so the function of this pin changes based on time division. When the VR4181A accesses a device that uses the ROMCS# pin or PCS# pin, the LBE(3:0)# signals become valid only when the SYSEN# signal is at low level. This signal indicates the data bus's valid byte lane. If the device connected to the ROMCS# pin or PCS# pin has 32-bit width, this pin can be used. When the SYSEN# pin is at high level, this pin operates as the DQM(3:0) pins that are referenced by SDRAM. Alternate Function -
IORD#
O
-
IOWR#
O
-
IORDY
I
-
IOCS16#
I
-
UBE#
O
-
LBE(3:0)#
O
DQM(3:0)
Data Sheet U16277EJ1V0DS
11
PD30181A, 30181AY
(3/3)
Signal Name SYSDIRNote I/O O Function Data bus isolation buffer direction control This signal is valid only when accessing devices other than SDRAM or SyncFlash memory devices. The signal is at high level during read cycles and at low level during write cycles. Enables data bus isolation buffer connection This signal is set to high level during SDRAM and SyncFlash memory cycles and is at low level when accessing any other devices. DMA service request signal The DRQ(1:0)# signals are sampled at the rising edge of TClock. Be sure to hold this signal at active level until a DMA request is acknowledged. Set this signal as inactive when not using the DRQ(1:0)# signals. Enables DMA service request This signal goes to active level when access to the target device occurs via DMA transfer. DMA transfer completion signal (open drain) This signal is driven at active level when a DMA transfer is completed. During a transfer, this signal operates as a DMA stop request input signal. Non-maskable interrupt input This is an interrupt request signal that cannot be masked in relation to the CPU core. When the VR4181A starts normally and the MPOWER signal is at high level, input from the NMI# pin is connected to the CPU core via the ICU. While the MPOWER signal is at low level, input to the NMI# pin is monitored by the PMU as a source of NMI shutdowns. Alternate Function -
SYSEN#Note
O
-
DRQ(1:0)#
I
-
DAK(1:0)#
O
-
TC(1:0)#
I/O
GPIO(53:52)
NMI#
I
-
Note The SYSEN# and SYSDIR signals are buffer control signals used to isolate the SDRAM and SyncFlash memory buses from other low-speed device buses. Isolating high-speed memory access paths from other devices reduces the load on the system bus between the VR4181A and the SDRAM or SyncFlash memory. When using the system bus isolation buffer, the correspondence between the SYSEN# and SYSDIR signals and the data bus isolation status is as shown below.
SYSEN# 0 SYSDIR 0 Bus Operation Enables connection via data bus isolation buffer * Write cycle for ROM, flash memory, SRAM, ISA device, CompactFlash/PC Card, or other general-purpose device * Hibernate mode Enables connection via data bus isolation buffer * Read cycle for ROM, flash memory, SRAM, ISA device, CompactFlash/PC Card, or general-purpose device Disables connection via data bus isolation buffer Read/write cycle for SDRAM or SyncFlash memory
0
1
1
0
12
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(2) Memory interface signals
Signal Name SDCLK I/O O Function Operating clock for SDRAM and SyncFlash memory This signal can also be set (via register settings) to stop clock output when not accessing SDRAM or SyncFlash memory. Operating clock enable signal for SyncFlash memory Operating clock enable signal for SDRAM Chip select signal for SyncFlash memory Chip select signal for SDRAM Row address strobe signal for SDRAM and SyncFlash memory Column address strobe signal for SDRAM and SyncFlash memory Byte enable signal for SDRAM and SyncFlash memory The DQM(3:0) signals for SDRAM and SyncFlash memory shares pins with the LBE(3:0)# signals for 32-bit general-purpose devices, so the function of these pins change based on time division. When the SYSEN# signal is at high level, the pin operates as the DQM(3:0) signals which are referenced by SDRAM. Write enable signal for SDRAM and SyncFlash memory SyncFlash memory initialization/power down signal A23 A24 - - - - - LBE(3:0)# Alternate Function -
CKE1 CKE0 SDCS(3:2)# SDCS(1:0)# RAS# CAS# DQM(3:0)
O O O O O O O
WE# RP#
O O
-
Data Sheet U16277EJ1V0DS
13
PD30181A, 30181AY
(3) Initialization interface signals
Signal Name POWER I/O I Function VR4181A activation request (power switch) signal When the rising edge of this signal is detected in Hibernate mode, an activation factor occurs (the VR4181A restores to Fullspeed mode). VR4181A reset signal This signal initializes the internal statuses of all resettable devices except the RTC timer, PMU, GIU, and PWMU channels 0 and 1. VR4181A RTC reset signal This signal initializes the internal statuses of all resettable devices, including the RTC timer. When supplying power to a device for the first time, be sure to set this signal as active for external circuits. VR4181A activation indication When an activation factor has been detected, this signal becomes active (high level) for a specified amount of time. VR4181A operation in progress indication When 2.5 V circuits are operating, this signal becomes active (high level). In Hibernate mode, it is inactive (low level). When this signal is inactive, the 2.5 V power supply can be stopped. Alternate Function -
RSTSW#
I
-
RTCRST#
I
-
POWERON
O
-
MPOWER
O
-
Remarks 1. Activation factors are used to restore from Hibernate mode to Fullspeed mode. 2. For further description of the operation of initialization interface signals, see Hardware User's Manual. (4) Clock interface signals
Signal Name RTCX(2:1) CLKX(2:1) I/O - - Function 32.768 kHz crystal resonator connection pin 18.432 MHz crystal resonator connection pin Alternate Function - -
14
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(5) LCD interface signals
Signal Name DCLK/SHCLK HSYNC/LOCLK VSYNC/FLM ENAB/M FPD15 I/O O O O O O Function Dot clock (DCLK) for TFT/shift clock (SHCLK) for STN Horizontal sync signal for TFT/load clock for STN Vertical sync signal for TFT/first line clock for STN Display enable signal for TFT/M clock for STN LCD display data Alternate Function - NWIREEN BMODE1 BMODE0 CF1_READY, GPIO51 CF1_STSCHG#, GPIO50 CF1_CE(2:1)#, GPIO(49:48) CF1_CD(2:1)#, GPIO(47:46) GPIO(45:40) - GPO63
FPD14
O
LCD display data
FPD(13:12)
O
LCD display data
FPD(11:10)
O
LCD display data
FPD(9:4) FPD(3:0) VPBIAS
O O O
LCD display data LCD display data LED bias power control This signal can be used as a general-purpose output when not using the LCD controller. LCD logic power control This signal can be used as a general-purpose output when not using the LCD controller.
VPLCD
O
GPO62
Caution The connection between the FPD(15:0) of the VR4181A and LCD panel data line corresponds to the panel data width, as shown below.
VR4181A STN Panel Data (4 Bits) Data line 0 Data line 1 Data line 2 Data line 3 - - - - - - - - - - - - STN Panel Data (8 Bits) Data line 0 Data line 1 Data line 2 Data line 3 Data line 4 Data line 5 Data line 6 Data line 7 - - - - - - - - TFT Panel Data (12 Bits) Data line (B0) Data line (B1) Data line (B2) Data line (B3) Data line (G0) Data line (G1) Data line (G2) Data line (G3) Data line (R0) Data line (R1) Data line (R2) Data line (R3) - - - - TFT Panel Data (16 Bits) Data line (B0) Data line (B1) Data line (B2) Data line (B3) Data line (B4) Data line (G0) Data line (G1) Data line (G2) Data line (G3) Data line (G4) Data line (G5) Data line (R0) Data line (R1) Data line (R2) Data line (R3) Data line (R4)
FPD0 FPD1 FPD2 FPD3 FPD4 FPD5 FPD6 FPD7 FPD8 FPD9 FPD10 FPD11 FPD12 FPD13 FPD14 FPD15
Data Sheet U16277EJ1V0DS
15
PD30181A, 30181AY
(6) CompactFlash/PC Card/IDE (ATA) interface signal
Signal Name CF1_CD(2:1)# I/O I Function CompactFlash/PC Card (slot 1) detection signal Alternate Function FPD(11:10), GPIO(47:46) FPD(13:12), GPIO(49:48) FPD14, GPIO50 FPD15, GPIO51 DBUS32 KPORT4, GPIO39 KPORT5, GPIO38 KSCAN4, GPIO37 GPIO(36:35) GPIO34 GPIO33 GPIO(32:31) GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24
CF1_CE(2:1)#
O
CompactFlash/PC Card (slot 1) enable signal
CF1_STSCHG# CF1_READY CF1_RESET CF1_DIR
I I O O
CompactFlash/PC Card (slot 1) status change signal CompactFlash/PC Card (slot 1) ready signal CompactFlash/PC Card (slot 1) reset signal CompactFlash/PC Card (slot 1) data bus direction control signal
CF1_EN#
O
CompactFlash/PC Card (slot 1) buffer enable signal
CF1_VCCEN#
O
CompactFlash/PC Card (slot 1) VCC enable signal
CF0_CD(2:1)# CF0_IOIS16# CF_WAIT# CF0_CE(2:1)# CF0_STSCHG# CF0_READY CF0_RESET CF0_DIR CF0_EN# CF_REG# CF0_VCCEN#
I I I O I I O O O O O
CompactFlash/PC Card (slot 0) detection signal CompactFlash/PC Card (slot 0) I/O 16-bit bus signal CompactFlash/PC Card (slots 0, 1) wait signal CompactFlash/PC Card (slot 0) enable signal CompactFlash/PC Card (slot 0) status change signal CompactFlash/PC Card (slot 0) ready signal CompactFlash/PC Card (slot 0) reset signal CompactFlash/PC Card (slot 0) data bus direction control signal CompactFlash/PC Card (slot 0) buffer enable signal CompactFlash/PC Card (slots 0, 1) register select signal CompactFlash/PC Card (slot 0) VCC enable signal
Cautions 1. Be sure to use MEMRD#, MEMWR#, IORD#, and IOWR# respectively as CompactFlash/PC Card access strobe signals OE#, WE#, IORD#, and IOWR#. 2. The CF0_EN#, CF1_EN#, CF0_DIR, and CF1_DIR signals are used to control the buffer that isolates the CompactFlash/PC Card's bus from other device's buses. This isolation of the CompactFlash/PC Card's bus enables hot plug-in support. The following table lists the correspondence between the CF0_EN#, CF1_EN#, CF0_DIR, and CF1_DIR signals and data bus isolation statuses when using the data bus isolation buffer.
CF0_EN#, CF1_EN# 0 CF0_DIR, CF1_DIR 0 Operation of Bus
Enable connection via data bus isolation buffer * Write cycle to CompactFlash/PC Card Enable connection via data bus isolation buffer * Read cycle to CompactFlash/PC Card Disable connection via data bus isolation buffer
0
1
1
- (Undefined)
16
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(7) USB (host/function) interface signals
Signal Name CLK48 UHDP I/O I I/O USB clock (48 MHz) USB host serial data (+) signal Be sure to connect a 22 resistor in series for impedance matching. USB host serial data (-) signal Be sure to connect a 22 resistor in series for impedance matching. USB host route hub power control signal USB host route hub overcurrent input signal USB function serial data (+) signal Be sure to connect a 22 resistor in series for impedance matching. USB function serial data (-) signal Be sure to connect a 22 resistor in series for impedance matching. Function Alternate Function - -
UHDN
I/O
-
UPON UOC UDP
O I I/O
- - -
UDN
I/O
-
(8) AC97/I S stereo audio interface signals
Signal Name BITCLK/SCLK I/O I/O Function Bit clock input (12.288 MHz) for AC97/input or output of I S clock (maximum frequency during input: 6.144 MHz). When used as the SCLK signal, this signal is output by the VR4181A when the I2SU is in master mode and is input from an external source in slave mode. Synchronous clock output for AC97/input or output of I2S word select signal When used as the WS signal, this signal is output by the VR4181A when the I2SU is in master mode and is input from an external source in slave mode. Serial data output signal for AC97/serial data output signal for I2S Serial data input signal for AC97/serial data input signal for I2S Reset signal for AC97
2
2
Alternate Function CTS2#
SYNC/WS
I/O
RTS2#, DIVMODE1
SDATAOUT/SDO
O
DTR2#, DIVMODE0 DCD2# DSR2#
SDATAIN/SDI SRESET#
I O
Data Sheet U16277EJ1V0DS
17
PD30181A, 30181AY
(9) Clocked serial interface signals
Signal Name SCK I/O I/O Function Serial clock (maximum frequency for input and output: 4.6 MHz) This signal is output by the VR4181A in master mode and is input from an external source in slave mode. Serial data input signal Alternate Function KSCAN11, GPIO23
SI
I
KSCAN10, GPIO22 KSCAN9 , GPIO21
SO
O
Serial data output signal This signal is set to high impedance when the value of the FRMEN bit and FRMMD bit is 1 in the CSIMODE register, and the FRM signal is at high level. Serial frame signal This signal determines the data direction (transmit/receive), or it can be used to enable (low level) or disable (high level) transfers.
FRM
I
KSCAN8, GPIO20
18
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(10) 16550 (UART) serial interface signals
Signal Name RxD0 TxD0 RTS0# I/O I O O Serial (channel 0) receive data Serial (channel 0) transmit data Serial (channel 0) transmit request signal Function Alternate Function - CLKSEL2 GPIO19, CLKSEL1 GPIO18 GPIO17, CLKSEL0 GPIO16 GPIO15
CTS0# DTR0#/RTS1#
I O
Serial (channel 0) transmit enable signal Serial (channel 0) terminal ready signal/serial (channel 1) transmit request signal Serial (channel 0) carrier detection signal Serial (channel 0) data set ready signal/serial (channel 1) transmit enable signal Serial (channel 1) receive data Serial (channel 1) transmit data Serial (channel 2) receive data Serial (channel 2) transmit data
DCD0# DSR0#/CTS1#
I I
RxD1 TxD1 RxD2 TxD2
I O I O
SCL1, GPIO14 SDA1, GPIO13 IRDIN IRDOUT, MIPS16EN SYNC, WS, DIVMODE1 BITCLK, SCLK SDATAOUT, SDO, DIVMODE0 SDATAIN, SDI SRESET#
RTS2#
O
Serial (channel 2) transmit request signal
CTS2# DTR2#
I O
Serial (channel 2) transmit enable signal Serial (channel 2) terminal ready signal
DCD2# DSR2#
I I
Serial (channel 2) carrier detection signal Serial (channel 2) data set ready signal
(11) IrDA interface signals
Signal Name IRDIN IRDOUT I/O I O IrDA receive data input IrDA transmit data output Function Alternate Function RxD2 TxD2, MIPS16EN
(12) I C serial interface signals (PD30181AY only)
2
Signal Name SCL1 SDA1 SCL0
I/O I/O I/O I/O
2
Function Serial clock (open drain) for I C (channel 1) Serial I/O data (open drain) for I C (channel 1) Serial clock (open drain) for I C (channel 0) Serial I/O data (open drain) for I2C (channel 0)
2 2
Alternate Function RxD1, GPIO14 TxD1, GPIO13 KPORT7, GPIO12 KPORT6, GPIO11
SDA0
I/O
Data Sheet U16277EJ1V0DS
19
PD30181A, 30181AY
(13) PWM interface signals
Signal Name PWM2 I/O O PWM output (channel 2) Function Alternate Function KSCAN5, GPIO10 KSCAN6, GPIO9 KSCAN7, GPIO8
PWM1 PWM0
O O
PWM output (channel 1) PWM output (channel 0)
(14) Keyboard interface signals
Signal Name KPORT7 KPORT6 KPORT5 I/O I I I Key scan input data Key scan input data Key scan input data Function Alternate Function SCL0, GPIO12 SDA0, GPIO11 CF1_EN#, GPIO38 CF1_DIR, GPIO39 GPIO(7:4) SCK, GPIO23 SI, GPIO22 SO, GPIO21 FRM, GPIO20 PWM0, GPIO8 PWM1, GPIO9 PWM2, GPIO10 CF1_VCCEN#, GPIO37 GPIO(3:0)
KPORT4
I
Key scan input data
KPORT(3:0) KSCAN11 KSCAN10 KSCAN9 KSCAN8 KSCAN7 KSCAN6 KSCAN5 KSCAN4
I O O O O O O O O
Key scan input data Key scan output data Key scan output data Key scan output data Key scan output data Key scan output data Key scan output data Key scan output data Key scan output data
KSCAN(3:0)
O
Key scan output data
(15) Touch panel/analog interface signals
Signal Name TPX(1:0) I/O I/O Function Touch panel X coordinate data This signal is used to detect the X coordinate of the touch panel location that has been pressed when the supply voltage is applied to the X coordinates and Y coordinates. Touch panel Y coordinate data This signal is used to detect the Y coordinate of the touch panel location that has been pressed when the supply voltage is applied to the Y coordinates and X coordinates. General-purpose A/D data input General-purpose D/A data output Alternate Function -
TPY(1:0)
I/O
-
AIN(3:0) AOUT
I O
- -
20
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(16) Debug interface signals
Signal Name JTCK JTMS I/O I I N-Wire clock N-Wire mode select signal This signal selects N-Wire serial transfer mode. N-Wire input data/N-Wire reset mode select signal This pin functions alternately as RMODE# and JTDI. When JTRST# is active it functions as RMODE#, and when JTRST# is inactive it functions as JTDI. * RMODE# input When JTRST# is active, this pin is the reset mode pin. The initial value for a debug reset is determined by the level of this signal. A debug reset is a reset of the processor, and there are two types: a debug cold reset and a debug soft reset. This serves the same function as Cold Reset input and Soft Reset input from various target systems. 0: Sets debug reset as valid and resets CPU core 1: Sets debug reset as invalid and does not reset CPU core * JTDI input When the JTRST# signal is inactive, this pin operates as the N-Wire serial data input. N-Wire serial data output N-Wire reset signal N-Wire break trigger I/O * BKTGIO#: When used for input setting When JTRST# is inactive and BKTGIO# is used for input setting, this pin is the event trigger/break request input pin. When break requests are valid, setting BKTGIO# to low level stops execution of user programs in normal mode and forcibly shifts the processor to debug mode. After BKTGIO# goes to low level in debug mode, break requests are retained until the processor is restored to normal mode. 0: Requests break and forcibly shifts processor to debug mode 1: Retains current status of processor * BKTGIO#: When used for output setting When JTRST# is inactive and BKTGIO# is used for output setting, this pin is the event trigger/break output pin. When the processor is operating in normal mode and an event is detected that meets any of the conditions for a hardware breakpoint (instruction address breakpoint or data access breakpoint), an event trigger is output from BKTGIO# as a low level signal (one pulse) and detection of the event is reported to the external debugging tool. Finally, after the event trigger is output, all detected events are reported as one event trigger. When the processor is shifted to debug mode, output continues at low level and all previously non-reported events are not reported. 0: Hardware breakpoint was detected The processor is shifted to debug mode. 1: The processor is in normal mode. Function Alternate Function - -
JTDI/RMODE#
I
-
JTDO JTRST# BKTGIO#
O I I/O
- - -
Data Sheet U16277EJ1V0DS
21
PD30181A, 30181AY
(17) General-purpose I/O signals (1/2)
Signal Name GPO63 GPO62 GPIO(61:54) GPIO(53:52) GPIO51 GPIO50 GPIO(49:48) GPIO(47:46) GPIO(45:40) GPIO39 GPIO38 GPIO37 GPIO(36:35) GPIO34 GPIO33 GPIO(32:31) GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 I/O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O General-purpose I/O ports General-purpose output ports Function Alternate Function VPBIAS VPLCD A(22:15) TC(1:0)# FPD15, CF1_READY FPD14, CF1_STSCHG# FPD(13:12), CF1_CE(2:1)# FPD(11:10), CF1_CD(2:1)# FPD(9:4) CF1_DIR, KPORT4 CF1_EN#, KPORT5 CF1_VCCEN#, KSCAN4 CF0_CD(2:1)# CF0_IOIS16# CF_WAIT# CF0_CE(2:1)# CF0_STSCHG# CF0_READY CF0_RESET CF0_DIR CF0_EN# CF_REG# CF0_VCCEN# SCK, KSCAN11 SI, KSCAN10 SO, KSCAN9 FRM, KSCAN8 RTS0#/ CLKSEL1 CTS0#
22
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(2/2)
Signal Name GPIO17 I/O I/O General-purpose I/O ports Function Alternate Function DTR0#, RTS1#, CLKSEL0 DCD0# DSR0#, CTS1# RxD1, SCL1 TxD1, SDA1 SCL0, KPORT7 SDA0, KPORT6 PWM2, KSCAN5 PWM1, KSCAN6 PWM0, KSCAN7 KPORT(3:0) KSCAN(3:0)
GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 GPIO(7:4) GPIO(3:0)
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Data Sheet U16277EJ1V0DS
23
PD30181A, 30181AY
(18) Mode setting signals These signals are used to set various modes. These signals are sampled only when the RTCRST# signal has changed to high level. At all other times, they can be used as alternate-function pins. In order to disconnect a pull-up or pull-down resistor for mode setting during normal operation, use a switch linked to the RTCRST# signal.
Signal Name BMODE1 BMODE0 I/O I I Function Boot ROM type setting BMODE(1:0) = 01: ROM/flash memory BMODE(1:0) = 10: SyncFlash memory BMODE(1:0) = 00 or 11: Setting prohibited N-Wire use enable signal 0: Disabled 1: Enabled Boot ROM bus width specification 0: 16 bits 1: 32 bits Set frequency of CPU core's pipeline reference clock (AClock) CLKSEL(2:0) = 111: Setting prohibited (147.4 MHz) CLKSEL(2:0) = 110: 131.1 MHz CLKSEL(2:0) = 101: 118.0 MHz CLKSEL(2:0) = 100: 98.3 MHz CLKSEL(2:0) = 011: 90.7 MHz CLKSEL(2:0) = 010: 84.1 MHz CLKSEL(2:0) = 001: 78.5 MHz CLKSEL(2:0) = 000: 73.7 MHz Set division ratio of AClock and internal system bus reference clock (TClock) DIVMODE(1:0) = 10: AClock/2 (DIV2 mode) DIVMODE(1:0) = 01: AClock/3 (DIV3 mode) DIVMODE(1:0) = 11, 00: Setting prohibited Enables use of MIPS16 instruction set 0: Use disabled 1: Use enabled Alternate Function VSYNC, FLM ENAB, M
NWIREEN
I
HSYNC, LOCLK
DBUS32
I
CF1_RESET
CLKSEL2 CLKSEL1 CLKSEL0
I I I
TxD0 RTS0#, GPIO19 DTR0#, RTS1#, GPIO17
DIVMODE1
I
RTS2#, SYNC, WS DTR2#, SDO, SDATAOUT TxD2, IRDOUT
DIVMODE0
I
MIPS16EN
I
24
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(19) Dedicated VDD/GND signals
Signal Name VDD2 GND2 VDD3 GND3 VDDU GNDU VDDP GNDP VDDO GNDO VDDAD Power Supply 2.5 V 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 2.5 V 3.3 V 3.3 V 3.3 V Power supply for internal logic GND for internal logic Power supply for I/O buffers (except for I/O buffer of USB transceiver) GND for I/O buffers (except for I/O buffer of USB transceiver) Dedicated power supply for USB transceiver Dedicated GND for USB transceiver Dedicated power supply for PLL (analog unit) Dedicated GND for PLL (analog unit) Dedicated power supply for oscillator Dedicated GND for oscillator Dedicated power supply for the A/D and D/A converters. The voltage applied to this pin becomes the maximum voltage value for the A/D and D/A converters' interface signals. Dedicated GND for the A/D and D/A converters. The voltage applied to this pin becomes the minimum voltage value for the A/D and D/A converters' interface signals. Dedicated power supply for touch panel interface Dedicated GND for touch panel interface Function
GNDAD
3.3 V
VDDTP GNDTP
3.3 V 3.3 V
Caution The VR4181A includes two power supply systems, a 2.5 V system and a 3.3 V system. When applying a voltage, be sure to apply it to the 3.3 V power supply system first. Apply voltage to the 2.5 V power supply system according to the status of the MPOWER pin.
Data Sheet U16277EJ1V0DS
25
PD30181A, 30181AY
1.2 Pin Statuses in Specific Status
(1/7)
Pin Name (Signal Name) AlternateFunction Pin Name (Alternate Signal Name) CKE1 RP# GPIO(61:54) - - - - - - - - - - - - - GPIO(53:52) - - - - A23 - A24 - - - - During RTC Reset After RTC Reset After Reset by RSTSW or Watchdog Timer In Suspend Mode In Hibernate Mode or During Shutdown by HALTimer 0 0 0 0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z 0 Hi-Z 0 0 Hi-Z Hi-Z Hi-Z - Hi-Z Hi-Z Hi-Z 0 0 0 0 0 0 0
A24 A23 A(22:15) A(14:0) SA10 D(31:0) IORD# IOWR# IORDY IOCS16# UBE# PCS(4:0)# SYSDIR SYSEN# DRQ(1:0)# DAK(1:0)# TC(1:0)# NMI# ROMCS# MEMRD# MEMWR# RP# SDCLK CKE1 CKE0 SDCS(3:2)# SDCS(1:0)# RAS#
0 0 0 0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z 0 Hi-Z 0 0 Hi-Z Hi-Z Hi-Z - Hi-Z Hi-Z Hi-Z 0 0 0 0 0 0 0
0 0 0 0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z 0 Hi-Z 0 0 Hi-Z Hi-Z Hi-Z - Hi-Z Hi-Z Hi-Z 0 Operating 1 1 1 1 1
0 0 0 0 0 0 1 1 - - 1/0 1 0 1/0 - 1 - - 1 1 1 1 Operating 1 Note 2 1/0 1/0 1/0
Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 - - Note 1 Note 1 Note 1 Note 1 - Note 1 Note 1 - Note 1 Note 1 Note 1 Note 1 0 Note 1 0 1/0 1/0 1/0
Notes 1. The status in the previous Fullspeed mode is retained. 2. Changes according to the setting in the SDRAMACT register in the GIU. When SDACT bit = 0: 1 When SDACT bit = 1: 0 Remarks 1. 0: Low level, 1: High level, Hi-Z: High impedance 2. When a pin has high impedance, the buffer's input enable setting is OFF. Leakage current will not occur even when an intermediate level is applied.
26
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(2/7)
Pin Name (Signal Name) AlternateFunction Pin Name (Alternate Signal Name) - - During RTC Reset After RTC Reset After Reset by RSTSW or Watchdog Timer In Suspend Mode In Hibernate Mode or During Shutdown by HALTimer 0 0
CAS# DQM(3:0), LBE(3:0)# WE# POWER RSTSW# RTCRST# POWERON MPOWER RTCX(2:1) CLKX(2:1) DCLK, SHCLK
0 0
1 0
1/0 1/0
1/0 1/0
- - - - - - - - -
0 - - - 0 0 - - 0 Note 2 Note 3 Note 3 Hi-Z
1 - - - 0 0 - - 0 0 0 0 Hi-Z
1/0 - - - 0 1 - - 0 0 0 0 0
1/0 - - - 0 1 - - Note 1 Note 1 Note 1 Note 1 Note 1
0 - - - 0 0 - - 0 0 0 0 Hi-Z
HSYNC, LOCLK NWIREEN VSYNC, FLM ENAB, M FPD15 BMODE1 BMODE0 CF1_READY, GPIO51 CF1_STSCHG#, GPIO50 CF1_CE(2:1)#, GPIO(49:48) CF1_CD(2:1)#, GPIO(47:46) GPIO(45:40) - GPO62 GPO63
FPD14
Hi-Z
Hi-Z
0
Note 1
Hi-Z
FPD(13:12)
Hi-Z
Hi-Z
0
Note 1
Hi-Z
FPD(11:10)
Hi-Z
Hi-Z
0
Note 1
Hi-Z
FPD(9:4) FPD(3:0) VPLCD VPBIAS
Hi-Z 0 Hi-Z Hi-Z
Hi-Z 0 Hi-Z Hi-Z
0 0 Hi-Z Hi-Z
Note 1 Note 1 Hi-Z Hi-Z
0 0 Hi-Z Hi-Z
Notes 1. The status in the previous Fullspeed mode is retained. If the LCD panel's voltage drops during Suspend mode, enter settings in the LCU register to stop output operations and set the pin's value to 0. 2. The input level is sampled when the RTCRST# signal has changed to high level in order to enable or disable use of the N-Wire. 3. The input level is sampled when the RTCRST# signal has changed to high level in order to set the boot ROM type. Remarks 1. 0: Low level, 1: High level, Hi-Z: High impedance 2. When a pin has high impedance, the buffer's input enable setting is OFF. Leakage current will not occur even when an intermediate level is applied.
Data Sheet U16277EJ1V0DS
27
PD30181A, 30181AY
(3/7)
Pin Name (Signal Name) AlternateFunction Pin Name (Alternate Signal Name) FPD(11:10), GPIO(47:46) FPD(13:12) , GPIO(49:48) FPD14, GPIO50 FPD15, GPIO51 DBUS32 KPORT4, GPIO39 KPORT5, GPIO38 KSCAN4, GPIO37 GPIO(36:35) GPIO34 GPIO33 GPIO(32:31) GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 - - - - - - During RTC Reset After RTC Reset After Reset by RSTSW or Watchdog Timer In Suspend Mode In Hibernate Mode or During Shutdown by HALTimer Hi-Z
CF1_CD(2:1)#
Hi-Z
Hi-Z
-
-
CF1_CE(2:1)#
Hi-Z
Hi-Z
Hi-Z
Note 1
Hi-Z
CF1_STSCHG# CF1_READY CF1_RESET CF1_DIR
Hi-Z Hi-Z Note 2 Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z
- - Hi-Z 0
- - Note 1 Note 1
Hi-Z Hi-Z Note 3 Hi-Z
CF1_EN#
Hi-Z
Hi-Z
Hi-Z
Note 1
Hi-Z
CF1_VCCEN#
Hi-Z
Hi-Z
1
Note 1
Hi-Z
CF0_CD(2:1)# CF0_IOIS16# CF_WAIT# CF0_CE(2:1)# CF0_STSCHG# CF0_READY CF0_RESET CF0_DIR CF0_EN# CF_REG# CF0_VCCEN# CLK48 UHDP UHDN UPON UOC UDP
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 Hi-Z Hi-Z
- - - Hi-Z - - Hi-Z 0 Hi-Z Hi-Z 1 Note 3 Hi-Z Hi-Z 0 Hi-Z Hi-Z
- - - Note 1 - - Note 1 Note 1 Note 1 Note 1 Note 1 Note 3 Hi-Z Hi-Z 0 Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z - Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 Hi-Z Hi-Z
Notes 1. The status in the previous Fullspeed mode is retained. 2. The input level is sampled when the RTCRST# signal has changed to high level in order to set the boot ROM bus width. 3. The registers in the GIU can be used to set 1, 0, or high impedance. Remarks 1. 0: Low level, 1: High level, Hi-Z: High impedance 2. When a pin has high impedance, the buffer's input enable setting is OFF. Leakage current will not occur even when an intermediate level is applied.
28
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(4/7)
Pin Name (Signal Name) AlternateFunction Pin Name (Alternate Signal Name) - SCLK, CTS2# WS, RTS2#, DIVMODE1 SDO, DTR2#, DIVMODE0 SDI, DCD2# DSR2# BITCLK, CTS2# SYNC, RTS2#, DIVMODE1 SDATAOUT, DTR2#, DIVMODE0 SDATAIN, DCD2# KSCAN11, GPIO23 KSCAN10, GPIO22 KSCAN9, GPIO21 KSCAN8, GPIO20 - CLKSEL2 GPIO19, CLKSEL1 GPIO18 During RTC Reset After RTC Reset After Reset by RSTSW or Watchdog Timer In Suspend Mode In Hibernate Mode or During Shutdown by HALTimer Hi-Z Hi-Z Hi-Z
UDN BITCLK SYNC
Hi-Z Hi-Z Note 1
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
SDATAOUT
Note 1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SDATAIN SRESET# SCLK WS
Hi-Z Hi-Z Hi-Z Note 1
Hi-Z Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z
SDO
Note 1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SDI
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
Hi-Z
Hi-Z
Hi-Z
Note 2
Hi-Z
SI
Hi-Z
Hi-Z
Hi-Z
Note 2
Hi-Z
SO
Hi-Z
Hi-Z
Hi-Z
Note 2
Hi-Z
FRM
Hi-Z
Hi-Z
-
Note 2
Hi-Z
RxD0 TxD0 RTS0#
Hi-Z Note 3 Note 3
Hi-Z Hi-Z Hi-Z
- 1 1
- Note 2 Note 2
Hi-Z 1 1
CTS0#
Hi-Z
Hi-Z
-
-
Hi-Z
Notes 1. The input level is sampled when the RTCRST# signal has changed to high level in order to set the division ratio for the CPU core's pipeline reference clock (AClock) and the peripheral system bus's reference clock (TClock). 2. The status in the previous Fullspeed mode is retained. 3. The input level is sampled when the RTCRST# signal has changed to high level in order to set the frequency of the CPU core's pipeline reference clock (AClock). Remarks 1. 0: Low level, 1: High level, Hi-Z: High impedance 2. When a pin has high impedance, the buffer's input enable setting is OFF. Leakage current will not occur even when an intermediate level is applied.
Data Sheet U16277EJ1V0DS
29
PD30181A, 30181AY
(5/7)
Pin Name (Signal Name) AlternateFunction Pin Name (Alternate Signal Name) RTS1#, GPIO17, CLKSEL0 GPIO16 CTS1#, GPIO15 SCL1, GPIO14 SDA1, GPIO13 DTR0#, GPIO17, CLKSEL0 DSR0#, GPIO15 IRDIN IRDOUT, MIPS16EN SYNC, WS, DIVMODE1 SCLK, BITCLK SDO, SDATAOUT, DIVMODE0 SDI, SDATAIN SRESET# RxD2 TxD2, MIPS16EN During RTC Reset After RTC Reset After Reset by RSTSW or Watchdog Timer In Suspend Mode In Hibernate Mode or During Shutdown by HALTimer Hi-Z
DTR0#
Note 1
Hi-Z
1
Note 2
DCD0# DSR0# RxD1 TxD1 RTS1#
- - Hi-Z Hi-Z Note 1
- - Hi-Z Hi-Z Hi-Z
- - - 1 1
- - - Note 2 Note 2
- Hi-Z Hi-Z Hi-Z Hi-Z
CTS1# RxD2 TxD2
- Hi-Z Note 3
- Hi-Z Hi-Z
- Hi-Z 1
- Hi-Z Note 2
Hi-Z Hi-Z Hi-Z
RTS2#
Note 4
Hi-Z
1
Note 2
Hi-Z
CTS2# DTR2#
Hi-Z Note 4
Hi-Z Hi-Z
Hi-Z 1
- Note 2
Hi-Z Hi-Z
DCD2# DSR2# IRDIN IRDOUT
Hi-Z Hi-Z Hi-Z Note 3
Hi-Z Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z 0
- - Hi-Z Note 2
Hi-Z Hi-Z Hi-Z Hi-Z
Notes 1. The input level is sampled when the RTCRST# signal has changed to high level in order to set the frequency of the CPU core's pipeline reference clock (AClock). 2. The status in the previous Fullspeed mode is retained. 3. The input level is sampled when the RTCRST# signal has changed to high level in order to set whether to use the MIPS16 instruction set or not. 4. The input level is sampled when the RTCRST# signal has changed to high level in order to set the division ratio for the CPU core's pipeline reference clock (AClock) and the peripheral system bus's reference clock (TClock). Remarks 1. 0: Low level, 1: High level, Hi-Z: High impedance 2. When a pin has high impedance, the buffer's input enable setting is OFF. Leakage current will not occur even when an intermediate level is applied.
30
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(6/7)
Pin Name (Signal Name) AlternateFunction Pin Name (Alternate Signal Name) RxD1, GPIO14 TxD1, GPIO13 KPORT7, GPIO12 KPORT6, GPIO11 KSCAN5, GPIO10 KSCAN6, GPIO9 KSCAN7, GPIO8 SCL0, GPIO12 SDA0, GPIO11 CF1_EN#, GPIO38 CF1_DIR, GPIO39 GPIO(7:4) SCK, GPIO23 SI, GPIO22 SO, GPIO21 FRM, GPIO20 PWM0, GPIO8 PWM1, GPIO9 PWM2, GPIO10 CF1_VCCEN#, GPIO37 GPIO(3:0) - - - - During RTC Reset After RTC Reset After Reset by RSTSW or Watchdog Timer In Suspend Mode In Hibernate Mode or During Shutdown by HALTimer Hi-Z Hi-Z Hi-Z
SCL1Note 1 SDA1Note 1 SCL0
Note 1
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
Note 2 Note 2 Note 2
SDA0Note 1
Hi-Z
Hi-Z
Hi-Z
Note 2
Hi-Z
PWM2
Hi-Z
Hi-Z
0
Note 2
Hi-Z
PWM1
Hi-Z
Hi-Z
Note 2
Note 2
Note 2
PWM0
Hi-Z
Hi-Z
Note 2
Note 2
Note 2
KPORT7 KPORT6 KPORT5
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
- - -
- - -
Hi-Z Hi-Z Hi-Z
KPORT4
Hi-Z
Hi-Z
-
-
Hi-Z
KPORT(3:0) KSCAN11 KSCAN10 KSCAN9 KSCAN8 KSCAN7 KSCAN6 KSCAN5 KSCAN4
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
- 0 0 0 0 0 0 0 0
- Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
KSCAN(3:0) TPX(1:0) TPY(1:0) AIN(3:0) AOUT
Hi-Z 1 Hi-Z - 0
Hi-Z 1 Hi-Z - 0
0 1 Hi-Z - 0
Note 2 Note 2 Note 2 - Note 2
Hi-Z 1 Hi-Z - 0
Notes 1. PD30181AY only 2. The status in the previous Fullspeed mode is retained. Remarks 1. 0: Low level, 1: High level, Hi-Z: High impedance 2. When a pin has high impedance, the buffer's input enable setting is OFF. Leakage current will not occur even when an intermediate level is applied.
Data Sheet U16277EJ1V0DS
31
PD30181A, 30181AY
(7/7)
Pin Name (Signal Name) AlternateFunction Pin Name (Alternate Signal Name) - - - During RTC Reset After RTC Reset After Reset by RSTSW or Watchdog Timer In Suspend Mode In Hibernate Mode or During Shutdown by HALTimer Hi-Z Hi-Z Hi-Z
JTCKNote 1 JTMSNote 1 JTDI , RMODE# JTDONote 1 JTRST#
Note 1 Note 1
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
- - - VPBIAS VPLCD
Note 2
Hi-Z Hi-Z Hi-Z Hi-Z HI-Z Hi-Z Hi-Z
Note 5
Hi-Z Hi-Z Hi-Z HI-Z Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note 3 Note 3
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note 3 Note 3
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note 3 Note 3
BKTGIO# GPO63 GPO62
Note 1
GPIO(61:54) GPIO(53:0)
A(22:15) Note 4
Notes 1. This is the pin status when the N-Wire function has been set to use prohibit status via a setting for the NWIREEN pin. 2. When SyncFlash memory has been selected as the boot ROM, this pin can be used as the GPIO pin. 3. The registers in the GIU can be used to set 1, 0, or high impedance. 4. See the other pin names and alternate-function pin names. 5. The GPIO19 and GPIO17 signals are sampled as CLKSEL(1:0) when the RTCRST# signal has changed to high level in order to set the frequency of the CPU core's pipeline reference clock (AClock). Caution After an RTC reset, the GPIO pins are set in the input direction and input disable status is set. Input enable status can be set by software after an RTC reset. Accordingly, there is no need to externally add elements such as pull-up or pull-down resistors for unused GPIO pins in order to determine the signal status. However, GPIO(61:54), which are shared with A(22:15), function as GPIO pins only when SyncFlash memory has been selected. registers in advance. Remarks 1. 0: Low level, 1: High level, Hi-Z: High impedance 2. When a pin has high impedance, the buffer's input enable setting is OFF. Leakage current will not occur even when an intermediate level is applied. The status of output pins in Hibernate mode can be specified by using software to enter the required settings in internal
32
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
1.3 Pin I/O Circuit Types and Recommended Connection of Unused Pins
(1/3)
Pin Name A24/CKE1 A23/RP# A(22:15)/GPIO(61:54) A(14:0) SA10 D(31:0) IORD# IOWR# IORDY IOCS16# UBE# PCS(4:0)# SYSDIR SYSEN# DRQ(1:0)# DAK(1:0)# TC(1:0)#/GPIO(53:52) NMI# ROMCS# MEMRD# MEMWR# SDCLK CKE0 SDCS(3:0)# RAS# CAS# DQM(3:0)/LBE(3:0)# WE# POWER RSTSW# RTCRST# POWERON MPOWER DCLK/SHCLK HSYNC/LOCLK/NWIREEN VSYNC/FLM/BMODE1
Note Note
I/O O O I/O O O I/O O O I I O O O O I O I/O I O O O O O O O O O O I I I O O O I/O I/O
I/O Circuit Type A A A A A A A A A A A A A A A A A A A A A A A A A A A A B B B A A A A A
Recommended Connection of Unused Pins Leave open Leave open Leave open Leave open Leave open Connect to VDD3 or GND3 via a resistor Leave open Leave open Connect to VDD3 Connect to VDD3 Leave open Leave open Leave open Leave open Connect to VDD3 Leave open Leave open Connect to VDD3 Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Connect to VDD3 Connect to VDD3 - Leave open Leave open Leave open Connect to VDD3 or GND3 via a resistor Connect to VDD3 or GND3 via a resistor
Note The signal level is sampled when the RTCRST# signal has changed to high level.
Data Sheet U16277EJ1V0DS
33
PD30181A, 30181AY
(2/3)
Pin Name ENAB/M/BMODE0Note FPD15/CF1_READY/GPIO51 FPD14/CF1_STSCHG#/GPIO50 FPD(13:12)/CF1_CE(2:1)#/GPIO(49:48) FPD(11:10)/CF1_CD(2:1)#/GPIO(47:46) FPD(9:4)/GPIO(45:40) FPD(3:0) VPLCD/GPO62 VPBIAS/GPO63 CF1_RESET/DBUS32
Note
I/O I/O I/O I/O I/O I/O I/O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O
Note
I/O Circuit Type A A A A A A A A A B B B B B B B B B B B B B B B B B B B B B B B B B B B B B
Recommended Connection of Unused Pins Connect to VDD3 or GND3 via a resistor Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Connect to VDD3 or GND3 via a resistor Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Connect to VDD3 or GND3 via a resistor Connect to VDD3 or GND3 via a resistor Leave open Connect to VDD3 or GND3 via a resistor Leave open Leave open Connect to VDD3 Connect to VDD3 or GND3 via a resistor Connect to VDD3 or GND3 via a resistor
CF1_DIR/KPORT4/GPIO39 CF1_EN#/KPORT5/GPIO38 CF1_VCCEN#/KSCAN4/GPIO37 CF0_CD(2:1)#/GPIO(36:35) CF0_IOIS16#/GPIO34 CF_WAIT#/GPIO33 CF0_CE(2:1)#/GPIO(32:31) CF0_STSCHG#/GPIO30 CF0_READY/GPIO29 CF0_RESET/GPIO28 CF0_DIR/GPIO27 CF0_EN#/GPIO26 CF_REG#/GPIO25 CF0_VCCEN#/GPIO24 SCK/KSCAN11/GPIO23 SI/KSCAN10/GPIO22 SO/KSCAN9/GPIO21 FRM/KSCAN8/GPIO20 RxD2/IRDIN TxD2/IRDOUT/MIPS16ENNote RTS2#/SYNC/WS/DIVMODE1Note CTS2#/BITCLK/SCLK DTR2#/SDATAOUT/SDO/DIVMODE0 DCD2#/SDATAIN/SDI DSR2#/SRESET# RxD0 TxD0/CLKSEL2
Note
I/O I I/O I I/O
RTS0#/GPIO19/CLKSEL1
Note
I/O
Note The signal level is sampled when the RTCRST# signal has changed to high level.
34
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(3/3)
Pin Name CTS0#/GPIO18 DTR0#/RTS1#/GPIO17/CLKSEL0Note DCD0#/GPIO16 DSR0#/CTS1#/GPIO15 RxD1/SCL1/GPIO14 TxD1/SDA1/GPIO13 SCL0/KPORT7/GPIO12 SDA0/KPORT6/GPIO11 PWM2/KSCAN5/GPIO10 PWM1/KSCAN6/GPIO9 PWM0/KSCAN7/GPIO8 KPORT(3:0)/GPIO(7:4) KSCAN(3:0)/GPIO(3:0) CLK48 UHDP UHDN UPON UOC UDP UDN TPX(1:0) TPY0 TPY1 AIN(3:0) AOUT JTCK JTMS JTDI/RMODE# JTDO JTRST# BKTGIO# I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O O I I/O I/O I/O I/O I/O I O I I I O I I/O I/O Circuit Type B B B B B B B B B B B B B A G G A B G G C C D E F A A A A A A Recommended Connection of Unused Pins Leave open Connect to VDD3 or GND3 via a resistor Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Connect to GND3 Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open
Note The signal level is sampled when the RTCRST# signal has changed to high level.
Data Sheet U16277EJ1V0DS
35
PD30181A, 30181AY
1.4 Pin I/O Circuits
Type A
VDD3 Data P-ch IN/OUT
Type D
VDDTP Data P-ch IN/OUT
Output disable
N-ch
Output disable P-ch
N-ch
Input enable
+ - Vref
N-ch
Type B
VDD3 Data P-ch IN/OUT Open drain Output disable
Input enable
N-ch
N-ch
Type E
IN P-ch N-ch Vref + -
Input enable
Type C
VDDTP Data P-ch IN/OUT
Type F
Analog output voltage OUT
Type G
Output disable P-ch + - Vref N-ch N-ch
Data Output disable
-IN/OUT
+IN/OUT
+ - Input enable
Remark Type A: Low slew-rate output Type B: Schmitt-triggered input, low slew-rate output Type G: Differential I/O
36
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD25 VDD33 Input voltage VI Condition 2.5 V (VDD2, VDDP pins) 3.3 V (VDD3, VDDU, VDDTP, VDDAD, VDDO pins) VDD33 3.7 V VDD33 < 3.7 V Storage temperature Tstg Rating -0.5 to +3.6 -0.5 to +4.0 -0.5 to +4.0 -0.5 to VDD33 + 0.3 -65 to +125 Unit V V V V C
Cautions 1. Do not short-circuit two or more output pins simultaneously. 2. If even one of the above parameters exceeds the absolute maximum ratings even momentarily, the quality of the product may be degraded. The absolute maximum ratings, therefore, specify the value exceeding which the product may be physically damaged. Use the product well within these ratings. The specifications and conditions shown in DC Characteristics and AC Characteristics are the ranges for normal operation and quality assurance of the product. 3. VI can be -1.5 V if the input pulse is less than 10 ns. Operating Conditions
Parameter Supply voltage Symbol VDD25 VDD33 Ambient temperature Oscillation start voltageNote 1 Oscillation hold voltage Oscillation hold voltage
Note 2
Condition 2.5 V (VDD2, VDDP pins) 3.3 V (VDD3, VDDU, VDDTP, VDDAD, VDDO pins) When operating at 131.1 MHz
MIN. 2.3 3.0 -40
MAX. 2.7 3.6 +85 3.0 2.5 3.0
Unit V V C V V V
TA VDDS VDDH1 VDDH2
Note 3
Notes 1. This is a voltage at which oscillation is always started after power application, and is applied to oscillators of 32.768 kHz and 18.432 MHz. 2. This is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal operation level, and is applied to an oscillator of 32.768 kHz. 3. This is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal operation level, and is applied to an oscillator of 18.432 MHz. Remark The VR4181A has two types of power supplies. The 3.3 V power supply should be turned on at first. Turn on/off the 2.5 V power supply depending on the status of the MPOWER pin.
Capacitance (TA = -40 to +85C, VDD33 = 0 V)
Parameter Input capacitance I/O capacitance I/O capacitance
Note 1
Symbol CI CI_USB CIO
Condition Unmeasured pins returned to 0 V.
MIN.
MAX. 10 20 10
Unit pF pF pF
Note 2
Notes 1. Applies to the UHDP, UHDN, UDP, and UDN pins. 2. Applies to I/O pins other than the UHDP, UHDN, UDP, and UDN pins.
Data Sheet U16277EJ1V0DS
37
PD30181A, 30181AY
DC Characteristics (TA = -40 to +85C, VDD25 = 2.3 to 2.7 V, VDD33 = 3.0 to 3.6 V) (1) Pins of I/O circuit types A, C, and D
Parameter Output voltage, high Symbol VOH Pins of types A IOH = -2 mA Output voltage, low VOL Pins of types A IOL = 2 mA Input voltage, high VIH Pins of types A
Note 1 Note 1
Conditions
Note 1
MIN.
Note 3
TYP.
MAX.
Unit V
,C
Note 2
, and D
,
0.8VDD33
,C
Note 2
, and D
Note 3
,
0.4
V
(excluding GPIO pin of
Note 2
2.0
VDD33 + 0.3
V
edge triggered interrupt), C VIH1E Pins of type A
Note 4
, and D
Note 3
(GPIO pin of edge
0.75VDD33 -0.3 -0.3
VDD33 + 0.3
V
triggered interrupt) Input voltage, low VIL Pins of type A
Note 1
(excluding GPIO pin of
Note 2
0.25VDD33
V
edge triggered interrupt), C VIL1E Pins of type A
Note 4
, and D
Note 3
(GPIO pin of edge
0.5
V
triggered interrupt)
Notes 1. Applies to the following pins. D(31:0), IORDY, IOCS16#, DRQ(1:0)#, TC(1:0)#/GPIO(53:52), NMI#, HSYNC/LOCLK/NWIREEN, ENAB/M/BMODE0, VSYNC/FLM/BMODE1, FPD15/CF1_READY/GPIO51, FPD14/CF1_STSCHG#/GPIO50, FPD(13:12)/CF1_CE(2:1)#/GPIO(49:48), FPD(11:10)/CF1_CD(2:1)#/GPIO(47:46), FPD(9:4)/GPIO(45:40), CLK48, JTCK, JTMS, JTDI/RMODE#, JTRST#, BKTGIO#, A(14:0), A23/RP#, A24/CKE1, CAS#, CKE0, DAK(1:0)#, DCLK/SHCLK, DQM(3:0), FPD(3:0), IORD#, JTDO, MEMRD#, MEMWR#, MPOWER, PCS(4:0)#, POWERON, RAS#, ROMCS#, SA10, SDCLK, SDCS(3:0)#, SYSDIR, SYSEN#, UBE#, UPON, VPBIAS/GPO63, VPLCD/GPO62, WE# 2. Applies to the TPX(1:0) and TPY0 pins. 3. Applies to the TPY1 pin. 4. Applies to the following pins. FPD(9:4)/GPIO(45:40), FPD(11:10)/CF1_CD(2:1)#/GPIO(47:46), FPD(13:12)/CF1_CE(2:1)#/GPIO(49:48), FPD14/CF1_STSCHG#/GPIO50, FPD15/CF1_READY/GPIO51, TC(1:0)#/GPIO(53:52), A(22:15)/GPIO(61:54) Remark For details of the I/O circuits, refer to 1.4 Pin I/O Circuits
38
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(2) Pins of I/O circuit types B and G
Parameter Output voltage, high Symbol VOH2 VOH_USB Output voltage, low VOL2 VOL_USB Input voltage, high VIH2 VIH_USB Input voltage, low VIL2 VIL_USB Hysteresis voltageNote 3 Output cross levelNote 4 Differential input sensitivityNote 4 Differential input common mode rangeNote 4 External pull-up resistor External pull-down resistor External resistor for impedance adjustmentNote 5 VH VCRS_USB VDI_USB Conditions Pins of type BNote 1, IOH = -2 mA Pins of type GNote 2, RPD = 15 k Pins of type BNote 1, IOL = 2 mA Pins of type G Pins of type B
Note 2
MIN. 0.8VDD33 2.8
TYP.
MAX.
Unit V
3.6 0.4 0.3
V V V V V
, RPU = 1.5 k 0.75VDD33 2.0 -0.3 , single end 0.17VDD33 1.3 0.2
Note 1
VDD33 + 0.3
Pins of type GNote 2, single end Pins of type B
Note 1
0.6 0.8
V V V
Pins of type G
Note 2
Pins of type BNote 1 Pins of type GNote 2 Pins of type GNote 2
2.0
V V
VCM_USB
Pins of type GNote 2, VDI < 200 mV
0.8
2.5
V
RPU RPD RS
Pins of type GNote 2 Pins of type G
Note 2
1.425 14.25 20.9
1.575 15.75 23.1
k k
Pins of type GNote 2
Notes 1. Applies to the following pins. POWER, RSTSW#, RTCRST#, CF1_RESET/DBUS32, RxD0, TxD0/CLKSEL2, RxD2/IRDIN, TxD2/IRDOUT/MIPS16EN, CTS2#/BITCLK/SCLK, DTR2#/SDATAOUT/SDO/DIVMODE0, RTS2#/SYNC/WS/DIVMODE1, DCD2#/SDATAIN/SDI, DSR2#/SRESET#, UOC, CF1_DIR/KPORT4/GPIO39, CF1_EN#/KPORT5/GPIO38, CF1_VCCEN#/KSCAN4/GPIO37, CF0_CD2#/GPIO36, CF0_CD1#/GPIO35, CF0_IOIS16#/GPIO34, CF_WAIT#/GPIO33, CF0_CE2#/GPIO32, CF0_CE1#/GPIO31, CF0_STSCHG#/GPIO30, CF0_READY/GPIO29, CF0_RESET/GPIO28, CF0_DIR/GPIO27, CF0_EN#/GPIO26, CF_REG#/GPIO25, CF0_VCCEN#/GPIO24, SCK/KSCAN11/GPIO23, SI/KSCAN10/GPIO22, SO/KSCAN9/GPIO21, FRM/KSCAN8/GPIO20, RTS0#/GPIO19/CLKSEL1, CTS0#/GPIO18, DTR0#/RTS1#/GPIO17/CLKSEL0, DCD0#/GPIO16, DSR0#/CTS1#/GPIO15, RxD1/SCL1/GPIO14, TxD1/SDA1/GPIO13, SCL0/KPORT7/GPIO12, SDA0/KPORT6/GPIO11, PWM(2:0)/KSCAN(5:7)/GPIO(10:8), KPORT(3:0)/GPIO(7:4), KSCAN(3:0)/GPIO(3:0) 2. Applies to the UHDP, UHDN, UDP, and UDN pins 3. Hysteresis voltage: Difference between the minimum voltage at which the high level of a Schmitt input signal is not recognized when the signal goes from low to high and the maximum voltage at which the low level is not recognized when the signal goes from high to low. 4. Precision tests have not been performed. Only guaranteed as design characteristics. 5. The recommended value is 22 . Remark For details of the I/O circuits, refer to 1.4 Pin I/O Circuits.
Data Sheet U16277EJ1V0DS
39
PD30181A, 30181AY
Connection example of external resistor (a) When pulled down
UHDP, UHDN, UDP, UDN
DUT RS RPD
GNDU
(b) When pulled up
VDDU
RPU RS UHDP, UHDN, UDP, UDN DUT
40
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(3) Common
Parameter Power supply currentNote 1 Symbol IDD25Note 2 Conditions Fullspeed mode Fullspeed mode, program using cache operating, DMA controller operating, clock supplied to PCI unit Fullspeed mode, program using cache operating, DMA controller operating Fullspeed mode, program not using cache operating, all peripheral bus masters stopped, all clocks of unused units stopped Standby mode, peripheral bus master operating continuously Standby mode, all peripheral bus masters stopped, all clocks of unused unit stopped Suspend mode Hibernate mode, VDD25 = 0 V IDD33
Note 3
MIN.
TYP.
MAX. 350
Unit mA mA
165
100
mA
80
mA
70
90
mA
45
53
mA
10 0 45 40 45 40 2
20 0 58 50 58 50 4
mA mA mA mA mA mA mA
Fullspeed mode
32-bit bus 16-bit bus
Standby mode, peripheral bus master operating continuously
32-bit bus 16-bit bus
Standby mode, all peripheral bus masters stopped, all clocks of unused units stopped Suspend mode Hibernate mode, PWMU channel 0 operating Hibernate mode, PWMU channel 0 stopped IDDAD Input leakage current
Note 5 Note 4
2 2 25 3
4 4 50 9 5 5
mA mA
A
mA
A/D, D/A converters operating VDD33 = 3.6 V, VI = VDD33, 0 V VDD33 = 3.6 V, VI = VDD33, 0 V
ILI ILO
A A
Output leakage current
Notes 1. Value when AClock = 131.1 MHz, TClock = 65.55 MHz, Div2 mode. 2. IDD25 is the total current flowing to the VDD2 and VDDP pins. 3. IDD33 is the total current flowing to the VDD3, VDDU, VDDTP, and VDDO pins. 4. IDDAD is the current flowing to the VDDAD pin when Vref is supplied to the A/D and D/A converters. 5. Excluding the I.C. pin. Remarks 1. In Suspend mode, the internal LCD controller does not operate because the memory controller (MCU) clock and LCD controller (LCU) clock are stopped. 2. Each current value is the average value that flows under the specified conditions. Design the power supply so that the current under the MAX. condition can be supplied stably (so that voltage drop or ripple do not occur in the whole system). 3. The peripheral bus master indicates the following peripheral units. LCU, DCU, IOPCIU, USBHU, USBFU, AC97U
Data Sheet U16277EJ1V0DS
41
PD30181A, 30181AY
Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention voltage Data retention high-level input voltage Symbol VDDDR3 VIHDR Conditions Hibernate mode, 3.3 V power supply Hibernate mode, RTCRST# pin MIN. 2.5 0.9VDDDR3 MAX. 3.6 Unit V V
The data retention voltage and data retention high-level input voltage are the voltages that guarantee the operation of ElapsedTime counter in the RTC and the data retention of the registers (using a 3.3 V power supply) of the following peripheral units. These voltages do not apply to the data in the CPU core (using a 2.5 V power supply). PMU: RTC: GIU: PMUINTREG, PMUCNTREG, PMUWAITREG, PMUDIVREG ETIMELREG, ETIMEMREG, ETIMEHREG, ECMPLREG, ECMPMREG, ECMPHREG GPMODE0, GPMODE1, GPMODE2, GPMODE3, GPMODE4, GPMODE5, GPMODE6, GPMODE7, GPDATA0, GPDATA1, GPDATA2, GPDATA3, GPINEN0, GPINEN1, GPINEN2, GPINEN3, GPINTMSK0, GPINTMSK1, GPINTMSK2, GPINTMSK3, GPINTTYP0, GPINTTYP1, GPINTTYP2, GPINTTYP3, GPINTTYP4, GPINTTYP5, GPINTTYP6, GPINTTYP7, GPINTSTAT0, GPINTSTAT1, GPINTSTAT2, GPINTSTAT3, PINMODE, SDRAMACT, NVREG0, NVREG1, NVREG2, NVREG3 PWMU: PWM0ATSREG, PWM0IATSREG, PWM0CNTREG, PWM0ASTCREG, PWM0INTREG, PWM1CTRL, PWM1BUF
42
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
AC Characteristics (TA = -40 to +85C, VDD25 = 2.3 to 2.7 V, VDD33 = 3.0 to 3.6 V) AC test input test points (a) D(31:0), IORDY, IOCS16#, DRQ(1:0)#, TC(1:0)#/GPIO(53:52), NMI#, HSYNC/LOCLK/NWIREEN, VSYNC/FLM/BMODE1, FPD15/CF1_READY/GPIO51, FPD14/CF1_STSCHG#/GPIO50, FPD(13:12)/CF1_CE(2:1)#/GPIO(49:48), FPD(11:10)/CF1_CD(2:1)#/GPIO(47:46), FPD(9:4)/GPIO(45:40), CLK48, JTCK, JTMS, JTDI/RMODE#, JTRST#, BKTGIO#, TPX(1:0), TPY(1:0)
VDD33 Input pins
2.0 V Test points 0.25VDD33
2.0 V 0.25VDD33
0V
(b) A(22:15)/GPIO(61:54), POWER, RSTSW#, RTCRST#, CF1_RESET/DBUS32, RxD0, TxD0/CLKSEL2, RxD2/IRDIN, TxD2/IRDOUT/MIPS16EN, CTS2#/BITCLK/SCLK, DTR2#/SDATAOUT/SDO/DIVMODE0, RTS2#/SYNC/WS/DIVMODE1, DCD2#/SDATAIN/SDI, DSR2#/SRESET#, UOC, CF1_DIR/KPORT4/GPIO39, CF1_EN#/KPORT5/GPIO38, CF1_VCCEN#/KSCAN4/GPIO37, CF0_CD(2:1)#/GPIO(36:35), CF0_IOIS16#/GPIO34, CF_WAIT#/GPIO33, CF0_CE(2:1)#/GPIO(32:31), CF0_STSCHG#/GPIO30, CF0_READY/GPIO29, CF0_RESET/GPIO28, CF0_DIR/GPIO27, CF0_EN#/GPIO26, CF_REG#/GPIO25, CF0_VCCEN#/GPIO24, SCK/KSCAN11/GPIO23, SI/KSCAN10/GPIO22, SO/KSCAN9/GPIO21, FRM/KSCAN8/GPIO20, RTS0#/GPIO19/CLKSEL1, CTS0#/GPIO18, DTR0#/RTS1#/GPIO17/CLKSEL0, DCD0#/GPIO16, DSR0#/CTS1#/GPIO15, RxD1/SCL1/GPIO14, TxD1/SDA1/GPIO13, SCL0/KPORT7/GPIO12, SDA0/KPORT6/GPIO11, PWM(2:0)/KSCAN(5:7)/GPIO(10:8), KPORT(3:0)/GPIO(7:4), KSCAN(3:0)/GPIO(3:0)
VDD33 Input pins
0.75VDD33 Test points 0.25VDD33
0.75VDD33 0.25VDD33
0V
Data Sheet U16277EJ1V0DS
43
PD30181A, 30181AY
AC test output test points
VDD33 All output pins 0V 0.5VDD33 Test points 0.5VDD33
Load condition
All output pins
DUT
CL = 50 pF
44
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(1) Clock parameters
Parameter CPU core operating frequency Symbol fAClock Conditions CLKSEL(2:0) = 111 CLKSEL(2:0) = 110 CLKSEL(2:0) = 101 CLKSEL(2:0) = 100 CLKSEL(2:0) = 011 CLKSEL(2:0) = 010 CLKSEL(2:0) = 001 CLKSEL(2:0) = 000 TClock, SDCLK frequency fTClock DIVMODE(1:0) = 11 DIVMODE(1:0) = 10 DIVMODE(1:0) = 01 DIVMODE(1:0) = 00 MasterOut frequency PCIClock frequency fMasterOut tPCIClock PCICLKDIV(1:0) = 00 PCICLKDIV(1:0) = 01 PCICLKDIV(1:0) = 10 PCICLKDIV(1:0) = 11 LClock frequency fLClock LCLKDIV(1:0) = 11 LCLKDIV(1:0) = 01 LCLKDIV(1:0) = 10 LCLKDIV(1:0) = 00 PClock frequency fPClock PCLKDIV(1:0) = 00 PCLKDIV(1:0) = 01 PCLKDIV(1:0) = 10 PCLKDIV(1:0) = 11 ECU_SysClock frequency
Note Note Note Note Note Note
MIN.
TYP. 147.4 131.1 118.0 98.3 90.7 84.1 78.5 73.7
MAX.
Unit MHz MHz MHz MHz MHz MHz MHz MHz
18.432 18.432 18.432 18.432
fAClock/1 fAClock/2 fAClock/3 fAClock/4 fTClock/4 fTClock/8 fTClock/4 fTClock/2 fTClock/1 fTClock/1 fTClock/2 fTClock/3 fTClock/4
65.55 65.55 65.55 65.55
MHz MHz MHz MHz MHz
32.78 32.78 32.78 32.78
MHz MHz MHz MHz MHz MHz MHz MHz
Note
18.432 18.432 18.432 18.432
Note
fTClock/1 fTClock/2 fTClock/4 fTClock/8 fTClock/1 fTClock/2 fTClock/4 fTClock/8
32.78 32.78 32.78 32.78 32.78 32.78 32.78 32.78
MHz MHz MHz MHz MHz MHz MHz MHz
fECU_SysClock ECUSYSCLKDIV(1:0) = 00 ECUSYSCLKDIV(1:0) = 01 ECUSYSCLKDIV(1:0) = 10 ECUSYSCLKDIV(1:0) = 11
Note These values cannot be set in the current VR4181A. Remarks 1. The settings of the CLKSEL(2:0) and DIVMODE(1:0) signals are sampled when the RTCRST# signal changes to high level. 2. PCICLKDIV(1:0): Bits 9 and 8 of the CLKDIVCTRL register in the CCU. Set these bits before starting use of the on-chip peripheral PCI unit. 3. LCLKDIV(1:0): Bits 5 and 4 of the EXIBUCFG register in the EXIBU. Set these bits before setting the timing parameters for each register of the EXIBU. 4. PCLKDIV(1:0): Bits 1 and 0 of the CLKDIVCTRL register in the CCU. 5. ECUSYSCLKDIV(1:0): Bits 5 and 4 of the CLKDIVCTRL register in the CCU. Set these bits before starting use of the ECU.
Data Sheet U16277EJ1V0DS
45
PD30181A, 30181AY
(2) Reset parameters
Parameter RTC reset input low-level width RSTSW reset input low-level width Symbol tWRSL tWRSWL Conditions Applies to RTCRST# signal Applies to RSTSW# signal MIN. 600 100 MAX. Unit ms
s
Remark If the low-level width of reset input is the MIN. value or lower, a reset sequence may not be started.
RTCRST# (input) tWRSL
RSTSW# (input) tWRSWL
(3) Initial setting parameters
Parameter Setup time (to RTCRST#) Hold time (from RTCRST#) Symbol tSS tSH Conditions MIN. 91.6 -10 MAX. Unit
s s
RTCRST# (input)
NWIREEN, BMODE(1:0), DBUS32, CLKSEL(2:0), MIPS16EN, DIVMODE(1:0) (input)
Hi-Z Normal operation tSS tSH
Remark The circles indicate the sampling timing.
46
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(4) SDRAM, SyncFlash interface (MCU) parameters
Parameter SDCLK frequency SDCLK cycle SDCLK high-level width SDCLK low-level width Output delay time (from SDCLK) Data setup time Data hold time Symbol fSDCLK tSDCLK tSDCH tSDCL tSDDP tSDS tSDH 15.26 3.5 3.5 1.5 6.2 2.9 11.7 Conditions MIN. MAX. 65.55 Unit MHz ns ns ns ns ns ns
tSDCLK tSDCL SDCLK (output) tSDDP A(14:11), SA10, A(9:0) (output) tSDCH
CKE(1:0), SDCS(3:0)#, DQM(3:0), RAS#, CAS#, WE# (output) D(31:0) (write)
D(31:0) (read)
Hi-Z
Hi-Z
tSDS
tSDH
Remark The circles indicate the sampling timing.
Data Sheet U16277EJ1V0DS
47
PD30181A, 30181AY
(5) ROM, flash memory, SRAM, ISA interface (EXIBU) parameters
Parameter TClock frequency TClock cycle LClock frequency LClock cycle Output delay time Data input setup time Data input hold time Data output float delay time Data output setup time (from command signal) IORDY input hold time IOCS16# input hold time DRQn# input inactive setup time tEXRDYH tEXCS16H tDRQNEG 0 0 20 ns ns ns Symbol fTClock tTClock fLClock tLClock tEXD tEXS tEXH tEXZ tEXCL 0 30.52 0 5 0 10 12 15.26 32.78 Conditions MIN. MAX. 65.55 Unit MHz ns MHz ns ns ns ns ns ns
Remarks 1. n = 0, 1 2. TClock is generated by dividing AClock in accordance with the setting of the DIVMODE(1:0) signals when the RTCRST# signal changes to high level. After releasing the RTC reset, the division ratio of TClock can be changed by setting the PMUDIVREG register. 3. LClock is generated by dividing Tclock in accordance with the setting of the LCLKDIV(1:0) bits of the EXIBUCFG register in the EXIBU. 4. The MEMRD#, MEMWR#, IORD#, and IOWR# signals are called as command signals for the external system bus interface.
48
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(a) Non-READY mode timing
CONSET+tEXD
CONWID+tEXD
CSOFF +tEXD
BUSIDLE +tEXD
A(24:0), UBE# (output)
ROMCS#, PCS(4:0)# (output) IORD#, IOWR#, MEMRD#, MEMWR# (output) tEXD SYSEN# (output) tEXD
SYSDIR (output) tTClock +tEXD tTClock +tEXD Note
D(31:0) (read)
Note tEXZ
Hi-Z
Input tEXS tEXH
Hi-Z
tEXD D(31:0) (write) tEXCL
tEXD
Note Output Remarks 1. CONSET, CONWID, CSOFF, and BUSIDLE are the timing parameters that can be changed by setting registers of the EXIBU. Each timing parameter is defined as the number of LClock cycles. 2. The circles indicate the sampling timing.
Data Sheet U16277EJ1V0DS
49
PD30181A, 30181AY
(b) Page access timing (CONSET = 0, CSOFF = 0)
CONWID+tEXD
SUBCWID SUBCWID SUBCWID +tEXD +tEXD +tEXD
A(24:0), UBE# (output)
ROMCS#, PCS(4:0)# (output) IORD#, IOWR#, MEMRD#, MEMWR# (output) SYSEN# (output) SYSDIR (output) tTClock +tEXD
tEXD
tEXD
D(31:0) (read)
Output tEXZ
Note
Note
Note
Note
tEXS tEXH D(31:0) (write)
tEXS tEXH
tEXS tEXH
tEXS tEXH
tEXD
tEXD
tEXD
tEXD
tEXD
Note Input Remarks 1. CONWID and SUBCWID are the timing parameters that can be changed by setting registers of the EXIBU. Each timing parameter is defined as the number of LClock cycles. 2. The circles indicate the sampling timing. 3. The broken lines indicate high impedance.
50
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(c) READY mode timing (RDYSYN = 1)
CONSET +tEXD
RMINWID +tEXD
CONOFF +tEXD
CSOFF +tEXD
BUSIDLE +tEXD
A(24:0), UBE# (output)
ROMCS#, PCS(4:0)# (output) IORD#, IOWR#, MEMRD#, MEMWR# (output) tEXD SYSEN# (output) tEXD
SYSDIR (output) tTClock +tEXD tTClock +tEXD D(31:0) (read) Note tEXZ tEXS tEXD D(31:0) (write) tEXCL tEXH tEXD Hi-Z Input Hi-Z Note
IORDY (input)
2tTClock+tLClock+tEXD
tEXRDYH
Note Output Remarks 1. CONSET, CSOFF, RMINWID, CONOFF, and BUSIDLE are the timing parameters that can be changed by setting registers of the EXIBU. Each timing parameter is defined as the number of LClock cycles. 2. The circles indicate the sampling timing.
Data Sheet U16277EJ1V0DS
51
PD30181A, 30181AY
(d) External ISA bus space access (READY mode) timing (RDYSYN = 1)
IOCS16SET CONSET RMINWID CONOFF +tEXD +tEXD +tEXD +tEXD
CSOFF +tEXD
BUSIDLE +tEXD
A(24:0), UBE# (output) IORD#, IOWR#, MEMRD#, MEMWR# (output) SYSEN# (output)
tEXD
tEXD
tEXD
SYSDIR (output) tTClock +tEXD tTClock +tEXD Note
D(15:0) (read)
Note tEXZ
Hi-Z
Input
Hi-Z
Hi-Z
tEXS tEXD D(15:0) (write) tEXCL
tEXH tEXD
IORDY (input)
2tTClock+tLClock+tEXD IOCS16# (input)
tEXRDYH
tLClock+tEXD
tEXCS16H
Note Output Remarks 1. IOCS16SET, CONSET, CSOFF, RMINWID, CONOFF, and BUSIDLE are the timing parameters that can be changed by setting registers of the EXIBU. Each timing parameter is defined as the number of LClock cycles. 2. The circles indicate the sampling timing.
52
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(e) DMA transfer timing
CONSET+tEXD
CONWID+tEXD
CSOFF +tEXD
BUSIDLE +tEXD
A(24:0), UBE# (output)
ROMCS#, PCS(4:0)# (output) IORD#, IOWR#, MEMRD#, MEMWR# (output) tEXD SYSEN# (output) tEXD
SYSDIR (output) DRQn# (input) DAKn# (output) Hi-Z Hi-Z tTClock +tEXD tDRQNEG
tTClock +tEXD
D(31:0) (read)
Note tEXZ
Input tEXS tEXH
Note
tEXD D(31:0) (write) tEXCL
tEXD
Note Output Remarks 1. CONSET, CONWID, CSOFF, and BUSIDLE are the timing parameters that can be changed by setting registers of the EXIBU. Each timing parameter is defined as the number of LClock cycles. 2. The circles indicate the sampling timing. 3. n = 0, 1
Data Sheet U16277EJ1V0DS
53
PD30181A, 30181AY
(6) CompactFlash/PC Card/ATA (IDE) interface (ECU) parameters
Parameter TClock frequency TClock cycle LClock frequency LClock cycle ECU_SysClock frequency ECU_SysClock cycle Output delay time (EXIBU) Output delay time (ECU) Data input setup time Data input hold time Data output float delay time Data output setup time (to command signal) CF_WAIT# input hold time CF0_IOIS16# input hold time tECURDYH tECUCS16H 0 0 ns ns Symbol fTClock tTClock fLClock tLClock fECU_SysClock tECU_SysClock tEXD tECUD tEXS tEXH tEXZ tEXCL 0 30.52 0 0 5 0 10 12 TBD 30.52 32.78 15.26 32.78 Conditions MIN. MAX. 65.55 Unit MHz ns MHz ns MHz ns ns ns ns ns ns ns
Remarks 1. TClock is generated by dividing AClock in accordance with the setting of the DIVMODE(1:0) signals when the RTCRST# signal changes to high level. After releasing the RTC reset, the division ratio of TClock can be changed by setting the PMUDIVREG register. 2. LClock is generated by dividing TClock in accordance with the setting of the LCLKDIV(1:0) bits of the EXIBUCFG register in the EXIBU. 3. ECU_SysClock is generated by dividing TClock in accordance with the setting of the ECUSYSCLKDIV(1:0) bits of the CLKDIVCTRL register in the CCU. 4. MEMRD#, MEMWR#, IORD#, and IOWR# signals are called as command signals for the external system bus interface. (a) Relationship between ECU bus cycle type and ECUWAIT
Bus Cycle Number of Wait Cycles 16-bit I/O cycle (IOnWT = 1) 16-bit I/O cycle(IOnWT = 0) 8-bit I/O cycle (Wn_IOWS = 1) 8-bit I/O cycle (Wn_IOWS = 0) 16-bit memory cycle (ZWSEN = 1 and M16W(1:0) = 0) 16-bit memory cycle (ZWSEN = 0 and M16W(1:0) = N) 8-bit memory cycle (ZWSEN = 1) 8-bit memory cycle (ZWSEN = 0) 0 5 0 tECU_SysClock x 4 N+1 tECU_SysClock x (N + 1) 2 3 4 5 0 MIN. tECU_SysClock x 2 tECU_SysClock x 3 tECU_SysClock x 4 tECU_SysClock x 5 ECUWAIT Value (ns) MAX.
Remarks 1. IOnWT, Wn_IOWS, ZWSEN, and M16W(1:0) are bits of the register in the ECU. 2. n = 0, 1
54
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(b) External ISA bus space access (READY mode) timing (RDYSYN = 1)
IOCS16SET CONSET RMINWID ECUWAIT +tEXD +tEXD +tEXD +tECUD
CONOFF +tEXD
CSOFF +tEXD
BUSIDLE +tEXD
A(24:0), UBE# (output) CFn_CE(2:1)#, CF_REG# (output) IORD#, IOWR#, MEMRD#, MEMWR# (output) tEXD SYSEN# (output) tEXD tEXD tTClock +tECUD tTClock +tECUD
SYSDIR (output) tTClock +tEXD CFn_EN# (output) tTClock +tECUD CFn_DIR (output) tTClock +tEXD Note tECUD tECUD tTClock +tECUD
D(15:0) (read)
Note tEXZ
Hi-Z
Input
Hi-Z
Hi-Z
tEXD D(15:0) (write) tEXCL CF_WAIT# (input) tTClock+tLClock+tECU_SysClock+tECUD CF0_IOIS16# (input) tLClock+tECUD
tEXS
tEXH tEXD
tECURDYH
tECUCS16H
Note Output Remarks 1. IOCS16SET, CONSET, CSOFF, RMINWID, CONOFF, and BUSIDLE are the timing parameters that can be changed by setting registers of the EXIBU. Each timing parameter is defined as the number of LClock cycles. 2. The circles indicate the sampling timing. 3. n = 0, 1
Data Sheet U16277EJ1V0DS
55
PD30181A, 30181AY
(7) USB interface (USBHU, USBFU) parameters
Parameter Rise time
Note 1
Symbol tR_FUSB tR_LUSB
Conditions Fullspeed (12 Mbps) mode Low speed (1.5 Mbps) mode Fullspeed (12 Mbps) mode Low speed (1.5 Mbps) mode Fullspeed (12 Mbps) mode Low speed (1.5 Mbps) mode
MIN. 4 75 4 75 90 80
MAX. 20 300 20 300 111 125
Unit ns ns ns ns % %
Fall time
Note 1
tF_FUSB tF_LUSB
Vp-p output potential width
Notes 1, 2
tRFM_FUSB tRFM_LUSB
Notes 1. Precision tests have not been performed. Only guaranteed as design characteristics. 2. Indicated by the following expressions. tRFM_FUSB = tR_FUSB/tF_FUSB tRFM_LUSB = tR_LUSB/tF_LUSB
UHDP, UHDN UDP, UDN (I/O)
90% 10% tR_FUSB tR_LUSB
90% 10% tF_FUSB tF_LUSB
56
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(8) AC97 interface (AC97U) parameters
Parameter BITCLK frequency BITCLK cycle BITCLK high-level width BITCLK low-level width SYNC frequency SYNC cycle SYNC high-level width SYNC low-level width SDATAIN input setup time (to BITCLK) SDATAIN input hold time (to BITCLK) SDATAOUT output delay time (to BITCLK) tSDATD 25 ns tSDATH 10 ns Symbol fBITCLK tBITCLK tBITCLKH tBITCLKL fSYNC tSYNC tSYNCH tSYNCL tSDATS 10 36 36 Conditions MIN. TYP. 12.288 81.4 40.7 40.7 48 20.8 1.3 19.5 45 45 MAX. Unit MHz ns ns ns kHz
s s s
ns
tBITCLK tBITCLKH BITCLK (input) tSDATS SDATAIN (input) tSDATD SDATAOUT (output) tSDATD tSDATH tBITCLKL
tSYNC tSYNCH SYNC (output) tSYNCL
Data Sheet U16277EJ1V0DS
57
PD30181A, 30181AY
(9) I S interface (I2SU) parameters
Parameter SCLK frequency SCLK cycle SCLK high-/low-level width SDI input setup time (to SCLK) SDI input hold time (from SCLK) SDO output delay time (from SCLK) WS delay time (from SCLK) Symbol fSCLK tSCLK tSCLKHL tSDIS tSDIH tSDOD tWSD 163 tSCLK/2 - 20 tSCLK/2 + 20 30 30 30 30 Conditions MIN. MAX. 6.114 Unit MHz ns ns ns ns ns ns
2
tSCLK tSCLKHL SCLK (I/O) tWSD WS (I/O) tSDIS SDI (input) tSDOD SDO (output) tSDOD tSDIH tSCLKHL
58
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(10) Serial interface (SIU) parameters
Parameter TxD0, TxD1, TxD2 output pulse width RxD0, RxD1, RxD2 input pulse width IRDOUT high-level output pulse width Symbol tTXD tRXD tIRDOUT Conditions MIN. N - 0.1 (9/16) x N (3/16) x N - 0.1 IRDIN input pulse width tIRDIN 1 (3/16) x N + 0.1 MAX. N + 0.1 Unit
s s s s
Remark N is the data transfer cycle per bit determined by the divisor of the baud rate generator set in the SIUDLL and SIUDLM registers.
Baud Rate (bps) 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 128000 144000 192000 230400 288000 384000 576000 1152000 Divisor (DLM(7:0)||DLL(7:0)) 23040 15360 10473 8565 7680 3840 1920 960 640 576 480 320 240 160 120 60 30 20 10 9 8 6 5 4 3 2 1 20000.00 13333.33 9090.91 7434.94 6666.67 3333.33 1666.67 833.33 555.56 500.00 416.67 277.78 208.33 138.89 104.17 52.08 26.04 17.36 8.68 7.81 6.94 5.21 4.34 3.47 2.60 1.74 0.868 N (s)
Remark Baud rate = (18.432 MHz/16)/(value set in the SIUDLM or SIUDLL register)
Data Sheet U16277EJ1V0DS
59
PD30181A, 30181AY
TxDn
(output)
tTXD RxDn
(input)
tRXD IRDOUT
(output)
tIRDOUT IRDIN
(input)
tIRDIN
Remark n = 0 to 2
60
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(11) I C bus interface (I2CU) parameters (PD30181AY only)
2
Parameter
Symbol
Condition
Normal Mode MIN. MAX. 100
High-Speed Mode MIN. 0 0.6 1.3 0.6 MAX. 400
Unit
SCLn frequency Start condition hold time SCLn low-level width SCLn high-level width Rise time Fall time Data setup time Data retention time Repeat start setup time Stop condition setup time Bus release time
fSCL tHD:STA tLOW tHIGH tRC tFC tSU:DAT tHD:DAT tSU:STA tSU:STO tBUF
0 4.0 4.7 4.0
kHz
s s s
0.3 0.3
1.0 0.3 0.25 0 4.7 4.0 4.7 0.1 0 0.6 0.6 1.3
s s s s s s s
tFC SDAn (I/O)
tRC
tSU:STA
tSU:STO tHD:STA SCLn (I/O) tLOW tHIGH tSU:DAT tHD:DAT tRC tFC
tBUF
Remark n = 0, 1
Data Sheet U16277EJ1V0DS
61
PD30181A, 30181AY
(12) Clocked serial interface (CSI) parameters
Parameter SCK frequency SCK cycle SCK high-/low-level width SI input setup time (to SCK edge
Note
Symbol fSCK tSCK tSCKHL ) ) tSIS tSIH tSOD
Condition
MIN.
MAX. 4.608
Unit MHz ns
217 tSCK/2 - 20 50 50 50 tSCK/2 + 20
ns ns ns ns
SI input hold time (from SCK edge SO output delay time (from SCK edge
Note
Note
)
Note The SCK edge used differs depending on the settings of the CKMD and CKPOL bits of the CSIMODE register.
tSCK tSCKHL SCK (I/O) tSIS SI (input) tSOD SO (output) tSIH tSCKHL
Remark This diagram shows the timing when using the SCK rising edge (CKMD = 0 and CKPOL = 0, or CKMD = 1 and CKPOL = 1).
62
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(13) LCD interface (LCU) parameters
Parameter DCLK/SHCLK frequency DCLK/SHCLK cycle DCLK/SHCLK high-/low-level width Output delay time (from DCLK/SHCLK edge
Note
Symbol fDCLK tDCLK tDCLKHL tLCDD )
Condition
MIN.
MAX. 32.775
Unit MHz ns
30 tDCLK/2 - 5 Applies to HSYNC/LOCLK, VSYNC/FLM, ENAB/M, and FPD(15: 0) signals tDCLK/2 + 5 30
ns ns
Note The DCLK/SHCLK edge used differs depending on the setting of the SCLKPOL bit of the LCDCTRLREG register.
tDCLK tDCLKHL DCLK/SHCLK (output) tLCDD HSYNC/LOCLK, VSYNC/FLM, ENAB/M, FPD(15:0) (output) tDCLKHL
Remark This diagram shows the timing when using the DCLK/SHCLK rising edge (SCLKPOL = 1).
Data Sheet U16277EJ1V0DS
63
PD30181A, 30181AY
(14) GPIO interface (GIU) parameters
Parameter GPIO input level width Symbol tGPIN1 Condition Restoring from Hibernate mode when level trigger is selected. tGPIN2 Interrupt input when level trigger is selected. GPIO input rise time
Note
MIN. 100
MAX.
Unit
s
(tTClock x 4) x3 10 200 10 200
ns
tGPINR tGPINR2
GPIO(61:40) pins GPIO pins other than above GPIO(61:40) pins GPIO pins other than above
ns ns ns ns
GPIO input fall time
Note
tGPINF tGPINF2
Note Precision tests have not been performed. Only guaranteed as design characteristics.
(a) GPIO input level width
tGPIN1, tGPIN2
GPIOn (input)
Remark n = 0 to 61
(b) GPIO input rise/fall time
tGPINF, tGPINF2 tGPINR, tGPINR2
GPIOn (input)
Remark n = 0 to 61
64
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
(15) NMI parameters
Parameter NMI# input low-level width Symbol tNMI Condition MIN. 100 MAX. Unit
s
NMI# (input) tNMI
Data Sheet U16277EJ1V0DS
65
PD30181A, 30181AY
A/D Converter Characteristics (TA = -40 to +85C, VDD25 = 2.3 to 2.7 V, VDD33 = 3.0 to 3.6 V)
Parameter Zero-scale error Full-scale error
Notes 1, 2
Symbol ZSE RSE
Condition
MIN.
TYP. 4.0 5.0 3.0 3.0
MAX.
Unit LSB LSB LSB LSB
Notes 1, 2
Integral linearity error
Notes 1, 2
INL DNL VIAN
Note 1
Differential linearity error Analog input voltage
Note 1
Notes 1, 2
-0.3 1.53 6.5 When pin input capacitance CI = 3 pF
VDDAD + 0.3
V k pF
Analog input equivalent resistance
RAIN CAIN REXOUT
Analog input equivalent capacitance
Note 1
Analog signal source allowable output impedance
Note 1
3.5
k
Notes 1. Applies to TPX(1:0), TPY(1:0), and AIN(3:0) pins. 2. Excluding quantization error.
Remark LSB:
Least significant bit
VDDAD: Voltage supplied to VDDAD pin
A/D converter input equivalent circuit
VR4181A
REXOUT
AINn
RAIN
CI
CAIN
Remark n = 0 to 3
66
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
D/A Converter Characteristics (TA = -40 to +85C, VDD25 = 2.3 to 2.7 V, VDD33 = 3.0 to 3.6 V)
Parameter Integral linearity error
Notes 1, 2
Symbol INL DNL RST RSTOUT
Condition
MIN.
TYP. 3.0 3.0 4 1110
MAX.
Unit LSB LSB
Differential linearity error String unit resistor
Notes 1, 2
String output equivalent resistor
Notes 1. Applies to AOUT pin. 2. Excluding quantization error. Remark LSB: Least significant bit Cautions 1. The output impedance of the D/A converter is too large to latch the current from AOUT pin. If the load input impedance is small, insert a buffer amplifier between the load and the AOUT pin. Make the wiring between the buffer amplifier and load as short as possible. If the wiring is long, processing is required such as enclosing the wiring in a with ground pattern. 2. The output voltage of the D/A converter changes in steps, so use the output signal from the D/A converter after passing it through a low pass filter. D/A converter output equivalent circuit
VR4181A VDDAD 1/2 RST 1023 RST
Series resistor string
Tap selector
RSTOUT AOUT
0 1/2 RST GNDAD
Remark The series resistor string is connected between the reference voltage for the A/D converter (VDDAD) and GND (GNDAD) for the A/D converter. To make the 1024 equivalent voltage steps between the two pins, this circuit consists of 1023 equivalent unit resistors (RST) and two resistors with a resistance of half RST. The equivalent output impedance of the AOUT pin is the value calculated by adding RSTOUT to the total RST value corresponding to the selected voltage step.
Data Sheet U16277EJ1V0DS
67
PD30181A, 30181AY
3. PACKAGE DRAWING
240-PIN PLASTIC FBGA (16x16)
E
wSB
ZD
ZE
B
A D
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 V U T R P NM L K J HG F E D C B A
INDEX MARK
wSA
A y1 S A2 S
(UNIT:mm) ITEM D E w A A1 A2 DIMENSIONS 16.000.10 16.000.10 0.20 1.480.10 0.350.06 1.13 0.80 0.50 +0.05 -0.10 0.08 0.10 0.20 1.20 1.20 P240F1-80-GA3
y
S
e
A1
M
e b x y y1 ZD ZE
b
x
S AB
68
Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
4. RECOMMENDED SOLDERING CONDITIONS
The PD30181A and 30181AY should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 4-1. Soldering Conditions for Surface-Mount Type (a) PD30181AF1-131-GA3: 240-pin plastic FBGA (16 x 16)
PD30181AYF1-131-GA3: 240-pin plastic FBGA (16 x 16)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Time: 30 seconds or less (210C or higher), Count: two times or less, Exposure limit: 3 daysNote (after that, prebake at 125C for 20 hours) Symbol IR35-203-2
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. (b) PD30181AF1-131-GA3-A
Note
: 240-pin plastic FBGA (16 x 16) : 240-pin plastic FBGA (16 x 16)
PD30181AYF1-131-GA3-A
Note
For soldering methods and conditions, contact an NEC sales representative. Note Lead-free product
Data Sheet U16277EJ1V0DS
69
PD30181A, 30181AY
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Purchase of NEC I C components conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. Reference document Electrical Characteristics for Microcomputer (U15170J)
Note 2 2
2
2
Note This document number is that of the Japanese version. The documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. EEPROM, VR4120, VR4181A, VR Series, and VR4100 Series are trademarks of NEC Corporation. MIPS is a registered trademark of MIPS Technologies, Inc. in the United States. SyncFlash is a trademark of Micron Technology, Inc. Bluetooth is a trademark of Bluetooth SIG, Inc.
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Data Sheet U16277EJ1V0DS
PD30181A, 30181AY
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
* Filiale Italiana Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 * Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 Fax: 040-244 45 80
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC do Brasil S.A.
Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829
* Branch Sweden Taeby, Sweden Tel: 08-63 80 820 NEC Electronics (Europe) GmbH Fax: 08-63 80 388 Duesseldorf, Germany * United Kingdom Branch Tel: 0211-65 03 01 Milton Keynes, UK Fax: 0211-65 03 327 Tel: 01908-691-133 Fax: 01908-670-290 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 Fax: 091-504 28 60 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China Tel: 021-6841-1138 Fax: 021-6841-1137
NEC Electronics Taiwan Ltd.
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 253-8311 Fax: 250-3583
J02.4
Data Sheet U16277EJ1V0DS
71
3'$ $<
Exporting this product or equipment that includes this product may require a governmental license from the U.S.A. for some countries because this product utilizes technologies limited by the export control regulations of the U.S.A.
* The information in this document is current as of July, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
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