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User's Manual
VR4181TM
64-/32-Bit Microprocessor Hardware
PD30181
Document No. U14272EJ3V0UM00 (3rd edition) Date Published November 2002 NS CP(K) NEC Electronics Corporation 2000 MIPS Technologies, Inc. 1998 Printed in Japan
[MEMO]
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User's Manual U14272EJ3V0UM
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
VR10000, VR12000, VR4000, VR4000 Series, VR4100, VR4100 Series, VR4110, VR4111, VR4121, VR4122, VR4181, VR4300, VR4305, VR4310, VR4400, VR5000A, VR5432, and VR Series are trademarks of NEC Electronics Corporation. MIPS is a registered trademark of MIPS Technologies, Inc. in the United States. MBA is a trademark of Vadem Corporation. Pentium, Intel, and StrataFlash are trademarks of Intel Corporation. DEC VAX is a trademark of Digital Equipment Corporation. PC/AT is a trademark of International Business Machines Corporation.
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Exporting this product or equipment that includes this product may require a governmental license from the U.S.A. for some countries because this product utilizes technologies limited by the export control regulations of the U.S.A.
* The information in this document is current as of January, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1
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User's Manual U14272EJ3V0UM
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics America, Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
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NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
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NEC Electronics (Europe) GmbH
Duesseldorf, Germany Tel: 0211-65 03 01 Fax: 0211-65 03 327 * Sucursal en Espana Madrid, Spain Tel: 091-504 27 87 Fax: 091-504 28 60 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99
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NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 6253-8311 Fax: 6250-3583
J02.11
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Major Revisions in This Edition (1/5)
Page Throughout this manual Description Separation of the following parts of the previous (the 2nd) edition CHAPTER 3 MIPS III INSTRUCTION SET SUMMARY, CHAPTER 4 MIPS16 INSTRUCTION SET, CHAPTER 5 VR4181 PIPELINE, CHAPTER 6 MEMORY MANAGEMENT SYSTEM (first half), CHAPTER 7 EXCEPTION PROCESSING (second half), CHAPTER 9 CACHE MEMORY, CHAPTER 10 CPU CORE INTERRUPTS, CHAPTER 27 MIPS III INSTRUCTION SET DETAILS, CHAPTER 28 MIPS16 INSTRUCTION SET FORMAT Deletion of modem block in Figure 1-1. Internal Block Diagram Modification of description in 1.3.16 LCD interface Modification of Remark in 1.3.17 Wake-up events Addition of 1.4.2 CPU instruction set overview and 1.4.3 Data formats and addressing Modification of description and deletion of figure in 1.4.4 CP0 registers Addition of 1.4.9 Power modes and 1.4.10 Code compatibility Addition of descriptions in 1.5 Clock Interface Addition of Figure 1-8. External Circuits of Clock Oscillator and Figure 1-9. Incorrect Connection Circuits of Resonator Modification of Note in 2.2.1 System bus interface signals Modification of descriptions for SYSDIR and SYSEN# and addition of description in Note in 2.2.1 System bus interface signals Addition of description for IRDIN/RxD2 in 2.2.10 IrDA interface signals Addition and modification in 2.3 Pin Status in Specific Status Addition of 2.4 Recommended Connection of Unused Pins and I/O Circuit Types and 2.5 Pin I/O Circuits Addition of CHAPTER 3 CP0 REGISTERS Modification of Table 4-6. DRAM Address Map Modification of description in 5.1.1 RTC reset Addition of description in Note in Figure 5-1 through Figure 5-5, Figure 5-8, and Figure 5-9 Modification in Figure 5-2. RSTSW Reset Modification of description in 5.1.5 HALTimer shutdown Addition of description in 5.3.1 Cold Reset Modification of description in 5.3.2 Soft Reset Addition of 5.4 Notes on Initialization Modification in Figure 6-1. VR4181 Internal Bus Structure Modification of description in 6.1.2 (3) LCD module (LCD Control Unit) Modification of description for bit 4 and addition of Caution and Remark in 6.2.1 BCUCNTREG1 (0x0A00 0000) Modification of descriptions for bits 14 to 12, bits 3 to 0, and Remark in 6.2.3 BCUSPEEDREG (0x0A00 000C) Modification of Figure 6-2. ROM Read Cycle and Access Parameters Deletion of description for Div4 mode and addition of description in Remark in 6.2.6 (2) Peripheral clock (TClock)
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Major Revisions in This Edition (2/5)
Page p. 119 p. 122 p. 123 pp. 125 to 128, 130 p. 129 p. 134 p. 135 p. 136 p. 137 p. 138 p. 140 Description Modification of description in 6.3.2 Connection to external ROM (x 16) devices Modification of Remark in 6.3.3 (4) 64 Mbit PageROM Modification of figure in 6.3.3 (5) 32 Mbit flash memory (when using IntelTM DD28F032) Modification of Figure 6-3 through Figure 6-8 Addition of description in Table 6-2. VR4181 EDO DRAM Capacity Addition of Caution and modification in Remark in 6.5.2 MEMCFG_REG (0x0A00 0304) Modification of description for bits 6 to 4 in 6.5.3 MODE_REG (0x0A00 0308) Modification of Note in 6.5.4 SDTIMINGREG (0x0A00 030C) Addition of description in 6.6 ISA Bridge Addition of description in 6.7.1 ISABRGCTL (0x0B00 02C0) Modification of description for bits 10 and 9 and addition of description in 6.7.3 XISACTL (0x0B00 02C4) Modification of description for bits 3 and 2 in 7.2.6 AIUDMAMSKREG (0x0A00 0046) Modification of values at reset in 7.2.7 MICRCLENREG (0x0A00 0658) and 7.2.8 SPKRCLENREG (0x0A00 065A) Addition of description for bit 8 in 7.2.9 MICDMACFGREG (0x0A00 065E) Addition of description for bit 0 in 7.2.10 SPKDMACFGREG (0x0A00 0660) Addition of description for bits 5 and 4 in 7.2.11 DMAITRQREG (0x0A00 0662) Modification of description and addition of Caution in 8.1 Overview Addition of Caution in Figure 8-1. SCK and SI/SO Relationship Addition and modification of descriptions in 8.2.2 SCK phase and CSI transfer timing Modification of description in 8.2.3 (1) Burst mode Addition of Remarks and description in 8.3.1 CSIMODE (0x0B00 0900) Addition of description in 9.1 Overview Modification of description in Table 9-1. ICU Registers Modification of address and description for bits 2 and 1, and addition of description in 9.2.9 KIUINTREG (0x0B00 0086) Modification of R/W and addition of description in 9.2.11 MAIUINTREG (0x0B00 0090) Modification of description in Figure 10-1. Transition of VR4181 Power Mode Addition and modification of descriptions in 10.2.1 Power mode and state transition Modification of description in Table 10-2. Operations During Reset Modification of location of 10.3.3 Deadman's Switch reset Modification of Figure 10-2. EDO DRAM Signals on RSTSW Reset (SDRAM Bit = 0) Modification of description in 10.3.4 (2) Preserving SDRAM data Modification of description in Table 10-3. Operations During Shutdown Modification of description of Caution in 10.5 Power-on Control Modification of signal name in 10.5.2 Activation via CompactFlash interrupt request Modification of description in 10.5.3 Activation via GPIO activation interrupt request
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Major Revisions in This Edition (3/5)
Page p. 198 pp. 201 to 204 pp. 205 to 207 p. 209 p. 211 p. 214 p. 215 p. 220 p. 238 p. 242 p. 254 p. 267 p. 270 p. 273 p. 275 p. 283 p. 286 p. 289 p. 290 p. 291 p. 292 p. 295 p. 298 p. 298 p. 301 pp. 303, 304 Description Modification of description of Cautions in 10.5.4 Activation via DCD interrupt request Modification of descriptions in 10.6.1 through 10.6.4 Addition of 10.6.5 through 10.6.8 Modification of description for bit 6 in 10.7.1 PMUINTREG (0x0B00 00A0) Modification of value at reset for bit 7 in 10.7.2 PMUCNTREG (0x0B00 00A2) Modification of description for bit 2 to 0 in 10.7.4 PMUDIVREG (0x0B00 00AC) Modification of description for bit 4 in 10.7.5 DRAMHIBCTL (0x0B00 00B2) Modification of value at reset for bit 15 in 11.2.2 (3) ECMPHREG (0x0B00 00CC) Modification and addition of descriptions in 13.1.3 General-purpose registers Modification of description in 13.2.5 16-bit bus cycles Modification of R/W for bits 15 to 8 in 13.3.5 GPDATHREG (0x0B00 0308) Modification of description in 13.3.15 KEYEN (0x0B00 031C) Modification of description for bit 15 in 13.3.19 PCS1STRA (0x0B00 0326) Modification of description for bit 7 in 13.3.23 LCDGPMODE (0x0B00 032E) Addition of Caution in 14.1 General Modification of location of Note in Table 14-3. PIUCNTREG Bit Manipulation and States Modification of description for bits 5 to 0 in 14.3.4 PIUSTBLREG (0x0B00 0128) Addition of description in 14.3.6 PIUASCNREG (0x0B00 0130) Modification of description in Table 14-4. PIUASCNREG Bit Manipulation and States Addition of description in 14.3.7 PIUAMSKREG (0x0B00 0132) Modification of values at reset for bits 2 to 0 in 14.3.8 PIUCIVLREG (0x0B00 013E) Modification of description in Table 14-7. Mask Clear During Scan Sequencer Operation Addition of Note in Figure 14-6. Touch/Release Detection Timing Modification of Figure 14-7. A/D Port Scan Timing Modification of description and addition of Caution in 15.1 General Modification of addresses in 15.2.1 SDMADATREG (0x0B00 0160) and 15.2.2 MDMADATREG (0x0B00 0162) Modification of values at reset for bits 11, 10 and 5 and addition of Caution in 15.2.6 SCNVC_END (0x0B00 016E) Modification of values at reset for bits 11, 10 and 5 and addition of Caution in 15.2.12 MCNVC_END (0x0B00 017E) Addition of descriptions in 15.3.1 Output (speaker) and 15.3.2 Input (microphone) Modification of description in 16.2.6 Interrupts and status reporting Modification of description in Table 16-3. KIU Interrupt Registers Modification of description for bits 1 and 0 in 16.3.3 KIUSCANS (0x0B00 0192) Modification of descriptions for bits 14 to 10 and bits 4 to 0 in 16.3.4 KIUWKS (0x0B00 0194) Modification and addition of descriptions for bits 2 to 0 in 16.3.6 KIUINT (0x0B00 0198) Modification of signal name in 17.1 General
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Major Revisions in This Edition (4/5)
Page p. 333 p. 333 p. 336 p. 337 p. 338 p. 341 p. 344 Description Modification of signal names in Figure 17-1. CompactFlash Interrupt Logic Modification of description for bit 0 in 17.3.3 CFG_REG_1 (0x0B00 08FE) Addition of Caution for bit 4 in 17.4.3 PWRRSETDRV (Index: 0x02) Modification of description for bit 7 in 17.4.4 ITGENCREG (Index: 0x03) Modification of description and addition of Caution for bit 0 in 17.4.5 CDSTCHGREG (Index: 0x04) Modification of descriptions for bits 7, 4, 3, and 0 in 17.4.8 IOCTRL_REG (Index: 0x07) Modification of description for bit 6 in 17.4.14 MEMWIDn_REG (Index: 0x11, 0x19, 0x21, 0x29, 0x31) Modification of description for bits 7 and 6 and addition of description in 17.4.16 MEMSELn_REG (Index: 0x13, 0x1B, 0x23, 0x2B, 0x33) Addition of description in 17.4.17 MEMOFFLnREG (Index: 0x14, 0x1C, 0x24, 0x2C, 0x34) Modification of Remark for bits 5 to 0 in 17.4.18 MEMOFFHnREG (Index: 0x15, 0x1D, 0x25, 0x2D, 0x35) Modification of description for bit 2 in 17.4.20 GLOCTRLREG (Index: 0x1E) Modification of description for bits 1 and 0 and addition of description in 17.4.22 VOLTSELREG (Index: 0x2F) Addition of 17.5 Memory Mapping of CompactFlash Card Addition of 17.6 Controlling Bus When CompactFlash Card Is Used Addition of function for bit 2 in 18.2.3 LEDCNTREG (0x0B00 0248) Modification of description in 18.2.4 LEDASTCREG (0x0B00 024A) Modification of figure in 18.3 Operation Flow Addition of Caution in 19.1 General Modification of description in Table 19-1. SIU1 Registers Modification of values at reset in 19.3.1 through 19.3.3, 19.3.5, and 19.3.12 Addition of description in Table 19-2. Correspondence between Baud Rates and Divisors Modification of descriptions for bits 2 to 0 in 19.3.7 SIUFC_1 (0x0C00 0012: Write) Modification of R/W and addition of description in 19.3.10 SIULS_1 (0x0C00 0015) Modification of descriptions for bits 7 to 4 in 19.3.11 SIUMS_1 (0x0C00 0016) Modification of R/W for bit 1 in 19.3.14 SIUACTMSK_1 (0x0C00 001C) Addition of description and Caution in 20.1 General Modification of description in Table 20-1. SIU2 Registers Modification of values at reset in 20.3.1 through 20.3.3, 20.3.5, and 20.3.12 Addition of description in Table 20-2. Correspondence between Baud Rates and Divisors Modification of descriptions for bits 2 to 0 in 20.3.7 SIUFC_2 (0x0C00 0002: Write) Modification of R/W and addition of description in 20.3.10 SIULS_2 (0x0C00 0005) Modification of descriptions for bits 7 to 4 in 20.3.11 SIUMS_2 (0x0C00 0006) Addition of description in 20.3.13 SIUIRSEL_2 (0x0C00 008) Modification of R/W for bit 1 in 20.3.16 SIUACTMSK_2 (0x0C00 000C)
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Major Revisions in This Edition (5/5)
Page p. 399 p. 401 p. 406 p. 420 p. 428 p. 429 p. 433 pp. 436 to 438 pp. 439 to 444 Description Modification of description in 21.1.1 LCD interface Modification of bus width in Figure 21-1. LCD Controller Block Diagram Modification of description in 21.3.4 Frame buffer memory and FIFO Addition of Remark in 21.4.11 LCDCFGREG0 (0x0A00 0414) Addition of Remark in 21.4.22 CPINDCTREG (0x0A00 047E) Addition of Caution in 21.4.23 CPALDATREG (0x0A00 0480) Addition of Caution in Table 23-1. Coprocessor 0 Hazards Addition of APPENDIX A RESTRICTIONS ON VR4181 Addition of APPENDIX B INDEX
The mark
shows major revised points.
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User's Manual U14272EJ3V0UM
PREFACE
Readers
This manual targets users who intend to understand the functions of the VR4181 and to design application systems using this microprocessor. This manual introduces the hardware functions of the VR4181 to users, following the organization described below. Two manuals are available for the VR4181: Hardware User's Manual (this manual) TM and Architecture User's Manual common to the VR4100 Series .
Purpose
Organization
Hardware User's Manual * * * * * Pin functions Physical address space Function of Coprocessor 0 Initialization interface Peripheral units
Architecture User's Manual * Pipeline operation * Cache organization and memory management system * Exception processing * Interrupts * Instruction set
How to read this manual
It is assumed that the reader of this manual has general knowledge in the fields of electric engineering, logic circuits, microcomputers, and SDRAMs. To learn about the overall functions of the VR4181, Read this manual in sequential order. To learn about instruction sets, Read VR4100 Series Architecture User's Manual that is separately available. To learn about electrical specifications, Refer to Data Sheet that is separately available.
Conventions
Data significance: Active low: Note: Caution: Remark: Numeric representation:
Higher on left and lower on right XXX# (trailing # after pin and signal names) Description of item marked with Note in the text Information requiring particular attention Supplementary information binary/decimal ... XXXX hexadecimal ... 0xXXXX Prefixes representing an exponent of 2 (for address space or memory capacity): 10 K (kilo) ... 2 = 1024 20 2 M (mega) ... 2 = 1024 30 3 G (giga) ... 2 = 1024 40 4 T (tera) ... 2 = 1024 50 5 P (peta) ... 2 = 1024 60 6 E (exa) ... 2 = 1024
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Related Documents
When using this manual, also refer to the following documents.
Document name VR4181 Hardware User's Manual
Document number This manual U14273E U15509E U10710E
PD30181 (VR4181) Data Sheet
VR4100 Series Architecture User's Manual VR Series
TM
Programming Guide Application Note
The related documents indicated here may include preliminary version. However, preliminary versions are not marked as such.
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User's Manual U14272EJ3V0UM
CONTENTS
CHAPTER 1 INTRODUCTION ............................................................................................................. 29 1.1 Features .................................................................................................................................... 29 1.2 Ordering Information ............................................................................................................... 30 1.3 VR4181 Key Features ............................................................................................................... 30
1.3.1 CPU core ..................................................................................................................................... 1.3.2 Bus interface ............................................................................................................................... 1.3.3 Memory interface ......................................................................................................................... 1.3.4 DMA controller (DCU) .................................................................................................................. 1.3.5 Interrupt controller (ICU) .............................................................................................................. 1.3.6 Real-time clock ............................................................................................................................ 1.3.7 Audio output (D/A converter) ....................................................................................................... 1.3.8 Touch panel interface and audio input (A/D converter) ............................................................... 1.3.9 CompactFlash interface (ECU) ................................................................................................... 1.3.10 Serial interface channel 1 (SIU1) .............................................................................................. 1.3.11 Serial interface channel 2 (SIU2) .............................................................................................. 1.3.12 Clocked serial interface (CSI) .................................................................................................... 1.3.13 Keyboard interface (KIU) ........................................................................................................... 1.3.14 General-purpose I/O .................................................................................................................. 1.3.15 Programmable chip selects ....................................................................................................... 1.3.16 LCD interface ............................................................................................................................ 1.3.17 Wake-up events ........................................................................................................................ 1.4.1 CPU registers .............................................................................................................................. 1.4.2 CPU instruction set overview ...................................................................................................... 1.4.3 Data formats and addressing ...................................................................................................... 1.4.4 CP0 registers ............................................................................................................................... 1.4.5 Floating-point unit (FPU) ............................................................................................................. 1.4.6 Memory management unit ........................................................................................................... 1.4.7 Cache .......................................................................................................................................... 1.4.8 Instruction pipeline ...................................................................................................................... 1.4.9 Power modes .............................................................................................................................. 1.4.10 Code compatibility ..................................................................................................................... 31 31 32 32 32 32 32 32 32 32 32 33 33 33 34 34 35 37 38 40 43 44 44 44 44 45 46
1.4 VR4110 CPU Core ..................................................................................................................... 35
1.5 Clock Interface ......................................................................................................................... 47 CHAPTER 2 PIN FUNCTIONS ............................................................................................................ 50 2.1 Pin Configuration ..................................................................................................................... 50 2.2 Pin Function Description ........................................................................................................ 52
2.2.1 System bus interface signals ....................................................................................................... 2.2.2 LCD interface signals .................................................................................................................. 2.2.3 Initialization interface signals ...................................................................................................... 2.2.4 Battery monitor interface signals ................................................................................................. 2.2.5 Clock interface signals ................................................................................................................ 2.2.6 Touch panel interface and audio interface signals ...................................................................... 52 54 55 55 55 56
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2.2.7 LED interface signals ................................................................................................................... 2.2.8 CompactFlash interface and keyboard interface signals ............................................................. 2.2.9 Serial interface channel 1 signals ................................................................................................ 2.2.10 IrDA interface signals ................................................................................................................ 2.2.11 General-purpose I/O signals ...................................................................................................... 2.2.12 Dedicated VDD/GND signals ......................................................................................................
56 56 57 58 58 59
2.3 Pin Status in Specific Status .................................................................................................. 60 2.4 Recommended Connection of Unused Pins and I/O Circuit Types .................................... 63 2.5 Pin I/O Circuits ......................................................................................................................... 66 CHAPTER 3 CP0 REGISTERS ............................................................................................................ 67 3.1 Coprocessor 0 (CP0) ............................................................................................................... 67 3.2 Details of CP0 Registers ......................................................................................................... 69
3.2.1 Index register (0) ......................................................................................................................... 3.2.2 Random register (1) ..................................................................................................................... 3.2.3 EntryLo0 (2) and EntryLo1 (3) registers ...................................................................................... 3.2.4 Context register (4) ...................................................................................................................... 3.2.5 PageMask register (5) ................................................................................................................. 3.2.6 Wired register (6) ......................................................................................................................... 3.2.7 BadVAddr register (8) .................................................................................................................. 3.2.8 Count register (9) ......................................................................................................................... 3.2.9 EntryHi register (10) .................................................................................................................... 3.2.10 Compare register (11) ............................................................................................................... 3.2.11 Status register (12) .................................................................................................................... 3.2.12 Cause register (13) .................................................................................................................... 3.2.13 Exception Program Counter (EPC) register (14) ....................................................................... 3.2.14 Processor Revision Identifier (PRId) register (15) ..................................................................... 3.2.15 Config register (16) .................................................................................................................... 3.2.16 Load Linked Address (LLAddr) register (17) ............................................................................. 3.2.17 WatchLo (18) and WatchHi (19) registers ................................................................................. 3.2.18 XContext register (20) ............................................................................................................... 3.2.19 Parity Error register (26) ............................................................................................................ 3.2.20 Cache Error register (27) ........................................................................................................... 3.2.21 TagLo (28) and TagHi (29) registers ......................................................................................... 3.2.22 ErrorEPC register (30) ............................................................................................................... 69 69 70 71 72 73 74 74 75 76 76 79 81 82 83 84 85 86 87 87 88 89
CHAPTER 4 MEMORY MANAGEMENT SYSTEM ............................................................................ 91 4.1 Overview ................................................................................................................................... 91 4.2 Physical Address Space ......................................................................................................... 92
4.2.1 ROM space .................................................................................................................................. 4.2.2 External system bus space .......................................................................................................... 4.2.3 Internal I/O space ........................................................................................................................ 4.2.4 DRAM space ............................................................................................................................... 93 93 94 95
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CHAPTER 5 INITIALIZATION INTERFACE ....................................................................................... 96 5.1 Reset Function ......................................................................................................................... 96
5.1.1 RTC reset .................................................................................................................................... 5.1.2 RSTSW reset .............................................................................................................................. 5.1.3 Deadman's Switch reset .............................................................................................................. 97 98 99
5.1.4 Software shutdown ...................................................................................................................... 100 5.1.5 HALTimer shutdown .................................................................................................................... 101
5.2 Power-on Sequence ................................................................................................................ 102 5.3 Reset of CPU Core ................................................................................................................... 104
5.3.1 Cold Reset ................................................................................................................................... 104 5.3.2 Soft Reset .................................................................................................................................... 105
5.4 Notes on Initialization ............................................................................................................. 106
5.4.1 CPU core ..................................................................................................................................... 106 5.4.2 Internal peripheral units ............................................................................................................... 106 5.4.3 Returning from power mode ........................................................................................................ 107
CHAPTER 6 BUS CONTROL .............................................................................................................. 108 6.1 MBA Host Bridge ..................................................................................................................... 108
6.1.1 MBA Host Bridge ROM and register address space ................................................................... 109 6.1.2 MBA modules address space ...................................................................................................... 109
6.2 Bus Control Registers ............................................................................................................. 110
6.2.1 BCUCNTREG1 (0x0A00 0000) ................................................................................................... 111 6.2.2 CMUCLKMSK (0x0A00 0004) ..................................................................................................... 112 6.2.3 BCUSPEEDREG (0x0A00 000C) ................................................................................................ 113 6.2.4 BCURFCNTREG (0x0A00 0010) ................................................................................................ 115 6.2.5 REVIDREG (0x0A00 0014) ......................................................................................................... 116 6.2.6 CLKSPEEDREG (0x0A00 0018) ................................................................................................. 117
6.3 ROM Interface .......................................................................................................................... 118
6.3.1 External ROM devices memory mapping .................................................................................... 118 6.3.2 Connection to external ROM (x 16) devices ................................................................................ 119 6.3.3 Example of ROM connection ....................................................................................................... 120 6.3.4 External ROM cycles ................................................................................................................... 125
6.4 DRAM Interface ........................................................................................................................ 128
6.4.1 EDO DRAM configuration ............................................................................................................ 128 6.4.2 Mixed memory mode (EDO DRAM only) ..................................................................................... 129 6.4.3 EDO DRAM timing parameters ................................................................................................... 129 6.4.4 SDRAM configuration .................................................................................................................. 130
6.5 Memory Controller Register Set ............................................................................................. 131
6.5.1 EDOMCYTREG (0x0A00 0300) .................................................................................................. 131 6.5.2 MEMCFG_REG (0x0A00 0304) .................................................................................................. 133 6.5.3 MODE_REG (0x0A00 0308) ....................................................................................................... 135 6.5.4 SDTIMINGREG (0x0A00 030C) .................................................................................................. 136
6.6 ISA Bridge ................................................................................................................................ 137
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6.7 ISA Bridge Register Set ........................................................................................................... 137
6.7.1 ISABRGCTL (0x0B00 02C0) ....................................................................................................... 138 6.7.2 ISABRGSTS (0x0B00 02C2) ....................................................................................................... 139 6.7.3 XISACTL (0x0B00 02C4) ............................................................................................................. 140
CHAPTER 7 DMA CONTROL UNIT (DCU) ....................................................................................... 142 7.1 General ...................................................................................................................................... 142 7.2 DCU Registers ......................................................................................................................... 144
7.2.1 Microphone destination 1 address registers ................................................................................ 145 7.2.2 Microphone destination 2 address registers ................................................................................ 146 7.2.3 Speaker source 1 address registers ............................................................................................ 147 7.2.4 Speaker source 2 address registers ............................................................................................ 148 7.2.5 DMARSTREG (0x0A00 0040) ..................................................................................................... 149 7.2.6 AIUDMAMSKREG (0x0A00 0046) ............................................................................................... 149 7.2.7 MICRCLENREG (0x0A00 0658) .................................................................................................. 150 7.2.8 SPKRCLENREG (0x0A00 065A) ................................................................................................. 150 7.2.9 MICDMACFGREG (0x0A00 065E) .............................................................................................. 151 7.2.10 SPKDMACFGREG (0x0A00 0660) ............................................................................................ 152 7.2.11 DMAITRQREG (0x0A00 0662) .................................................................................................. 153 7.2.12 DMACTLREG (0x0A00 0664) .................................................................................................... 154 7.2.13 DMAITMKREG (0x0A00 0666) .................................................................................................. 155
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) ............................................................. 156 8.1 Overview ................................................................................................................................... 156 8.2 Operation of CSI ....................................................................................................................... 156
8.2.1 Transmit/receive operations ........................................................................................................ 156 8.2.2 SCK phase and CSI transfer timing ............................................................................................. 157 8.2.3 CSI transfer types ........................................................................................................................ 159 8.2.4 Transmit and receive FIFOs ........................................................................................................ 160
8.3 CSI Registers ............................................................................................................................ 160
8.3.1 CSIMODE (0x0B00 0900) ........................................................................................................... 161 8.3.2 CSIRXDATA (0x0B00 0902) ........................................................................................................ 163 8.3.3 CSITXDATA (0x0B00 0904) ........................................................................................................ 163 8.3.4 CSILSTAT (0x0B00 0906) ........................................................................................................... 164 8.3.5 CSIINTMSK (0x0B00 0908) ......................................................................................................... 166 8.3.6 CSIINTSTAT (0x0B00 090A) ....................................................................................................... 167 8.3.7 CSITXBLEN (0x0B00 090C) ........................................................................................................ 169 8.3.8 CSIRXBLEN (0x0B00 090E) ....................................................................................................... 170
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) ............................................................................ 171 9.1 Overview ................................................................................................................................... 171 9.2 Register Set .............................................................................................................................. 173
9.2.1 SYSINT1REG (0x0A00 0080) ..................................................................................................... 174 9.2.2 MSYSINT1REG (0x0A00 008C) .................................................................................................. 176 9.2.3 NMIREG (0x0A00 0098) .............................................................................................................. 178
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9.2.4 SOFTINTREG (0x0A00 009A) .................................................................................................... 179 9.2.5 SYSINT2REG (0x0A00 0200) ..................................................................................................... 180 9.2.6 MSYSINT2REG (0x0A00 0206) .................................................................................................. 181 9.2.7 PIUINTREG (0x0B00 0082) ........................................................................................................ 182 9.2.8 AIUINTREG (0x0B00 0084) ........................................................................................................ 183 9.2.9 KIUINTREG (0x0B00 0086) ........................................................................................................ 184 9.2.10 MPIUINTREG (0x0B00 008E) ................................................................................................... 185 9.2.11 MAIUINTREG (0x0B00 0090) ................................................................................................... 186 9.2.12 MKIUINTREG (0x0B00 0092) ................................................................................................... 187
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) ...................................................................... 188 10.1 General ................................................................................................................................... 188 10.2 VR4181 Power Mode .............................................................................................................. 188
10.2.1 Power mode and state transition ............................................................................................... 188
10.3 Reset Control ......................................................................................................................... 191
10.3.1 RTC reset .................................................................................................................................. 191 10.3.2 RSTSW reset ............................................................................................................................ 192 10.3.3 Deadman's Switch reset ............................................................................................................ 192 10.3.4 Preserving DRAM data on RSTSW reset .................................................................................. 192
10.4 Shutdown Control ................................................................................................................. 193
10.4.1 HALTimer shutdown .................................................................................................................. 193 10.4.2 Software shutdown .................................................................................................................... 193 10.4.3 BATTINH shutdown ................................................................................................................... 193
10.5 Power-on Control ................................................................................................................... 194
10.5.1 Activation via Power Switch interrupt request ........................................................................... 195 10.5.2 Activation via CompactFlash interrupt request .......................................................................... 196 10.5.3 Activation via GPIO activation interrupt request ........................................................................ 197 10.5.4 Activation via DCD interrupt request ......................................................................................... 198 10.5.5 Activation via ElapsedTime (RTC alarm) interrupt request ....................................................... 200
10.6 DRAM Interface Control ........................................................................................................ 201
10.6.1 Entering Hibernate mode (EDO DRAM) .................................................................................... 201 10.6.2 Entering Hibernate mode (SDRAM) .......................................................................................... 202 10.6.3 Exiting Hibernate mode (EDO DRAM) ...................................................................................... 203 10.6.4 Exiting Hibernate mode (SDRAM) ............................................................................................. 204 10.6.5 Entering Suspend mode (EDO DRAM) ..................................................................................... 205 10.6.6 Entering Suspend mode (SDRAM) ............................................................................................ 206 10.6.7 Exiting Suspend mode (EDO DRAM) ........................................................................................ 207 10.6.8 Exiting Suspend mode (SDRAM) .............................................................................................. 207
10.7 Register Set ............................................................................................................................ 208
10.7.1 PMUINTREG (0x0B00 00A0) .................................................................................................... 209 10.7.2 PMUCNTREG (0x0B00 00A2) .................................................................................................. 211 10.7.3 PMUWAITREG (0x0B00 00A8) ................................................................................................. 213 10.7.4 PMUDIVREG (0x0B00 00AC) ................................................................................................... 214 10.7.5 DRAMHIBCTL (0x0B00 00B2) .................................................................................................. 215
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CHAPTER 11 REALTIME CLOCK UNIT (RTC) ................................................................................ 216 11.1 General .................................................................................................................................... 216 11.2 Register Set ............................................................................................................................ 216
11.2.1 ElapsedTime registers ............................................................................................................... 217 11.2.2 ElapsedTime compare registers ................................................................................................ 219 11.2.3 RTCLong1 registers .................................................................................................................. 221 11.2.4 RTCLong1 count registers ......................................................................................................... 223 11.2.5 RTCLong2 registers .................................................................................................................. 225 11.2.6 RTCLong2 count registers ......................................................................................................... 227 11.2.7 RTC interrupt register ................................................................................................................ 229
CHAPTER 12 DEADMAN'S SWITCH UNIT (DSU) ........................................................................... 230 12.1 General .................................................................................................................................... 230 12.2 Register Set ............................................................................................................................ 230
12.2.1 DSUCNTREG (0x0B00 00E0) ................................................................................................... 231 12.2.2 DSUSETREG (0x0B00 00E2) ................................................................................................... 232 12.2.3 DSUCLRREG (0x0B00 00E4) ................................................................................................... 233 12.2.4 DSUTIMREG (0x0B00 00E6) .................................................................................................... 234
12.3 Register Setting Flow ............................................................................................................ 235 CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) ...................................................................... 236 13.1 Overview ................................................................................................................................. 236
13.1.1 GPIO pins and alternate functions ............................................................................................. 236 13.1.2 I/O direction control ................................................................................................................... 238 13.1.3 General-purpose registers ......................................................................................................... 238
13.2 Alternate Functions Overview .............................................................................................. 238
13.2.1 Clocked serial interface (CSI) .................................................................................................... 238 13.2.2 Serial interface channels 1 and 2 .............................................................................................. 239 13.2.3 LCD interface ............................................................................................................................. 241 13.2.4 Programmable chip selects ....................................................................................................... 242 13.2.5 16-bit bus cycles ........................................................................................................................ 242 13.2.6 General purpose input/output .................................................................................................... 242 13.2.7 Interrupt requests and wake-up events ..................................................................................... 243
13.3 Register Set ............................................................................................................................ 244
13.3.1 GPMD0REG (0x0B00 0300) ...................................................................................................... 246 13.3.2 GPMD1REG (0x0B00 0302) ...................................................................................................... 248 13.3.3 GPMD2REG (0x0B00 0304) ...................................................................................................... 250 13.3.4 GPMD3REG (0x0B00 0306) ...................................................................................................... 252 13.3.5 GPDATHREG (0x0B00 0308) ................................................................................................... 254 13.3.6 GPDATLREG (0x0B00 030A) .................................................................................................... 255 13.3.7 GPINTEN (0x0B00 030C) .......................................................................................................... 256 13.3.8 GPINTMSK (0x0B00 030E) ....................................................................................................... 257 13.3.9 GPINTTYPH (0x0B00 0310) ...................................................................................................... 258 13.3.10 GPINTTYPL (0x0B00 0312) .................................................................................................... 260 13.3.11 GPINTSTAT (0x0B00 0314) .................................................................................................... 262
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13.3.12 GPHIBSTH (0x0B00 0316) ...................................................................................................... 263 13.3.13 GPHIBSTL (0x0B00 0318) ...................................................................................................... 264 13.3.14 GPSICTL (0x0B00 031A) ........................................................................................................ 265 13.3.15 KEYEN (0x0B00 031C) ........................................................................................................... 267 13.3.16 PCS0STRA (0x0B00 0320) ..................................................................................................... 268 13.3.17 PCS0STPA (0x0B00 0322) ..................................................................................................... 268 13.3.18 PCS0HIA (0x0B00 0324) ........................................................................................................ 269 13.3.19 PCS1STRA (0x0B00 0326) ..................................................................................................... 270 13.3.20 PCS1STPA (0x0B00 0328) ..................................................................................................... 270 13.3.21 PCS1HIA (0x0B00 032A) ........................................................................................................ 271 13.3.22 PCSMODE (0x0B00 032C) ..................................................................................................... 272 13.3.23 LCDGPMODE (0x0B00 032E) ................................................................................................ 273 13.3.24 MISCREGn (0x0B00 0330 to 0x0B00 034E) ........................................................................... 274
CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU) ................................................................. 275 14.1 General ................................................................................................................................... 275
14.1.1 Block diagrams .......................................................................................................................... 276
14.2 Scan Sequencer State Transition ......................................................................................... 278 14.3 Register Set ............................................................................................................................ 280
14.3.1 PIUCNTREG (0x0B00 0122) ..................................................................................................... 281 14.3.2 PIUINTREG (0x0B00 0124) ...................................................................................................... 284 14.3.3 PIUSIVLREG (0x0B00 0126) .................................................................................................... 285 14.3.4 PIUSTBLREG (0x0B00 0128) ................................................................................................... 286 14.3.5 PIUCMDREG (0x0B00 012A) .................................................................................................... 287 14.3.6 PIUASCNREG (0x0B00 0130) .................................................................................................. 289 14.3.7 PIUAMSKREG (0x0B00 0132) .................................................................................................. 291 14.3.8 PIUCIVLREG (0x0B00 013E) .................................................................................................... 292 14.3.9 PIUPBnmREG (0x0B00 02A0 to 0x0B00 02AE, 0x0B00 02BC to 0x0B00 02BE) .................... 293 14.3.10 PIUABnREG (0x0B00 02B0 to 0x0B00 02B6) ........................................................................ 294
14.4 State Transition Flow ............................................................................................................ 295 14.5 Relationships among TPX, TPY, ADIN, and AUDIOIN Pins and States ............................ 297 14.6 Timing ..................................................................................................................................... 298
14.6.1 Touch/release detection timing ................................................................................................. 298 14.6.2 A/D port scan timing .................................................................................................................. 298
14.7 Data Loss Conditions ............................................................................................................ 299 CHAPTER 15 AUDIO INTERFACE UNIT (AIU) ................................................................................ 301 15.1 General ................................................................................................................................... 301 15.2 Register Set ............................................................................................................................ 302
15.2.1 SDMADATREG (0x0B00 0160) ................................................................................................. 303 15.2.2 MDMADATREG (0x0B00 0162) ................................................................................................ 304 15.2.3 DAVREF_SETUP (0x0B00 0164) ............................................................................................. 305 15.2.4 SODATREG (0x0B00 0166) ...................................................................................................... 306 15.2.5 SCNTREG (0x0B00 0168) ........................................................................................................ 307 15.2.6 SCNVC_END (0x0B00 016E) ................................................................................................... 308 15.2.7 MIDATREG (0x0B00 0170) ....................................................................................................... 309
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15.2.8 MCNTREG (0x0B00 0172) ........................................................................................................ 310 15.2.9 DVALIDREG (0x0B00 0178) ..................................................................................................... 311 15.2.10 SEQREG (0x0B00 017A) ........................................................................................................ 312 15.2.11 INTREG (0x0B00 017C) .......................................................................................................... 313 15.2.12 MCNVC_END (0x0B00 017E) ................................................................................................. 314
15.3 Operation Sequence ............................................................................................................. 315
15.3.1 Output (speaker) ........................................................................................................................ 315 15.3.2 Input (microphone) .................................................................................................................... 316
CHAPTER 16 KEYBOARD INTERFACE UNIT (KIU) ....................................................................... 317 16.1 General .................................................................................................................................... 317 16.2 Functional Description .......................................................................................................... 317
16.2.1 Automatic keyboard scan mode (Auto Scan mode) .................................................................. 318 16.2.2 Manual keyboard scan mode (Manual Scan mode) .................................................................. 318 16.2.3 Key press detection ................................................................................................................... 318 16.2.4 Scan operation .......................................................................................................................... 319 16.2.5 Reading scanned data ............................................................................................................... 320 16.2.6 Interrupts and status reporting ................................................................................................... 320
16.3 Register Set ............................................................................................................................ 321
16.3.1 KIUDATn (0x0B00 0180 to 0x0B00 018E) ................................................................................ 322 16.3.2 KIUSCANREP (0x0B00 0190) ................................................................................................... 323 16.3.3 KIUSCANS (0x0B00 0192) ........................................................................................................ 324 16.3.4 KIUWKS (0x0B00 0194) ............................................................................................................ 325 16.3.5 KIUWKI (0x0B00 0196) ............................................................................................................. 326 16.3.6 KIUINT (0x0B00 0198) .............................................................................................................. 327
CHAPTER 17 COMPACTFLASH CONTROLLER (ECU) .................................................................. 328 17.1 General .................................................................................................................................... 328 17.2 Register Set Summary ........................................................................................................... 328 17.3 ECU Control Registers .......................................................................................................... 331
17.3.1 INTSTATREG (0x0B00 08F8) ................................................................................................... 331 17.3.2 INTMSKREG (0x0B00 08FA) .................................................................................................... 332 17.3.3 CFG_REG_1 (0x0B00 08FE) .................................................................................................... 333
17.4 ECU Registers ........................................................................................................................ 334
17.4.1 ID_REV_REG (Index: 0x00) ...................................................................................................... 334 17.4.2 IF_STAT_REG (Index: 0x01) ..................................................................................................... 335 17.4.3 PWRRSETDRV (Index: 0x02) ................................................................................................... 336 17.4.4 ITGENCTREG (Index: 0x03) ..................................................................................................... 337 17.4.5 CDSTCHGREG (Index: 0x04) ................................................................................................... 338 17.4.6 CRDSTATREG (Index: 0x05) .................................................................................................... 339 17.4.7 ADWINENREG (Index: 0x06) .................................................................................................... 340 17.4.8 IOCTRL_REG (Index: 0x07) ...................................................................................................... 341 17.4.9 IOADSLBnREG (Index: 0x08, 0x0C) ......................................................................................... 342 17.4.10 IOADSHBnREG (Index: 0x09, 0x0D) ...................................................................................... 342 17.4.11 IOSLBnREG (Index: 0x0A, 0x0E) ............................................................................................ 343 17.4.12 IOSHBnREG (Index: 0x0B, 0x0F) ........................................................................................... 343
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17.4.13 SYSMEMSLnREG (Index: 0x10, 0x18, 0x20, 0x28, 0x30) ...................................................... 344 17.4.14 MEMWIDn_REG (Index: 0x11, 0x19, 0x21, 0x29, 0x31) ........................................................ 344 17.4.15 SYSMEMELnREG (Index: 0x12, 0x1A, 0x22, 0x2A, 0x32) ..................................................... 345 17.4.16 MEMSELn_REG (Index: 0x13, 0x1B, 0x23, 0x2B, 0x33) ........................................................ 345 17.4.17 MEMOFFLnREG (Index: 0x14, 0x1C, 0x24, 0x2C, 0x34) ....................................................... 346 17.4.18 MEMOFFHnREG (Index: 0x15, 0x1D, 0x25, 0x2D, 0x35) ...................................................... 346 17.4.19 DTGENCLREG (Index: 0x16) .................................................................................................. 347 17.4.20 GLOCTRLREG (Index: 0x1E) ................................................................................................. 348 17.4.21 VOLTSENREG (Index: 0x1F) .................................................................................................. 348 17.4.22 VOLTSELREG (Index: 0x2F) .................................................................................................. 349
17.5 Memory Mapping of CompactFlash Card ............................................................................ 350 17.6 Controlling Bus When CompactFlash Card Is Used .......................................................... 352
17.6.1 Controlling bus size ................................................................................................................... 352 17.6.2 Controlling wait .......................................................................................................................... 352
CHAPTER 18 LED CONTROL UNIT (LED) ...................................................................................... 353 18.1 General ................................................................................................................................... 353 18.2 Register Set ............................................................................................................................ 353
18.2.1 LEDHTSREG (0x0B00 0240) .................................................................................................... 354 18.2.2 LEDLTSREG (0x0B00 0242) ..................................................................................................... 355 18.2.3 LEDCNTREG (0x0B00 0248) .................................................................................................... 356 18.2.4 LEDASTCREG (0x0B00 024A) ................................................................................................. 357 18.2.5 LEDINTREG (0x0B00 024C) ..................................................................................................... 358
18.3 Operation Flow ....................................................................................................................... 359 CHAPTER 19 SERIAL INTERFACE UNIT 1 (SIU1) ........................................................................ 360 19.1 General ................................................................................................................................... 360 19.2 Clock Control Logic ............................................................................................................... 360 19.3 Register Set ............................................................................................................................ 361
19.3.1 SIURB_1 (0x0C00 0010: LCR7 = 0, Read) ............................................................................... 362 19.3.2 SIUTH_1 (0x0C00 0010: LCR7 = 0, Write) ............................................................................... 362 19.3.3 SIUDLL_1 (0x0C00 0010: LCR7 = 1) ........................................................................................ 362 19.3.4 SIUIE_1 (0x0C00 0011: LCR7 = 0) ........................................................................................... 363 19.3.5 SIUDLM_1 (0x0C00 0011: LCR7 = 1) ....................................................................................... 364 19.3.6 SIUIID_1 (0x0C00 0012: Read) ................................................................................................ 366 19.3.7 SIUFC_1 (0x0C00 0012: Write) ................................................................................................ 368 19.3.8 SIULC_1 (0x0C00 0013) ........................................................................................................... 371 19.3.9 SIUMC_1 (0x0C00 0014) .......................................................................................................... 372 19.3.10 SIULS_1 (0x0C00 0015) ......................................................................................................... 373 19.3.11 SIUMS_1 (0x0C00 0016) ........................................................................................................ 375 19.3.12 SIUSC_1 (0x0C00 0017) ......................................................................................................... 376 19.3.13 SIURESET_1 (0x0C00 0019) .................................................................................................. 376 19.3.14 SIUACTMSK_1 (0x0C00 001C) .............................................................................................. 377 19.3.15 SIUACTTMR_1 (0x0C00 001E) .............................................................................................. 378
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CHAPTER 20 SERIAL INTERFACE UNIT 2 (SIU2) ......................................................................... 379 20.1 General .................................................................................................................................... 379 20.2 Clock Control Logic ............................................................................................................... 379 20.3 Register Set ............................................................................................................................ 380
20.3.1 SIURB_2 (0x0C00 0000: LCR7 = 0, Read) ............................................................................... 381 20.3.2 SIUTH_2 (0x0C00 0000: LCR7 = 0, Write) ............................................................................... 381 20.3.3 SIUDLL_2 (0x0C00 0000: LCR7 = 1) ........................................................................................ 381 20.3.4 SIUIE_2 (0x0C00 0001: LCR7 = 0) ........................................................................................... 382 20.3.5 SIUDLM_2 (0x0C00 0001: LCR7 = 1) ....................................................................................... 383 20.3.6 SIUIID_2 (0x0C00 0002: Read) ................................................................................................. 385 20.3.7 SIUFC_2 (0x0C00 0002: Write) ................................................................................................. 387 20.3.8 SIULC_2 (0x0C00 0003) ........................................................................................................... 390 20.3.9 SIUMC_2 (0x0C00 0004) .......................................................................................................... 391 20.3.10 SIULS_2 (0x0C00 0005) ......................................................................................................... 392 20.3.11 SIUMS_2 (0x0C00 0006) ......................................................................................................... 394 20.3.12 SIUSC_2 (0x0C00 0007) ......................................................................................................... 395 20.3.13 SIUIRSEL_2 (0x0C00 0008) .................................................................................................... 395 20.3.14 SIURESET_2 (0x0C00 0009) .................................................................................................. 396 20.3.15 SIUCSEL_2 (0x0C00 000A) .................................................................................................... 396 20.3.16 SIUACTMSK_2 (0x0C00 000C) .............................................................................................. 397 20.3.17 SIUACTTMR_2 (0x0C00 000E) ............................................................................................... 398
CHAPTER 21 LCD CONTROLLER ..................................................................................................... 399 21.1 Overview ................................................................................................................................. 399
21.1.1 LCD interface ............................................................................................................................. 399
21.2 LCD Module Features ............................................................................................................ 400 21.3 LCD Controller Specification ................................................................................................ 402
21.3.1 Panel configuration and interface .............................................................................................. 402 21.3.2 Controller clocks ........................................................................................................................ 405 21.3.3 Palette ....................................................................................................................................... 406 21.3.4 Frame buffer memory and FIFO ................................................................................................ 406 21.3.5 Panel power ON/OFF sequence ................................................................................................ 407 21.3.6 Operation of LCD controller ....................................................................................................... 408
21.4 Register Set ............................................................................................................................ 413
21.4.1 HRTOTALREG (0x0A00 0400) .................................................................................................. 414 21.4.2 HRVISIBREG (0x0A00 0402) .................................................................................................... 414 21.4.3 LDCLKSTREG (0x0A00 0404) .................................................................................................. 415 21.4.4 LDCLKENDREG (0x0A00 0406) ............................................................................................... 415 21.4.5 VRTOTALREG (0x0A00 0408) .................................................................................................. 416 21.4.6 VRVISIBREG (0x0A00 040A) .................................................................................................... 416 21.4.7 FVSTARTREG (0x0A00 040C) ................................................................................................. 417 21.4.8 FVENDREG (0x0A00 040E) ...................................................................................................... 417 21.4.9 LCDCTRLREG (0x0A00 0410) .................................................................................................. 418 21.4.10 LCDINRQREG (0x0A00 0412) ................................................................................................ 419 21.4.11 LCDCFGREG0 (0x0A00 0414) ................................................................................................ 420 21.4.12 LCDCFGREG1 (0x0A00 0416) ................................................................................................ 421
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21.4.13 FBSTADREG1 (0x0A00 0418) ................................................................................................ 422 21.4.14 FBSTADREG2 (0x0A00 041A) ................................................................................................ 422 21.4.15 FBENDADREG1 (0x0A00 0420) ............................................................................................. 423 21.4.16 FBENDADREG2 (0x0A00 0422) ............................................................................................. 423 21.4.17 FHSTARTREG (0x0A00 0424) ................................................................................................ 424 21.4.18 FHENDREG (0x0A00 0426) .................................................................................................... 424 21.4.19 PWRCONREG1 (0x0A00 0430) .............................................................................................. 425 21.4.20 PWRCONREG2 (0x0A00 0432) .............................................................................................. 426 21.4.21 LCDIMSKREG (0x0A00 0434) ................................................................................................ 427 21.4.22 CPINDCTREG (0x0A00 047E) ................................................................................................ 428 21.4.23 CPALDATREG (0x0A0 0480) .................................................................................................. 429
CHAPTER 22 PLL PASSIVE COMPONENTS ................................................................................... 430 CHAPTER 23 COPROCESSOR 0 HAZARDS ................................................................................... 431 APPENDIX A RESTRICTIONS ON VR4181 ....................................................................................... 436 A.1 RSTSW# During HALTimer Operation .................................................................................. 436 A.2 RSTSW# in Hibernate Mode ................................................................................................... 437 APPENDIX B INDEX ............................................................................................................................. 439
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LIST OF FIGURES (1/3)
Fig. No. 1-1. 1-2. 1-3. 1-4. 1-5. 1-6. 1-7. 1-8. 1-9. 3-1. 3-2. 3-3. 3-4. 3-5. 3-6. 3-7. 3-8. 3-9. 3-10. 3-11. 3-12. 3-13. 3-14. 3-15. 3-16. 3-17. 3-18. 3-19. 3-20. 3-21. 3-22. 3-23. 3-24. 3-25. 3-26. 3-27. 3-28. 4-1. Title Page
Internal Block Diagram ................................................................................................................................ 30 VR4110 CPU Core Internal Block Diagram ................................................................................................. 35 CPU Registers ............................................................................................................................................ 37 CPU Instruction Formats (32-Bit Length Instruction) .................................................................................. 38 CPU Instruction Formats (16-Bit Length Instruction) .................................................................................. 39 Byte Address in Little-Endian Byte Order .................................................................................................... 41 Unaligned Word Accessing (Little Endian) .................................................................................................. 42 External Circuits of Clock Oscillator ............................................................................................................ 48 Incorrect Connection Circuits of Resonator ................................................................................................ 49 Index Register ............................................................................................................................................. 69 Random Register ........................................................................................................................................ 69 EntryLo0 and EntryLo1 Registers ............................................................................................................... 70 Context Register ......................................................................................................................................... 71 PageMask Register ..................................................................................................................................... 72 Positions Indicated by the Wired Register .................................................................................................. 73 Wired Register ............................................................................................................................................ 73 BadVAddr Register ..................................................................................................................................... 74 Count Register ............................................................................................................................................ 74 EntryHi Register .......................................................................................................................................... 75 Compare Register ....................................................................................................................................... 76 Status Register ............................................................................................................................................ 76 Status Register Diagnostic Status Field ...................................................................................................... 77 Cause Register ........................................................................................................................................... 79 EPC Register (When MIPS16 ISA Is Disabled) .......................................................................................... 81 EPC Register (When MIPS16 ISA Is Enabled) ........................................................................................... 82 PRId Register .............................................................................................................................................. 82 Config Register ........................................................................................................................................... 83 LLAddr Register .......................................................................................................................................... 84 WatchLo Register ........................................................................................................................................ 85 WatchHi Register ........................................................................................................................................ 85 XContext Register ....................................................................................................................................... 86 Parity Error Register .................................................................................................................................... 87 Cache Error Register .................................................................................................................................. 87 TagLo Register ............................................................................................................................................ 88 TagHi Register ............................................................................................................................................ 88 ErrorEPC Register (When MIPS16 ISA Is Disabled) .................................................................................. 90 ErrorEPC Register (When MIPS16 ISA Is Enabled) ................................................................................... 90 VR4181 Physical Address Space ................................................................................................................ 92
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Fig. No. 5-1. 5-2. 5-3. 5-4. 5-5. 5-6. 5-7. 5-8. 5-9. 6-1. 6-2. 6-3. 6-4. 6-5. 6-6. 6-7. 6-8. 8-1. 9-1. 10-1. 10-2. 10-3. 10-4. 10-5. 10-6. 10-7. 10-8. 10-9. 10-10. 10-11. 10-12. 13-1. Title Page
RTC Reset .................................................................................................................................................. 97 RSTSW Reset ............................................................................................................................................. 98 Deadman's Switch Reset ............................................................................................................................ 99 Software Shutdown ..................................................................................................................................... 100 HALTimer shutdown ................................................................................................................................... 101 VR4181 Activation Sequence (When Activation Is OK) ............................................................................... 102 VR4181 Activation Sequence (When Activation Is NG) .............................................................................. 103 Cold Reset .................................................................................................................................................. 104 Soft Reset ................................................................................................................................................... 105 VR4181 Internal Bus Structure .................................................................................................................... 108 ROM Read Cycle and Access Parameters ................................................................................................. 114 Ordinary ROM Read Cycle (WROMA(3:0) = 0101) .................................................................................... 125 PageROM Read Cycle (WROMA(3:0) = 0011, WPROM(2:0) = 001) ......................................................... 126 Flash Memory Read Cycle (Rtype(1:0) = 01, WROMA(3:0) = 0101) .......................................................... 127 Flash Memory Write Cycle (Rtype(1:0) = 01, WROMA(3:0) = 0100) .......................................................... 127 External EDO DRAM Configuration ............................................................................................................ 128 SDRAM Configuration ................................................................................................................................. 130 SCK and SI/SO Relationship ...................................................................................................................... 157 Outline of Interrupt Control .......................................................................................................................... 172 Transition of VR4181 Power Mode .............................................................................................................. 189 EDO DRAM Signals on RSTSW Reset (SDRAM Bit = 0) ........................................................................... 192 Activation via Power Switch Interrupt Request (BATTINH = H) .................................................................. 195 Activation via Power Switch Interrupt Request (BATTINH = L) .................................................................. 195 Activation via CompactFlash Interrupt Request (BATTINH = H) ................................................................ 196 Activation via CompactFlash Interrupt Request (BATTINH = L) ................................................................. 196 Activation via GPIO Activation Interrupt Request (BATTINH = H) .............................................................. 197 Activation via GPIO Activation Interrupt Request (BATTINH = L) ............................................................... 197 Activation via DCD Interrupt Request (BATTINH = H) ................................................................................ 199 Activation via DCD Interrupt Request (BATTINH = L) ................................................................................ 199 Activation via ElapsedTime Interrupt Request (BATTINH = H) ................................................................... 200 Activation via ElapsedTime Interrupt Request (BATTINH = L) ................................................................... 200 GPIO(15:0) Interrupt Request Detecting Logic ........................................................................................... 243
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LIST OF FIGURES (3/3)
Fig. No. 14-1. 14-2. 14-3. 14-4. 14-5. 14-6. 14-7. 15-1. 15-2. 16-1. 17-1. 17-2. 17-3. 19-1. 20-1. 21-1. 21-2. 21-3. 21-4. 21-5. 21-6. 21-7. 21-8. 21-9. 21-10. 22-1. A-1. A-2. A-3. Title Page
PIU Peripheral Block Diagram .................................................................................................................... 276 Coordinate Detection Equivalent Circuits .................................................................................................... 277 Internal Block Diagram of PIU ..................................................................................................................... 277 Scan Sequencer State Transition Diagram ................................................................................................. 278 Interval Times and States ........................................................................................................................... 286 Touch/Release Detection Timing ................................................................................................................ 298 A/D Port Scan Timing .................................................................................................................................. 298 Speaker Output and AUDIOOUT Pin .......................................................................................................... 315 AUDIOIN Pin and Microphone Operation .................................................................................................... 316 SCANOUT Signal Output Timing ................................................................................................................ 319 CompactFlash Interrupt Logic ..................................................................................................................... 333 Mapping of CompactFlash Memory Space ................................................................................................. 350 Mapping of CompactFlash I/O Space ......................................................................................................... 351 SIU1 Block Diagram .................................................................................................................................... 360 SIU2 Block Diagram .................................................................................................................................... 379 LCD Controller Block Diagram .................................................................................................................... 401 View Rectangle and Horizontal/Vertical Blank ............................................................................................ 402 Position of Load Clock (LOCLK) ................................................................................................................. 403 Position of Frame Clock (FLM) ................................................................................................................... 404 Monochrome Panel ..................................................................................................................................... 408 Color Panel in 8-Bit Data Bus ..................................................................................................................... 409 Load Clock (LOCLK) ................................................................................................................................... 410 Frame Clock (FLM) ..................................................................................................................................... 410 LCD Timing Parameters .............................................................................................................................. 411 FLM Period .................................................................................................................................................. 411 Example of Connection of PLL Passive Components ................................................................................. 430 Mask Circuit for RSTSW# Signal ................................................................................................................ 436 Release of Self-Refresh Mode by RSTSW# Signal (EDO DRAM) .............................................................. 437 Release of Self-Refresh Mode by RSTSW# Signal (SDRAM) .................................................................... 438
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Table No. 1-1. 1-2. 1-3. 1-4. 1-5. 1-6. 1-7. 3-1. 3-2. 3-3. 3-4. 4-1. 4-2. 4-3. 4-4. 4-5. 4-6. 6-1. 6-2. 6-3. 6-4. 7-1. 8-1. 9-1. 10-1. 10-2. 10-3. 10-4. 11-1. 12-1. 13-1. 13-2. 13-3. 13-4. Title Page
Supported PClock and TClock Frequencies ............................................................................................... 31 Devices Supported by System Bus ............................................................................................................. 31 GPIO(31:0) Pin Functions ........................................................................................................................... 33 LCD Panel Resolutions (in Pixels, TYP.) .................................................................................................... 34 Functions of LCD Interface Pins when LCD Controller Is Disabled ............................................................ 34 System Control Coprocessor (CP0) Register Definitions ........................................................................... 43 List of Instructions Supported by VR Series Processors ............................................................................. 46 CP0 Registers ............................................................................................................................................. 68 Cache Algorithm ......................................................................................................................................... 71 Mask Values and Page Sizes ..................................................................................................................... 72 Cause Register Exception Code Field ........................................................................................................ 80 VR4181 Physical Address Space ................................................................................................................ 93 ROM Address Map ..................................................................................................................................... 93 Internal I/O Space 1 .................................................................................................................................... 94 Internal I/O Space 2 .................................................................................................................................... 94 MBA Bus I/O Space .................................................................................................................................... 95 DRAM Address Map ................................................................................................................................... 95 Bus Control Registers ................................................................................................................................. 110 VR4181 EDO DRAM Capacity ..................................................................................................................... 129 Memory Controller Registers ...................................................................................................................... 131 ISA Bridge Registers ................................................................................................................................... 137 DCU Registers ............................................................................................................................................ 144 CSI Registers .............................................................................................................................................. 160 ICU Registers .............................................................................................................................................. 173 Overview of Power Modes .......................................................................................................................... 190 Operations During Reset ............................................................................................................................ 191 Operations During Shutdown ...................................................................................................................... 193 PMU Registers ............................................................................................................................................ 208 RTC Registers ............................................................................................................................................ 216 DSU Registers ............................................................................................................................................ 230 Alternate Functions of GPIO(15:0) Pins ...................................................................................................... 236 Alternate Functions of GPIO(31:16) Pins .................................................................................................... 237 CSI Interface Signals .................................................................................................................................. 238 Serial Interface Channel 1 (SIU1) Signals .................................................................................................. 239
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Table No. 13-5. 13-6. 13-7. 13-8. 13-9. 13-10. 13-11. 14-1. 14-2. 14-3. 14-4. 14-5. 14-6. 14-7. 15-1. 15-2. 16-1. 16-2. 16-3. 17-1. 17-2. 18-1. 19-1. 19-2. 19-3. 20-1. 20-2. 20-3. 21-1. 21-2. 21-3. 21-4. 23-1. 23-2. Title Page
Serial Interface Channel 1 (SIU1) Loopback Control .................................................................................. 239 Serial Interface Channel 2 (SIU2) Signals .................................................................................................. 240 Serial Interface Channel 2 (SIU2) Loopback Control .................................................................................. 240 STN Color LCD Interface Signals ............................................................................................................... 241 External LCD Controller Interface Signals .................................................................................................. 241 Programmable Chip Select Signals ............................................................................................................ 242 GIU Registers .............................................................................................................................................. 244 PIU Registers .............................................................................................................................................. 280 PIU Interrupt Registers ................................................................................................................................ 280 PIUCNTREG Bit Manipulation and States .................................................................................................. 283 PIUASCNREG Bit Manipulation and States ................................................................................................ 290 Detected Data and Page Buffers ................................................................................................................ 293 A/D Ports and Data Buffers ......................................................................................................................... 294 Mask Clear During Scan Sequencer Operation .......................................................................................... 295 AIU Registers .............................................................................................................................................. 302 AIU Interrupt Registers ................................................................................................................................ 302 Settings of Keyboard Scan Mode ................................................................................................................ 318 KIU Registers .............................................................................................................................................. 321 KIU Interrupt Registers ................................................................................................................................ 321 ECU Control Registers ................................................................................................................................ 328 ECU Registers ............................................................................................................................................ 329 LED Registers ............................................................................................................................................. 353 SIU1 Registers ............................................................................................................................................ 361 Correspondence between Baud Rates and Divisors .................................................................................. 365 Interrupt Function ........................................................................................................................................ 367 SIU2 Registers ............................................................................................................................................ 380 Correspondence between Baud Rates and Divisors .................................................................................. 384 Interrupt Function ........................................................................................................................................ 386 LCD Panel Resolutions (in Pixels, TYP.) .................................................................................................... 399 Redefining LCD Interface Pins When LCD Controller Is Disabled .............................................................. 400 LCD Controller Parameters ......................................................................................................................... 412 LCD Controller Registers ............................................................................................................................ 413 Coprocessor 0 Hazards .............................................................................................................................. 432 Calculation Example of CP0 Hazard and Number of Instructions Inserted ................................................. 435
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This chapter describes the outline of the VR4181 ( PD30181), which is a 64-/32-bit microprocessor.
1.1 Features
The VR4181, which is a high-performance 64-/32-bit microprocessor employing the RISC (reduced instruction set computer) architecture developed by MIPS , is one of the VR-Series microprocessor products manufactured by NEC Electronics. The VR4181 contains the VR4110
TM TM
CPU core of ultra-low-power consumption with cache memory, high-speed
product-sum operation unit, and memory management unit. It also has interface units for peripheral circuits such as LCD controller, CompactFlash controller, DMA controller, keyboard interface, serial interface, IrDA interface, touch panel interface, real-time clock, A/D converter and D/A converter required for the battery-driven portable information equipment. The features of the VR4181 are described below. * Employs 0.25 m process * 64-bit RISC VR4110 CPU core with pipeline clock up to 66 MHz (operation in 32-bit mode is available) * Optimized 5-stage pipeline * On-chip instruction and data caches with 4 KB each in size * Write-back cache for reducing store operation that use the system bus * 32-bit physical address space and 40-bit virtual address space, and 32 double-entry TLB * Instruction set: MIPS III (with the FPU, LL and SC instructions left out) and MIPS16 * Supports MADD16 and DMADD16 instructions for executing a multiply-and-accumulate operation of 16-bit data x 16-bit data + 64-bit data within one clock cycle * Effective power management features, which include four operating modes, Fullspeed, Standby, Suspend and Hibernate mode * On-chip PLL and clock generator * DRAM interface supporting 16-bit width SDRAM and EDO DRAM * Ordinary ROM/PageROM/flash memory interface * UMA based LCD controller * 4-channel DMA controller * RTC unit including 3-channel timers and counters * Two UART-compatible serial interfaces and one clocked serial interface * IrDA (SIR) interface * Keyboard scan interface supporting 8 x 8 key matrix * X-Y auto-scan touch panel interface * CompactFlash interface compatible with ExCA * A/D and D/A converters * Includes ISA-subset bus * Supply voltage: 2.5 V for CPU core, 3.3 V for I/O * Package: 160-pin LQFP
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1.2 Ordering Information
Part number Package 160-pin plastic LQFP (fine pitch) (24 x 24) Maximum internal operating frequency 66 MHz
PD30181GM-66-8ED
1.3 VR4181 Key Features
Figure 1-1. Internal Block Diagram
LCD Panel
EDO DRAM/ SDRAM
ROM/ Flash memory System bus (ISA)
Buf
Buf
LCD controller
DCU
Memory controller MBA bus
Bus control
ECU
CompactFlash card
AIU D/A
32.768 kHz 18.432 MHz
Clock generator
VR4110 CPU core
ICU MBATM Host Bridge ISA bridge ISA bus
PMU
Speaker
Microphone
RTC KIU LED GIU CSI SIU2 SIU1 DSU PIU A/D
Touch panel
VR4181
IR module Keyboard (8 x 8) RS-232-C driver
Battery monitor
LED
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1.3.1 CPU core The VR4181 integrates an NEC Electronics' VR4110 CPU core supporting both the MIPS III and MIPS16 instruction sets. The VR4181 supports the following pipeline clock (PClock) and internal bus clock (TClock) frequencies. The PClock is set by attaching pull-up or pull-down resistors to the CLKSEL(2:0) pins. The frequency of the TClock, which is used in MBA bus, is set by PMUDIVREG register in Power Management Unit. Table 1-1. Supported PClock and TClock Frequencies
PClock frequency 65.4 MHz 62.0 MHz 49.1 MHz TClock frequency 65.4/32.7/21.8 MHz 62.0/31.0/20.7 MHz 49.1/24.6 MHz
The VR4110 core of the VR4181 includes 4 KB of instruction cache and 4 KB of data cache. The VR4110 core also supports the following power management modes: * Fullspeed * Standby * Suspend
Note
* Hibernate Note Suspend mode is supported only when the internal LCD controller has been disabled or the LCD panel has been powered off. 1.3.2 Bus interface The VR4181 incorporates single bus architecture. All external memory and I/O devices are connected to the same 22-bit address bus and 16-bit data bus. These external address and data bus are together called the system bus. When the external bus operates at a very high speed, the DRAM data bus must be isolated from other low speed devices such as ROM array. The VR4181 provides two pins, SYSEN# and SYSDIR, to control the data buffers for this isolation. The VR4181 supports the following types of devices connected to the system bus. Table 1-2. Devices Supported by System Bus
Device ROM, flash memory DRAM CompactFlash External I/O External memory 16 bits only 16 bits only 8 or 16 bits 8 or 16 bits 8 or 16 bits Data width
Six of the external bus interface signals, IORD#, IOWR#, IORDY, IOCS16#, MEMCS16# and RESET#, can be individually defined as general-purpose I/O pins or LCD interface pin if they are not needed by external system components.
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1.3.3 Memory interface The VR4181 provides control for both ROM/flash memory and DRAM. Up to four 16-bit ROM/flash memory banks may be supported utilizing either 32-Mbit or 64-Mbit single cycle or page mode devices. Bank mixing is not supported for ROM/flash memory. When a system implements less than the maximum 4 banks of ROM/flash memory, unused ROM chip select pins can be defined as general-purpose I/O pins. The VR4181 also supports up to 2 banks of 1M x 16 or 4M x 16 EDO-type DRAM or SDRAM at bus frequencies of up to 66 MHz. When both banks are EDO-type DRAM, bank mixing is supported. 1.3.4 DMA controller (DCU) The VR4181 provides a 4-channel DMA controller to support internal DMA transfers. The 4 channels are allocated as follows: * Channel 1 - Audio input * Channel 2 - Audio output * Channel 3, 4 - Reserved 1.3.5 Interrupt controller (ICU) The VR4181 provides an interrupt controller which combines all interrupt request sources into one of the VR4110 core interrupt inputs - NMI and Int(2:0). The interrupt controller also provides interrupt request status reporting. 1.3.6 Real-time clock The VR4181 includes a real-time clock (RTC), which allows time keeping based on the 32.768 kHz clock as a source. The RTC operates as long as the VR4181 remains powered. 1.3.7 Audio output (D/A converter) The VR4181 provides a 1-channel 10-bit D/A converter for generating audio output. 1.3.8 Touch panel interface and audio input (A/D converter) The VR4181 provides an 8-channel 10-bit A/D converter for interfacing to a touch panel, an external microphone, and other types of analog input. 1.3.9 CompactFlash interface (ECU) The VR4181 provides an ExCA-compatible bus controller supporting a single CompactFlash slot. This interface is shared with the keyboard interface logic and must be disabled when an 8 x 8 key matrix is connected to the VR4181. 1.3.10 Serial interface channel 1 (SIU1) The VR4181 provides a 16550 UART for implementing an RS-232-C type serial interface. When the serial interface is not needed, each of the 7 serial interface pins can be individually redefined as general-purpose I/O pins. 1.3.11 Serial interface channel 2 (SIU2) The serial interface channel 2 is also based on a 16550 UART but only reserves 2 pins for the interface. The serial interface channel 2 can be configured in one of the following modes: * Simple 2-wire serial interface using TxD2 and RxD2 * SIR-type IrDA interface using IRDIN and IRDOUT * Full RS-232-C compatible interface using TxD2, RxD2 and 5 GPIO pins
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1.3.12 Clocked serial interface (CSI) The VR4181 provides a clocked serial interface (CSI) which has an option to be configured as general-purpose I/O pins. This interface supports slave mode operation only. The clocked serial interface requires allocation of 4 signals; SI, SO, SCK, and FRM. The clock source for this interface is input on the pin assigned to SCK. 1.3.13 Keyboard interface (KIU) The VR4181 provides support for an 8 x 8 key matrix. This keyboard interface can only be supported when the CompactFlash interface is disabled and reconfigured to provide the SCANIN(7:0) inputs and the SCANOUT(7:0) outputs. 1.3.14 General-purpose I/O The VR4181 provides total 32 bits of general-purpose I/O. Sixteen of these, GPIO(31:16), are available through pins allocated to other functions as shown in the following table. The DCD1#/GPIO29 is the only one of the 16 pins that can cause the system's waking up from a low power mode if enabled by software. The other pins have no functions other than those listed below. The remaining 16 bits of general-purpose I/O, GPIO(15:0), are allocated to pins by default. Each of these pins can be configured to support a particular interface such as CSI, secondary serial interface (RS-232-C), programmable chip selects, or color LCD control. Otherwise, each of these pins can be also defined as one of the following: * General-purpose input * General-purpose output * Interrupt request input * Wake-up input Table 1-3. GPIO(31:0) Pin Functions
Pin designation GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 SI SO SCK PCS0# - DCD2# RTS2# DTR2# DSR2# CTS2# FRM/SYSCLK PCS1# FPD4 FPD5 FPD6/CD1# FPD7/CD2# Alternate function Pin designation GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31
Note
Alternate function IORD# IOWR# IORDY IOCS16# M/UBE# RESET# ROMCS0# ROMCS1# ROMCS2# RxD1 TxD1 RTS1# CTS1# DCD1# DTR1# DSR1#
Note This signal supports input only.
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1.3.15 Programmable chip selects The VR4181 provides support for 2 programmable chip selects (PCS) which are also available as general-purpose I/O pins. Each PCS can decode either I/O or memory accesses and can optionally be qualified to read, write, or both read and write. 1.3.16 LCD interface The LCD controller of the VR4181 is Unified Memory Architecture (UMA) based in which the frame buffer is part of system DRAM. The LCD controller supports monochrome STN LCD panels having 4-bit data bus interfaces and color STN LCD panels having 8-bit data bus interface. When interfacing to a color LCD panel, general-purpose I/O pins must be allocated to provide the upper nibble of the 8-bit LCD data bus. In monochrome mode, the LCD controller supports 1-bpp mode (mono), 2-bpp mode (4 gray levels) and 4-bpp mode (16 gray levels). In color mode, it supports 4-bpp mode (16 colors) and 8-bpp mode (256 colors). The LCD controller includes a 256-entry x 18-bit color pallet. In 8-bpp color modes, the pallet is used to select 256 colors out of possible 262,144 colors. The LCD controller supports LCD panels of up to 320 x 320 pixels. Typical LCD panel horizontal/vertical resolutions are as follows. Table 1-4. LCD Panel Resolutions (in Pixels, TYP.)
Horizontal resolution 320 320 320 240 240 240 160 160 160 Vertical resolution 320 240 160 320 240 160 320 240 160
The LCD controller also provides power-on and power-down sequence control for the LCD panel via the VPLCD and VPBIAS pins. Power sequencing is provided to prevent latch-up damage to the panel. The LCD controller can be disabled to allow connection of an external LCDC with integrated frame buffer RAM such as NEC Electronics' PD16661. When the internal LCD controller is disabled, the SHCLK, LOCLK, VPLCD, and VPBIAS pins are redefined as follows: Table 1-5. Functions of LCD Interface Pins when LCD Controller Is Disabled
Redefined function LCDCS# MEMCS16# VPGPIO1 VPGPIO0 Default function SHCLK LOCLK VPLCD VPBIAS
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1.3.17 Wake-up events The VR4181 supports 4 power management modes: Fullspeed, Standby, Suspend, and Hibernate. Of these modes, Hibernate is the lowest power mode and results in the powering off of all system components including the 2.5 V logic in the VR4181. The VR4181 3.3 V logic, which includes RTC, PMU, and non-volatile registers, remain powered during the Hibernate mode, as does the system DRAM. Software can configure the VR4181 waking up from the Hibernate mode and returning to Fullspeed mode due to any one of the following events: * Activation of the DCD1# pin * Activation of the POWER pin * RTC alarm * Activation of one of the GPIO(15:0) pins * Activation of the CF_BUSY# pin (CompactFlash interrupt request (IREQ)) Remark Different from the VR4111 wake-up events.
TM
or the VR4121 , the VR4181 will wake up after RTC reset without these
TM
1.4 VR4110 CPU Core
Figure 1-2 shows the internal block diagram of the VR4110 CPU core. In addition to the conventional high-performance integer operation units, this CPU core has the full-associative format translation lookaside buffer (TLB), which has 32 entries that provide mapping to 2-page pairs (odd and even) for one entry. Moreover, it also includes instruction cache, data cache, and bus interface. Figure 1-2. VR4110 CPU Core Internal Block Diagram
Virtual address bus Internal data bus
Control(o) Control(i) Address/Data(o) Address/Data(i)
Bus interface
Data cache (4 KB)
Instruction cache (4 KB)
CP0
CPU
TLB
Clock generator Internal clock
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(1) CPU The CPU has hardware resources to process an integer instruction. They are the 64-bit register file, 64-bit integer data path, and multiply-and-accumulate operation unit. (2) Coprocessor 0 (CP0) The CP0 incorporates a memory management unit (MMU) and exception handling function. MMU checks whether there is an access between different memory segments (user, supervisor, and kernel) by executing address translation. The translation lookaside buffer (TLB) translates virtual addresses to physical addresses. (3) Instruction cache The instruction cache employs direct mapping, virtual index, and physical tag. Its capacity is 4 KB. (4) Data cache The data cache employs direct mapping, virtual index, physical tag, and writeback. Its capacity is 4 KB. (5) CPU bus interface The CPU bus interface controls data transmission/reception between the VR4110 core and the MBA Host Bridge. This interface consists of two 32-bit multiplexed address/data buses (one is for input, and another is for output), clock signal, and control signals such as interrupt requests. (6) Clock generator The following clock inputs are oscillated and supplied to internal units. * 32.768 kHz clock for RTC unit Crystal resonator input oscillated via an internal oscillator and supplied to the RTC unit. * 18.432 MHz clock for serial interface and the VR4181's reference operating clock Crystal resonator input oscillated via an internal oscillator, and then multiplied by phase-locked loop (PLL) to generate a pipeline clock (PClock). The internal bus clock (TClock) is generated from PClock and supplied to peripheral units.
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1.4.1 CPU registers The VR4110 core has thirty-two 64-bit general-purpose registers (GPRs). In addition, the processor provides the following special registers: * 64-bit Program Counter (PC) * 64-bit HI register, containing the integer multiply and divide upper doubleword result * 64-bit LO register, containing the integer multiply and divide lower doubleword result Two of the general-purpose registers have assigned functions as follows: * r0 is hardwired to a value of zero, and can be used as the target register for any instruction whose result is to be discarded. r0 can also be used as a source when a zero value is needed. * r31 is the link register used by link instructions, such as JAL (Jump and Link) instruction. This register can be used for other instructions. However, be careful that use of the register by a link instruction will not coincide with use of the register for other operations. The register group is provided within the CP0, to process exceptions and to manage addresses. CPU registers can operate as either 32-bit or 64-bit registers, depending on the VR4181 processor mode of operation. The operation of the CPU registers differs depending on what instructions are executed: 32-bit instructions or MIPS16 instructions. For details, refer to VR4100 Series Architecture User's Manual. The VR4181 has no Program Status Word (PSW) register as such; this is covered by the Status and Cause registers incorporated within the CP0 (see 1.4.4 CP0 registers). Figure 1-3 shows the CPU registers. Figure 1-3. CPU Registers
General-purpose registers 63 32 31 r0 = 0 r1 r2 63 32 31 LO 0 0 63 Multiply/divide registers 32 31 HI 0
r29 r30 r31 = LinkAddress 63
Program Counter 32 31 PC 0
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1.4.2 CPU instruction set overview There are two types of CPU instructions: 32-bit length instructions (MIPS III) and 16-bit length instructions (MIPS16). Use of the MIPS16 instructions is enabled or disabled by setting MIPS16EN pin during a reset. For details about instruction formats and their fields in each instruction set and operation of each instruction, refer to VR4100 Series Architecture User's Manual. (1) MIPS III instructions All the CPU instructions are 32-bit length when executing MIPS III instructions, and they are classified into three instruction formats as shown in Figure 1-4: immediate (I type), jump (J type), and register (R type). Figure 1-4. CPU Instruction Formats (32-Bit Length Instruction)
31 I - type (Immediate) 31 J - type (Jump) 31 R - type (Register) op op op
26 25 rs 26 25
21 20 rt
16 15 immediate
0
0 target
26 25 rs
21 20 rt
16 15 rd
11 10 sa
65 funct
0
The instruction set can be further divided into the following five groupings: (a) Load and store instructions move data between the memory and the general-purpose registers. They are all immediate (I-type) instructions, since the only addressing mode supported is base register plus 16-bit, signed immediate offset. (b) Computational instructions perform arithmetic, logical, shift, and multiply and divide operations on values in registers. They include R-type (in which both the operands and the result are stored in registers) and I-type (in which one operand is a 16-bit signed immediate value) formats. (c) Jump and branch instructions change the control flow of a program. Jumps are made either to an absolute address formed by combining a 26-bit target address with the higher bits of the program counter (J-type format) or register-specified address (R-type format). register 31. (d) System control coprocessor (CP0) instructions perform operations on CP0 registers to control the memorymanagement and exception-handling facilities of the processor. (e) Special instructions perform system calls and breakpoint exceptions, or cause a branch to the general exception-handling vector based upon the result of a comparison. These instructions occur in both R-type and I-type formats. The format of the branch instructions is I type. Branches have 16-bit offsets relative to the program counter. JAL instructions save their return address in
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(2) MIPS16 instructions All the CPU instructions except for JAL and JALX are 16-bit length when executing MIPS16 instructions, and they are classified into thirteen instruction formats as shown in Figure 1-5. Figure 1-5. CPU Instruction Formats (16-Bit Length Instruction)
15 I-type 15 RI-type 15 RR-type 15 RRI-type 15 RRR-type 15 RRI-A-type 15 Shift-type 15 I8-type 15 I8_MOVR32-type 15 I8_MOV32R-type 15 I64-type 15 RI64-type I64 I64 I8 I8 I8 SHIFT RRI-A RRR RRI op op op
11 10 immediate 11 10 rx 11 10 rx 11 10 rx 11 10 rx 11 10 rx 11 10 rx 11 10 funct 11 10 funct 11 10 funct 11 10 funct 11 10 funct 87 ry 87 immediate 54 immediate 87 r32(2:0) 87 ry 54 87 immediate 54 r32(4:0) 32 rz 87 ry 87 ry 54 Shamt 87 ry 5 4 F 87 ry 54 rz 3 immediate 21 F 87 ry 54 immediate 21 F 87 immediate 54 funct
0
0
0
0
0
0
0
0
0
0
r32(4:3)
0
0
JAL/JALX-type 31 Immediate(15:0) 16 15 JAL 11 10 9 X 54 0
Immediate(20:16) Immediate(25:21)
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The instruction set can be further divided into the following four groupings: (a) Load and store instructions move data between memory and general-purpose registers. They include RRI, RI, I8, and RI64 types. (b) Computational instructions perform arithmetic, logical, shift, and multiply and divide operations on values in registers. They include RI, RRIA, I8, RI64, I64, RR, RRR, I8_MOVR32, and I8_MOV32R types. (c) Jump and branch instructions change the control flow of a program. They include JAL/JALX, RR, RI, I8, and I types. (d) Special instructions are BREAK and Extend instructions. The BREAK instruction transfers control to an exception handler. The Extend instruction extends the immediate field of the next instruction. They are RR and I types. When extending the immediate field of the next instruction by using the Extend instruction, one cycle is needed for executing the Extend instruction, and another cycle is needed for executing the next instruction. 1.4.3 Data formats and addressing The VR4181 uses the following four data formats: * Doubleword (64 bits) * Word (32 bits) * Halfword (16 bits) * Byte (8 bits) If the data format is any one of halfword, word, or doubleword, the byte ordering can be set as either big endian or little endian. However, the VR4181 only support the little-endian order. Endianness refers to the location of byte 0 within the multi-byte data structure. Figure 1-6 show the configuration. When configured as a little-endian system, byte 0 is always the least-significant (rightmost) byte, which is compatible with PentiumTM and DEC VAXTM conventions. In this manual, bit designations are always little endian.
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Figure 1-6. Byte Address in Little-Endian Byte Order
(a) Word data
Word address 12 8 4 0
31 High-order address 15 11 7 Low-order address 3
24 23 14 10 6 2
16 15 13 9 5 1
87 12 8 4 0
0
(b) Doubleword data
Word 63 High-order address 23 15 Low-order address 7 22 14 6 21 13 5 32 31 20 12 4 19 11 3 Halfword 16 15 18 10 2 17 9 1 87 16 8 0 Byte 0 Doubleword address 16 8 0
Remarks 1. The lowest byte is the lowest address. 2. The address of word data is specified by the lowest byte's address.
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The CPU core uses the following byte boundaries for halfword, word, and doubleword accesses: * Halfword: * Word: * Doubleword: An even byte boundary (0, 2, 4...) A byte boundary divisible by four (0, 4, 8...) A byte boundary divisible by eight (0, 8, 16...)
The following special instructions are used to load and store data that are not aligned on 4-byte (word) or 8-byte (doubleword) boundaries: * Word access: LWL, LWR, SWL, SWR
* Doubleword access: LDL, LDR, SDL, SDR These instructions are used in pairs of L and R. Accessing unaligned data requires one additional instruction cycle (1 PCycle) over that required for accessing aligned data. Figure 1-7 shows the access of an unaligned word that has byte address 3. Figure 1-7. Unaligned Word Accessing (Little Endian)
31 High-order address Low-order address 3
24 23 6
16 15 5
87 4
0
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1.4.4 CP0 registers The CP0 has thirty-two registers, each of which has its own register number. Table 1-6 shows simple descriptions of each register. For the detailed descriptions of the registers, refer to CHAPTER 3 CP0 REGISTERS. Table 1-6. System Control Coprocessor (CP0) Register Definitions
Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 to 25 26 27 28 29 30 31 Index Random EntryLo0 EntryLo1 Context PageMask Wired - BadVAddr Count EntryHi Compare Status Cause EPC PRId Config LLAddr
Note1
Register
Usage Memory management Memory management Memory management Memory management Exception processing Memory management Memory management - Exception processing Exception processing Memory management Exception processing Exception processing Exception processing Exception processing Memory management Memory management Memory management Exception processing Exception processing Exception processing
Description Programmable pointer to TLB array Pseudo-random pointer to TLB array (read only) Lower half of TLB entry for even VPN Lower half of TLB entry for odd VPN Pointer to kernel virtual PTE in 32-bit mode Page size specification Number of wired TLB entries Reserved for future use Virtual address where the most recent error occurred Timer count Higher half of TLB entry (including ASID) Timer compare value Status indication Cause of last exception Exception Program Counter Processor revision identifier Configuration (memory system modes) specification Physical address for self diagnostics Memory reference trap address low bits Memory reference trap address high bits Pointer to kernel virtual PTE in 64-bit mode Reserved for future use Cache parity bits Index and status of cache error Lower half of cache tag Higher half of cache tag Error Exception Program Counter Reserved for future use
TM
WatchLo WatchHi XContext - Parity Error
Note2
- Exception processing Exception processing Memory management Memory management Exception processing
Cache Error TagLo TagHi ErrorEPC -
Note2
-
Notes1. This register is defined to maintain compatibility with the VR4000 meaningless during normal operations.
TM
and VR4400 . This register is
TM
2. This register is defined to maintain compatibility with the VR4100 . This register is not used in the VR4181 hardware.
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1.4.5 Floating-point unit (FPU) The VR4181 does not support the floating-point unit (FPU). Coprocessor Unusable exception will occur if any FPU instructions are executed. If necessary, FPU instructions should be emulated by software in an exception handler. 1.4.6 Memory management unit The VR4181 has a 32-bit physical addressing range of 4 GB. However, since it is rare for systems to implement a physical memory space as large as that memory space, the CPU provides a logical expansion of memory space by translating addresses composed in the large virtual address space into available physical memory addresses. The VR4181 has three operating modes: User, Supervisor, and Kernel. The manner in which memory addresses are mapped depends on these operating modes. In addition, the VR4181 supports the 32-bit and 64-bit addressing modes. addresses are translated or mapped depends on these addressing modes. A detailed description of the physical address space is given in CHAPTER 4 MEMORY MANAGEMENT SYSTEM. For details about the virtual address space, refer to VR4100 Series Architecture User's Manual. (1) Translation lookaside buffer (TLB) Virtual memory mapping is performed using the translation lookaside buffer (TLB). The TLB translates virtual addresses to physical addresses. It runs by a full-associative method and has 32 entries, each of which two successive pages are mapped. The TLB of the VR4181 holds both instruction addresses and data addresses so that it is called as joint TLB (JTLB). The page size can be configured, on a per-entry basis, to map a page size of 1 KB to 256 KB, in power of four. A CP0 register stores the size of the page to be mapped, and that size is entered into the TLB when a new entry is written. Thus, operating systems can provide special purpose maps; for example, a typical frame buffer can be memory-mapped using only one TLB entry. Translating a virtual address to a physical address begins by comparing the virtual address from the processor with the physical addresses in the TLB. There is a match when the virtual page number (VPN) of the address is the same as the VPN field of an entry, and either the Global (G) bit of the TLB entry is set, or the ASID field of the virtual address is the same as the ASID field of the TLB entry. This match is referred to as a TLB hit. If there is no match, a TLB Miss exception is taken by the processor and software is allowed to refill the TLB from a page table of virtual/physical addresses in memory. 1.4.7 Cache The VR4181 chip incorporates instruction and data caches, which are independent of each other. This configuration enables high-performance pipeline operations. Both caches have a 64-bit data bus, enabling a oneclock access. These buses can be accessed in parallel. The instruction cache of the VR4181 has a storage capacity of 4 KB, while the data cache has a capacity of 4 KB. For details about caches, refer to VR4100 Series Architecture User's Manual. 1.4.8 Instruction pipeline The VR4181 has a 5-stage instruction pipeline. Under normal circumstances, one instruction is issued each cycle. For details, refer to VR4100 Series Architecture User's Manual. The manner in which memory
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1.4.9 Power modes The VR4181 supports four power modes: Fullspeed mode, Standby mode, Suspend mode, and Hibernate mode. A detailed description of these power modes is also given in CHAPTER 10 POWER MANAGEMENT UNIT (PMU). (1) Fullspeed mode This is the normal operation mode. The VR4181's default status sets operation under Fullspeed mode. After a reset, the VR4181 returns to Fullspeed mode. (2) Standby mode When a STANDBY instruction has been executed, the processor can be set to Standby mode. During Standby mode, the pipeline clock (PClock) in the CPU core is held at high level. The peripheral units all operate as they do during Fullspeed mode. This means that DMA operations are enabled during Standby mode. During Standby mode, the processor returns to Fullspeed mode if any interrupt request occurs. (3) Suspend mode When the SUSPEND instruction has been executed, the processor can be set to Suspend mode. During Suspend mode, the pipeline clock (PClock) in the CPU core is held at high level. The VR4181 also stops supplying TClock and PCLK to peripheral units. While in this mode, the register and cache contents are retained. Contents of DRAM can also be retained by putting DRAM into self-refresh mode. During Suspend mode, the processor returns to Fullspeed mode if any of power-on factors or some of interrupt requests occurs. (4) Hibernate mode When the HIBERNATE instruction has been executed, the processor can be set to Hibernate mode. During Hibernate mode, clocks other than the RTC clock (32.768 kHz) are held at high level and the PLL stops. While in this mode, contents of the registers and caches are not retained. Contents of DRAM can be retained by putting DRAM into self-refresh mode. Power consumption during Hibernate mode is about 0 W if power to 2.5 V power supply is not applied (it does not go completely to 0 W due to the existence of a 32.768 kHz oscillator or on-chip peripheral circuits that operate at 32.768 kHz). During Hibernate mode, the processor returns to Fullspeed mode if any of power-on factors or some of interrupt requests occurs.
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1.4.10 Code compatibility The VR4110 core is designed in consideration of the program compatibility to other VR-Series processors. However since it has some differences from other processors on their architecture, it cannot necessarily execute all programs that can be executed in other VR-Series processors, and also other VR-Series processors cannot necessarily execute all programs that can be executed in the VR4110 core. Matters that should be paid attention to when porting programs between the VR4110 core and other VR-Series processors are listed below. * A 16-bit length MIPS16 instruction set is added in the VR4110 core. * Multiply-add instructions (MADD16, DMADD16) are added in the VR4110 core. * Instructions for power modes (HIBERNATE, STANDBY, SUSPEND) are added in the VR4110 core to support power modes. * The VR4110 core does not support floating-point instructions since it has no Floating-Point Unit (FPU). * The VR4110 core does not have the LL bit to perform synchronization of multiprocessing. Therefore, it does not support instructions that manipulate the LL bit (LL, LLD, SC, SCD). * The CP0 hazards of the VR4110 core are equally or less stringent than those of the VR4000. For more information about each instruction, refer to VR4100 Series Architecture User's Manual, and user's manuals of each product other than the VR4100 Series. Instructions supported by each of the VR Series processors are listed below. Table 1-7. List of Instructions Supported by VR Series Processors
Products VR4181 VR4111 Supported instructions MIPS I MIPS II MIPS III LL bit manipulation MIPS IV MIPS16 Multiply-add A A A N/A A A A N/A VR4121 VR4122 TM VR4300 TM VR4305 TM VR4310 TM A A A A A A A A A A A A A A A A VR5000A TM VR5432 TM VR10000TM VR12000TM
N/A A A (16 bits) N/A A
N/A A A (32 bits) N/A A
N/A N/A N/A
A N/A N/A
A N/A A (32 bits) A A
A N/A N/A
Floating-point operation Power mode transition
A N/A
A A
A N/A
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1.5 Clock Interface
The VR4181 has the following eight clocks. * CLKX1, CLKX2 (input) These are oscillation inputs of 18.432 MHz, and used to generate operation clocks for the CPU core, serial interface, and other peripheral units. * RTCX1, RTCX2 (input) These are oscillation inputs of 32.768 kHz, and used for PMU, RTC, and so on. * PClock (internal) This clock is used to control the pipeline in the VR4110 core, and for units relating to the pipeline. This clock is generated from the clock input of CLKX1 and CLKX2 pins via the PLL. Its frequency is determined by CLKSEL(2:0) pins. * MasterOut (internal) This is a bus clock of the VR4110 core, and used for interrupt control. This clock operates in frequency of 1/4 of the TClock frequency. The contents of the CP0's Count register are incremented synchronously with this clock. * TClock (internal) This is an operation clock for internal MBA bus and is supplied to the internal MBA modules (memory controller, LCD controller, and DMA controller). This clock is generated from PClock and its frequency is 1/1, 1/2, or 1/3 of the PClock frequency (it is determined by internal register setting). It is set to 1/2 by default. * PCLK (internal) This clock is supplied to the internal ISA peripherals. This clock is generated from TClock and its frequency is determined by internal register setting. PCLK will operate only when accesses to the internal ISA bus occur. * SYSCLK (internal, output) This clock is used as the external ISA bus clock. It is also supplied to the internal CompactFlash controller. This clock is generated from PCLK and its frequency is determined by internal register setting. SYSCLK will operate only when accesses to the external ISA bus occur. * SDCLK (output) This clock is supplied to SDRAM. This clock operates in the same frequency as that of TClock. SDCLK will operate only when accesses to SDRAM occur.
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Figure 1-8 shows the external circuits of the clock oscillator. Figure 1-8. External Circuits of Clock Oscillator
(a) Crystal oscillation
VR4181 GND_OSC Note 1 External clock
(b) External clock
VR 4181
Note 1
Open Note 2
Note 2
Notes 1. CLKX1, RTCX1 2. CLKX2, RTCX2 Cautions 1. When using the clock oscillator, wire as follows in the area enclosed by the broken line in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as GND. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. Ensure that no load such as wiring capacity is applied to the CLKX2 or RTCX2 pin when inputting an external clock.
Figure 1-9 shows examples of the incorrect connection circuit of the resonator.
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Figure 1-9. Incorrect Connection Circuits of Resonator
(a) Connection circuit wiring is too long.
(b) There is another signal line crossing.
Note 1
Note 2 Note 3
Note 1
Note 2 Note 3
(c) A high fluctuating current flows near a signal line.
(d) A current flows over the ground line of the oscillator (The potentials of points A, B, and C change). VDD
Note 1 Large current
Note 2 Note 3 Note 1 Note 2 Note 3
A
B
C
(e) A signal is fetched.
Note 2
Note 1 Note 3
Notes 1. CLKX2, RTCX2 2. CLKX1, RTCX1 3. GND_OSC
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2.1 Pin Configuration
* 160-pin plastic LQFP (fine pitch) (24 x 24)
GND_AD GND_TP TPX0 TPX1 TPY0 TPY1 VDD_TP ADIN0 ADIN1 ADIN2 AUDIOIN VDD_AD AUDIOOUT IORDY/GPIO18 IOCS16#/GPIO19 RESET#/GPIO21 ROMCS3# ROMCS2#/GPIO24 ROMCS1#/GPIO23 ROMCS0#/GPIO22 SYSEN# SYSDIR MEMWR# MEMRD# GND_LOGIC VDD_LOGIC LDQM/LCAS# UDQM/UCAS# SDRAS# CAS# RAS0#/SDCS0# GND_IO VDD_IO RAS1#/SDCS1# CLKEN DATA0 DATA1 DATA2 DATA3 DATA4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
FPD0 FPD1 FPD2 FPD3 GPIO12/FPD4 GPIO13/FPD5 GPIO14/FPD6/CD1# GPIO15/FPD7/CD2# UBE#/GPIO20/M IOWR#/GPIO17 IORD#/GPIO16 FLM/MIPS16EN VDD_LOGIC GND_LOGIC LOCLK/MEMCS16# SHCLK/LCDCS# VPBIAS/VPGPIO0 VPLCD/VPGPIO1 VDD_IO GND_IO GPIO0/SI GPIO1/SO GPIO2/SCK GPIO3/PCS0# GPIO4 GPIO5/DCD2# GND_LOGIC GPIO6/RTS2# GPIO7/DTR2# GPIO8/DSR2# GPIO9/CTS2# GPIO10/FRM/SYSCLK GPIO11/PCS1# IRDOUT/TxD2 IRDIN/RxD2 RxD1/GPIO25 TxD1/GPIO26/CLKSEL0 RTS1#/GPIO27/CLKSEL1 CTS1#/GPIO28 DCD1#/GPIO29
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DTR1#/GPIO30/CLKSEL2 DSR1#/GPIO31 POWER RSTSW# RTCRST# POWERON MPOWER BATTINH/BATTINT# VDD_LOGIC GND_LOGIC CF_AEN#/SCANIN0 CF_DIR/SCANIN1 CF_DEN#/SCANIN2 CF_VCCEN#/SCANIN3 CF_IOIS16#/SCANIN4 CF_WAIT#/SCANIN5 CF_RESET/SCANIN6 CF_REG#/SCANIN7 VDD_IO GND_IO CF_BUSY#/SCANOUT0 CF_CE1#/SCANOUT1 CF_CE2#/SCANOUT2 CF_STSCHG#/SCANOUT3 CF_IOR#/SCANOUT4 CF_IOW#/SCANOUT5 CF_OE#/SCANOUT6 CF_WE#/SCANOUT7 LEDOUT GND_IO GND_IO VDD_PLL GND_PLL VDD_OSC CLKX1 CLKX2 RTCX2 RTCX1 GND_OSC GND_IO
Remark
# indicates active low.
50
DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 GND_IO VDD_IO SDCLK ADD0 ADD1 ADD2 ADD3 ADD4 ADD5 GND_LOGIC VDD_LOGIC ADD6 ADD7 ADD8 ADD9 ADD10 ADD11 GND_IO VDD_IO ADD12 ADD13 ADD14 ADD15 ADD16 ADD17 ADD18 ADD19 ADD20 ADD21
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
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Pin Identification
ADD(21:0) : ADIN(2:0) : AUDIOIN : AUDIOOUT : BATTINH : BATTINT# : CAS# : CD1#, CD2# : CF_AEN# : CF_BUSY# : CF_CE(2:1)# : CF_DEN# : CF_DIR : CF_IOIS16# : CF_IOR# : CF_IOW# : CF_OE# : CF_REG# : CF_RESET : CF_VCCEN# : CF_WAIT# : CF_WE# : CLKEN : CLKSEL(2:0) : Address Bus Analog Data Input Audio Input Audio Output Battery Inhibit Battery Interrupt Column Address Strobe Card Detect for CompactFlash Address Enable for CompactFlash Buffer Ready/Busy/Interrupt Request for CompactFlash Card Enable for CompactFlash Data Enable for CompactFlash Buffer Data Direction for CompactFlash Buffer I/O is 16 bits for CompactFlash I/O Read Strobe for CompactFlash I/O Write Strobe for CompactFlash Output Enable for CompactFlash Register Memory Access for CompactFlash Reset for CompactFlash VCC Enable for CompactFlash Wait Input for CompactFlash Write Enable for CompactFlash Clock Enable for SDRAM Clock Select LDQM : LEDOUT : LOCLK : M: MEMCS16# : MEMRD# : MEMWR# : MIPS16EN : MPOWER : PCS(1:0)# : POWER : POWERON : RAS(1:0)# : RESET# : ROMCS(3:0)# : RSTSW# : RTCRST# : Lower Byte Enable for SDRAM LED Output Load Clock for LCD LCD Modulation Clock Memory 16-bit Bus Sizing Memory Read Memory Write MIPS16 Enable Main Power Programmable Chip Select Power Switch Power On State Row Address Strobe for DRAM Reset Output Chip Select for ROM Reset Switch Real-time Clock Reset
RTCX1, RTCX2 : Real-time Clock Input RTS1#, RTS2# : Request to Send RxD1, RxD2 : SCANIN(7:0) : SCK : SDCLK : SDCS(1:0)# : SDRAS# : SHCLK : SI : SO : SYSCLK : SYSDIR : SYSEN# : TPX(1:0) : TPY(1:0) : TxD1, TxD2 : UBE# : UCAS# : UDQM : VDD_AD : VDD_IO : VDD_LOGIC : VDD_OSC : VDD_PLL : VDD_TP : VPBIAS : VPGPIO(1:0) : VPLCD : Receive Data Scan Data Input CSI (Clocked Serial Interface) Clock Operation Clock for SDRAM Chip Select for SDRAM Row Address Strobe for SDRAM Shift Clock for LCD Clocked Serial Data Input Clocked Serial Data Output System Clock for System Bus System Data Direction System Data Enable Touch Panel Data of X Touch Panel Data of Y Transmit Data Upper Byte Enable for System Bus Upper Column Address Strobe for DRAM Upper Byte Enable for SDRAM Power Supply for A/D and D/A Converter Power Supply for I/O Power Supply for Logic Power Supply for Oscillator Power Supply for PLL Power Supply for Touch Panel Bias Power Control for LCD General Purpose Output for LCD Panel Power Control Logic Power Control for LCD
CF_STSCHG# : Status Change of CompactFlash
SCANOUT(7:0) : Scan Data Output
CLKX1, CLKX2 : Clock Input CTS1#, CTS2# : Clear to Send DATA(15:0) : Data Bus DCD1#, DCD2# : Data Carrier Detect DSR1#, DSR2# : Data Set Ready DTR1#, DTR2# : Data Terminal Ready FLM : FPD(7:0) : FRM : GND_AD : GND_IO : GND_LOGIC : GND_OSC : GND_PLL : GND_TP : GPIO(31:0) : IOCS16# : IORD# : IORDY : IOWR# : IRDIN : IRDOUT : LCAS# : LCDCS# : First Line Clock for LCD Screen Data of LCD Clocked Serial Frame Ground for A/D and D/A Converter Ground for I/O Ground for Logic Ground for Oscillator Ground for PLL Ground for Touch Panel General Purpose I/O I/O 16-bit Bus Sizing I/O Read I/O Ready I/O Write IrDA Data Input IrDA Data Output Lower Column Address Strobe Chip Select for LCD
Remark # indicates active low.
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2.2 Pin Function Description
Remark # indicates active low.
2.2.1 System bus interface signals (1/2)
Signal name ADD(21:0)
Note
I/O Output
Description of function Address bus. Used to specify address for the DRAM, ROM, flash memory, or system bus (ISA). Data bus. Used to transmit and receive data between the VR4181 and DRAM, ROM, flash memory, or system bus. System bus I/O read signal output or general-purpose I/O. It is active when the VR4181 accesses the system bus to read data from an I/O port when configured as IORD#. System bus I/O write signal output or general-purpose I/O. It is active when the VR4181 accesses the system bus to write data to an I/O port when configured as IOWR#. System bus I/O channel ready input or general-purpose I/O. Set this signal as active when system bus controller is ready to be accessed by the VR4181 when configured as IORDY. Bus sizing request input for system bus I/O or general-purpose I/O. Set this signal as active when system bus I/O accesses data in 16-bit width, if configured as IOCS16#. System bus upper byte enable output, general-purpose input, or LCD modulation output. During system bus accesses, this signal is active when the high-order byte is valid on the data bus. System bus reset output or general-purpose I/O. It is active when the VR4181 resets the system bus controller when configured as RESET#.
DATA(15:0)
I/O
IORD#/GPIO16
I/O
IOWR#/GPIO17
I/O
IORDY/GPIO18
I/O
IOCS16#/GPIO19
I/O
UBE#/GPIO20/M
I/O
RESET#/GPIO21
I/O
Note The VR4181 utilizes different addressings depending on the types of the external accesses. During ROM accesses, bits 22 to 1 of the internal address lines are output to the ADD(21:0) pins (the minimum transfer data width is a half word (1 word = 32 bits)). During accesses other than ROM accesses, bits 21 to 0 of the internal address lines are output to the ADD(21:0) pins (the minimum transfer data width is 1 byte).
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(2/2)
Signal name SYSDIR
Note
I/O Output
Description of function Data bus isolation buffer direction control. This signal is valid only when ROM, ISA, or CompactFlash accesses are enabled. This becomes low level during ROM, ISA, or CompactFlash read cycle, or becomes high level during ROM, ISA, or CompactFlash write cycle. Data bus isolation buffer enable. This signal is valid only when ROM, ISA, or CompactFlash accesses are enabled. This becomes active during ROM or ISA cycle. SDRAM chip select for bank 0 and bank 1 or EDO DRAM row address strobes. SDRAM column address strobe. Leave unconnected when using EDO DRAM. SDRAM row address strobe. Leave unconnected when using EDO DRAM. SDRAM upper byte enable or EDO DRAM upper byte column address strobe. SDRAM lower byte enable or EDO DRAM lower byte column address strobe. SDRAM operating clock. SDRAM clock enable output (CKE). ROM chip select output for bank 3. ROM chip select output for bank 2, or general-purpose I/O. ROM chip select output for bank 1, or general-purpose I/O. ROM chip select output for bank 0, or general-purpose I/O. Memory read signal for ROM and system bus. Memory write signal for ROM, DRAM and system bus.
SYSEN#
Note
Output
SDCS(1:0)#/RAS(1:0)# CAS# SDRAS# UDQM/UCAS# LDQM/LCAS# SDCLK CLKEN ROMCS3# ROMCS2#/GPIO24 ROMCS1#/GPIO23 ROMCS0#/GPIO22 MEMRD# MEMWR#
Output Output Output Output Output Output Output Output I/O I/O I/O Output Output
Note The SYSEN# and SYSDIR signals control a buffer which is used to isolate SDRAM data bus from the bus of other low speed devices. By isolating the high-speed data bus of SDRAM, the load of the data bus between the VR4181 and SDRAM is reduced. When the EXBUFFEN bit of the XISACTL register is cleared to 0, the SYSEN# and SYSDIR signals start their operation. These signals keep low level until EXBUFFEN bit is cleared to 0 after a reset. When an isolation buffer is used, SYSEN# and SYSDIR signals function as follows;
SYSEN# 0 0 1 SYSDIR 0 1 Don't care Bus operation External ISA, CompactFlash, or ROM read cycle External ISA, CompactFlash, or flash memory mode write cycle External Buffer Disable DRAM read/write cycle or Hibernate mode
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2.2.2 LCD interface signals
Signal name SHCLK/LCDCS# LOCLK/MEMCS16# I/O Output I/O Description of function LCD shift clock output or chip select for external LCD controller. LCD load clock output or bus sizing request input for system bus memory access. When using as MEMCS16#, the external agent must activate this signal at the system bus memory access in 16-bit width. The function of this pin differs depending on the operating status. This signal enables use of MIPS16 instructions. 0: Disable use of MIPS16 instructions 1: Enable use of MIPS16 instructions LCD first line clock output. FPD(7:4)/GPIO(15:12) FPD(3:0)
Note Note
FLM/MIPS16EN
I/O
Output Output Output
See 2.2.11 General-purpose I/O signals in this section. LCD screen data. LCD logic power control. This signal may be defined as a general-purpose output when an external LCD controller is used. LCD bias power control. This signal may be defined as a general-purpose output when an external LCD controller is used.
VPLCD/VPGPIO1
VPBIAS/VPGPIO0
Output
Note Connection between FPD(7:0) of the VR4181 and LCD panel data lines differs depending on the panel data width as below. For details, refer to CHAPTER 21 LCD CONTROLLER.
VR4181 FPD0 FPD1 FPD2 FPD3 FPD4 FPD5 FPD6 FPD7 LCD Panel Data (4-bit width) Data Line 0 Data Line 1 Data Line 2 Data Line 3 - - - - LCD Panel Data (8-bit width) Data Line 4 Data Line 5 Data Line 6 Data Line 7 Data Line 0 Data Line 1 Data Line 2 Data Line 3
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2.2.3 Initialization interface signals
Signal name POWER RSTSW# RTCRST# I/O Input Input Input VR4181 activation signal. VR4181 reset signal. Reset signal for internal Real-time clock and internal logic. When power is first supplied to the system, the external agent must activate this signal. This signal indicates that the VR4181 is ready to operate. It becomes active when a power-on factor is detected and becomes inactive when the BATTINH/BATTINT# signal check has been completed. This signal indicates that the VR4181 is operating. This signal is inactive during Hibernate mode. During this signal being inactive, turn off the 2.5 V power supply. Description of function
POWERON
Output
MPOWER
Output
2.2.4 Battery monitor interface signals
Signal name BATTINH/BATTINT# I/O Input Description of function The function of this pin differs depending on the state of the MPOWER pin. BATTINH signal Enables or disables activation on power application. 1: Enable activation 0: Disable activation BATTINT# signal This is an interrupt signal that is input when remaining battery power is low during normal operations. The external agent checks the remaining battery power and activates this signal if voltage sufficient for operations cannot be supplied.
2.2.5 Clock interface signals
Signal name RTCX(2:1) CLKX(2:1) I/O - - Description of function Connections to 32.768 kHz crystal resonator. Connections to 18.432 MHz crystal resonator.
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2.2.6 Touch panel interface and audio interface signals
Signal name TPX(1:0) I/O I/O Description of function Touch panel X coordinate data. They use the voltage applied to the X coordinate and the voltage input to the Y coordinate to detect which coordinates on the touch panel are being pressed. Touch panel Y coordinate data. They use the voltage applied to the Y coordinate and the voltage input to the X coordinate to detect which coordinates on the touch panel are being pressed. General-purpose A/D data inputs. Audio input. Audio output.
TPY(1:0)
I/O
ADIN(2:0) AUDIOIN AUDIOOUT
Input Input Output
2.2.7 LED interface signals
Signal name LEDOUT I/O Output Description of function This is an output signal for lighting LEDs.
2.2.8 CompactFlash interface and keyboard interface signals
Signal name CF_WE#/SCANOUT7 CF_OE#/SCANOUT6 CF_IOW#/SCANOUT5 CF_IOR#/SCANOUT4 CF_STSCHG#/SCANOUT3 CF_CE(2:1)#/ SCANOUT(2:1) CF_BUSY#/SCANOUT0 I/O Output Output Output Output I/O Output Description of function CompactFlash write enable output or keyboard scan data output. CompactFlash output enable or keyboard scan data output. CompactFlash I/O write strobe output or keyboard scan data output. CompactFlash I/O read strobe output or keyboard scan data output. CompactFlash status changed input or keyboard scan data output. CompactFlash card enable outputs or keyboard scan data outputs.
I/O
CompactFlash ready/busy/interrupt request indication input or keyboard scan data output. CompactFlash register select output or keyboard scan data input. CompactFlash reset output or keyboard scan data input. CompactFlash wait input or keyboard scan data input. CompactFlash I/O 16-bit bus input or keyboard scan data input. CompactFlash VCC enable output or keyboard scan data input. CompactFlash data buffer enable output or keyboard scan data input. CompactFlash data direction control output or keyboard scan data input. CompactFlash address buffer enable output or keyboard scan data input.
CF_REG#/SCANIN7 CF_RESET/SCANIN6 CF_WAIT#/SCANIN5 CF_IOIS16#/SCANIN4 CF_VCCEN#/SCANIN3 CF_DEN#/SCANIN2 CF_DIR/SCANIN1 CF_AEN#/SCANIN0
I/O I/O Input Input I/O I/O I/O I/O
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2.2.9 Serial interface channel 1 signals
Signal name RxD1/GPIO25 TxD1/GPIO26/CLKSEL0 I/O I/O I/O Description of function Serial channel 1 receive data input or general-purpose I/O. The function of this pin differs depending on the operating status. Note This signal is used to set CPU core operation clock frequency . Serial channel 1 transmit data output or general-purpose I/O. RTS1#/GPIO27/CLKSEL1 I/O The function of this pin differs depending on the operating status. Note This signal is used to set CPU core operation clock frequency . Serial channel 1 request to send output or general-purpose I/O. CTS1#/GPIO28 DCD1#/GPIO29 DTR1#/GPIO30/CLKSEL2 I/O I/O I/O Serial channel 1 clear to send input or general-purpose I/O. Serial channel 1 data carrier detect input or general-purpose I/O. The function of this pin differs depending on the operating status. Note This signal is used to set CPU core operation clock frequency . Serial channel 1 data terminal ready output or general-purpose I/O. DSR1#/GPIO31 I/O Serial channel 1 Data set ready input or general-purpose I/O.
Note CLKSEL(2:0) signals are used to set the frequency of the CPU core operation clock (PClock). These signals are sampled when the RTCRST# signal goes high. The relationship between the CLKSEL(2:0) pin settings and clock frequency is shown below.
CLKSEL(2:0) 111 110 101 100 011 010 001 000 CPU core operation frequency (PClock) Reserved (98.1 MHz) Reserved (90.6 MHz) Reserved (84.1 MHz) Reserved (78.5 MHz) Reserved (69.3 MHz) 65.4 MHz 62.0 MHz 49.1 MHz
TClock is generated from PClock and its frequency is always 1/2 of the PClock frequency after RTC reset.
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2.2.10 IrDA interface signals
Signal name IRDIN/RxD2 I/O Input Description of function IrDA receive data input or serial channel 2 receive data input. Connect this pin to GND (digital) via resistor when an IrDA receive component is connected. IrDA transmit data output or serial channel 2 transmit data output.
IRDOUT/TxD2
Output
2.2.11 General-purpose I/O signals
Signal name GPIO(31:25) GPIO(24:16) GPIO15/FPD7/CD2# GPIO14/FPD6/CD1# GPIO13/FPD5 GPIO12/FPD4 GPIO11/PCS1# GPIO10/FRM/SYSCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O Description of function See 2.2.9 Serial interface channel 1 signals in this section See 2.2.1 System bus interface signals in this section. General-purpose I/O, LCD screen data output, or CompactFlash card detect 2 input. General-purpose I/O, LCD screen data output, or CompactFlash card detect 1 input. General-purpose I/O or LCD screen data output. General-purpose I/O or LCD screen data output. General-purpose I/O or programmable chip select 1. General-purpose I/O, serial frame input for clocked serial interface, or external bus system clock output. General-purpose I/O or serial channel 2 clear to send output. General-purpose I/O or serial channel 2 data set ready input. General-purpose I/O or serial channel 2 data terminal ready input. General-purpose I/O or serial channel 2 request to send output. General-purpose I/O or serial channel 2 data carrier detect input. General-purpose I/O. General-purpose I/O or programmable chip select 0. General-purpose I/O or serial clock input for clocked serial interface. General-purpose I/O or serial data output signal for clocked serial interface. General-purpose I/O or serial data input signal for clocked serial interface.
GPIO9/CTS2# GPIO8/DSR2# GPIO7/DTR2# GPIO6/RTS2# GPIO5/DCD2# GPIO4 GPIO3/PCS0# GPIO2/SCK GPIO1/SO GPIO0/SI
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
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2.2.12 Dedicated VDD/GND signals
Signal name Power supply 2.5 V 2.5 V 3.3 V 3.3 V 3.3 V Description of function
VDD_PLL GND_PLL VDD_TP GND_TP VDD_AD
Power supply dedicated for the PLL analog block. Ground dedicated for the PLL analog block. Power supply dedicated for the touch panel interface. Ground dedicated for the touch panel interface. Power supply dedicated for the A/D and D/A converters. The voltage applied to this pin becomes the maximum value for the A/D and D/A interface signals. Ground dedicated for the A/D and D/A converters. The voltage applied to this pin becomes the minimum value for the A/D and D/A interface signals. Power supply dedicated for the oscillator. Ground dedicated for the oscillator. Ordinary power supply of 2.5 V Ordinary ground of 2.5 V Ordinary power supply of 3.3 V Ordinary ground of 3.3 V
GND_AD
3.3 V
VDD_OSC GND_OSC VDD_LOGIC GND_LOGIC VDD_IO GND_IO
3.3 V 3.3 V 2.5 V 2.5 V 3.3 V 3.3 V
Caution
The VR4181 has two types of power supplies. The 3.3 V power supply should be turned on at first. Turn on/off the 2.5 V power supply depending on the status of the MPOWER pin.
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2.3 Pin Status in Specific Status
(1/3)
Signal Name During RTC Reset After RTC Reset After Reset by Deadman's Switch or RSTSW 0 Hi-Z 1 1 1 1 1 1 1 0 1 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1 0/1 0/- 0 0 Hi-Z Hi-Z - - - During Suspend Mode During Hibernate Mode or Shutdown by HALTimer 0 Hi-Z Hi-Z 1 1/0 1/0 1/0
Note2
ADD(21:0) DATA(15:0) MEMRD# MEMWR# SDCS(1:0)#/RAS(1:0)# UDQM/UCAS# LDQM/LCAS# CAS# SDRAS# SDCLK CLKEN SYSDIR SYSEN# IORD#/GPIO16 IOWR#/GPIO17 IORDY/GPIO18 IOCS16#/GPIO19 UBE#/GPIO20/M RESET#/GPIO21 ROMCS(2:0)#/GPIO(24:22) ROMCS3# SHCLK/LCDCS# LOCLK/MEMCS16# FLM/MIPS16EN FPD(3:0) VPLCD/VPGPIO1 VPBIAS/VPGPIO0 POWER RTCRST# RSTSW#
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z - - - - - - - Hi-Z Hi-Z Hi-Z Note 4 Hi-Z Hi-Z Hi-Z - - -
0 Hi-Z 1 1 1 1 1 1 1 Run 1 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 0 0 0 Hi-Z Hi-Z - - -
Note 1 Hi-Z 1 1 1/0 1/0 1/0
Note2
Note2
Note2
Note2
Note2
0 0 0 1 0 0 1/Note 1 1/Note 1 Note 1 Note 1 1/Note 1/0 Note 1 1/Note 1 1 0/1 0/- 0 0 Hi-Z Hi-Z - - -
0 0 0 0 0 0 Hi-Z/Note 3 Hi-Z/Note 3 Note 3 Note 3 Hi-Z/Note 3/0 0/Note 3 Hi-Z/Note 3 Hi-Z 0/Hi-Z 0/- 0 0 Hi-Z Hi-Z - - -
Notes1. Maintains the state of the previous Fullspeed mode. 2. The state depends on the MEMCFG_REG register setting. 3. The state depends on the GPHIBSTH/GPHIBSTL register setting. 4. The input level is sampled to determine the MIPS16 instruction mode. Remark 0: low level, 1: high level, Hi-Z: high impedance
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Signal Name During RTC Reset After RTC Reset After Reset by Deadman's Switch or RSTSW 0 1 - - - 1 Hi-Z - - 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z During Suspend Mode During Hibernate Mode or Shutdown by HALTimer 0 0 - - - 1 Hi-Z - - 0 Note 2/Hi-Z Note 2/Hi-Z Note 2/Hi-Z Note 2/Hi-Z Note 1/Hi-Z Note 2/Hi-Z
POWERON MPOWER BATTINH/BATTINT# RTCX2, RTCX1 CLKX2, CLKX1 TPX(1:0) TPY(1:0) ADIN(2:0) AUDIOIN AUDIOOUT CF_WE#/SCANOUT7 CF_OE#/SCANOUT6 CF_IOW#/SCANOUT5 CF_IOR#/SCANOUT4 CF_STSCHG#/SCANOUT3 CF_CE(2:1)#/ SCANOUT(2:1) CF_BUSY#/SCANOUT0 CF_REG#/SCANIN7 CF_RESET/SCANIN6 CF_WAIT#/SCANIN5 CF_IOIS16#/SCANIN4 CF_VCCEN#/SCANIN3 CF_DEN#/SCANIN2 CF_DIR/SCANIN1 CF_AEN#/SCANIN0
- 0 - - - - - - - - Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
- 0 - - - 1 Hi-Z - - 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
0 1 - - - Note 1 Note 1 - - Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
Hi-Z Hi-Z Hi-Z - - Hi-Z Hi-Z Hi-Z Hi-Z
Hi-Z - - - - - - - -
Hi-Z Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
Note 1/Hi-Z Note 2/Note 1 Note 3/Note 1 - - Note 4/Note 1 1/Note 1 1/Note 1 1/Note 1
Notes1. Maintains the state of the previous Fullspeed mode. 2. When CF wake-up is enabled: Outputs high level. When CF wake-up is disabled: Becomes high impedance. 3. When CF wake-up is enabled: Outputs low level. When CF wake-up is disabled: Becomes high impedance. 4. When CF wake-up is enabled: Outputs low level. When CF wake-up is disabled: Outputs high level. Remark 0: low level, 1: high level, Hi-Z: high impedance
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(3/3)
Signal Name During RTC Reset After RTC Reset After Reset by Deadman's Switch or RSTSW Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z - 1 Hi-Z During Suspend Mode During Hibernate Mode or Shutdown by HALTimer Note 1/Note 2 Note 1/Note 2 Note 1/Note 2 Note 1/Note 2 Note 1/Note 2 Note 1/Note 2 Note 1/Note 2 - Hi-Z Note 2/Note 1
RxD1/GPIO25 TxD1/GPIO26/CLKSEL0 RTS1#/GPIO27/CLKSEL1 CTS1#/GPIO28 DCD1#/GPIO29 DTR1#/GPIO30/CLKSEL2 DSR1#/GPIO31 IRDIN/RxD2 IRDOUT/TxD2 GPIO(15:14)/FPD(7:6)/ CD(2:1)# GPIO(13:12)/FPD(5:4) GPIO11/PCS1# GPIO10/FRM/SYSCLK
- Note 3 Note 3 - - Note 3 - - Hi-Z - - - /Hi-Z - /Hi-Z - - - - - - - /Hi-Z - - - Hi-Z
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z - Hi-Z Hi-Z
Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 - Note 1 Note 1/0/ Note 1 Note 1/0 Note 1/1 Note 1/0
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z/1 Hi-Z
Note 2/Note 1 Note 2/Hi-Z Note 2/Note 1/ Hi-Z
GPIO9/CTS2# GPIO8/DSR2# GPIO7/DTR2# GPIO6/RTS2# GPIO5/DCD2# GPIO4 GPIO3/PCS0# GPIO2/SCK GPIO1/SO GPIO0/SI LEDOUT
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 1
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z/1 Hi-Z Hi-Z Hi-Z Note 1
Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1/1 Note 1 Note 1 Note 1 Note 1
Note 2/Note 1 Note 2/Note 1 Note 2/Note 1 Note 2/Note 1 Note 2/Note 1 Note 2 Note 2/Hi-Z Note 2/Note 1 Note 2/Note 1 Note 2/Note 1 Note 1
Notes1. Maintains the state of previous Fullspeed mode. 2. The state depends on the GPHIBSTH/GPHIBSTL register setting. 3. The input level is sampled to determine the CPU core operation frequency. Remark 0: low level, 1: high level, Hi-Z: high impedance
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2.4 Recommended Connection of Unused Pins and I/O Circuit Types
(1/3)
Pin Name ADD(21:0) DATA(15:0) MEMRD# MEMWR# SDCS(1:0)#/RAS(1:0)# UDQM/UCAS# LDQM/LCAS# CAS# SDRAS# SDCLK CLKEN SYSDIR SYSEN# IORD#/GPIO16 IOWR#/GPIO17 IORDY/GPIO18 IOCS16#/GPIO19 UBE#/GPIO20/M RESET#/GPIO21 ROMCS(2:0)#/GPIO(24:22) ROMCS3# SHCLK/LCDCS# LOCLK/MEMCS16# FLM/MIPS16EN FPD(3:0) VPLCD/VPGPIO1 VPBIAS/VPGPIO0 POWER RTCRST# RSTSW# POWERON MPOWER BATTINH/BATTINT# TPX(1:0) TPY(1:0) Leave open - - - - Leave open Leave open Connect to VDD_IO or GND_IO via resistor Leave open Leave open Leave open Connect to GND_IO via resistor - - Leave open Leave open Leave open Leave open Leave open Leave open Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor - Recommended Connection When Not Used - - - - - - - I/O Circuit Type A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A B C
Remark No specification (-) in the Recommended Connection When Not Used column indicates that the pin is always connected.
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Pin Name ADIN(2:0) AUDIOIN AUDIOOUT CF_WE#/SCANOUT7 CF_OE#/SCANOUT6 CF_IOW#/SCANOUT5 CF_IOR#/SCANOUT4 CF_STSCHG#/SCANOUT3 CF_CE(2:1)#/SCANOUT(2:1) CF_BUSY#/SCANOUT0 CF_REG#/SCANIN7 CF_RESET/SCANIN6 CF_WAIT#/SCANIN5 CF_IOIS16#/SCANIN4 CF_VCCEN#/SCANIN3 CF_DEN#/SCANIN2 CF_DIR/SCANIN1 CF_AEN#/SCANIN0 RxD1/GPIO25 TxD1/GPIO26/CLKSEL0 RTS1#/GPIO27/CLKSEL1 CTS1#/GPIO28 DCD1#/GPIO29 DTR1#/GPIO30/CLKSEL2 DSR1#/GPIO31 IRDIN/RxD2 IRDOUT/TxD2 GPIO(15:14)/FPD(7:6)/CD(2:1)# GPIO(13:12)/FPD(5:4) GPIO11/PCS1# GPIO10/FRM/SYSCLK GPIO9/CTS2# GPIO8/DSR2# GPIO7/DTR2# GPIO6/RTS2# GPIO5/DCD2# GPIO4 Recommended Connection When Not Used Connect to GND_AD Connect to GND_AD Leave open Leave open Leave open Leave open Leave open Connect to VDD_IO via resistor Leave open Connect to VDD_IO via resistor Leave open Leave open Connect to VDD_IO via resistor Connect to VDD_IO via resistor Leave open Leave open Leave open Leave open Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Leave open Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor I/O Circuit Type D D E A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
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Pin Name GPIO3/PCS0# GPIO2/SCK GPIO1/SO GPIO0/SI LEDOUT Recommended Connection When Not Used Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Connect to VDD_IO or GND_IO via resistor Leave open I/O Circuit Type A A A A A
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2.5 Pin I/O Circuits
Type A VDD Data P-ch IN/OUT Output disable Output disable P-ch Input enable Type B VDD Data P-ch IN/OUT Input enable N-ch + - Vref N-ch Data Type C VDD P-ch IN/OUT
N-ch
N-ch
Output disable P-ch + - Vref N-ch
N-ch Type D IN P-ch N-ch Vref Type E Analog output voltage OUT + -
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3.1 Coprocessor 0 (CP0)
The Coprocessor 0 (CP0), which is also called as System Control Coprocessor, is implemented as an integral part of the CPU, and supports memory management, address translation, exception handling, and operation mode control. Memory management, address translation, and operation mode control are provided by a block called memory management unit (MMU). The MMU contains a 32-entry TLB (translation lookaside buffer) that is used when translating virtual addresses to physical addresses. The CP0 has registers shown in Table 3-1 that are used to set various modes for memory management and exception handling and to indicate statuses of the processor. Each CP0 register has a unique number that is used as an operand to specify a CP0 register to be accessed. Caution When accessing the CP0 registers, some instructions require consideration of the interval time until the next instruction is executed, because there is a delay from when the contents of the CP0 register change to when this change is reflected in the CPU operation. This time lag is called a CP0 hazard. For details, refer to CHAPTER 23 COPROCESSOR 0 HAZARDS. For details about functions of the CP0, refer to VR4100 Series Architecture User's Manual.
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Table 3-1. CP0 Registers
Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 to 25 26 27 28 29 30 31 Index Random EntryLo0 EntryLo1 Context PageMask Wired - BadVAddr Count EntryHi Compare Status Cause EPC PRId Config LLAddr
Note1
Register
Usage Memory management Memory management Memory management Memory management Exception processing Memory management Memory management - Exception processing Exception processing Memory management Exception processing Exception processing Exception processing Exception processing Memory management Memory management Memory management Exception processing Exception processing Exception processing
Description Programmable pointer to TLB array Pseudo-random pointer to TLB array (read only) Lower half of TLB entry for even VPN Lower half of TLB entry for odd VPN Pointer to kernel virtual PTE in 32-bit mode Page size specification Number of wired TLB entries Reserved for future use Virtual address where the most recent error occurred Timer count Higher half of TLB entry (including ASID) Timer compare value Status indication Cause of last exception Exception Program Counter Processor revision identifier Configuration (memory system modes) specification Physical address for self diagnostics Memory reference trap address low bits Memory reference trap address high bits Pointer to kernel virtual PTE in 64-bit mode Reserved for future use Cache parity bits Index and status of cache error Lower half of cache tag Higher half of cache tag Error Exception Program Counter Reserved for future use
WatchLo WatchHi XContext - Parity Error
Note2
- Exception processing Exception processing Memory management Memory management Exception processing
Cache Error Note2 TagLo TagHi ErrorEPC -
-
Notes1. This register is defined to maintain compatibility with the VR4000 and VR4400. This register is meaningless during normal operations. 2. This register is defined to maintain compatibility with the VR4100. This register is not used in the VR4181 hardware.
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3.2 Details of CP0 Registers
3.2.1 Index register (0) The Index register is a 32-bit, read/write register containing five low-order bits to index an entry in the TLB. The most-significant bit of the register shows the success or failure of a TLB probe (TLBP) instruction. The Index register also specifies the TLB entry affected by TLB read (TLBR) or TLB write index (TLBWI) instructions. The contents of the Index register are undefined after a reset so that it must be initialized by software. Figure 3-1. Index Register
31 30 P 0
5
4 Index
0
P: Index: 0:
Indicates whether probing is successful or not. It is set to 1 if the latest TLBP instruction fails. It is cleared to 0 when the TLBP instruction is successful. Specifies an index to a TLB entry that is a target of the TLBR or TLBWI instruction. Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
3.2.2 Random register (1) The Random register is a read-only register. The low-order 5 bits are used in referencing a TLB entry. This register is decremented each time an instruction is executed. The values that can be set in the register are as follows: * The lower bound is the content of the Wired register. * The upper bound is 31. The Random register specifies the entry in the TLB that is affected by the TLBWR instruction. The register is readable to verify proper operation of the processor. The Random register is set to the value of the upper bound upon Cold Reset. This register is also set to the upper bound when the Wired register is written. Figure 3-2 shows the format of the Random register. Figure 3-2. Random Register
31 0
5
4 Random
0
Random: TLB random index 0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
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3.2.3 EntryLo0 (2) and EntryLo1 (3) registers The EntryLo register consists of two registers that have identical formats: EntryLo0, used for even virtual pages and EntryLo1, used for odd virtual pages. The EntryLo0 and EntryLo1 registers are both read-/write-accessible. They are used to access the built-in TLB. When a TLB read/write operation is carried out, the EntryLo0 and EntryLo1 registers hold the contents of the low-order 32 bits of TLB entries at even and odd addresses, respectively. The contents of these registers are undefined after a reset so that they must be initialized by software. Figure 3-3. EntryLo0 and EntryLo1 Registers
(a) 32-bit mode
31 EntryLo0 0 28 27 PFN 6 5 C 3 2 D 1 V 0 G
31 EntryLo1 0
28 27 PFN
6
5 C
3
2 D
1 V
0 G
(b) 64-bit mode
63 EntryLo0 0 28 27 PFN 6 5 C 3 2 D 1 V 0 G
63 EntryLo1 0
28 27 PFN
6
5 C
3
2 D
1 V
0 G
PFN: C: D: V: G: 0:
Page frame number; high-order bits of the physical address. Specifies the TLB page attribute (see Table 3-2). Dirty. If this bit is set to 1, the page is marked as dirty and, therefore, writable. This bit is actually a write-protect bit that software can use to prevent alteration of data. Valid. If this bit is set to 1, it indicates that the TLB entry is valid; otherwise, a TLB Invalid exception (TLBL or TLBS) occurs. Global. If this bit is set in both EntryLo0 and EntryLo1, then the processor ignores the ASID during TLB lookup. Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
The coherency attribute (C) bits are used to specify whether to use the cache in referencing a page. When the cache is used, whether the page attribute is "cached" or "uncached" is selected by algorithm. Table 3-2 lists the page attributes selected according to the value in the C bits.
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Table 3-2. Cache Algorithm
C bit value 0 1 2 3 4 5 6 7 Cached Cached Uncached Cached Cached Cached Cached Cached Cache algorithm
3.2.4 Context register (4) The Context register is a read/write register containing the pointer to an entry in the page table entry (PTE) array on the memory; this array is a table that stores virtual-to-physical address translations. When there is a TLB miss, the operating system loads the unsuccessfully translated entry from the PTE array to the TLB. The Context register is used by the TLB Refill exception handler for loading TLB entries. The Context register duplicates some of the information provided in the BadVAddr register, but the information is arranged in a form that is more useful for a software TLB exception handler. Figure 3-4. Context Register
(a) 32-bit mode
31 PTEBase 25 24 BadVPN2 4 3 0 0
(b) 64-bit mode
63 PTEBase 25 24 BadVPN2 4 3 0 0
PTEBase: The PTEBase field is a base address of the PTE entry table. BadVPN2: This field holds the value (VPN2) obtained by halving the virtual page number of the most recent virtual address for which translation failed. 0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
The PTEBase field is used by software as the pointer to the base address of the PTE table in the current user address space. The 21-bit BadVPN2 field contains bits 31 to 11 of the virtual address that caused the TLB miss; bit 10 is excluded because a single TLB entry maps to an even-odd page pair. For a 1 KB page size, this format can directly address the pair-table of 8-byte PTEs. When the page size is 4 KB or more, shifting or masking this value produces the correct PTE reference address.
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3.2.5 PageMask register (5) The PageMask register is a read/write register used for reading from or writing to the TLB; it holds a comparison mask that sets the page size for each TLB entry, as shown in Table 3-3. Five page sizes can be selected between 1 KB and 256 KB. TLB read and write instructions use this register as either a source or a destination; Bits 18 to 11 that are targets of comparison are masked during address translation. The contents of the PageMask register are undefined after a reset so that it must be initialized by software. Figure 3-5. PageMask Register
31 0
19 18 MASK
11 10 0
0
MASK: 0:
Page comparison mask, which determines the virtual page size for the corresponding entry. Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
Table 3-3 lists the mask pattern for each page size. If the mask pattern is one not listed below, the TLB behaves unexpectedly. Table 3-3. Mask Values and Page Sizes
Page size 18 1 KB 4 KB 16 KB 64 KB 256 KB 0 0 0 0 1 17 0 0 0 0 1 16 0 0 0 1 1 15 0 0 0 1 1 Bit 14 0 0 1 1 1 13 0 0 1 1 1 12 0 1 1 1 1 11 0 1 1 1 1
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3.2.6 Wired register (6) The Wired register is a read/write register that specifies the lower boundary of the random entry of the TLB as shown in Figure 3-6. Wired entries cannot be overwritten by a TLBWR instruction, but by a TLBWI instruction. Random entries can be overwritten by both instructions. Figure 3-6. Positions Indicated by the Wired Register
TLB 31
Range specified by the Random register
Value in the Wired register Range of Wired entries 0
The Wired register is set to 0 upon Cold Reset. Writing this register also sets the Random register to the value of its upper bound (see 3.2.2 Random register (1)). Figure 3-7. Wired Register
31 0
54 Wired
0
Wired: 0:
TLB wired boundary Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
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3.2.7 BadVAddr register (8) The Bad Virtual Address (BadVAddr) register is a read-only register that saves the most recent virtual address that failed to have a valid translation, or that had an addressing error. Caution This register saves no information after a bus error exception, because it is not an address error exception. Figure 3-8. BadVAddr Register
(a) 32-bit mode
31 BadVAddr 0
(b) 64-bit mode
63 BadVAddr 0
BadVAddr: Most recent virtual address for which an addressing error occurred, or for which address translation failed.
3.2.8 Count register (9) The read/write Count register acts as a timer. It is incremented in synchronization with the MasterOut clock (1/8, 1/12, or 1/16 frequencies of the PClock), regardless of whether instructions are being executed, retired, or any forward progress is actually made through the pipeline. This register is a free-running type. When the register reaches all ones, it rolls over to zero and continues counting. This register is used for self-diagnostic test, system initialization, or the establishment of inter-process synchronization. Figure 3-9. Count Register
31 Count
0
Count:
Up-to-date count value that is compared with the value of the Compare register.
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3.2.9 EntryHi register (10) The EntryHi register is write-accessible. It is used to access the built-in TLB. The EntryHi register holds the highorder bits of a TLB entry for TLB read and write operations. If a TLB Refill, TLB Invalid, or TLB Modified exception occurs, the EntryHi register holds the high-order bit of the TLB entry. The EntryHi register is also set with the virtual page number (VPN2) for a virtual address where an exception occurred and the ASID. Architecture User's Manual for details of the TLB exception. The ASID is used to read from or write to the ASID field of the TLB entry. It is also checked with the ASID of the TLB entry as the ASID of the virtual address during address translation. The EntryHi register is accessed by the TLBP, TLBWR, TLBWI, and TLBR instructions. The contents of the EntryHi register are undefined after a reset so that it must be initialized by software. Figure 3-10. EntryHi Register See VR4100 Series
(a) 32-bit mode
31 VPN2 11 10 0 8 7 ASID 0
(b) 64-bit mode
63 R 62 61 Fill 40 39 VPN2 11 10 0 87 ASID 0
VPN2: ASID: R: Fill: 0:
Virtual page number divided by two (mapping to two pages) Address space ID. An 8-bit ASID field that allows multiple processes to share the TLB; each process has a distinct mapping of otherwise identical virtual page numbers. Space type (00 user, 01 supervisor, 11 kernel). Matches bits 63 and 62 of the virtual address. Reserved. Ignored on write. When read, returns zero. Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
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3.2.10 Compare register (11) The Compare register causes a timer interrupt; it maintains a stable value that does not change on its own. When the value of the Count register (see 3.2.8 Count register (9)) equals the value of the Compare register, the IP7 bit in the Cause register is set. This causes an interrupt as soon as the interrupt is enabled. Writing a value to the Compare register, as a side effect, clears the timer interrupt request. For diagnostic purposes, the Compare register is a read/write register. Normally, this register should be only used for a write. The contents of the Compare register are undefined after a reset. Figure 3-11. Compare Register
31 Compare
0
Compare: Value that is compared with the count value of the Count register.
3.2.11 Status register (12) The Status register is a read/write register that contains the operating mode, interrupt enabling, and the diagnostic states of the processor. Figure 3-12. Status Register (1/2)
31 0
29 28 27 26 25 24 CU0 0 RE DS
16 15 IM
8
7
6
5
4
3
2
1
0
KX SX UX
KSU
ERL EXL IE
CU0: RE: DS: IM:
Enables/disables the use of the coprocessor (1 Enabled, 0 Disabled). CP0 can be used in Kernel mode at all times. Enables/disables reversing of the endian setting in User mode (0 Disabled, 1 Enabled). This bit must be set to 0 since the VR4181 supports the little-endian order only. Diagnostic Status field (see Figure 3-13). Interrupt mask field used to enable/disable interrupts (0 Disabled, 1 Enabled). This field consists of 8 bits that are used to control eight interrupts. The bits are assigned to interrupts as follows: IM7: IM(6:2): IM(1:0): Masks a timer interrupt. Mask ordinary interrupts (Int(4:0) Mask software interrupts.
Note
). However, Int(4:3)
Note
never occur in the VR4181.
Note Int(4:0) are internal signals of the VR4110 CPU core. For details about connection to the on-chip peripheral units, refer to CHAPTER 9 (ICU). INTERRUPT CONTROL UNIT
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Figure 3-12. Status Register (2/2)
KX: SX: UX: KSU: ERL: EXL: IE: 0:
Enables 64-bit addressing in Kernel mode (0 32-bit, 1 64-bit). 64-bit operations are always valid in Kernel mode. Enables 64-bit addressing and operation in Supervisor mode (0 32-bit, 1 64-bit). Enables 64-bit addressing and operation in User mode (0 32-bit, 1 64-bit). Sets and indicates the operating mode (10 User, 01 Supervisor, 00 Kernel). Sets and indicates the error level (0 Normal, 1 Error). Sets and indicates the exception level (0 Normal, 1 Exception). Sets and indicates interrupt enabling/disabling (0 Disabled, 1 Enabled). Reserved for future use. Write 0 in a write operation. When this bit is read, 0 is read.
Figure 3-13 shows the details of the Diagnostic Status (DS) field. All DS field bits other than the TS bit are writable. Figure 3-13. Status Register Diagnostic Status Field
24 0
23
22 BEV
21 TS
20 SR
19 0
18 CH
17 CE
16 DE
BEV: TS:
Specifies the base address of a TLB Refill exception vector and common exception vector (0 Normal, 1 Bootstrap). Occurs the TLB to be shut down (read-only) (0 Not shut down, 1 Shut down). This bit is used to avoid any problems that may occur when multiple TLB entries match the same virtual address. After the TLB has been shut down, reset the processor to enable restart. Note that the TLB is shut down even if a TLB entry matching a virtual address is marked as being invalid (with the V bit cleared).
SR: CH: CE, DE: 0:
Occurs a Soft Reset or NMI exception (0 Not occurred, 1 Occurred). CP0 condition bit (0 False, 1 True). This bit can be read and written by software only; it cannot be accessed by hardware. These are prepared to maintain compatibility with the VR4100, and are not used in the VR4181 hardware. Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
The Status register has the following fields where the modes and access statuses are set.
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(1) Interrupt enable Interrupts are enabled when all of the following conditions are true: * IE bit is set to 1. * EXL bit is cleared to 0. * ERL bit is cleared to 0. * The appropriate bit of the IM field is set to 1. (2) Operating modes The following Status register bit settings are required for User, Kernel, and Supervisor modes. * The processor is in User mode when KSU = 10, EXL = 0, and ERL = 0. * The processor is in Supervisor mode when KSU = 01, EXL = 0, and ERL = 0. * The processor is in Kernel mode when KSU = 00, EXL = 1, or ERL = 1. Access to the kernel address space is allowed when the processor is in Kernel mode. Access to the supervisor address space is allowed when the processor is in Supervisor or Kernel mode. Access to the user address space is allowed in any of the three operating modes. (3) Addressing modes The following Status register bit settings select 32- or 64-bit operation for each of User, Kernel, and Supervisor operating modes. Enabling 64-bit operation permits the execution of 64-bit opcodes and translation of 64-bit addresses. 64-bit operation for User, Kernel and Supervisor modes can be set independently. * 64-bit addressing for Kernel mode is enabled when KX bit = 1. 64-bit operations are always valid in Kernel mode. If this bit is set, an XTLB Refill exception occurs if a TLB miss occurs in the Kernel mode address space. * 64-bit addressing and operations are enabled for Supervisor mode when SX bit = 1. If this bit is set, an XTLB Refill exception occurs if a TLB miss occurs in the Supervisor mode address space. * 64-bit addressing and operations are enabled for User mode when UX bit = 1. If this bit is set, an XTLB Refill exception occurs if a TLB miss occurs in the User mode address space. (4) Status after reset The contents of the Status register are undefined after Cold Resets, except for the following bits in the Diagnostic Status field. * TS and SR bits are cleared to 0. SR bit is 0 after Cold Reset, and is 1 after Soft Reset or NMI. * ERL and BEV bits are set to 1. Remark Cold Reset and Soft Reset are resets for the CPU core (see 5.3 Reset of CPU Core). For the reset of all the VR4181 including peripheral units, refer to CHAPTER 5 INTERFACE and CHAPTER 10 POWER MANAGEMENT UNIT (PMU). INITIALIZATION
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3.2.12 Cause register (13) The 32-bit read/write Cause register holds the cause of the most recent exception. A 5-bit exception code indicates one of the causes (see Table 3-4). Other bits hold the detailed information of the specific exception. All bits in the Cause register, with the exception of the IP1 and IP0 bits, are read-only; IP1 and IP0 bits are used for software interrupts. Figure 3-14. Cause Register
31 30 29 28 27 BD 0 CE 0
16 15 IP(7:0)
8
7 0
6
2
1 0
0
ExcCode
BD: CE: IP:
Indicates whether the most recent exception occurred in the branch delay slot (1 In delay slot, 0 Normal). Indicates the coprocessor number in which a Coprocessor Unusable exception occurred. This field will remain undefined for as long as no exception occurs. Indicates whether an interrupt is pending (1 Interrupt pending, 0 No interrupt pending). IP7: IP(6:2): IP(1:0): A timer interrupt. Ordinary interrupts (Int(4:0) to 1 by means of software. Note Int(4:0) are internal signals of the VR4110 CPU core. For details about connection to the on-chip peripheral units, refer to CHAPTER 9 (ICU). INTERRUPT CONTROL UNIT
Note
). However, Int(4:3)
Note
never occurs in the VR4181.
Software interrupts. Only these bits cause an interrupt exception, when they are set
ExcCode: Exception code field (refer to Table 3-4 for details). 0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
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Table 3-4. Cause Register Exception Code Field
Exception code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 to 22 23 24 to 31 Int Mod TLBL TLBS AdEL AdES IBE DBE Sys Bp RI CpU Ov Tr WATCH Mnemonic Interrupt exception TLB Modified exception TLB Refill exception (load or fetch) TLB Refill exception (store) Address Error exception (load or fetch) Address Error exception (store) Bus Error exception (instruction fetch) Bus Error exception (data load or store) System Call exception Breakpoint exception Reserved Instruction exception Coprocessor Unusable exception Integer Overflow exception Trap exception Reserved for future use Watch exception Reserved for future use Description
The VR4181 has eight interrupt request sources, IP7 to IP0. They are used for the purpose as follows. For the detailed description of interrupts of the CPU core, refer to VR4100 Series Architecture User's Manual. (1) IP7 This bit indicates whether there is a timer interrupt request. It is set when the values of the Count register and Compare register match. (2) IP6 to IP2 IP6 to IP2 reflect the state of the interrupt request signals of the CPU core. (3) IP1 and IP0 These bits are used to set/clear a software interrupt request.
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3.2.13 Exception Program Counter (EPC) register (14) The Exception Program Counter (EPC) is a read/write register that contains the address at which processing resumes after an exception has been serviced. The contents of this register change depending on whether Setting the MIPS16EN pin after RTC reset specifies execution of MIPS16 instructions is enabled or disabled.
whether execution of the MIPS16 instructions is enabled or disabled. When the MIPS16 instruction execution is disabled, either of the following addresses is contained in the EPC register: * Virtual address of the instruction that caused the exception * Virtual address of the immediately preceding branch or jump instruction (when the instruction associated with the exception is in a branch delay slot, and the BD bit in the Cause register is set to 1) When the MIPS16 instruction execution is enabled, either of the following addresses is contained in the EPC register during a 32-bit instruction execution: * Virtual address of the instruction that caused the exception and ISA mode at which an exception occurs * Virtual address of the immediately preceding branch or jump instruction and ISA mode at which an exception occurs (when the instruction associated with the exception is in a branch delay slot of the jump instruction, and the BD bit in the Cause register is set to 1) When the 16-bit instruction is executed, either of the following addresses is contained in the EPC register: * Virtual address of the instruction that caused the exception and ISA mode at which an exception occurs * Virtual address of the immediately preceding Extend or jump instruction and ISA mode at which an exception occurs (when the instruction associated with the exception is in a branch delay slot of the jump instruction or in the instruction following the Extend instruction, and the BD bit in the Cause register is set to 1) The EXL bit in the Status register is set to 1 to keep the processor from overwriting the address of the exceptioncausing instruction contained in the EPC register in the event of another exception. The EPC register never indicates the address of the instruction in a branch delay slot. Figure 3-15. EPC Register (When MIPS16 ISA Is Disabled)
(a) 32-bit mode
31 EPC 0
(b) 64-bit mode
63 EPC 0
EPC:
Restart address (virtual) after exception processing.
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Figure 3-16. EPC Register (When MIPS16 ISA Is Enabled)
(a) 32-bit mode
31 EPC 1 0 EIM
EPC: EIM:
Bits 31 to 1 of restart address (virtual) after exception processing. ISA mode at which an exception occurs (1 When MIPS16 SIA instruction is executed, 0 When MIPS III ISA instruction is executed).
(b) 64-bit mode
63 EPC 1 0 EIM
EPC: EIM:
Bits 63 to 1 of restart address (virtual) after exception processing. ISA mode at which an exception occurs (1 When MIPS16 SIA instruction is executed, 0 When MIPS III ISA instruction is executed).
3.2.14 Processor Revision Identifier (PRId) register (15) The 32-bit, read-only Processor Revision Identifier (PRId) register contains information identifying the implementation and revision level of the CPU and CP0. Figure 3-17. PRId Register
31 0
16 15 Imp
8
7 Rev
0
Imp: Rev: 0:
CPU core processor ID number (0x0C for the VR4181) CPU core processor revision number Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
The processor revision number is stored as a value in the form y.x, where y is a major revision number in bits 7 to 4 and x is a minor revision number in bits 3 to 0. The processor revision number can distinguish CPU core revisions of the VR4181, however there is no guarantee that changes to the CPU core will necessarily be reflected in the PRId register, or that changes to the revision number necessarily reflect real CPU core changes. Therefore, create a program that does not depend on the processor revision number field.
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3.2.15 Config register (16) The Config register specifies various configuration options selected on the VR4181. Some configuration options, as defined by the EC and BE fields, are set by the hardware during Cold Reset and are included in the Config register as read-only status bits for the software to access. Other configuration options (AD, EP, and K0 fields) can be read/written and controlled by software; on Cold Reset these fields are undefined. Since only a subset of the VR4000 Series caches are used. The contents of the Config register are undefined after a reset so that it must be initialized by software. Caution Be sure to set the EP field and the AD bit to 0. If they are set with any other values, the processor may behave unexpectedly. Figure 3-18. Config Register (1/2)
TM
options are available in the VR4181, some bits are set to constants (e.g.,
bits 14 and 13) that were variable in the VR4000 Series. The Config register should be initialized by software before
31 30 0 EC
28 27
24 23 22 21 20 19 18 17 16 15 14 13 12 11 AD 0 M16 0 1 0 BE 10 CS IC
98 DC
65 0
32 K0
0
EP
EC:
System clock ratio (read only) 0 Processor clock frequency divided by 2 1 Processor clock frequency divided by 3 2 Processor clock frequency divided by 4 3 to 7 Reserved
EP:
Transfer data pattern (cache write-back pattern) setting 0 DD: 1 word per 1 cycle Others Reserved
AD:
Accelerate data mode 0 VR4000 Series compatible mode 1 Reserved
M16:
MIPS16 ISA mode enable/disable indication (read only) 0 MIPS16 instruction cannot be executed 1 MIPS16 instruction can be executed.
BE:
BigEndianMem (Endian mode indication) 0 Little endian 1 Reserved
CS:
Cache size mode indication (n = IC, DC) 0 Reserved 12
(n+10)
bytes
(IC+10)
IC:
Instruction cache size indication. 2 2 4 KB Others Reserved
bytes in the VR4181.
DC:
Data cache size indication. 2 2 4 KB Others Reserved
(DC+10)
bytes in the VR4181.
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Figure 3-18. Config Register (2/2)
K0:
kseg0 cache coherency algorithm 2 Uncached Others Cached
1: 0:
1 is returned when read. 0 is returned when read.
3.2.16 Load Linked Address (LLAddr) register (17) The read/write Load Linked Address (LLAddr) register is not used with the VR4181 processor except for diagnostic purpose, and serves no function during normal operation. The LLAddr register is implemented just for compatibility between the VR4181 and VR4000 or VR4400. The contents of the LLAddr register are undefined after a reset. Figure 3-19. LLAddr Register
31 PAddr
0
PAddr:
32-bit physical address
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3.2.17 WatchLo (18) and WatchHi (19) registers The VR4181 processor provides a debugging feature to detect references to a selected physical address; load and store instructions to the location specified by the WatchLo and WatchHi registers cause a Watch exception. The contents of these registers are undefined after a reset so that they must be initialized by software. Figure 3-20. WatchLo Register
31 PAddr0
3
2 0
1 R
0 W
PAddr0: R: W: 0:
Specifies physical address bits 31 to 3. Specifies detection of watch address references when load instructions are executed (1 Detect, 0 Not detect). Specifies detection of watch address references when store instructions are executed (1 Detect, 0 Not detect). Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
Figure 3-21. WatchHi Register
31 0
0
0:
Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
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3.2.18 XContext register (20) The read/write XContext register contains a pointer to an entry in the page table entry (PTE) array, an operating system data structure that stores virtual-to-physical address translations. If a TLB miss occurs, the operating system loads the untranslated data from the PTE into the TLB to handle the software error. The XContext register is used by the XTLB Refill exception handler to load TLB entries in 64-bit addressing mode. The XContext register duplicates some of the information provided in the BadVAddr register, and puts it in a form useful for the XTLB exception handler. This register is included solely for operating system use. The operating system sets the PTEBase field in the register, as needed. Figure 3-22. XContext Register
63 PTEBase
35 34 33 32 R BadVPN2
4
3 0
0
PTEBase: Base address of the PTE entry table. R: Space type (00 User, 01 Supervisor, 11 Kernel). The setting of this field matches virtual address bits 63 and 62. BadVPN2: The value (VPN2) obtained by halving the virtual page number of the most recent virtual address for which translation failed. 0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
The 29-bit BadVPN2 field has bits 39 to 11 of the virtual address that caused the TLB miss; bit 10 is excluded because a single TLB entry maps to an even-odd page pair. For a 1 KB page size, this format may be used directly to address the pair-table of 8-byte PTEs. When the page size is 4 KB or more, shifting or masking this value produces the appropriate PTE reference address.
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3.2.19 Parity Error register (26) The Parity Error (PErr) register is a readable/writable register. This register is defined to maintain softwarecompatibility with the VR4100, and is not used in hardware because the VR4181 has no parity. Figure 3-23. Parity Error Register
31 0
87 Diagnostic
0
Diagnostic:8-bit self diagnostic field. 0: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
3.2.20 Cache Error register (27) The Cache Error register is a readable/writable register. This register is defined to maintain software-compatibility with the VR4100, and is not used in hardware because the VR4181 has no parity. Figure 3-24. Cache Error Register
31 0
0
0:
Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
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3.2.21 TagLo (28) and TagHi (29) registers The TagLo and TagHi registers are 32-bit read/write registers that hold the primary cache tag during cache initialization, cache diagnostics, or cache error processing. The Tag registers are written by the CACHE and MTC0 instructions. The contents of these registers are undefined after a reset. Figure 3-25. TagLo Register
(a) When used with data cache
31 PTagLo 10 9 V 8 D 7 W 6 0 0
(b) When used with instruction cache
31 PTagLo 10 9 V 8 0 0
PTagLo: V: D:
Specifies physical address bits 31 to 10. Valid bit Dirty bit. However, this bit is defined only for the compatibility with the VR4000 Series processors, and does not indicate the status of cache memory in spite of its readability and writability. This bit cannot change the status of cache memory.
W: 0:
Writeback bit (set if cache line has been updated) Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
Figure 3-26. TagHi Register
31 0
0
0:
Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.
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3.2.22 ErrorEPC register (30) The Error Exception Program Counter (ErrorEPC) register is similar to the EPC register. It is used to store the Program Counter value at which the Cold Reset, Soft Reset, or NMI exception has been serviced. The read/write ErrorEPC register contains the virtual address at which instruction processing can resume after servicing an error. The contents of this register change depending on whether execution of MIPS16 instructions is enabled or disabled. Setting the MIPS16EN pin after RTC reset specifies whether the execution of MIPS16 instructions is enabled or disabled. When the MIPS16 instruction execution is disabled, either of the following addresses is contained in the ErrorEPC register: * Virtual address of the instruction that caused the exception * Virtual address of the immediately preceding branch or jump instruction, when the instruction associated with the error exception is in a branch delay slot, and the BD bit in the Cause register is set to 1 When the MIPS16 instruction execution is enabled, either of the following addresses is contained in the ErrorEPC register during a 32-bit instruction execution: * Virtual address of the instruction that caused the exception and ISA mode at which an exception occurs * Virtual address of the immediately preceding branch or jump instruction and ISA mode at which an exception occurs when the instruction associated with the error exception is in a branch delay slot, and the BD bit in the Cause register is set to 1 When the 16-bit instruction is executed, either of the following addresses is contained in the ErrorEPC register: * Virtual address of the instruction that caused the exception and ISA mode at which an exception occurs * Virtual address of the immediately preceding jump instruction or Extend instruction and ISA mode at which an exception occurs when the instruction associated with the error exception is in a branch delay slot of the jump instruction or is the instruction following the Extend instruction, and the BD bit in the Cause register is set to 1 The contents of the ErrorEPC register do not change when the ERL bit of the Status register is set to 1. This prevents the processor when other exceptions occur from overwriting the address of the instruction in this register that causes an error exception. The ErrorEPC register never indicates the address of the instruction in a branch delay slot.
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Figure 3-27. ErrorEPC Register (When MIPS16 ISA Is Disabled)
(a) 32-bit mode
31 ErrorEPC 0
(b) 64-bit mode
63 ErrorEPC 0
ErrorEPC: Virtual restart address after Cold reset, Soft reset, or NMI exception.
Figure 3-28. ErrorEPC Register (When MIPS16 ISA Is Enabled)
(a) 32-bit mode
31 ErrorEPC 1 0 ErIM
ErrorEPC: Bits 31 to 1 of virtual restart address after Cold reset, Soft reset, or NMI exception. ErIM: ISA mode at which an error exception occurs (1 MIPS16 ISA, 0 MIPS III ISA). (b) 64-bit mode
63 ErrorEPC 1 0 ErIM
ErrorEPC: Bits 63 to 1 of virtual restart address after Cold reset, Soft reset, or NMI exception. ErIM: ISA mode at which an error exception occurs (1 MIPS16 ISA, 0 MIPS III ISA).
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4.1 Overview
The VR4181 provides a memory management unit (MMU) which uses a translation lookaside buffer (TLB) to translate virtual addresses into physical addresses. Virtual addresses are translated into physical addresses using an on-chip TLB. The on-chip TLB is a fullassociative memory that holds 32 entries, which provide mapping to 32 odd/even page pairs for one entry. The TLB is accessed through the CP0 registers. Note that the virtual address space includes areas that are translated to physical addresses without using a TLB, and areas where the use of cache memory can be selected. The VR4181 has three operating modes: User, Supervisor, and Kernel; the manner in which memory addresses are mapped depends on these operating modes. In addition, the VR4181 supports the 32-bit and 64-bit addressing modes; the manner in which memory addresses are translated or mapped depends on these addressing modes. For details about the memory management system and virtual address space, refer to VR4100 Series Architecture User's Manual.
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4.2 Physical Address Space
Using a 32-bit address, the processor physical address space encompasses 4 GB. The VR4181 uses this 4 GB physical address space as shown in Figure 4-1. Figure 4-1. VR4181 Physical Address Space
0xFFFF FFFF (Mirror image of 0x0000 0000 to 0x1FFF FFFF area) 0x2000 0000 0x1FFF FFFF
ROM space (including a boot ROM)
0x1800 0000 0x17FF FFFF External system bus I/O space (ISA I/O) 0x1400 0000 0x13FF FFFF External system bus memory space (ISA memory) 0x1000 0000 0x0FFF FFFF RFU 0x0D00 0000 0x0CFF FFFF Internal ISA I/O space 1 0x0C00 0000 0x0BFF FFFF Internal ISA I/O space 2 0x0B00 0000 0x0AFF FFFF MBA bus I/O space 0x0A00 0000 0x09FF FFFF
RFU
0x0400 0000 0x03FF FFFF
DRAM space
0x0000 0000
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Table 4-1. VR4181 Physical Address Space
Physical address 0xFFFF FFFF to 0x2000 0000 0x1FFF FFFF to 0x1800 0000 0x17FF FFFF to 0x1400 0000 0x13FF FFFF to 0x1000 0000 0x0FFF FFFF to 0x0D00 0000 0x0CFF FFFF to 0x0C00 0000 0x0BFF FFFF to 0x0B00 0000 0x0AFF FFFF to 0x0A00 0000 0x09FF FFFF to 0x0400 0000 0x03FF FFFF to 0x0000 0000 Space Mirror image of 0x1FFF FFFF to 0x0000 0000 ROM space External system bus I/O space (ISA I/O) External system bus memory space (ISA memory) Space reserved for future use Internal ISA I/O space 1 Internal ISA I/O space 2 MBA bus I/O space Space reserved for future use DRAM (SDRAM) space Capacity (bytes) 3.5 G 128 M 64 M 64 M 48 M 16 M 16 M 16 M 96 M 64 M
4.2.1 ROM space The ROM space mapping differs depending on the capacity of the ROM being used. The ROM capacity is set via the ROMs(1:0) bits in the BCUCNTREG1 register. The physical addresses of the ROM space are listed below. Table 4-2. ROM Address Map
Physical address 0x1FFF FFFF to 0x1FC0 0000 0x1FBF FFFF to 0x1F80 0000 0x1F7F FFFF to 0x1F40 0000 0x1F3F FFFF to 0x1F00 0000 0x1EFF FFFF to 0x1E80 0000 0x1E7F FFFF to 0x1E00 0000 When using 32-Mbit ROM Bank 3 (ROMCS3#) Bank 2 (ROMCS2#) Bank 1 (ROMCS1#) Bank 0 (ROMCS0#) Reserved for future use Bank 1 (ROMCS1#) Bank 0 (ROMCS0#) Bank 2 (ROMCS2#) When using 64-Mbit ROM Bank 3 (ROMCS3#)
4.2.2 External system bus space The following two types of system bus space are available. * External system bus I/O space This corresponds to the ISA's I/O space. * External system bus memory space This corresponds to the ISA's memory space.
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4.2.3 Internal I/O space The VR4181 has three internal I/O spaces. Each of these spaces is described below. Table 4-3. Internal I/O Space 1
Physical address 0x0C00 001F to 0x0C00 0010 0x0C00 000F to 0x0C00 0000 SIU1 SIU2 Internal I/O
Table 4-4. Internal I/O Space 2
Physical address 0x0B00 09FF to 0x0B00 0900 0x0B00 08FF to 0x0B00 0800 0x0B00 07FF to 0x0B00 0400 0x0B00 03FF to 0x0B00 0300 0x0B00 02FF to 0x0B00 02D0 0x0B00 02CF to 0x0B00 02C0 0x0B00 02BF to 0x0B00 02A0 0x0B00 029F to 0x0B00 0280 0x0B00 027F to 0x0B00 0260 0x0B00 025F to 0x0B00 0240 0x0B00 023F to 0x0B00 01E0 0x0B00 01DF to 0x0B00 01C0 0x0B00 01BF to 0x0B00 01A0 0x0B00 019F to 0x0B00 0180 0x0B00 017F to 0x0B00 0160 0x0B00 015F to 0x0B00 0140 0x0B00 013F to 0x0B00 0120 0x0B00 011F to 0x0B00 0100 0x0B00 00FF to 0x0B00 00E0 0x0B00 00DF to 0x0B00 00C0 0x0B00 00BF to 0x0B00 00A0 0x0B00 009F to 0x0B00 0080 0x0B00 007F to 0x0B00 0000 CSI ECU Reserved for future use GIU Reserved for future use ISA Bridge PIU-2 Reserved for future use A/D test LED Reserved for future use RTC-2 Reserved for future use KIU AIU Reserved for future use PIU-1 Reserved for future use DSU RTC-1 PMU ICU-3 Reserved for future use Internal I/O
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Table 4-5. MBA Bus I/O Space
Physical address 0x0A00 06FF to 0x0A00 0600 0x0A00 05FF to 0x0A00 0500 0x0A00 04FF to 0x0A00 0400 0x0A00 03FF to 0x0A00 0300 0x0A00 02FF to 0x0A00 0220 0x0A00 021F to 0x0A00 0200 0x0A00 01FF to 0x0A00 00A0 0x0A00 009F to 0x0A00 0080 0x0A00 007F to 0x0A00 0050 0x0A00 004F to 0x0A00 0020 0x0A00 001F to 0x0A00 0000 DCU-2 Reserved for future use LCD controller Memory controller Reserved for future use ICU-2 Reserved for future use ICU-1 Reserved for future use DCU-1 MBA Host Bridge Internal I/O
4.2.4 DRAM space The DRAM space differs depending on the capacity of the DRAM being used. The DRAM capacity is set via the B1Config(1:0) bits in the MEMCFG_REG register. The physical addresses of the DRAM space are listed below. Table 4-6. DRAM Address Map
Physical address 0x00FF FFFF to 0x0080 0000 0x007F FFFF to 0x0040 0000 0x003F FFFF to 0x0020 0000 0x001F FFFF to 0x0000 0000 Bank 1 (SDCS1#/RAS1#) Bank 0 (SDCS0#/RAS0#) When using 16-Mbit DRAM Reserved for future use When using 64-Mbit DRAM Bank 1 (SDCS1#/RAS1#) Bank 0 (SDCS0#/RAS0#)
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This chapter describes the reset signal descriptions and types, signal- and timing-related dependence, and the initialization sequence during each mode that can be selected by the user. A detailed description of the operation during and after a reset and its relationships to the power modes are also provided in CHAPTER 10 POWER MANAGEMENT UNIT (PMU). Remark # that follows signal names indicates active low.
5.1 Reset Function
There are five ways to reset the VR4181. Each is summarized below.
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5.1.1 RTC reset During power-on, set the RTCRST# pin as active. After waiting about 600 ms for the 32.768 kHz oscillator to begin oscillating when the power supply is stable at 3.0 V or above, setting the RTCRST# pin as inactive causes the RTC unit to begin counting. Then, the states of the MIPS16EN and CLKSEL(2:0) pins are read after one RTC cycle. Next, the VR4181 asserts the POWERON pin and checks the state of the BATTINH/BATTINT# signal. If it is at high level, the VR4181 asserts the MPOWER pin and activates the external agent's DC/DC converter. After the stabilization time period (about 350 ms) of the DC/DC converter, the VR4181 begins PLL oscillation and starts all clocks (a period of about 16 ms following the start of PLL oscillation is required for stabilization of PLL oscillation). An RTC reset does not save any of the status information and it completely initializes the processor's internal state. Since the DRAM is not switched to self refresh mode, the contents of DRAM after an RTC reset are not at all guaranteed. After a reset, the processor becomes the system bus master, which executes a Cold Reset exception sequence and begins to access the reset exception vectors in the ROM space. Since only part of the internal status is reset when a reset occurs in the VR4181, the processor should be completely initialized by software (see 5.4 Notes on Initialization). After power-on, the processor's pin statuses are undefined since the RTCRST# is asserted, until the 32.768 kHz clock oscillator starts oscillation. The pin statuses after oscillation starts are described in CHAPTER 2 PIN FUNCTIONS in this document. Figure 5-1. RTC Reset
RTCRST# (Input)
POWER (Input)
L
POWERON (Output)
MPOW ER (Output)
ColdReset# (Internal)
Reset# (Internal) Stable oscillation PLL (Internal) Undefined Stable oscillation RTC (Internal, 32.768 kHz) Undefined > 32 ms > 600 ms 350 ms 16 ms 16MasterClockNote
Note MasterClock is the basic clock used in the CPU core. Its frequency is one forth of TClock frequency.
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5.1.2 RSTSW reset After the RSTSW# pin becomes active and then becomes inactive 100 s later, the VR4181 starts PLL oscillation and starts all clocks (a period of about 16 ms following the start of PLL oscillation is required for stabilization of PLL oscillation). An RSTSW reset basically initializes the entire internal state except for the RTC timer, the GIU, and the PMU. The VR4181 has function to preserve DRAM data during RSTSW reset. For detail, refer to CHAPTER 10 POWER MANAGEMENT UNIT (PMU). After a reset, the processor becomes the system bus master, which executes a Cold Reset exception sequence and begins to access the reset exception vectors in the ROM space. Since only part of the internal status is reset when a reset occurs in the VR4181, the processor should be completely initialized by software (see 5.4 Notes on Initialization). Figure 5-2. RSTSW Reset
RSTSW# (Input)
POWER (Input)
L
MPOW ER (Output)
H
ColdReset# (Internal)
Reset# (Internal) Stable oscillation PLL (Internal) Undefined RTC (Internal, 32.768 kHz) Stable oscillation > 3RTC 16 ms 16MasterClockNote Stable oscillation
Note MasterClock is the basic clock used in the CPU core. Its frequency is one forth of TClock frequency.
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5.1.3 Deadman's Switch reset After the Deadman's Switch unit is enabled, if the Deadman's Switch is not cleared within the specified time period, the VR4181 immediately enters to reset status. Setting and clearing of the Deadman's Switch is performed by software. A Deadman's Switch reset initializes the entire internal state except for the RTC timer, the GIU, and the PMU. Since the DRAM is not switched to self-refresh mode, the contents of DRAM after a Deadman's Switch reset are not at all guaranteed. After a reset, the processor becomes the system bus master, which executes a Cold Reset exception sequence and begins to access the reset vectors in the ROM space. Since only part of the internal status is reset when a reset occurs in the VR4181, the processor should be completely initialized by software (see 5.4 Notes on Initialization). Figure 5-3. Deadman's Switch Reset
RSTSW# (Input)
H
POWER (Input)
L
MPOW ER (Output)
H
ColdReset# (Internal)
Reset# (Internal) Stable oscillation PLL (Internal) Undefined RTC (Internal, 32.768 kHz) Stable oscillation 16 ms 16MasterClockNote Stable oscillation
Note MasterClock is the basic clock used in the CPU core. Its frequency is one forth of TClock frequency.
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5.1.4 Software shutdown When the software executes the HIBERNATE instruction, the VR4181 sets the MPOWER pin as inactive, then enters reset status. Recovery from reset status occurs when the POWER pin or DCD# signal is asserted or when an unmasked wake-up interrupt request is occurred. A reset by software shutdown initializes the entire internal state except for the RTC timer, the GIU, and the PMU. After a reset, the processor becomes the system bus master, which executes a Cold Reset exception sequence and begins to access the reset vectors in the ROM space. Since only part of the internal status is reset when a reset occurs in the VR4181, the processor should be completely initialized by software (see 5.4 Notes on Initialization). Cauiton The VR4181 does not set the DRAM to self-refresh mode at the transition to Hibernate mode from Fullspeed mode. To preserve DRAM data, software must set the DRAM to self-refresh mode. For details, refer to CHAPTER 10 POWER MANAGEMENT UNIT (PMU). Figure 5-4. Software Shutdown
POWER (Input)
POWERON (Output)
MPOW ER (Output)
ColdReset# (Internal)
Reset# (Internal) Stable oscillation PLL (Internal) Stopped Undefined RTC (Internal, 32.768 kHz) Stable oscillation > 32 ms Note1 16 ms 16MasterClockNote2
Notes 1. Wait time for activation. It can be changed by setting the PMUWAITREG register. 2. MasterClock is the basic clock used in the CPU core. frequency. Its frequency is one forth of TClock
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5.1.5 HALTimer shutdown After an RTC reset or RSTSW reset is canceled, if the HALTimer is not canceled (the HALTIMERRST bit of the PMUCNTREG register is not set) by software within about four seconds, the VR4181 enters reset status. Recovery from reset status occurs when the POWER pin is asserted or when a ElapsedTime interrupt request occurs. A reset by HALTimer initializes the entire internal state except for the RTC timer, the GIU, and the PMU. After a reset, the processor becomes the system bus master, which executes a Cold Reset exception sequence and begins to access the reset vectors in the ROM space. Since only part of the internal status is reset when a reset occurs in the VR4181, the processor should be completely initialized by software (see 5.4 Notes on Initialization). Caution The VR4181 does not sets the DRAM to self-refresh mode by HALTimer shutdown. Therefore, the contents of DRAM after a HALTimer shutdown are not at all guaranteed. Figure 5-5. HALTimer Shutdown
POWER (Input)
POWERON (Output)
MPOW ER (Output)
ColdReset# (Internal)
Reset# (Internal) Stable oscillation PLL (Internal) Stable oscillation RTC (Internal, 32.768 kHz) about 4 s > 32 ms Note1 16 ms 16MasterClockNote2 Stopped Undefined
Notes 1. Wait time for activation. It can be changed by setting the PMUWAITREG register. 2. MasterClock is the basic clock used in the CPU core. frequency. Its frequency is one forth of TClock
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5.2 Power-on Sequence
The factors that cause the VR4181 to switch from Hibernate mode or shutdown mode to Fullspeed mode are called activation factors. There are five activation factors: assertion of the POWER pin, the DCD1# pin or the GPIO(15:0) pins, or activation of the ElapsedTime or CompactFlash interrupt request. When an activation factor occurs, the VR4181 asserts the POWERON pin to notify to external agents that the VR4181 is ready for power-on. Three RTC clock cycles after the POWERON pin is asserted, the VR4181 checks the state of the BATTINH/BATTINT# pin. If the BATTINH/BATTINT# pin's state is low, the POWERON pin is deasserted one RTC clock after the BATTINH/BATTINT# pin check is completed, then the VR4181 is not activated. If the BATTINH/BATTINT# pin's state is high, the POWERON pin is deasserted and the MPOWER pin is asserted three RTC clocks after the BATTINH/BATTINT# pin check is completed, then the VR4181 is activated. Figure 5-6 shows a timing chart of VR4181 activation and Figure 5-7 shows a timing chart of when activation fails due to the BATTINH/BATTINT# pin's "low" state. Remark While the MPOWER pin is inactive, 2.5 V power supply of the VR4181 (VDD_LOGIC, VDD_PLL) is not needed. In order to reduce leak current, it is recommended to turn on/off the 2.5 V power supply of the VR4181 according to MPOWER pin state. Figure 5-6. VR4181 Activation Sequence (When Activation Is OK)
POWERON (Output)
MPOW ER (Output)
ColdReset# (Internal)
Reset# (Internal)
BATTINH/BATTINT# (Input) Stable oscillation PLL (Internal) Stopped Undefined RTC (Internal, 32.768 kHz)
Detection of activation factor Check BATTINH/BATTINT# pin
Activation of CPU
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Figure 5-7. VR4181 Activation Sequence (When Activation Is NG)
POWERON (Output)
MPOW ER (Output)
L
ColdReset# (Internal)
L
Reset# (Internal)
L
BATTINH/BATTINT# (Input) PLL (Internal) H
RTC (Internal, 32.768 kHz)
Detection of activation factor Check BATTINH/BATTINT# pin
CPU not activated
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5.3 Reset of CPU Core
This section describes the reset sequence of the VR4110 CPU core. 5.3.1 Cold Reset In the VR4181, a Cold Reset sequence is executed in the CPU core in the following cases: * RTC reset * RSTSW reset * Deadman's Switch reset * Software shutdown * HALTimer shutdown * BATTINH shutdown (shutdown according to battery state) A Cold Reset completely initializes the CPU core, except for the following register bits. * The TS and SR bits of the Status register are cleared to 0. * The ERL and BEV bits of the Status register are set to 1. * The upper limit value (31) is set in the Random register. * The Wired register is initialized to 0. * The Count register is initialized to 0. * Bits 31 to 28 of the Config register are set to 0 and bits 22 to 3 to 0x04800; the other bits are undefined. * The values of the other registers are undefined. Once power to the processor is established, the ColdReset# (internal) and the Reset# (internal) signals are asserted and a Cold Reset is started. After approximately 2 ms assertion, the ColdReset# signal is deasserted synchronously with the rising edge of MasterOut (internal). Then the Reset# signal is deasserted synchronously with the rising edge of MasterOut, and the Cold Reset is completed. Upon reset, the CPU core becomes bus master and drives the SysAD bus (internal). After Reset# is deasserted, the CPU core branches to the Reset exception vector and begins executing the reset exception code. Figure 5-8. Cold Reset
VDD MasterClockNote (Internal) ColdReset# (Internal)
Reset# (Internal)
MasterOut (Internal) Undefined TClock (Internal) Undefined
Note MasterClock is the basic clock used in the CPU core. Its frequency is one forth of TClock frequency.
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5.3.2 Soft Reset Caution Soft Reset is not supported in the current VR4181.
A Soft Reset initializes the CPU core without affecting the output clocks; in other words, a Soft Reset is a logical reset. In a Soft Reset, the CPU core retains as much state information as possible; all state information except for the following is retained: * The TS bit of the Status register is cleared to 0. * The SR, ERL and BEV bits of the Status register are set to 1. * The IP7 bit of the Cause register is cleared to 0. * Any interrupts generated on the SysAD bus are cleared. * NMI is cleared. * The Config register is initialized. A Soft Reset is started by assertion of the Reset# signal, and is completed at the deassertion of the Reset# signal synchronized with the rising edge of MasterOut. In general, data in the CPU core is preserved for debugging purpose. Upon reset, the CPU core becomes bus master and drives the SysAD bus (internal). After Reset# is deasserted, the CPU core branches to the Reset exception vector and begins executing the reset exception code. Figure 5-9. Soft Reset
VDD MasterClockNote (Internal) Reset# (Internal)
H
MasterOut (Internal)
TClock (Internal)
Note MasterClock is the basic clock used in the CPU core. Its frequency is one forth of TClock frequency.
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5.4 Notes on Initialization
This section explains the case in which manipulation by software is necessary after the VR4181 has been reset. When a Cold Reset sequence is executed, the reset exception vector is accessed. Perform manipulation described here by using the software (handler) for reset exceptions located at the reset exception vector. 5.4.1 CPU core (1) Coprocessor 0 Be sure to initialize at least the following internal registers of the coprocessor 0 (CP0) after the RTC reset, RSTSW reset, or Deadman's Switch reset has been cleared, or the VR4181 has returned from the Hibernate mode. * Config register * Status register * WatchLo register (2) Cache tag The contents of the tag RAM of the cache are undefined immediately after a voltage has been applied to the 2.5 V power supply when the RTC reset or Deadman's Switch reset has been cleared, or when the VR4181 has returned from the Hibernate mode. Before accessing an address at which the cache can be used, therefore, be sure to initialize the contents of the tag RAM of both the instruction cache and data cache. Use the TagLo register in CP0 to initialize the tags. 5.4.2 Internal peripheral units (1) HALTimer Set the HALTIMERRST bit of the PMUCNTREG register in the PMU to 1 within 4 seconds after clearing the RTC reset or RSTSW reset. This resets the HALTimer. (2) Memory controller Before accessing the DRAM space, be sure to initialize the registers in the memory controller. Especially when SDRAM is used, initialize SDRAM by executing the procedure described in 6.5.2 MEMCFG_REG (0x0A00 0304). A function to operate SDCLK only when SDRAM is accessed, for example, is not valid unless a mode setting command is issued to SDRAM by using the MEMCFG_REG register. (3) Clock supply to peripheral units The clock is not supplied in the default status to the peripheral units such as CSI, AIU, PIU, SIU1, and SIU2, and the A/D and D/A converters. To start using these units and converters, supply the necessary clock to them by setting the CMUCLKMSK register in the MBA Host Bridge. If these units are not used or they have finished being used, mask the clock supply by setting the CMUCLKMSK register. (4) Alternate-function pins The function of an alternate-function pin and the I/O direction of the GPIO pins are selected by the registers in the GIU. Be sure to set these registers in accordance with the unit or the function of the pin to be used. Exercise care in setting the registers so that signals do not conflict on the board or that a signal whose level is required does not go into a high-impedance state.
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5.4.3 Returning from power mode For initialization after the VR4181 has returned from the Hibernate mode or Suspend mode, refer to 10.6 DRAM Interface Control.
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6.1 MBA Host Bridge
The MBA (Modular Bus Architecture) Host Bridge is an interface between the CPU core and the MBA bus and operates as an external agent to the CPU core. It handles all requests from the CPU core if it is provided proper resources. The MBA Host Bridge can decode the entire physical address space to start appropriate bus accesses such as MBA requests, MBA - ISA protocols, or external ROM accesses through the peripheral bus. It also has functions as a host bridge to implement proper cycle timings and bus transaction protocols. Figure 6-1. VR4181 Internal Bus Structure
VR4110 CPU Core
SysAD Bus
MBA Peripherals (LCD, DMA)
Memoty Controller
MBA Host Bridge
MBA Bus
ISA Bridge
Internal ISA Peripherals
Internal ISA Bus
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6.1.1 MBA Host Bridge ROM and register address space
Physical address 0x1FFF FFFF to 0x1800 0000 0x0A00 0014 to 0x0A00 0000 0x0A00 0080 0x0A00 008C 0x0A00 0098 0x0A00 009A 0x0A00 0200 0x0A00 0206 Type Memory (range) I/O (range) I/O I/O I/O I/O I/O I/O ROM Bus control registers Interrupt register Interrupt register Interrupt register Interrupt register Interrupt register Interrupt register Device
In addition to the decoding of above addresses, the Host Bridge generates MBA select signals if other MBA masters intend to access the above devices. The Host Bridge responds to the above addresses only upon a CPU access. For any other addresses the Host Bridge initiates an MBA cycle to access an appropriate resources. 6.1.2 MBA modules address space (1) Memory controller
Physical address 0x03FF FFFF to 0x0000 0000 0x0A00 03FF to 0x0A00 0300 Type Memory (range) I/O (range) DRAM Control registers Device
The MBA memory controller is selected when the above address ranges are accessed. (2) DMA controller
Physical address 0x0A00 0048 to 0x0A00 0020 0x0A00 06FF to 0x0A00 0600 I/O (range) I/O (range) Type Device Control registers 1 Control registers 2
The MBA DMA controller is selected when the above I/O ranges are accessed. (3) LCD module (LCD Control Unit)
Physical address 0x0A00 05FF to 0x0A00 0400 I/O (range) Type Device Control registers
The LCD module is selected when the above I/O range is accessed.
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(4) ISA Bridge
Physical address 0x17FF FFFF to 0x1400 0000 0x13FF FFFF to 0x1000 0000 0x0BFF FFFF to 0x0B00 0000 0x0CFF FFFF to 0x0C00 0000 Type I/O (64M, range) Memory (64M, range) I/O (16M, range) I/O (16M, range ) Device External ISA bus (I/O) External ISA bus (Memory) ISA internal I/O 1 ISA internal I/O 2
The ISA Bridge is selected when the above address ranges are accessed.
6.2 Bus Control Registers
External ROM accesses and supply of clocks to several internal units are controlled by the bus control registers listed below. Table 6-1. Bus Control Registers
Physical address 0x0A00 0000 0x0A00 0004 0x0A00 000C 0x0A00 0010 0x0A00 0014 0x0A00 0018 R/W R/W R/W R/W R/W R R Register symbol BCUCNTREG1 CMUCLKMSK BCUSPEEDREG BCURFCNTREG REVIDREG CLKSPEEDREG BCU control register 1 Clock mask register BCU access time parameters register BCU refresh control register Revision ID register Clock speed register Function
Caution
Since these registers are powered by 2.5 V power supply, the contents of these registers are cleared after Hibernate mode.
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6.2.1 BCUCNTREG1 (0x0A00 0000)
Bit Name R/W At reset 15 ROMs1 R/W 1 14 ROMs0 R/W 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 Reserved R 0
Bit Name R/W At reset
7 Reserved R 0
6 Reserved R 0
5 Reserved R 0
4 ROMWEN0 R/W 0
3 Reserved R 0
2 Rtype1 R/W 0
1 Rtype0 R/W 0
0 RSTOUT R/W 0
Bit 15, 14 ROMs(1:0)
Name
Function Defines ROM size to be used (for all banks) 00 : Reserved 01 : 32 Mbit 10 : 64 Mbit 11 : Reserved
13 to 5 4
Reserved ROMWEN0
0 is returned when read Enables flash memory write (for all banks). Write strobe can be generated when this bit is set to 1. 0 : Disabled 1 : Enabled
3 2, 1
Reserved Rtype(1:0)
0 is returned when read ROM type (for all banks) 00 : Ordinary ROM 01 : Flash memory 10 : Page ROM 11 : Reserved
0
RSTOUT
RESET# output control. This bit does not affect GPIO21/RESET# pin's state when this pin is not defined as RESET# output. 0 : RESET# is active (low level) 1 : RESET# is inactive (high level)
This register is used to set ROM type and capacity of ROM Bank 0, 1, 2 and 3. Caution When writing to flash memory, be sure to set Rtype(1:0) bits to 01 in addition to a setting of ROMWEN0 bit to 1. Remark When a ROM type other than flash memory is selected (Rtype(1:0) bits are set to other than 01), the operation of the VR4181 is undefined if a write to the ROM space is performed.
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6.2.2 CMUCLKMSK (0x0A00 0004)
Bit Name R/W At reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 Reserved R 0
Bit Name
7 Reserved
6 MSKCSU PCLK R/W 0
5 MSKAIU PCLK R/W 0
4 MSKPIU PCLK R/W 0
3 MSKADU PCLK R/W 0
2 MSKSIU 18M R/W 0
1 MSKADU 18M R/W 0
0 Reserved
R/W At reset
R 0
R/W 0
Bit 15 to 7 6 Reserved
Name 0 is returned when read
Function
MSKCSUPCLK
Supply/Mask Clocked Serial Interface (CSI) peripheral clock (PCLK) 0 : Mask 1 : Supply
5
MSKAIUPCLK
Supply/Mask Audio Interface (AIU) peripheral clock (PCLK) 0 : Mask 1 : Supply
4
MSKPIUPCLK
Supply/Mask Touch Panel Interface (PIU) peripheral clock (PCLK) 0 : Mask 1 : Supply
3
MSKADUPCLK
Supply/Mask A/D converter and D/A converter peripheral clock (PCLK) 0 : Mask 1 : Supply
2
MSKSIU18M
Supply/Mask Serial Interface 1 and 2 (SIU1/SIU2) 18.432 MHz clock 0 : Mask 1 : Supply
1
MSKADU18M
Supply/Mask A/D converter and D/A converter 18.432 MHz clock 0 : Mask 1 : Supply
0
Reserved
Write 0 when write. 0 is returned when read.
This register is used to mask the clocks that are supplied to CSI, AIU, PIU, SIU1, and SIU2.
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6.2.3 BCUSPEEDREG (0x0A00 000C)
Bit Name R/W At reset 15 Reserved R 0 14 WPROM2 R/W 1 13 WPROM1 R/W 1 12 WPROM0 R/W 1 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 Reserved R 0
Bit Name R/W At reset
7 Reserved R 0
6 Reserved R 0
5 Reserved R 0
4 Reserved R 0
3 WROMA3 R/W 1
2 WROMA2 R/W 1
1 WROMA1 R/W 1
0 WROMA0 R/W 1
Bit 15 14 to 12 Reserved
Name 0 is returned when read Page ROM access speed 000 : 1.5 TClock 001 : 2.5 TClock 010 : 3.5 TClock 011 : 4.5 TClock 100 : 5.5 TClock 101 : 6.5 TClock 110 : 7.5 TClock 111 : 8.5 TClock
Function
WPROM(2:0)
11 to 4 3 to 0
Reserved WROMA(3:0)
0 is returned when read ROM access speed 0000 : 1.5 TClock 0001 : 2.5 TClock 0010 : 3.5 TClock 0011 : 4.5 TClock 0100 : 5.5 TClock 0101 : 6.5 TClock 0110 : 7.5 TClock 0111 : 8.5 TClock 1000 : 9.5 TClock 1001 : 10.5 TClock 1010 : 11.5 TClock 1011 : 12.5 TClock 1100 : 13.5 TClock 1101 : 14.5 TClock 1110 : 15.5 TClock 1111 : 16.5 TClock
This register is used to set ROM access parameter of Bank 0, 1, 2, and 3. About the relationship between these bits and ROM cycles, refer to Figure 6-2. ROM Read Cycle and Access Parameters. Remark The maximum burst number when using a PageROM is 8 halfwords (i.e. 128 bits; 1 word = 32 bits).
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Figure 6-2. ROM Read Cycle and Access Parameters
(a) Ordinary ROM cycle
TClock (internal)
ADD(21:0) (output)
Valid
ROMCS(3:0)# (output)
MEMRD# (output) WROMA(3:0) DATA(15:0) (read)
Valid
(b) PageROM cycle
TClock (internal)
ADD(21:3) (output)
Valid
ADD(2:0) (output)
Valid
Valid
ROMCS(3:0)# (output) WROMA(3:0) DATA(15:0) (read) WPROM(2:0)
Valid
Valid
Remarks 1. ROMCS(2:0)# signals are alternated with general-purpose I/O signals and are defined as general-purpose inputs after RTC reset. Set GPMD2REG and GPMD3REG registers in the GIU to use them as ROMCS(2:0)#. 2. A circle in the figure indicates the sampling timing.
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6.2.4 BCURFCNTREG (0x0A00 0010)
Bit Name R/W At reset 15 Reserved R 0 14 Reserved R 0 13 BRF13 R/W 0 12 BRF12 R/W 1 11 BRF11 R/W 1 10 BRF10 R/W 1 9 BRF9 R/W 1 8 BRF8 R/W 1
Bit Name R/W At reset
7 BRF7 R/W 1
6 BRF6 R/W 1
5 BRF5 R/W 1
4 BRF4 R/W 1
3 BRF3 R/W 1
2 BRF2 R/W 1
1 BRF1 R/W 1
0 BRF0 R/W 1
Bit 15, 14 13 to 0 Reserved BRF(13:0)
Name 0 is returned when read
Function
These bits select the DRAM refresh rate that is based on the TClock. The refresh rate is obtained by following expression. Refresh rate = BRF(13:0) x TClock period For example, to select a 15.6 s refresh rate with a 50 MHz TClock: BRF(13:0) = 15600 (ns) / 20 (ns) = 0x30C
Remarks 1. When the IORDY signal does not become high level though the DRAM refresh rate has elapsed during the external ISA memory or I/O cycles, a DRAM refresh cycle may be lost. 2. Refresh timing is generated from detecting match between values of the internal up counter and BCURFCNTREG register. Therefore, when the BCURFCNTREG register value is changed smaller than current value, and if the internal counter value is larger than the new BCURFCNTREG register value, the next CBR refresh timing is at next match after the counter rounds over.
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6.2.5 REVIDREG (0x0A00 0014)
Bit Name R/W 15 RID3 R 14 RID2 R 13 RID1 R 12 RID0 R 11 MJREV3 R 10 MJREV2 R 9 MJREV1 R 8 MJREV0 R
Bit Name R/W
7 Reserved R
6 Reserved R
5 Reserved R
4 Reserved R
3 MNREV3 R
2 MNREV2 R
1 MNREV1 R
0 MNREV0 R
Bit 15 to 12 11 to 8 7 to 4 3 to 0 RID(3:0)
Name Processor revision ID (Read Only)
Function
MJREV(3:0) Reserved MNREV(3:0)
Major revision ID number (Read only) 0 is returned when read Minor revision ID (Read only)
This register is used to indicate the revision of the VR4181. The relationship between the values and the revision of the VR4181 is as follows.
VR4181 Revision 1.0 1.1 1.2 1.3 0x0 0x0 0x0 0x0 RID(3:0) MJREV(3:0) 0x0 0x0 0x0 0x0 MINREV(3:0) 0x0 0x1 0x2 0x2
Even if the CPU core or the peripheral unit has been changed, there is no guarantee that REVIDREG register will be reflected, or that the changes to the revision number necessarily reflect real changes of the CPU core or the peripheral unit. For this reason, software should not rely on the revision number in REVIDREG register to characterize the units. Caution Values of this register bits differ depending on the delivery date.
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6.2.6 CLKSPEEDREG (0x0A00 0018)
Bit Name R/W 15 DIV2 R 14 DIV3 R 13 DIV4 R 12 Reserved R 11 Reserved R 10 Reserved R 9 Reserved R 8 Reserved R
Bit Name R/W
7 Reserved R
6 Reserved R
5 Reserved R
4 CLKSP4 R
3 CLKSP3 R
2 CLKSP2 R
1 CLKSP1 R
0 CLKSP0 R
Bit 15 to 13 12 to 5 4 to 0 DIV(2:4) Reserved
Name
Function Value used to calculate the TClock, MBA clock, and SDCLK operating frequency 0 is returned when read Value used to calculate the CPU core operating clock (PClock) frequency
CLKSP(4:0)
The following expression is used to calculate the PClock and TClock frequency: (1) CPU core clock (PClock) PClock = (18.432 MHz / CLKSP(4:0)) x 64 (2) Peripheral clock (TClock)
DIV(2:4) 111 011 101 Others Ratio TClock = PClock / 1 TClock = PClock / 2 TClock = PClock / 3 Reserved Mode Div1 mode Div2 mode Div3 mode -
Remark
PClock frequency is decided by CLKSEL(2:0) pin statuses during RTC reset. TClock frequency is always a half of PClock frequency (Div2 mode) immediately after RTC reset. Software can change TClock Div mode by setting the PMUDIVREG register (0x0B00 00AC). A change becomes valid when the VR4181 restores from the Hibernate mode after setting the PMUDIVREG register.
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6.3 ROM Interface
The VR4181 supports three ROM modes, ordinary ROM, PageROM, and flash memory. The mode setting is made via the BCUCNTREG1 register's Rtype(1:0) bits and ROMWEN0 bit. Access speed setting in ordinary ROM or PageROM mode is made via the BCUSPEEDREG register. Remark The VR4181 supports only 16-bit access for external ROM devices.
6.3.1 External ROM devices memory mapping
Physical address 0x1FFF FFFF to 0x1FC0 0000 0x1FBF FFFF to 0x1F80 0000 0x1F7F FFFF to 0x1F40 0000 0x1F3F FFFF to 0x1F00 0000 0x1EFF FFFF to 0x1E80 0000 0x1E7F FFFF to 0x1E00 0000 32 Mbit ROM Bank 3 (ROMCS3#) Bank 2 (ROMCS2#) Bank 1 (ROMCS1#) Bank 0 (ROMCS0#) Reserved Reserved Bank 1 (ROMCS1#) Bank 0 (ROMCS0#) Bank 2 (ROMCS2#) 64 Mbit ROM Bank 3 (ROMCS3#)
Bank 3 contains boot vector and has a dedicated pin for chip select (ROMCS3#). Chip select pins for Bank 2, 1, and 0, ROMCS(2:0)#, are alternated with general-purpose I/O signals and are defined as general-purpose inputs after RTC reset. Set GPMD2REG and GPMD3REG registers in the GIU to use them as ROMCS(2:0)#.
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6.3.2 Connection to external ROM (x 16) devices The ADD(21:0) pins are connected to the address line ADD(21:0) inside the VR4181 during DRAM accesses. However, during ROM or flash memory accesses, they are connected to the address line ADD(22:1) inside the VR4181. This allows providing a greater address space capacity for ROM or flash memory.
ROM address pin 32 Mbit ROM (2 Mbits x 16) VR4181 pin CPU core physical address line 64 Mbit ROM (4 Mbits x 16) VR4181 pin CPU core physical address adr22 adr21 adr20 adr19 adr18 adr17 adr16 adr15 adr14 adr13 adr12 adr11 adr10 adr9 adr8 adr7 adr6 adr5 adr4 adr3 adr2 adr1
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ADD20 ADD19 ADD18 ADD17 ADD16 ADD15 ADD14 ADD13 ADD12 ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 adr21 adr20 adr19 adr18 adr17 adr16 adr15 adr14 adr13 adr12 adr11 adr10 adr9 adr8 adr7 adr6 adr5 adr4 adr3 adr2 adr1
ADD21 ADD20 ADD19 ADD18 ADD17 ADD16 ADD15 ADD14 ADD13 ADD12 ADD11 ADD10 ADD9 ADD8 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0
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6.3.3 Example of ROM connection (1) 32 Mbit ordinary ROM
ADD(20:0)
A(20:0) ROMCS0# ROM Bank0 D(15:0) ROMCS1#
A(20:0) ROM Bank1 D(15:0) ROMCS2#
A(20:0) ROM Bank2 D(15:0) ROMCS3#
A(20:0) ROM Bank3 D(15:0)
DATA(15:0)
(2) 64 Mbit ordinary ROM
ADD(21:0)
A(21:0) ROMCS0# ROM Bank0 D(15:0) ROMCS1#
A(21:0) ROM Bank1 D(15:0) ROMCS2#
A(21:0) ROM Bank2 D(15:0) ROMCS3#
A(21:0) ROM Bank3 D(15:0)
DATA(15:0)
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(3) 32 Mbit PageROM Remark The maximum burst number when using a PageROM is 8 halfwords (i.e. 128 bits; 1 word = 32 bits).
ADD(20:3) ADD(2:0)
A(19:2) A(1:-1)
A(19:2) A(1:-1)
A(19:2) A(1:-1)
A(19:2) A(1:-1)
Page ROM Bank0
Page ROM Bank1
Page ROM Bank2
Page ROM Bank3
ROMCS0#
CE DW/W# D(15:0)
ROMCS1#
CE DW/W# D(15:0)
ROMCS2#
CE DW/W# D(15:0)
ROMCS3#
CE DW/W# D(15:0)
DATA(15:0)
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(4) 64 Mbit PageROM Remark The maximum burst number when using a PageROM is 8 halfwords (i.e. 128 bits; 1 word = 32 bits).
ADD(21:3) ADD(2:0)
A(20:2) A(1:-1)
A(20:2) A(1:-1)
A(20:2) A(1:-1)
A(20:2) A(1:-1)
Page ROM Bank0
Page ROM Bank1
Page ROM Bank2
Page ROM Bank3
ROMCS0#
CE DW/W# D(15:0)
ROMCS1#
CE DW/W# D(15:0)
ROMCS2#
CE DW/W# D(15:0)
ROMCS3#
CE DW/W# D(15:0)
DATA(15:0)
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(5) 32 Mbit flash memory (when using Intel
TM
DD28F032)
ADD(19:0) ADD20
A(20:1) CE2 CE1 Flash memory Bank0 Flash ReadyNote ROMCS0# MEMWR# MEMRD# RDY/BSY# CE0 WE OE D(15:0) ROMCS1#
A(20:1) CE2 CE1 Flash memory Bank1 RDY/BSY# CE0 WE OE D(15:0) ROMCS2#
A(20:1) CE2 CE1 Flash memory Bank2 RDY/BSY# CE0 WE OE D(15:0) ROMCS3#
A(20:1) CE2 CE1 Flash memory Bank3 RDY/BSY# CE0 WE OE D(15:0)
DATA(15:0)
Note There is no corresponding pin in the VR4181. Use one of the GPIO pins for this function. Remark Use one of the GPIO pins in the VR4181 to control ON/OFF of VPP (program/erase supply voltage).
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(6) 64 Mbit flash memory (when using Intel StrataFlash
TM
28F640J5)
ADD(21:0)
A(21:0) CE2 CE1 Flash memory Bank0 Flash StatusNote ROMCS0# MEMWR# MEMRD# STS CE0 WE OE D(15:0) ROMCS1#
A(21:0) CE2 CE1 Flash memory Bank1 STS CE0 WE OE D(15:0) ROMCS2#
A(21:0) CE2 CE1 Flash memory Bank2 STS CE0 WE OE D(15:0) ROMCS3#
A(21:0) CE2 CE1 Flash memory Bank3 STS CE0 WE OE D(15:0)
DATA(15:0)
Note There is no corresponding pin in the VR4181. Using one of the GPIO pins for this function. Remark Using one of the GPIO pins in the VR4181 to control ON/OFF of VPP (program/erase supply voltage).
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6.3.4 External ROM cycles The following timing diagrams illustrate the external ROM cycles depending on the settings in the bus control register and bus speed control register. (1) Ordinary ROM read cycle Figure 6-3. Ordinary ROM Read Cycle (WROMA(3:0) = 0101)
TClock (internal)
ADD(21:0) (output)
Valid
ROMCS(3:0)# (output)
MEMRD# (output) WROMA(3:0) DATA(15:0) (read)
Valid
Remark
A circle in the figure indicates the sampling timing.
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(2) PageROM read cycle Figure 6-4. PageROM Read Cycle (WROMA(3:0) = 0011, WPROM(2:0) = 001)
TClock (internal)
ADD(21:0) (output)
Adr0
Adr1
Adr2
Adr3
Adr4
Adr5
Adr6
Adr7
ROMCS(3:0)# (output)
MEMRD# (output)
L WROMA(3:0) WPROM(2:0) WPROM(2:0) WPROM(2:0) WPROM(2:0) WPROM(2:0) WPROM(2:0) WPROM(2:0) Data7
DATA(15:0) (read)
Data0
Data1
Data2
Data3
Data4
Data5
Data6
Remark
A circle in the figure indicates the sampling timing.
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(3) Flash memory read cycle Figure 6-5. Flash Memory Read Cycle (Rtype(1:0) = 01, WROMA(3:0) = 0101)
TClock (internal)
ADD(21:0) (output)
Valid
ROMCS(3:0)# (output)
MEMRD# (output) WROMA(3:0) DATA(15:0) (read)
Valid
Remark
A circle in the figure indicates the sampling timing.
(4) Flash memory write cycle Figure 6-6. Flash Memory Write Cycle (Rtype(1:0) = 01, WROMA(3:0) = 0100)
TClock (internal)
ADD(21:0) (output)
Valid
ROMCS(3:0)# (output)
MEMWR# (output) WROMA(3:0) DATA(15:0) (write)
Valid
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6.4 DRAM Interface
The VR4181 supports 16 Mbit or 64 Mbit DRAM (EDO DRAM or SDRAM). The DRAM size, type, and access speed is set via the memory controller's registers. 6.4.1 EDO DRAM configuration Figure 6-7. External EDO DRAM Configuration
ADD(12:0) UCAS# LCAS# MEMWR# RAS0# DATA(15:0)
A(12:0) UCAS# LCAS# WE# RAS# D(15:0) OE# EDO DRAM Bank0
VR4181
A(12:0) UCAS# LCAS# WE# RAS1# RAS# D(15:0) OE# EDO DRAM Bank1
Figure 6-7 illustrates an example when connecting devices of 4 Mbits x 16. Addresses when connecting devices of 16 Mbits or 64 Mbits are mapped as follows.
DRAM bank Bank 0 Bank 1 Physical address (16 Mbits) 0x001F FFFF to 0x0000 0000 0x003F FFFF to 0x0020 0000 Physical address (64 Mbits) 0x007F FFFF to 0x0000 0000 0x00FF FFFF to 0x0080 0000
Remark
64 Mbit EDO DRAMs of other than 13 rows and 9 columns cannot be used with the VR4181.
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6.4.2 Mixed memory mode (EDO DRAM only) The MEMCFG_REG register provides two bits each for Bank 0 and Bank 1 to set types of DRAMs to be used. This allows the two banks to be configured with different types of DRAMs, for example, Bank 0 can be mapped on 64 Mbit devices and Bank 1 on 16 Mbit devices, to optimize the cost of the total memory required. Table 6-2. VR4181 EDO DRAM Capacity
Bank 0 16 Mbits 16 Mbits 64 Mbits 16 Mbits 64 Mbits 64 Mbits 0 16 Mbits 0 64 Mbits 16 Mbits 64 Mbits Bank 1 Total DRAM capacity 2 MB 4 MB 8 MB 10 MB 10 MB 16 MB
6.4.3 EDO DRAM timing parameters The following table shows examples of EDO DRAM timing parameters when using EDO DRAMs with access time of 60 ns. These parameters are set in EDOMCYTREG register.
TClock frequency 66 MHz 50 MHz 33 MHz 25 MHz RAS to CAS delay 3 TClock 2 TClock 2 TClock 2 TClock CAS pulse width 1 TClock 1 TClock 1/2 TClock 1/2 TClock CAS precharge RAS precharge RAS pulse width 3 TClock 3 TClock 2 TClock 2 TClock Self refresh RAS precharge 8 TClock 6 TClock 4 TClock 3 TClock
1 TClock 1 TClock 1/2 TClock 1/2 TClock
3 TClock 2 TClock 2 TClock 1 TClock
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6.4.4 SDRAM configuration Figure 6-8. SDRAM Configuration
ADD(13:0) SDRAS# CAS# UDQM LDQM MEMWR# SDCS0# DATA(15:0) SDCLK CLKEN VR4181
A(13:0) RAS# CAS# UDQM LDQM WE# CS# D(15:0) CLK CKE SDRAM Bank0
A(13:0) RAS# CAS# UDQM LDQM WE# SDCS1# CS# D(15:0) CLK CKE SDRAM Bank1
Figure 6-8 illustrates an example when connecting devices of 4 Mbits x 16. Remark The SDRAMs supported by the VR4181 are as follows.
Capacity 16 Mbits 64 Mbits 64 Mbits Configuration 512 Kbits x 16 x 2 banks 2 Mbits x 16 x 2 banks 1 Mbits x 16 x 4 banks Address pins A(10:0) A(12:0) A(11:0) Bank address A11 A13 A(13:12)
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6.5 Memory Controller Register Set
Table 6-3. Memory Controller Registers
Physical address 0x0A00 0300 0x0A00 0304 0x0A00 0308 0x0A00 030C R/W R/W R/W R/W R/W Register symbol EDOMCYTREG MEMCFG_REG MODE_REG SDTIMINGREG EDO DRAM timing register Memory configuration register SDRAM mode register SDRAM timing register Function
Caution
Since these registers are powered by 2.5 V power supply, the contents of these registers are cleared after Hibernate mode.
6.5.1 EDOMCYTREG (0x0A00 0300) (1/2)
Bit Name R/W At reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 SrefRpre2 R/W 0 11 SrefRpre1 R/W 0 10 SrefRpre0 R/W 0 9 Caspre1 R/W 0 8 Caspre0 R/W 0
Bit Name R/W At reset
7 Rcasdly1 R/W 0
6 Rcasdly0 R/W 0
5 Tcas1 R/W 0
4 Tcas0 R/W 0
3 Trp1 R/W 0
2 Trp0 R/W 0
1 Tras1 R/W 0
0 Tras0 R/W 0
Bit 15 to 13 12 to 10 Reserved
Name 0 is returned when read Self refresh RAS precharge time 000 : 3 TClock 001 : 4 TClock 010 : 6 TClock 011 : 8 TClock 100 : 11 TClock Others : Reserved
Function
SrefRpre(2:0)
9, 8
Caspre(1:0)
CAS precharge time 00 : 1/2 TClock 01 : 1 TClock 10 : 2 TClock 11 : Reserved
7, 6
Rcasdly(1:0)
RAS to CAS delay time 00 : 2 TClock 01 : 3 TClock 10 : 5 TClock 11 : 6 TClock
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(2/2)
Bit 5, 4 Tcas(1:0) Name CAS pulse width 00 : 1/2 TClock 01 : 1 TClock 10 : 2 TClock 11 : Reserved 3, 2 Trp(1:0) RAS precharge time 00 : 1 TClock 01 : 2 TClock 10 : 3 TClock 11 : 4 TClock 1, 0 Tras(1:0) RAS pulse width 00 : 2 TClock 01 : 3 TClock 10 : 5 TClock 11 : 6 TClock Function
This register is used to set EDO DRAM timing parameters. Software must set these parameters suitable before using DRAM. Remark Do not set Tcas = 1/2 TClock and Caspre = 1 TClock, or Tcas = 1 TClock and Caspre = 1/2 TClock at the same time.
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6.5.2 MEMCFG_REG (0x0A00 0304) (1/2)
Bit Name R/W At reset 15 Init R/W 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 B1Config1 R/W 0 10 B1Config0 R/W 0 9 Reserved R 0 8 Bstreftype R/W 0
Bit Name
7 BstRefr
6 EDOAsym
5 Reserved
4 Reserved
3 Reserved
2 B0Config1
1 B0Config0
0 EDO/ SDRAM R/W 0
R/W At reset
R/W 0
R/W 0
R 0
R 0
R 0
R/W 0
R/W 0
Bit 15 Init
Name
Function This bit is for SDRAM only. When software writes 1 to this bit, the memory controller issues a SDRAM mode set command. After the SDRAM mode is set, hardware automatically resets this bit to 0. When EDO DRAM is used, this bit must not be set to 1. 0 is returned when read Bank 1 capacity 00 : Bank 1 is not installed 01 : 16 Mbits 10 : 64 Mbits 11 : Reserved
14 to 12 11, 10
Reserved B1Config(1:0)
9 8
Reserved Bstreftype
0 is returned when read Burst refresh type. This bit determines the number of CBR burst refresh cycles executed before entering and exiting self-refresh mode. 0 : 8 rows refreshed 1 : All rows refreshed
7
BstRefr
Burst refresh enable. This bit enables or disables burst CBR refresh cycles when entering or exiting self-refresh mode. 0 : Disable CBR burst refresh 1 : Enable CBR burst refresh Burst and distributive CBR refresh are mixed if this bit is set to 1. For some kind of DRAMs, mix use of burst and distributive CBR refresh may not be allowed.
6
EDOAsym
EDO DRAM configuration 0 : Asymmetrical 16 Mbit EDO DRAM : 12 rows by 8 columns 64 Mbit EDO DRAM : 13 rows by 9 columns 1 : Symmetrical 16 Mbit EDO DRAM : 10 rows by 10 columns 64 Mbit EDO DRAM : Setting prohibited
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(2/2)
Bit 5 to 3 2, 1 Reserved B0Config(1:0) Name 0 is returned when read Bank 0 Capacity 00 : Bank 0 is not installed 01 : 16 Mbit 10 : 64 Mbit 11 : Reserved 0 EDO/SDRAM DRAM Type 0 : EDO DRAM 1 : SDRAM Function
This register is used to set DRAM type (capacity, type, organization, etc.) of Bank 0 and Bank 1. Caution When using SDRAMs, set the Init bit to 1 to initialize SDRAMs before accessing them after an RTC reset or RSTSW reset is canceled or after the VR4181 restores from the Hibernate mode. An initialization of SDRAMs must be executed until the VR4181 issues the first CBR auto refresh cycle. Remark During the 64 Mbit SDRAM mode register write, A13 of the address bus is at high level. On the other hand, during the 16 Mbit SDRAM mode register write, A13 is at low level. In order to initialize 64-Mbit SDRAM correctly, software must execute the following sequence. <1> Set B0Config(1:0) and B1Config(1:0) bits of MEMCFG_REG register to 01 <2> Set MODE_REG register to appropriate value (0x00n7, n can be any value) <3> Initialize SDRAM by setting Init bit of MEMCFG_REG register <4> Set B0Config(1:0) and B1Config(1:0) bits of MEMCFG_REG register to 10
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6.5.3 MODE_REG (0x0A00 0308)
Bit Name R/W At reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 0 R/W 0 10 0 R/W 0 9 BR-SW R/W 0 8 TE-Ven1 R/W 0
Bit Name R/W At reset
7 TE-Ven2 R/W 0
6 LTMode2 R/W 0
5 LTMode1 R/W 0
4 LTMode0 R/W 0
3 WT R/W 0
2 BL2 R/W 0
1 BL1 R/W 0
0 BL0 R/W 0
Bit 15 to 12 11, 10 9 Reserved 0 BR-SW
Name 0 is returned when read
Function
These bits should be always written to 00. Burst read - single write This bit should be always written to 0. These two bits define a JEDEC test cycle and vendor specific cycles. These bits should be always written to 00. CAS latency mode
Note
8, 7
TE-Ven(1:2)
6 to 4
LTMode(2:0)
010 : 2 clocks 011 : 3 clocks Others : Reserved 3 WT Wrap type for the burst cycles. This bit should be always written to 0. 0 : Sequential (default) 2 to 0 BL(2:0) Burst length. These bits should be always written to 111. 111 : Full page (When WT = 0 only. Setting prohibited when WT = 1)
Note The CAS latency mode must be set according to the operation frequency of the SDCLK (SDRAM clock). This register is used to set the value output to ADD(13:0) pins during the SDRAM mode register setting cycle. This register should be written before the Init bit of MEMCFG_REG register is set to 1.
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6.5.4 SDTIMINGREG (0x0A00 030C)
Bit Name R/W At reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R/W 0 8 Reserved R/W 0
Bit Name R/W At reset
7 TRAS1 R/W 0
6 TRAS0 R/W 0
5 TRC1 R/W 0
4 TRC0 R/W 0
3 TRP1 R/W 0
2 TRP0 R/W 0
1 TRCD1 R/W 0
0 TRCD0 R/W 0
Bit 15 to 10 9 8 7, 6 Reserved Reserved Reserved TRAS(1:0)
Name 0 is returned when read Write 0 when write. Write 1 when write.
Note Note
Function
TRAS in clock cycles 00 : 3 SDCLK (for 25 MHz SDCLK) 01 : 5 SDCLK (for 66, 50, or 33 MHz SDCLK) Others : Prohibited
5, 4
TRC(1:0)
TRC in clock cycles 00 : 4 SDCLK (for 25 MHz SDCLK) 01 : 7 SDCLK (for 66, 50, or 33 MHz SDCLK) Others : Prohibited
3, 2
TRP(1:0)
TRP in clock cycles 00 : 1 SDCLK (for 25 MHz SDCLK) 01 : Prohibited 10 : 3 SDCLK (for 66, 50, or 33 MHz SDCLK) 11 : Prohibited
1, 0
TRCD(1:0)
TRCD in clock cycles 00 : 1 SDCLK (for 25 MHz SDCLK) 01 : 2 SDCLK (for 66, 50, or 33 MHz SDCLK) Others : Prohibited
Note Bits 9 and 8 must be set to 01 before using SDRAM. Especially, be sure to set 1 to bit 8 since its default value is 0. When these bits are not 01, the VR4181 may not work correctly. This register is used to set SDRAM timing parameters. Software must set this register suitable before using SDRAM.
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6.6 ISA Bridge
The VR4181 has an external bus used for ROM, flash memory, DRAM, and I/O. This bus's operation emulates an ISA bus at accesses to external memory and I/O spaces. The VR4181 also uses an ISA bus internally for the slow, embedded peripherals. Among the pins used for accesses in the external ISA bus, UBE#, IOCS16#, IORDY, IOWR#, and IORD# share the pins with GPIO(20:16), as well as MEMCS16# with LOCLK. To use these pins as an external ISA bus interface, make settings in the GIU in advance.
6.7 ISA Bridge Register Set
The following registers provide configuration and control of the ISA Bridge. Table 6-4. ISA Bridge Registers
Physical address 0x0B00 02C0 0x0B00 02C2 0x0B00 02C4 R/W R/W R/W R/W Register symbol ISABRGCTL ISABRGSTS XISACTL ISA Bridge control register ISA Bridge status register External ISA control register Function
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6.7.1 ISABRGCTL (0x0B00 02C0)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 Reserved R 0 0
2 Reserved R 0 0
1 PCLKDIV1 R/W 0 0
0 PCLKDIV0 R/W 0 0
Bit 15 to 2 1, 0 Reserved
Name 0 is returned when read
Function
PCLKDIV(1:0)
PCLK (peripheral clock) divisor rate selection. These bits select the operating frequency of PCLK. 00 : TClock / 8 01 : TClock / 4 10 : TClock / 2 11 : TClock / 1
This register is used to set the PCLK divisor rate. PCLK is a clock for internal ISA peripherals, and its frequency must be set to between 18.432 MHz and 33 MHz.
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6.7.2 ISABRGSTS (0x0B00 02C2)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 Reserved R 0 0
2 Reserved R 0 0
1 Reserved R 0 0
0 IDLE R 0 0
Bit 15 to 1 0 Reserved IDLE
Name 0 is returned when read ISA Bridge status 0 : ISA Bridge is busy 1 : ISA Bridge is idle
Function
This register shows the ISA Bridge operation status.
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6.7.3 XISACTL (0x0B00 02C4) (1/2)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 EXTRESULT R/W 1 1 9 INTRESULT R/W 0 0 8 EXBUFFEN R/W 1 1
Bit Name R/W RTCRST Other resets
7 MEMWS1 R/W 0 0
6 MEMWS0 R/W 0 0
5 IOWS1 R/W 0 0
4 IOWS0 R/W 0 0
3 Reserved R 0 0
2 Reserved R 0 0
1 SCLKDIV1 R/W 0 0
0 SCLKDIV0 R/W 0 0
Bit 15 to 11 10 Reserved
Name 0 is returned when read External ISA result cycle enable
Function
EXTRESULT
0 : Disabled. The MBA bus arbiter waits until an external ISA read is finished. 1 : Enabled. The MBA bus arbiter issues a result cycle to the ISA bridge after finishing an external ISA cycle and obtains results of the read. Normally, set 1 to this bit. 9 INTRESULT Internal ISA result cycle enable 0 : Disabled. The MBA bus arbiter waits until an internal ISA read is finished. 1 : Enabled. The MBA bus arbiter issues a result cycle to the ISA bridge after finishing an internal ISA cycle and obtains results of the read. Normally, set 1 to this bit. 8 EXBUFFEN External buffer enable 0 : Enable external buffer control with SYSDIR and SYSEN# pins 1 : Disable external buffer control with SYSDIR and SYSEN# pins (SYSEN# and SYSDIR pins are both forced to low level) 7, 6 MEMWS(1:0) External ISA memory wait states (read/write strobe width) 00 : 1.5 SYSCLK cycles 01 : 2.5 SYSCLK cycles 10 : 3.5 SYSCLK cycles 11 : 4.5 SYSCLK cycles 5, 4 IOWS(1:0) External ISA I/O wait states (read/write strobe width) 00 : 1.5 SYSCLK cycles 01 : 2.5 SYSCLK cycles 10 : 3.5 SYSCLK cycles 11 : 4.5 SYSCLK cycles
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(2/2)
Bit 3, 2 1, 0 Reserved SCLKDIV(1:0) Name 0 is returned when read SYSCLK (external ISA bus clock) divisor rate selection 00 : PCLK / 2 01 : PCLK / 3 10 : PCLK / 6 11 : PCLK / 8 Function
This register is used to set the external ISA configurations. SYSCLK is an operation clock for the external ISA bus, and is output only when an external ISA cycle is generated.
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CHAPTER 7 DMA CONTROL UNIT (DCU)
7.1 General
The DMA Control Unit (DCU) controls four channels of DMA transfer. Two of them are allocated for the AIU (microphone and speaker), though the remaining two are reserved for future use. The Microphone channel performs the I/O-to-memory transfers from the A/D converter included in the AIU to memory. The Speaker channel performs the memory-to-I/O transfers from memory to the D/A converter included in the AIU. Each DMA channel supports both the primary and the secondary memory buffers. The Source1/Source2 or Destination1/Destination2 Address registers for the associated channel determine the starting address of each memory buffer. The sizes of memory buffers are determined in the associated record length registers. The DCU uses the primary and secondary DMA buffers alternately when transferring. For example, during the first DMA transfer following either hardware or software reset of the DCU, the transfer starts using the primary DMA buffer. If the total number of DMA transfers through the primary DMA buffer reaches the value set in the associated record length register, the next DMA transfer is performed using the secondary DMA buffer. Software must keep track of which buffer contains valid DMA data. Software may configure any of the DMA channels to operate in one of two modes; auto-stop or auto-load. When a channel is configured to operate in auto-stop mode, the DCU terminates DMA transfers after the number of transfers specified by the record length register and automatically resets the DMA mask bit for that channel. Once the mask bit is automatically reset, the DCU ignores all subsequent DMA requests for this channel. To resume DMA transfers in this mode, software must again unmask DMA transfers for this channel. Once software unmasks DMA requests, the DCU resumes DMA transfers utilizing the secondary memory buffer. When a channel is configured to operate in auto-load mode, the DCU does not terminate DMA transfers after the number of DMA transfers specified by the record length register. Instead, the DCU automatically switchs to the secondary DMA buffer and continues servicing DMA requests. In either mode, auto-stop or auto-load, the DCU always alternates the DMA buffer to be used between the primary and secondary buffers. Software must keep track of the total number of transfers and assure the appropriate DMA buffer is loaded with new DMA data before starting another DMA transfer. The DCU can be programmed to generate an EOP (end of process) interrupt request independent of auto-stop or auto-load mode. An EOP interrupt request is generated once the number of DMA transfers has reached to the value specified by the record length register.
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Priority of each DMA channel is fixed. The channel priority is as follows. 1. AIU Microphone channel 2. AIU Speaker channel DCU runs at the MBA bus clock (TClock) frequency. Remark The DCU contains a 32-bit temporary storage register for each DMA channel. For memory-to-I/O transfers, the DCU performs a 32-bit memory read from DRAM and stores the read data into the temporary storage register. The DCU then transfers data from this register to the target I/O device. For a 16-bit device such as the Speaker channel, the DCU performs two I/O writes to the D/A converter for each memory read. During DMA transfers, all DCU registers are write-protected if valid data is present in the temporary storage registers. Because of this, to start DMA transfers, software must read the register that is written immediately after the write to confirm that the register has been correctly set.
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7.2 DCU Registers
Table 7-1. DCU Registers
Physical address 0x0A00 0020 0x0A00 0022 0x0A00 0024 0x0A00 0026 0x0A00 0028 0x0A00 002A 0x0A00 002C 0x0A00 002E 0x0A00 0040 0x0A00 0046 0x0A00 0600 to 0x0A00 0654 0x0A00 0658 0x0A00 065A 0x0A00 065C 0x0A00 065E 0x0A00 0660 0x0A00 0662 0x0A00 0664 0x0A00 0666 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register symbol MICDEST1REG1 MICDEST1REG2 MICDEST2REG1 MICDEST2REG2 SPKRSRC1REG1 SPKRSRC1REG2 SPKRSRC2REG1 SPKRSRC2REG2 DMARSTREG AIUDMAMSKREG - MICRCLENREG SPKRCLENREG - MICDMACFGREG SPKDMACFGREG DMAITRQREG DMACTLREG DMAITMKREG Function Microphone destination 1 address register 1 Microphone destination 1 address register 2 Microphone destination 2 address register 1 Microphone destination 2 address register 2 Speaker source 1 address register 1 Speaker source 1 address register 2 Speaker source 2 address register 1 Speaker source 2 address register 2 DMA reset register Audio DMA mask register Reserved. Write 0 when write. 0 is returned after a read.
R/W R/W R/W R/W R/W R/W R/W R/W
Microphone record length register Speaker record length register Reserved. Write 0 when write. 0 is returned after a read. Microphone DMA configuration register Speaker DMA configuration register DMA interrupt request register DMA control register DMA interrupt mask register
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7.2.1 Microphone destination 1 address registers (1) MICDEST1REG1 (0x0A00 0020)
Bit Name R/W At reset 15 MD1A15 R/W 0 14 MD1A14 R/W 0 13 MD1A13 R/W 0 12 MD1A12 R/W 0 11 MD1A11 R/W 0 10 MD1A10 R/W 0 9 MD1A9 R/W 0 8 MD1A8 R/W 0
Bit Name R/W At reset
7 MD1A7 R/W 0
6 MD1A6 R/W 0
5 MD1A5 R/W 0
4 MD1A4 R/W 0
3 MD1A3 R/W 0
2 MD1A2 R/W 0
1 MD1A1 R/W 0
0 MD1A0 R/W 0
Bit 15 to 0
Name MD1A(15:0)
Function Lower 16 bits (A(15:0)) of DMA destination 1 address for Microphone
(2) MICDEST1REG2 (0x0A00 0022)
Bit Name R/W At reset 15 MD1A31 R/W 0 14 MD1A30 R/W 0 13 MD1A29 R/W 0 12 MD1A28 R/W 0 11 MD1A27 R/W 0 10 MD1A26 R/W 0 9 MD1A25 R/W 0 8 MD1A24 R/W 0
Bit Name R/W At reset
7 MD1A23 R/W 0
6 MD1A22 R/W 0
5 MD1A21 R/W 0
4 MD1A20 R/W 0
3 MD1A19 R/W 0
2 MD1A18 R/W 0
1 MD1A17 R/W 0
0 MD1A16 R/W 0
Bit 15 to 0
Name MD1A(31:16)
Function Upper 16 bits (A(31:16)) of DMA destination 1 address for Microphone
These two registers specify the destination memory address of the primary DMA buffer for the Microphone channel.
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7.2.2 Microphone destination 2 address registers (1) MICDEST2REG1 (0x0A00 0024)
Bit Name R/W At reset 15 MD2A15 R/W 0 14 MD2A14 R/W 0 13 MD2A13 R/W 0 12 MD2A12 R/W 0 11 MD2A11 R/W 0 10 MD2A10 R/W 0 9 MD2A9 R/W 0 8 MD2A8 R/W 0
Bit Name R/W At reset
7 MD2A7 R/W 0
6 MD2A6 R/W 0
5 MD2A5 R/W 0
4 MD2A4 R/W 0
3 MD2A3 R/W 0
2 MD2A2 R/W 0
1 MD2A1 R/W 0
0 MD2A0 R/W 0
Bit 15 to 0
Name MD2A(15:0)
Function Lower 16 bits (A(15:0)) of DMA destination 2 address for Microphone
(2) MICDEST2REG2 (0x0A00 0026)
Bit Name R/W At reset 15 MD2A31 R/W 0 14 MD2A30 R/W 0 13 MD2A29 R/W 0 12 MD2A28 R/W 0 11 MD2A27 R/W 0 10 MD2A26 R/W 0 9 MD2A25 R/W 0 8 MD2A24 R/W 0
Bit Name R/W At reset
7 MD2A23 R/W 0
6 MD2A22 R/W 0
5 MD2A21 R/W 0
4 MD2A20 R/W 0
3 MD2A19 R/W 0
2 MD2A18 R/W 0
1 MD2A17 R/W 0
0 MD2A16 R/W 0
Bit 15 to 0
Name MD2A(31:16)
Function Upper 16 bits (A(31:16)) of DMA destination 2 address for Microphone
These two registers specify the destination memory address of the secondary DMA buffer for the Microphone channel.
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7.2.3 Speaker source 1 address registers (1) SPKRSRC1REG1 (0x0A00 0028)
Bit Name R/W At reset 15 SS1A15 R/W 0 14 SS1A14 R/W 0 13 SS1A13 R/W 0 12 SS1A12 R/W 0 11 SS1A11 R/W 0 10 SS1A10 R/W 0 9 SS1A9 R/W 0 8 SS1A8 R/W 0
Bit Name R/W At reset
7 SS1A7 R/W 0
6 SS1A6 R/W 0
5 SS1A5 R/W 0
4 SS1A4 R/W 0
3 SS1A3 R/W 0
2 SS1A2 R/W 0
1 SS1A1 R/W 0
0 SS1A0 R/W 0
Bit 15 to 0 SS1A(15:0)
Name
Function Lower 16 bits (A(15:0)) of DMA source 1 address for Speaker
(2) SPKRSRC1REG2 (0x0A00 002A)
Bit Name R/W At reset 15 SS1A31 R/W 0 14 SS1A30 R/W 0 13 SS1A29 R/W 0 12 SS1A28 R/W 0 11 SS1A27 R/W 0 10 SS1A26 R/W 0 9 SS1A25 R/W 0 8 SS1A24 R/W 0
Bit Name R/W At reset
7 SS1A23 R/W 0
6 SS1A22 R/W 0
5 SS1A21 R/W 0
4 SS1A20 R/W 0
3 SS1A9 R/W 0
2 SS1A18 R/W 0
1 SS1A17 R/W 0
0 SS1A16 R/W 0
Bit 15 to 0
Name SS1A(31:16)
Function Upper 16 bits (A(31:16)) of DMA source 1 address for Speaker
These two registers specify the source memory address of the primary DMA buffer for the Speaker channel.
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7.2.4 Speaker source 2 address registers (1) SPKRSRC2REG1 (0x0A00 002C)
Bit Name R/W At reset 15 SS2A15 R/W 0 14 SS2A14 R/W 0 13 SS2A13 R/W 0 12 SS2A12 R/W 0 11 SS2A11 R/W 0 10 SS2A10 R/W 0 9 SS2A9 R/W 0 8 SS2A8 R/W 0
Bit Name R/W At reset
7 SS2A7 R/W 0
6 SS2A6 R/W 0
5 SS2A5 R/W 0
4 SS2A4 R/W 0
3 SS2A3 R/W 0
2 SS2A2 R/W 0
1 SS2A1 R/W 0
0 SS2A0 R/W 0
Bit 15 to 0 SS2A(15:0)
Name
Function Lower 16 bits (A(15:0)) of DMA source 2 address for Speaker
(2) SPKRSRC2REG2 (0x0A00 002E)
Bit Name R/W At reset 15 SS2A31 R/W 0 14 SS2A30 R/W 0 13 SS2A29 R/W 0 12 SS2A28 R/W 0 11 SS2A27 R/W 0 10 SS2A26 R/W 0 9 SS2A25 R/W 0 8 SS2A24 R/W 0
Bit Name R/W At reset
7 SS2A23 R/W 0
6 SS2A22 R/W 0
5 SS2A21 R/W 0
4 SS2A20 R/W 0
3 SS2A9 R/W 0
2 SS2A18 R/W 0
1 SS2A17 R/W 0
0 SS2A16 R/W 0
Bit 15 to 0
Name SS2A(31:16)
Function Upper 16 bits (A(31:16)) of DMA source 2 address for Speaker
These two registers specify the source memory address of the secondary DMA buffer for the Speaker channel.
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7.2.5 DMARSTREG (0x0A00 0040)
Bit Name R/W At reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 Reserved R 0
Bit Name R/W At reset
7 Reserved R 0
6 Reserved R 0
5 Reserved R 0
4 Reserved R 0
3 Reserved R 0
2 Reserved R 0
1 Reserved R 0
0 DMARST R/W 1
Bit 15 to 1 0 Reserved DMARST
Name 0 is returned after a read. Resets DMA functions 0 : Resets DMA channels 1 : Normal operation
Function
When DMARST bit is written to zero, all active DMA transfers are immediately terminated and the DCU enters in the reset state. While DMARST bit is 0, all DMA requests become pending until this bit is set to 1. 7.2.6 AIUDMAMSKREG (0x0A00 0046)
Bit Name R/W At reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 Reserved R 0
Bit Name R/W At reset
7 Reserved R 0
6 Reserved R 0
5 Reserved R 0
4 Reserved R 0
3 MICMSK R/W 0
2 SPKMSK R/W 0
1 Reserved R 0
0 Reserved R 0
Bit 15 to 4 3 Reserved MICMSK
Name 0 is returned after a read.
Function
Masks DMA for Microphone (audio input) channel 0 : Microphone channel disabled 1 : Microphone channel enabled
2
SPKMSK
Masks DMA for Speaker (audio output) channel 0 : Speaker channel disabled 1 : Speaker channel enabled
1, 0
Reserved
0 is returned after a read.
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7.2.7 MICRCLENREG (0x0A00 0658)
Bit Name R/W At reset 15 MICRL15 R/W 1 14 MICRL14 R/W 1 13 MICRL13 R/W 1 12 MICRL12 R/W 1 11 MICRL11 R/W 1 10 MICRL10 R/W 1 9 MICRL9 R/W 1 8 MICRL8 R/W 1
Bit Name R/W At reset
7 MICRL7 R/W 1
6 MICRL6 R/W 1
5 MICRL5 R/W 1
4 MICRL4 R/W 1
3 MICRL3 R/W 1
2 MICRL2 R/W 1
1 MICRL1 R/W 1
0 MICRL0 R/W 1
Bit 15 to 0
Name MICRL(15:0)
Function DMA Record Length for Microphone. MICRL0 bit must be written to zero.
This register defines the number of 16-bit words to be transferred during DMA operation in the Microphone channel. 7.2.8 SPKRCLENREG (0x0A00 065A)
Bit Name R/W At reset 15 SPKRL15 R/W 1 14 SPKRL14 R/W 1 13 SPKRL13 R/W 1 12 SPKRL12 R/W 1 11 SPKRL11 R/W 1 10 SPKRL10 R/W 1 9 SPKRL9 R/W 1 8 SPKRL8 R/W 1
Bit Name R/W At reset
7 SPKRL7 R/W 1
6 SPKRL6 R/W 1
5 SPKRL5 R/W 1
4 SPKRL4 R/W 1
3 SPKRL3 R/W 1
2 SPKRL2 R/W 1
1 SPKRL1 R/W 1
0 SPKRL0 R/W 1
Bit 15 to 0
Name SPKRL(15:0)
Function DMA Record Length for Speaker. SPKRL0 bit must be written to zero.
This register defines the number of 16-bit words to be transferred during DMA operation in the Speaker channel.
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7.2.9 MICDMACFGREG (0x0A00 065E)
Bit Name R/W At reset 15 Reserved R 0 14 MicDsize1 R 0 13 MicDsize0 R 1 12 MicSrctype R 1 11 MicDestype R 0 10 Reserved R 0 9 Reserved R 0 8 MicLoad R/W 0
Bit Name R/W At reset
7 Reserved R 0
6 Reserved R 0
5 Reserved R 0
4 Reserved R 0
3 Reserved R 0
2 Reserved R 0
1 Reserved R 0
0 Reserved R 0
Bit 15 14, 13 Reserved
Name 0 is returned after a read.
Function
MicDsize(1:0)
Indicates Microphone channel data size 01 : 16 bits Values other than above do not appear.
12
MicSrctype
Indicates Microphone channel source address type 1 : I/O 0 does not appear.
11
MicDestype
Indicates Microphone channel destination address type 0 : Memory 1 does not appear.
10, 9 8
Reserved MicLoad
0 is returned after a read. DMA auto-stop/auto-load mode setting for Microphone channel 0 : Auto-stop 1 : Auto-load When this bit is set to 1, the DCU automatically begins transferring data to the secondary buffer when the primary buffer is full. When this bit is set to 0, the DCU uses the primary buffer only.
7 to 0
Reserved
0 is returned after a read.
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7.2.10 SPKDMACFGREG (0x0A00 0660)
Bit Name R/W At reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 Reserved R 0
Bit Name R/W At reset
7 Reserved R 0
6 SpkDsize1 R 0
5 SpkDsize0 R 1
4 SpkSrctype R 0
3 SpkDestype R 1
2 Reserved R 0
1 Reserved R 0
0 SpkLoad R/W 0
Bit 15 to 7 6, 5 Reserved
Name 0 is returned after a read. Indicates Speaker channel data size 01 : 16 bits
Function
SpkDsize(1:0)
Values other than above do not appear. 4 SpkSrctype Indicates Speaker channel source address type 0 : Memory 1 does not appear. 3 SpkDestype Indicates Speaker channel destination address type 1 : I/O 0 does not appear. 2, 1 0 Reserved SpkLoad 0 is returned after a read. DMA auto-stop/auto-load mode setting for Speaker channel 0 : Auto-stop 1 : Auto-load When this bit is set to 1, the DCU automatically begins transferring data from the secondary buffer when the primary buffer is empty. When this bit is set to 0, the DCU uses the primary buffer only.
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7.2.11 DMAITRQREG (0x0A00 0662)
Bit Name R/W At reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 Reserved R 0
Bit Name R/W At reset
7 Reserved R 0
6 Reserved R 0
5 SpkEOP R/W 0
4 MicEOP R/W 0
3 Reserved R 0
2 Reserved R/W 0
1 Reserved R/W 0
0 Reserved R 0
Bit 15 to 6 5 Reserved SpkEOP
Name 0 is returned after a read.
Function
Speaker channel end of process (EOP) interrupt status 0 : None 1 : Speaker channel EOP interrupt pending The interrupt request is cleared when this bit is written to 1.
4
MicEOP
Microphone channel EOP interrupt status 0 : None 1 : Microphone channel EOP interrupt pending The interrupt request is cleared when this bit is written to 1.
3 2, 1 0
Reserved Reserved Reserved
0 is returned after a read. Write 0 when write. 0 is returned after a read. 0 is returned after a read.
This register indicates interrupt status of each DMA channel by end of process (EOP). Once an interrupt occurs, clear the interrupt request by writing a zero to the corresponding status bit in this register.
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CHAPTER 7 DMA CONTROL UNIT (DCU)
7.2.12 DMACTLREG (0x0A00 0664)
Bit Name R/W At reset 15 SpkCNT1 R/W 0 14 SpkCNT0 R/W 0 13 MicCNT1 R/W 0 12 MicCNT0 R/W 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 Reserved R 0
Bit Name R/W At reset
7 Reserved R/W 0
6 Reserved R/W 0
5 Reserved R/W 0
4 Reserved R/W 0
3 Reserved R/W 0
2 Reserved R/W 0
1 Reserved R/W 0
0 Reserved R/W 0
Bit 15, 14
Name SpkCNT(1:0)
Function Speaker channel source address count control 00 : Increment 01 : Decrement Others : Reserved
13, 12
MicCNT(1:0)
Microphone channel destination address count control 00 : Increment 01 : Decrement Others : Reserved
11 to 8 7 to 0
Reserved Reserved
0 is returned after a read. Write 0 when write. 0 is returned after a read.
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7.2.13 DMAITMKREG (0x0A00 0666)
Bit Name R/W At reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 Reserved R 0
Bit Name R/W At reset
7 Reserved R 0
6 Reserved R 0
5 SpkEOPMsk R/W 0
4 MicEOPMsk R/W 0
3 Reserved R 0
2 Reserved R/W 0
1 Reserved R/W 0
0 Reserved R 0
Bit 15 to 6 5 Reserved
Name 0 is returned after a read.
Function
SpkEOPMsk
Speaker channel end of process (EOP) interrupt mask 0 : Disable 1 : Enable
4
MicEOPMsk
Microphone channel EOP interrupt mask 0 : Disable 1 : Enable
3 2, 1 0
Reserved Reserved Reserved
0 is returned after a read. Write 0 when write. 0 is returned after a read. 0 is returned after a read.
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CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI)
8.1 Overview
The CSI manages communication via a synchronous serial bus. The CSI of the VR4181 has the following key characteristics: * Slave-only synchronous serial interface * Able to transmit and receive data simultaneously * Supports fixed 8-bit character length * Supports burst lengths of 1 to 65535 bits * Continuous transfer mode for of peripherals supporting auto-scan * Programmable clock phase and clock polarity The CSI interface shares pins with GPIO signals as follows. When using the CSI, set these pins to use as CSI signals in the registers of the GIU in advance.
GPIO Pin GPIO10 CSI Signal FRM Definition Optional multifunction control input. In one mode, FRM determines data direction (transmit or receive). In the other mode, FRM enables (low level) or inhibits (high level) transmissions. Serial clock input (Maximum frequency: 1.6 MHz) Serial data output Serial data input
GPIO2 GPIO1 GPIO0
SCK SO SI
Caution
No clock is supplied to the CSI in the initial state. When using the CSI, set the MSKCSUPCLK bit of the CMUCLKMSK register in the MBA Host Bridge to 1 in advance so that a clock is supplied.
8.2 Operation of CSI
8.2.1 Transmit/receive operations Transmit and receive operations are initiated by an external master to drive the serial clock, SCK. The characteristics of the protocol are controlled by the CSIMODE register, in particular by CKPOL, CKMD, FRMEN, and FRMMD bits. CKPOL and CKMD bits control the relationship between data driven on SO and SI, and the phase of the serial clock input to SCK. FRMEN and FRMMD bits enable and control the FRM input.
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8.2.2 SCK phase and CSI transfer timing The external master drives SCK and SI and samples data driven on SO. The CSI supports 4 basic operating modes of SCK depending on the settings of CKPOL and CKMD bits. These are illustrated in the following figure. Figure 8-1. SCK and SI/SO Relationship
(a) When CKMD bit = 0
SCK (input) (when CKPOL = 0)
SCK (input) (when CKPOL = 1)
SI (input)
SO (output)
D7
D6
D5
D4
D3
D2
D1
D0
Undefined
(b) When CKMD bit = 1
SCK (input) (when CKPOL = 0)
SCK (input) (when CKPOL = 1)
SI (input)
SO (output)
Undefined
D7
D6
D5
D4
D3
D2
D1
D0
Caution
When the CKMD bit is set to 1, the next byte data is output during the latter half of the cycle for the eighth bit of a transmit data.
This figure illustrates CSI cycles when the FRM input is disabled (FRMEN bit = 0) or configured to provide direction control (FRMEN bit = 1 and FRMMD bit = 0). When FRMEN bit = 1 and FRMMD bit = 1, SO is driven as high impedance during a high level input to FRM. In addition, this figure illustrates the CSI cycles when bit 7 of a data is transmitted or received first (i.e. when the LSBMSB bit of the CSIMODE register = 0).
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The four modes of SCK are described below. (1) When CKMD bit = 0 and CKPOL bit = 0 * Transmission The first transmit data bit is output before the first rising edge of SCK. The second transmit data and those that follow are output synchronized with the falling edge of SCK. Therefore, the external master must sample the data synchronizing with the rising edge of SCK. * Reception The external master must output the first data bit before the first rising edge of SCK. The VR4181 samples receive data synchronizing with the rising edge of SCK. Therefore, the external master must output data synchronizing with the falling edge of SCK. (2) When CKMD bit = 0 and CKPOL bit = 1 * Transmission The first transmit data bit is output before the first falling edge of SCK. The second transmit data bit and those that follow are output synchronized with the rising edge of SCK. Therefore, the external master must sample the data synchronizing with the falling edge of SCK. * Reception The external master must output the first data bit before the first falling edge of SCK. The VR4181 samples receive data synchronizing with the falling edge of SCK. Therefore, the external master must output data synchronizing with the rising edge of SCK. (3) When CKMD bit = 1 and CKPOL bit = 0 * Transmission The first transmit data bit is output synchronized with the first rising edge of SCK. The second transmit data bit and those that follow are output synchronized with the rising edge of SCK. Therefore, the external master must sample the data synchronizing with the falling edge of SCK. * Reception The VR4181 samples receive data synchronizing with the falling edge of SCK. Therefore, the external master must output data synchronizing with the rising edge of SCK. (4) When CKMD bit = 1 and CKPOL bit = 1 * Transmission The first transmit data bit is output synchronized with the first falling edge of SCK. The second transmit data bit and those that follow are output synchronized with the falling edge of SCK. Therefore, the external master must sample the data synchronizing with the rising edge of SCK. * Reception The VR4181 samples receive data synchronizing with the rising edge of SCK. Therefore, the external master must output data synchronizing with the falling edge of SCK.
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8.2.3 CSI transfer types (1) Burst mode Burst mode is supported for both transmit and receive transfers. Burst lengths for transmission and reception are independently programmable and can be set from 1 to 65535 bits. The transmit and receive shift registers are both 8-bit lengths. During burst mode, when the receive shift register goes "full", the data is automatically transferred to the receive FIFO. When the transmit shift register goes "empty", it is automatically reloaded from the transmit FIFO. Once the burst length has been set and the burst transaction enabled, the CSI behaves as follows: The CSI begins tracking the number of bits transmitted and/or received. At the end of each bit transfer, the bit count is updated and compared to the corresponding burst length value (transmit and/or receive). If the number of bits transferred is equal to the burst length, the CSI shift register is halted. If the transfer is a reception, the contents of the shift register will be copied to the receive FIFO, a Receive Burst End interrupt request will be generated if unmasked, and additional activities on the SCK input will be ignored. If the transfer is a transmission, a Transmit Burst End interrupt request will be generated if unmasked and additional SCK cycles will cause an invalid data to be output on SO. (2) Continuous mode Continuous mode transfers are always defined as 8-bit fixed length transfers. In continuous mode, software must control the flow of data between the VR4181 and the external master. When continuous mode is enabled and the receive shift register goes "full", the data is automatically transferred to the receive FIFO. When the transmit shift register goes "empty", it is automatically reloaded from the transmit FIFO.
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8.2.4 Transmit and receive FIFOs The CSI contains two 8-deep 16-bit FIFOs. One is for transmission and the other for reception. The transmit and receive shift registers access the FIFOs by 8 bits at a time. The CPU core accesses the FIFOs in either 8-bit or 16-bit units. The threshold of each FIFO is independently programmable. For the transmit FIFO, an interrupt request is generated to inform the CPU that 1, 2, or 4 16-bit words are empty in the FIFO. For the receive FIFO, an interrupt request is generated to inform the CPU core that 1, 2, or 4 16-bit words can be read from the FIFO. The FIFO control logic can also generate interrupt requests to signal an overrun condition for the receive FIFO or an underrun condition for the transmit FIFO. An overrun occurs when the receive shift register attempts to transfer data to a location in the FIFO which has not be read by the CPU core. An underrun occurs when the transmit shift register attempts to load a value from the FIFO which has not been updated by the CPU core. (1) Overrun/underrun errors When an overrun error occurs, the receive FIFO logic generates an overrun interrupt request if unmasked, and overwrites the next location in the FIFO with the contents of the receive shift register. When an underrun error occurs, the transmit FIFO logic generates an underrun interrupt request if unmasked, and reloads the transmit shift register with the contents of the next location in the FIFO. The software must recover the data loss caused by the overrun or underrun error.
8.3 CSI Registers
The CSI provides the following registers: Table 8-1. CSI Registers
Physical address 0x0B00 0900 0x0B00 0902 0x0B00 0904 0x0B00 0906 0x0B00 0908 0x0B00 090A 0x0B00 090C 0x0B00 090E R/W R/W R R/W R/W R/W R/W R/W R/W Register symbol CSIMODE CSIRXDATA CSITXDATA CSILSTAT CSIINTMSK CSIINTSTAT CSITXBLEN CSIRXBLEN CSI mode register CSI receive data register CSI transmit data register CSI line status register CSI interrupt mask register CSI interrupt status register CSI transmit burst length register CSI receive burst length register Function
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8.3.1 CSIMODE (0x0B00 0900) (1/2)
Bit Name R/W RTCRST Other resets 15 FRMEN R/W 0 0 14 TXEN R/W 0 0 13 TXBMD R/W 0 0 12 TXCLR R/W 0 0 11 Reserved R 0 0 10 RXEN R/W 0 0 9 RXBMD R/W 0 0 8 RXCLR R/W 0 0
Bit Name R/W RTCRST Other resets
7 FRMMD R/W 0 0
6 CKPOL R/W 0 0
5 CKMD R/W 0 0
4 Reserved R 0 0
3 Reserved R 0 0
2 Reserved R 0 0
1 Reserved R 0 0
0 LSBMSB R/W 0 0
Bit 15 FRMEN
Name CSI FRM enable
Function
0 : Disabled. FRM signal input is ignored. 1 : Enabled. Mode is set by FRMMD bit. 14 TXEN CSI transmit enable 0 : Disable 1 : Enable
Remark When using the transmit function only, communication must be performed with the RXEN bit = 0 and the RXCLR bit = 1. 13 TXBMD CSI transmit burst mode 0 : Continuous mode 1 : Burst mode 12 TXCLR CSI transmit buffer clear 0 : Enable transmit shift register and FIFO 1 : Reset transmit shift register and FIFO 11 10 Reserved RXEN 0 is returned after read CSI receive enable 0 : Disable 1 : Enable
Remark When using the receive function only, communication must be performed with the TXEN bit = 0 and the TXCLR bit = 1. 9 RXBMD CSI receive burst mode 0 : Continuous mode 1 : Burst mode 8 RXCLR CSI receive buffer clear 0 : Enable receive shift register and FIFO 1 : Reset receive shift register and FIFO
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Bit 7 FRMMD Name FRM mode 0 : FRM controls transfer directions (receive when FRM= 1, transmit when FRM= 0) 1 : FRM enables transfers (transmit/receive enabled when FRM = 0) 6 CKPOL CSI clock polarity
Note
Function
0 : SCK is active high (1st transition is low to high) 1 : SCK is active low (1st transition is high to low) 5 CKMD CSI clocking mode
Note
0 : Character data is valid prior to the 1st transition of SCK 1 : Character data is valid at the 1st transition of SCK 4 to 1 0 Reserved LSBMSB 0 is returned after read Transmit/receive mode bit ordering 0 : Bit 7 is the first bit transmitted or received (MSB mode) 1 : Bit 0 is the first bit transmitted or received (LSB mode)
Note The TXCLR and RXCLR bits must be cleared after changing the CKPOL or CKMD bit. The CKPOL bit must be set as follows according to the state of SCK when a communication is not performed: * When SCK is at low level during no communication ... CKPOL bit = 0 * When SCK is at high level during no communication ... CKPOL bit = 1
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8.3.2 CSIRXDATA (0x0B00 0902)
Bit Name R/W RTCRST Other resets 15 RXD15 R 0 0 14 RXD14 R 0 0 13 RXD13 R 0 0 12 RXD12 R 0 0 11 RXD11 R 0 0 10 RXD10 R 0 0 9 RXD9 R 0 0 8 RXD8 R 0 0
Bit Name R/W RTCRST Other resets
7 RXD7 R 0 0
6 RXD6 R 0 0
5 RXD5 R 0 0
4 RXD4 R 0 0
3 RXD3 R 0 0
2 RXD2 R 0 0
1 RXD1 R 0 0
0 RXD0 R 0 0
Bit 15 to 0 RXD(15:0)
Name
Function CSI receive data. CSI data received on the SI pin is read through these data bits.
8.3.3 CSITXDATA (0x0B00 0904)
Bit Name R/W RTCRST Other resets 15 TXD15 R/W 0 0 14 TXD14 R/W 0 0 13 TXD13 R/W 0 0 12 TXD12 R/W 0 0 11 TXD11 R/W 0 0 10 TXD10 R/W 0 0 9 TXD9 R/W 0 0 8 TXD8 R/W 0 0
Bit Name R/W RTCRST Other resets
7 TXD7 R/W 0 0
6 TXD6 R/W 0 0
5 TXD5 R/W 0 0
4 TXD4 R/W 0 0
3 TXD3 R/W 0 0
2 TXD2 R/W 0 0
1 TXD1 R/W 0 0
0 TXD0 R/W 0 0
Bit 15 to 0 TXD(15:0)
Name
Function CSI transmit data. CSI data written to these bits is transmitted on the SO pin.
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8.3.4 CSILSTAT (0x0B00 0906) (1/2)
Bit Name R/W RTCRST Other resets 15 TFIFOT1 R/W 0 0 14 TFIFOT0 R/W 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 TXFIFOF R 0 0 9 TXFIFOE R 1 1 8 TXBUSY R 0 0
Bit Name R/W RTCRST Other resets
7 RFIFOT1 R/W 0 0
6 RFIFOT0 R/W 0 0
5 Reserved R 0 0
4 FRMDIR R 0 0
3 Reserved R 0 0
2 RXFIFOF R 0 0
1 RXFIFOE R 0 0
0 RXBUSY R 0 0
Bit 15, 14
Name TFIFOT(1:0)
Function CSI transmit FIFO threshold. These bits select the level at which the transmit FIFO empty status is notified. 00 : 1 or more words are free in transmit FIFO 01 : 2 or more words are free in transmit FIFO 10 : 4 or more words are free in transmit FIFO 11 : Reserved
13 to 11 10
Reserved TXFIFOF
0 is returned after read CSI transmit FIFO full status. This bit is set to 1 when the transmit FIFO contains no free space. 0 : Transmit FIFO not full 1 : Transmit FIFO full
9
TXFIFOE
CSI transmit FIFO empty status. This bit is set to 1 when the transmit FIFO reaches to the empty level defined by TFIFOT bits. 0 : Transmit FIFO not empty 1 : Transmit FIFO empty
8
TXBUSY
CSI transmit shift register status 0 : Idle 1 : Character transmission in progress
7, 6
RFIFOT(1:0)
CSI receive FIFO threshold. These bits select the level at which the receive FIFO full status is notified. 00 : 1 or more words are valid in receive FIFO 01 : 2 or more words are valid in receive FIFO 10 : 4 or more words are valid in receive FIFO 11 : Reserved
5
Reserved
0 is returned after read
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Bit 4 FRMDIR Name FRM input pin status 0 : Low level (transmit direction) 1 : High level (receive direction) 3 2 Reserved RXFIFOF 0 is returned after read CSI receive FIFO full status. This bit is set to 1 when the receive FIFO reaches to the full level defined by RFIFOT bits. 0 : Receive FIFO not full 1 : Receive FIFO full 1 RXFIFOE CSI receive FIFO empty status. This bit is set to 1 when the receive FIFO contains no valid data. 0 : Receive FIFO not empty 1 : Receive FIFO empty 0 RXBUSY CSI receive shift register status 0 : Idle 1 : Character reception in progress Function
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8.3.5 CSIINTMSK (0x0B00 0908)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 MUNDRN R/W 1 1 10 MTXBEND R/W 1 1 9 MTXFIFOE R/W 1 1 8 MTXBUSY R/W 1 1
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 MOVRRN R/W 1 1
2 MRXBEND R/W 1 1
1 MRXFIFOF R/W 1 1
0 MRXBUSY R/W 1 1
Bit 15 to 12 11 Reserved MUNDRN
Name 0 is returned after read
Function
Mask of transmit FIFO underrun interrupt requests 0 : Unmasked 1 : Masked
10
MTXBEND
Mask of Transmit Burst End interrupt requests 0 : Unmasked 1 : Masked
9
MTXFIFOE
Mask of Transmit FIFO Empty interrupt requests 0 : Unmasked 1 : Masked
8
MTXBUSY
Mask of Transmit Shift Register Busy interrupt requests 0 : Unmasked 1 : Masked
7 to 4 3
Reserved MOVRRN
0 is returned after read Mask of Receive FIFO Overrun interrupt requests 0 : Unmasked 1 : Masked
2
MRXBEND
Mask of Receive Burst End interrupt requests 0 : Unmasked 1 : Masked
1
MRXFIFOF
Mask of Receive FIFO Full interrupt requests 0 : Unmasked 1 : Masked
0
MRXBUSY
Mask of Receive Shift Register Busy interrupt requests 0 : Unmasked 1 : Masked
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8.3.6 CSIINTSTAT (0x0B00 090A) (1/2)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 URNINT R/W 0 0 10 TXBEINT R/W 0 0 9 TXFEINT R/W 0 0 8 TXBSYINT R/W 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 ORNINT R/W 0 0
2 RXBEINT R/W 0 0
1 RXFFINT R/W 0 0
0 RXBSYINT R/W 0 0
Bit 15 to 12 11 Reserved URNINT
Name 0 is returned after read
Function
Transmit FIFO Underrun interrupt request status 0 : Not pending 1 : Pending This bit is cleared by writing 1.
10
TXBEINT
Transmit Burst End interrupt request status 0 : Not pending 1 : Pending This bit is cleared by writing 1.
9
TXFEINT
Transmit FIFO Empty interrupt request status 0 : Not pending 1 : Pending This bit is cleared by writing 1.
8
TXBSYINT
Transmit Shift Register Busy interrupt request status 0 : Not pending 1 : Pending This bit is cleared by writing 1.
7 to 4 3
Reserved ORNINT
0 is returned after read Receive FIFO Overrun interrupt request status 0 : Not pending 1 : Pending This bit is cleared by writing 1.
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(2/2)
Bit 2 RXBEINT Name Function Receive Burst End interrupt request status 0 : Not pending 1 : Pending This bit is cleared by writing 1. 1 RXFFINT Receive FIFO Full interrupt request status 0 : Not pending 1 : Pending This bit is cleared by writing 1. 0 RXBSYINT Receive Shift Register Busy interrupt request status 0 : Not pending 1 : Pending This bit is cleared by writing 1.
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8.3.7 CSITXBLEN (0x0B00 090C)
Bit Name R/W RTCRST Other resets 15 TXBLN15 R/W 0 0 14 TXBLN14 R/W 0 0 13 TXBLN13 R/W 0 0 12 TXBLN12 R/W 0 0 11 TXBLN11 R/W 0 0 10 TXBLN10 R/W 0 0 9 TXBLN9 R/W 0 0 8 TXBLN8 R/W 0 0
Bit Name R/W RTCRST Other resets
7 TXBLN7 R/W 0 0
6 TXBLN6 R/W 0 0
5 TXBLN5 R/W 0 0
4 TXBLN4 R/W 0 0
3 TXBLN3 R/W 0 0
2 TXBLN2 R/W 0 0
1 TXBLN1 R/W 0 0
0 TXBLN0 R/W 0 0
Bit 15 to 0
Name TXBLN(15:0)
Function Transmit burst length. These bits determine the number of bits transmitted during one burst cycle. 0x0000 : Reserved 0x0001 : 1 bit 0x0002 : 2 bits : : 0x00FD : 253 bits 0x00FE : 254 bits 0x00FF : 255 bits : : 0xFFFD : 65533 bits 0xFFFE : 65534 bits 0xFFFF : 65535 bits
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8.3.8 CSIRXBLEN (0x0B00 090E)
Bit Name R/W RTCRST Other resets 15 RXBLN15 R/W 0 0 14 RXBLN14 R/W 0 0 13 RXBLN13 R/W 0 0 12 RXBLN12 R/W 0 0 11 RXBLN11 R/W 0 0 10 RXBLN10 R/W 0 0 9 RXBLN9 R/W 0 0 8 RXBLN8 R/W 0 0
Bit Name R/W RTCRST Other resets
7 RXBLN7 R/W 0 0
6 RXBLN6 R/W 0 0
5 RXBLN5 R/W 0 0
4 RXBLN4 R/W 0 0
3 RXBLN3 R/W 0 0
2 RXBLN2 R/W 0 0
1 RXBLN1 R/W 0 0
0 RXBLN0 R/W 0 0
Bit 15 to 0
Name RXBLN(15:0)
Function Receive burst length. These bits determine the number of bits received during one burst cycle. 0x0000 : Reserved 0x0001 : 1 bit 0x0002 : 2 bits : : 0x00FD : 253 bits 0x00FE : 254 bits 0x00FF : 255 bits : : 0xFFFD : 65533 bits 0xFFFE : 65534 bits 0xFFFF : 65535 bits
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9.1 Overview
The ICU collects interrupt requests from the various on-chip peripheral units and transfers them with internal interrupt request signals (Int0, Int1, Int2, Int3, Int4, and NMI) to the CPU core. The signals used to notice interrupt requests to the CPU are as below. NMI: battint only. However, the signal for battint can be switched between NMI and Int0 is enabled according to NMIREG register's settings. Because NMI's interrupt masking cannot be controlled by means of software, switch to Int0 to mask battint. Int4: Not used (fixed to 1 (inactive)) Int3: Not used (fixed to 1 (inactive)) Int2: rtclong2 only (RTCLong2 Timer) Int1: rtclong1 only (RTCLong1 Timer) Int0: All other interrupts. For details of the interrupt sources, see 9.2 Register Set. How an interrupt request is notified to the CPU core is shown below. If an interrupt request occurs in the peripheral units, the corresponding bit in the interrupt indication register of Level 2 (xxxINTREG) is set to 1. The interrupt indication register is ANDed bit-wise with the corresponding interrupt mask register of Level 2 (MxxxINTREG). If the occurred interrupt request is enabled (set to 1) in the mask register, the interrupt request is notified to the interrupt indication register of Level 1 (SYSINTREG) and the corresponding bit is set to 1. At this time, the interrupt requests from the same register of Level 2 are notified to the SYSINTREG as a single interrupt request. Interrupt requests from some units directly set their corresponding bits in the SYSINTREG. The SYSINTREG is ANDed bit-wise with the interrupt mask register of Level 1 (MSYSINTREG). If the interrupt request is enabled (set to 1) in the MSYSINTREG, a corresponding interrupt request signal is output from the ICU to the CPU core. battintr is connected to the NMI or Int0 signal of the CPU core (selected by setting of NMIREG). rtclong2 and rtclong1 signals are connected to the Int2 or Int1 signal of the CPU core. The other interrupt requests are connected to the Int0 signal of the CPU core as a single interrupt request. The following figure shows an outline of interrupt control in the ICU.
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Figure 9-1. Outline of Interrupt Control
Level 2 registers and signals from peripheral units
Level 1 registers NMIREG SOFTINTREG
dozepiuint
Dual Stage Synchronizer
siuint giuint ecuint etimerint rtclong1int powerint battint KIUINTREG MKIUINTREG AIUINTREG MAIUINTREG PIUINTREG MPIUINTREG 3 3 3 3 6 6 AND/OR AND/OR AND/OR 3 8
AND NMI SYSINT1REG 10 Selector
MSYSINT1REG
10
AND/OR
Int0
ledint rtclong2int 5 lcdint dmaint csuint
Dual Stage Synchronizer
4
SYSINT2REG
AND
Int1
TClock
4 Int2
MSYSINT2REG
AND
MasterClock
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9.2 Register Set
Table 9-1. ICU Registers
Physical address 0x0A00 0080 0x0A00 008C 0x0A00 0098 0x0A00 009A 0x0A00 0200 0x0A00 0206 0x0B00 0082 0x0B00 0084 0x0B00 0086 0x0B00 008E 0x0B00 0090 0x0B00 0092 R R/W R/W R/W R R/W R R R/W R/W W R/W R/W Register symbol SYSINT1REG MSYNT1REG NMIREG SOFTINTREG SYSINT2REG MSYSINT2REG PIUINTREG AIUINTREG KIUINTREG MPIUINTREG MAIUINTREG MKIUINTREG Level 1 system register 1 Level 1 mask system register 1 NMI register Software interrupt register Level 1 system register 2 Level 1 mask system register 2 Level 2 PIU register Level 2 AIU register Level 2 KIU register Level 2 mask PIU register Level 2 mask AIU register Level 2 mask KIU register Function
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9.2.1 SYSINT1REG (0x0A00 0080) (1/2)
Bit Name 15 Reserved 14 Reserved 13 DOZEPIU INTR R 0 0 12 Reserved 11 SOFTINTR 10 Reserved 9 SIUINTR 8 GIUINTR
R/W RTCRST Other resets
R 0 0
R 0 0
R 0 0
R 0 0
R 0 0
R 0 0
R 0 0
Bit Name
7 KIUINTR
6 AIUINTR
5 PIUINTR
4 Reserved
3 ETIMER INTR R 0 0
2 RTCL1 INTR R 0 0
1 POWER INTR R 0 0
0 BATINTR
R/W RTCRST Other resets
R 0 0
R 0 0
R 0 0
R 0 0
R 0 0
Bit 15, 14 13 Reserved
Name 0 is returned when read
Function
DOZEPIUINTR
PIU interrupt request during Suspend mode 0 : Not occurred 1 : Occurred
12 11
Reserved SOFTINTR
0 is returned when read Software interrupt request 0 : Not occurred 1 : Occurred
10 9
Reserved SIUINTR
0 is returned when read SIU interrupt request 0 : Not occurred 1 : Occurred
8
GIUINTR
GIU interrupt request 0 : Not occurred 1 : Occurred
7
KIUINTR
KIU interrupt request 0 : Not occurred 1 : Occurred
6
AIUINTR
AIU interrupt request 0 : Not occurred 1 : Occurred
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(2/2)
Bit 5 PIUINTR Name PIU interrupt request 0 : Not occurred 1 : Occurred 4 3 Reserved ETIMERINTR 0 is returned when read ElapsedTime interrupt request 0 : Not occurred 1 : Occurred 2 RTCL1INTR RTCLong1 interrupt request 0 : Not occurred 1 : Occurred 1 POWERINTR Power switch interrupt request 0 : Not occurred 1 : Occurred 0 BATINTR Battery low interrupt request 0 : Not occurred 1 : Occurred Function
This register indicates level-1 interrupt requests' status.
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9.2.2 MSYSINT1REG (0x0A00 008C) (1/2)
Bit Name 15 Reserved 14 Reserved 13 MDOZEPIU INTR R/W 0 0 12 Reserved 11 MSOFT INTR R/W 0 0 10 Reserved 9 MSIUINTR 8 MGIUINTR
R/W RTCRST Other resets
R 0 0
R 0 0
R 0 0
R 0 0
R/W 0 0
R/W 0 0
Bit Name
7 MKIUINTR
6 MAIUINTR
5 MPIUINTR
4 Reserved
3 METIMER INTR R/W 0 0
2 MRTCL1 INTR R/W 0 0
1 MPOWER INTR R/W 0 0
0 MBATINTR
R/W RTCRST Other resets
R/W 0 0
R/W 0 0
R/W 0 0
R 0 0
R/W 0 0
Bit 15, 14 13 Reserved
Name 0 is returned when read
Function
MDOZEPIUINTR
Enables PIU interrupt during Suspend mode 0 : Disable 1 : Enable
12 11
Reserved MSOFTINTR
0 is returned when read Enables software interrupt 0 : Disable 1 : Enable
10 9
Reserved MSIUINTR
0 is returned when read Enables SIU interrupt 0 : Disable 1 : Enable
8
MGIUINTR
Enables GIU interrupt 0 : Disable 1 : Enable
7
MKIUINTR
Enables KIU interrupt 0 : Disable 1 : Enable
6
MAIUINTR
Enables AIU interrupt 0 : Disable 1 : Enable
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(2/2)
Bit 5 MPIUINTR Name Enables PIU interrupt 0 : Disable 1 : Enable 4 3 Reserved METIMERINTR 0 is returned when read Enables ElapsedTime interrupt 0 : Disable 1 : Enable 2 MRTCL1INTR Enables RTCLong1 interrupt 0 : Disable 1 : Enable 1 MPOWERINTR Enables Power switch interrupt 0 : Disable 1 : Enable 0 MBATINTR Enables battery low interrupt 0 : Disable 1 : Enable Function
This register is used to enable/disable level-1 interrupts.
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9.2.3 NMIREG (0x0A00 0098)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 Reserved R 0 0
2 Reserved R 0 0
1 Reserved R 0 0
0 NMIORINT R/W 0 0
Bit 15 to 1 0 Reserved NMIORINT
Name 0 is returned when read Battery low interrupt request routing 0 : NMI 1 : Int0
Function
This register is used to set the interrupt request signal used to notify the VR4110 CPU core when a battery low interrupt request has occurred.
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9.2.4 SOFTINTREG (0x0A00 009A)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 Reserved R 0 0
2 Reserved R 0 0
1 Reserved R 0 0
0 SOFTINTR W 0 0
Bit 15 to 1 0 Reserved SOFTINTR
Name 0 is returned when read
Function
Set/clear a software interrupt request. This bit is a write-only bit. Software interrupt request pending status is reported in the SYSINT1REG (0x0A000080). 0 : Clear 1 : Set
This register is used to set a software interrupt request.
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9.2.5 SYSINT2REG (0x0A00 0200)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 LCDINTR R 0 0
5 DMAINTR R 0 0
4 Reserved R 0 0
3 CSUINTR R 0 0
2 ECUINTR R 0 0
1 LEDINTR R 0 0
0 RTCL2INTR R 0 0
Bit 15 to 7 6 Reserved LCDINTR
Name 0 is returned when read LCD interrupt request 0 : Not occurred 1 : Occurred
Function
5
DMAINTR
DMA interrupt request 0 : Not occurred 1 : Occurred
4 3
Reserved CSUINTR
0 is returned when read CSI interrupt request 0 : Not occurred 1 : Occurred
2
ECUINTR
CompactFlash interrupt request 0 : Not occurred 1 : Occurred
1
LEDINTR
LED interrupt request 0 : Not occurred 1 : Occurred
0
RTCL2INTR
RTCLong2 interrupt request 0 : Not occurred 1 : Occurred
This register indicates level-1 interrupt requests' status.
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9.2.6 MSYSINT2REG (0x0A00 0206)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name
7 Reserved
6 MLCDINTR
5 MDMAINTR
4 Reserved
3 MCSUINTR
2 MECUINTR
1 MLEDINTR
0 MRTCL2 INTR R/W 0 0
R/W RTCRST Other resets
R 0 0
R/W 0 0
R/W 0 0
R/W 0 0
R/W 0 0
R/W 0 0
R/W 0 0
Bit 15 to 7 6 Reserved MLCDINTR
Name 0 is returned when read Enables LCD interrupt 0 : Disable 1 : Enable
Function
5
MDMAINTR
Enables DMA interrupt 0 : Disable 1 : Enable
4 3
Reserved MCSUINTR
Write 0 when write. 0 is returned when read Enables CSI interrupt 0 : Disable 1 : Enable
2
MECUINTR
Enables CompactFlash interrupt 0 : Disable 1 : Enable
1
MLEDINTR
Enables LED interrupt 0 : Disable 1 : Enable
0
MRTCL2INTR
Enables RTCLong2 interrupt 0 : Disable 1 : Enable
This register is used to enable/disable level-1 interrupts.
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9.2.7 PIUINTREG (0x0B00 0082)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name
7 Reserved
6 PADCMD INTR R 0 0
5 PADADP INTR R 0 0
4 PADPAGE1 INTR R 0 0
3 PADPAGE0 INTR R 0 0
2 PADDLOST INTR R 0 0
1 Reserved
0 PENCHG INTR R 0 0
R/W RTCRST Other resets
R 0 0
R 0 0
Bit 15 to 7 6 Reserved
Name 0 is returned when read
Function
PADCMDINTR
PIU command scan interrupt request. This interrupt request occurs when a valid data is detected during a command scan. 0 : Not occurred 1 : Occurred
5
PADADPINTR
PIU AD Port Scan interrupt request. This interrupt request occurs when a valid data is obtained during an A/D port scan. 0 : Not occurred 1 : Occurred
4
PADPAGE1INTR
PIU data buffer page 1 interrupt request. This interrupt request occurs when a set of valid data is stored in the page 1 of the data buffer. 0 : Not occurred 1 : Occurred
3
PADPAGE0INTR
PIU data buffer page 0 interrupt request. This interrupt request occurs when a set of valid data is stored in the page 0 of the data buffer. 0 : Not occurred 1 : Occurred
2
PADDLOSTINTR
Data loss interrupt request. This interrupt request occurs when a set of data cannot be obtained within the specified time. 0 : Not occurred 1 : Occurred
1 0
Reserved PENCHGINTR
0 is returned when read Touch panel contact status change interrupt request. 0 : Not occurred 1 : Occurred
This register indicates when various PIU-related interrupt requests (level 2) occur.
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9.2.8 AIUINTREG (0x0B00 0084)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 INTMIDLE R 0 0 8 INTMST R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 Reserved R 0 0
2 Reserved R 0 0
1 INTSIDLE R 0 0
0 Reserved R 0 0
Bit 15 to 10 9 Reserved INTMIDLE
Name 0 is returned when read
Function
Audio input (microphone) idle interrupt request (received data is lost). This interrupt request occurs if a valid data exists in the MIDATREG register when data is received from the A/D converter. 0 : Not occurred 1 : Occurred
8
INTMST
Audio input (microphone) receive completion interrupt request. This interrupt request occurs when a 10-bit converted data from the A/D converter is received. 0 : Not occurred 1 : Occurred
7 to 2 1
Reserved INTSIDLE
0 is returned when read Audio output (speaker) idle interrupt request (mute). This interrupt request occurs if there is no valid data in the SODATREG register when data is transferred to the D/A converter. 0 : Not occurred 1 : Occurred
0
Reserved
0 is returned when read
This register indicates when various AIU-related interrupt requests occur.
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9.2.9 KIUINTREG (0x0B00 0086)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 Reserved R 0 0
2 KDATLOST R/W 0 0
1 KDATRDY R/W 0 0
0 KDOWNINT R/W 0 0
Bit 15 to 3 2 Reserved
Name 0 is returned when read
Function
KDATLOST
Keyboard Data Lost interrupt request. This interrupt request occurs if the KIUDAT0 register is updated with the next key data prior to being read by the CPU core. 0 : Not occurred 1 : Occurred This bit is cleared by writing 1.
1
KDATRDY
Keyboard Data Ready interrupt request. This interrupt request occurs when a set of scanning is completed and all the KIUDAT registers are updated. 0 : Not occurred 1 : Occurred This bit is cleared by writing 1.
0
KDOWNINT
Key Down interrupt request. This interrupt request occurs when the KIU sequencer is idle and any of the SCANIN inputs has been sampled as low level. 0 : Not occurred 1 : Occurred This bit is cleared by writing 1.
The KDATLOST bit is also cleared when the KIUDAT0 register is read.
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9.2.10 MPIUINTREG (0x0B00 008E)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name
7 Reserved
6 PADCMD INTR R/W 0 0
5 PADADP INTR R/W 0 0
4 PADPAGE1 INTR R/W 0 0
3 PADPAGE0 INTR R/W 0 0
2 PADDLOST INTR R/W 0 0
1 Reserved
0 PENCHG INTR R/W 0 0
R/W RTCRST Other resets
R 0 0
R 0 0
Bit 15 to 7 6 Reserved
Name 0 is returned when read
Function
PADCMDINTR
Enables PIU command scan interrupt 0 : Disable 1 : Enable
5
PADADPINTR
Enables PIU A/D Port Scan interrupt 0 : Disable 1 : Enable
4
PADPAGE1INTR
Enables PIU data buffer page 1 interrupt 0 : Disable 1 : Enable
3
PADPAGE0INTR
Enables PIU data buffer page 0 interrupt 0 : Disable 1 : Enable
2
PADDLOSTINTR
Enables data loss interrupt 0 : Disable 1 : Enable
1 0
Reserved PENCHGINTR
0 is returned when read Enables touch panel contact status change interrupt 0 : Disable 1 : Enable
This register is used to mask various PIU-related interrupts.
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9.2.11 MAIUINTREG (0x0B00 0090)
Bit Name R/W RTCRST Other resets 15 Reserved W 0 0 14 Reserved W 0 0 13 Reserved W 0 0 12 Reserved W 0 0 11 Reserved W 0 0 10 Reserved W 0 0 9 INTMIDLE W 0 0 8 INTMST W 0 0
Bit Name R/W RTCRST Other resets
7 Reserved W 0 0
6 Reserved W 0 0
5 Reserved W 0 0
4 Reserved W 0 0
3 Reserved W 0 0
2 Reserved W 0 0
1 INTSIDLE W 0 0
0 Reserved W 0 0
Bit 15 to 10 9 Reserved INTMIDLE
Name Write 0 when write
Function
Enables audio input (microphone) idle interrupt (received data is lost) 0 : Disable 1 : Enable
8
INTMST
Enables audio input (microphone) receive completion interrupt 0 : Disable 1 : Enable
7 to 2 1
Reserved INTSIDLE
Write 0 when write Enables audio output (speaker) idle interrupt (mute) 0 : Disable 1 : Enable
0
Reserved
Write 0 when write
This register is used to mask various AIU-related interrupts. This register is a write-only register and its contents when it is read are undefined.
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9.2.12 MKIUINTREG (0x0B00 0092)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name
7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 Reserved
2 MSKKDAT LOST R/W 0 0
1 MSKKDAT RDY R/W 0 0
0 MSKK DOWNINT R/W 0 0
R/W RTCRST Other resets
R 0 0
R 0 0
R 0 0
R 0 0
R 0 0
Bit 15 to 3 2 Reserved
Name 0 is returned when read
Function
MSKKDATLOST
Enables Keyboard Data Lost interrupt 0 : Disable 1 : Enable This bit may be used to temporarily mask the Keyboard Data Lost interrupt request and does not affect Keyboard Data Lost event detection.
1
MSKKDATRDY
Enables Keyboard Data Ready interrupt 0 : Disable 1 : Enable This bit may be used to temporarily mask the Keyboard Data Ready interrupt request and does not affect Keyboard Data Ready event detection.
0
MSKKDOWNINT
Enables Key Down interrupt 0 : Disable 1 : Enable This bit may be used to temporarily mask the Key Down interrupt request and does not affect Key Down event detection.
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CHAPTER 10 POWER MANAGEMENT UNIT (PMU)
This chapter describes the Power Management Unit (PMU) operation, register settings and power modes.
10.1 General
The PMU performs power management within the VR4181 and controls the power supply throughout the system. The PMU provides the following functions: * Reset control * Shutdown control * Power-on control * Low-power mode control
10.2 VR4181 Power Mode
This section describes the VR4181 power modes in detail. The VR4181 supports the following four power modes: * Fullspeed mode * Standby mode * Suspend mode * Hibernate mode 10.2.1 Power mode and state transition The VR4181 transits from Fullspeed mode to Standby mode, Suspend mode, or Hibernate mode by executing a STANBY, SUSPEND, or HIBERNATE instruction respectively. An RTC reset is always valid in every mode, and initializes (resets) units in the VR4181 including the RTC. The figure on the following page, Figure 10-1, is a conceptual diagram showing the interaction and control of the four power modes of the VR4181.
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Figure 10-1. Transition of VR4181 Power Mode
Standby mode
(2) (3)
Suspend mode
(1)
(4)
Fullspeed mode
(8)
(6)
(5)
RTC reset
(9)
(7)
Hibernate mode
Transition No. (1) (2) (3) STANDBY instruction All interrupt requests SUSPEND instruction DRAM self refresh
Factors
(4)
Assertion of POWER Assertion and then deassertion of RSTSW# Interrupt request such as: ElapsedTime timer RTCLong1 RTCLong2 HIBERNATE instruction DRAM self refresh Deassertion of MPOWER Assertion of POWER Interrupt request such as: ElapsedTime timer DCD1# Assertion of RTCRST# Deassertion of MPOWER Assertion and then deassertion of RTCRST# BATTINH = high (normal activation) Assertion and then deassertion of RTCRST# BATTINH = low (BATTINH shutdown)
Key press Pen touch GPIO(15:0)
DCD1# (SIU1) CF_BUSY# BATTINTR
(5)
(6)
GPIO(15:0) CF_BUSY#
(7)
(8)
(9)
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Table 10-1 shows power mode overview and transaction: Table 10-1. Overview of Power Modes
Mode RTC Fullspeed Standby Suspend Hibernate Off On On On On Off On On On Off Off ICU On On Off Off Off Internal peripheral unit DMA On On Off Off Off LCDC Others Selectable Selectable Off Off Off On Off Off Off Off CPU core
(1) Fullspeed mode All internal clocks and bus clocks operate. The VR4181 can perform every function during the Fullspeed mode. (2) Standby mode The pipeline clock (PClock) of the CPU core is fixed to high level. PLL, timer/interrupt function of the CPU core, interrupt clock (MasterOut), internal bus clock (TClock and PCLK), and RTC clock continue their operation. Therefore, all the on-chip peripheral units continue their operation (operation of the LCD controller and DMA also continue). The contents of caches and registers in the CPU core are retained. To enter to Standby mode from Fullspeed mode, execute the STANDBY instruction. After the STANDBY instruction has passed the WB stage, the VR4181 waits until SysAD bus (internal) enters idle state. Then, internal clocks are shut down, and pipeline operation stops. To restore to Fullspeed mode, generate an interrupt request of any kind. When the processor restores to Fullspeed mode from Standby mode, it starts a program execution from the General exception vector (0xBFC0 0380 when BEV = 0 or 0x8000 0180 when BEV = 1). (3) Suspend mode The pipeline clock (PClock) of the CPU core and the internal bus clocks (TClock and PCLK) are fixed to high level. PLL, timer/interrupt function of the CPU core, interrupt clock (MasterOut), and RTC clock continue their operation. The contents of caches and registers in the CPU core are retained. The contents of connected DRAMs can be preserved by putting DRAMs into self-refresh mode. To enter to Suspend mode from Fullspeed mode, execute a Suspend mode sequence (see 10.6 DRAM Interface Control) first. After the SUSPEND instruction has passed the WB stage and DRAMs enter self-refresh mode, the VR4181 waits until SysAD bus (internal) enters idle state. Then, internal clocks are shut down, and pipeline operation stops. To restore to Fullspeed mode from Suspend mode, one of the interrupt requests listed in Figure 10-1 (interrupt requests that can be used are limited since the internal bus clocks (TClock and PCLK) stop). When the processor restores to Fullspeed mode from Suspend mode, it starts a program execution from the General exception vector (0xBFC0 0380 when BEV = 0 or 0x8000 0180 when BEV = 1).
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(4) Hibernate mode All clocks other than the RTC clock (32.768 kHz) are fixed to high level and the PLL operation stops. An RTC and a monitor for activation factors in the PMU continue their operation. To enter to Hibernate mode from Fullspeed mode, execute a Hibernate mode sequence (see 10.6 DRAM Interface Control) first. After the HIBERNATE instruction has passed the WB stage and DRAMs enter selfrefresh mode, the VR4181 waits until SysAD bus (internal) enters idle state. Then, MPOWER signal becomes inactive after internal clocks are shut down and pipeline operation stops. 2.5 V power supply can be stopped during MPOWER signal is inactive. If it is stopped, however, the contents of registers in the peripheral units other than PMU, GIU, LED, and RTC are not retained. To restore to Fullspeed mode from Hibernate mode, one of the interrupt requests listed in Figure 10-1. When the processor restores to Fullspeed mode from Hibernate mode, it starts a program execution from the Cold Reset exception vector (0xBFC0 0000).
10.3 Reset Control
The operations of the RTC, peripheral units, and CPU core, and PMUINTREG register bit settings during a reset are listed below. Table 10-2. Operations During Reset
Reset type RTC reset RSTSW reset 1 RTC, GIU Reset Active Peripheral units Reset Reset CPU core Cold Reset Cold Reset PMUINTREG bits RTCRST = 1 RSTSW = 1 SDRAM = 0 RSTSW = 1 SDRAM = 1 DMSRST = 1
RSTSW reset 2
Active
Active
Cold Reset
Deadman's Switch reset
Active
Reset
Cold Reset
Caution
When bit 6 of the PMUINTREG register is set to 1, only the CPU core is reset during a RSTSW reset cycle, and all internal peripheral units retain their current state. Software must re-initialize or reset all peripheral units in this case. To preserve SDRAM data during a RSTSW reset, bit 6 of the PMUINTREG register should be set to 1 when SDRAM is used.
10.3.1 RTC reset When the RTCRST# signal becomes active, the PMU resets all internal peripheral units including the RTC unit. It also resets (Cold Reset) the CPU core. In addition, the RTCRST bit in the PMUINTREG register is set to 1. After the CPU core is restarted, the RTCRST bit must be checked and cleared to 0 by software. For details of the timing of RTC reset, refer to CHAPTER 5 INITIALIZATION INTERFACE.
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10.3.2 RSTSW reset When the RSTSW# signal becomes active, the PMU resets (Cold Reset) the CPU core. When bit 6 of the PMUINTREG register is cleared to 0, the PMU also resets all internal peripheral units except for the RTC and GIU. In addition, the RSTSW bit in the PMUINTREG register is set to 1. After the CPU core is restarted, the RSTSW bit must be checked and cleared to 0 by software. For details of the timing of RSTSW reset, refer to CHAPTER 5 INITIALIZATION INTERFACE. 10.3.3 Deadman's Switch reset When the Deadman's Switch function is enabled, software must write 1 to DSWCLR bit in the DSUCLRREG register each set time, to clear the Deadman's Switch counter (for more information, refer to CHAPTER 12 DEADMAN'S SWITCH UNIT (DSU)). If the Deadman's Switch counter is not cleared within the set time, the PMU resets all peripheral units except for RTC, GIU, and PMU. Then the PMU resets (Cold Reset) the CPU core. In addition, DMSRST bit in the PMUINTREG register is set to 1. After the CPU core is restarted, DMSRST bit must be checked and cleared to 0 by software. 10.3.4 Preserving DRAM data on RSTSW reset (1) Preserving EDO-DRAM data When an RSTSW reset takes place, the PMU activates the CAS#/RAS# pins to generate a CBR self refresh request to EDO DRAM. Remark There is no burst CBR refresh before and after CBR self refresh by RSTSW reset. Figure 10-2. EDO DRAM Signals on RSTSW Reset (SDRAM Bit = 0)
RTC (Internal)
RSTSW# (Input)
CAS# (Output)
RAS(1:0)# (Output)
(2) Preserving SDRAM data The SDRAM bit of the PMUINTREG register can be used to preserve the contents of SDRAM connected to the VR4181 during an RSTSW reset. When the SDRAM bit is set to 1, the PMU does not reset the memory controller. Therefore, the memory controller completes current SDRAM access and performs CBR refresh cycle on an RSTSW reset. On the other hand, when the SDRAM bit is set to 0, the memory controller is reset regardless of accesses under processing and does not perform CBR refresh cycle (SDRAM data will be destroyed).
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10.4 Shutdown Control
The operations of the RTC, peripheral units, and CPU core, and PMUINTREG register bit settings during a reset are listed below. For detail of the timing of each shutdown, refer to CHAPTER 5 INITIALIZATION INTERFACE. Table 10-3. Operations During Shutdown
Shutdown type HALTimer shutdown Software shutdown BATTINH shutdown RTC, GIU Active Active Active Peripheral units Reset Reset Reset CPU core Cold Reset Cold Reset Cold Reset PMUINTREG bits TIMOUTRST = 1 - BATTINH = 1
10.4.1 HALTimer shutdown After the CPU core is activated (following the mode change from Shutdown or Hibernate mode to Fullspeed mode), or the CPU core is reset by RSTSW reset, software must write 1 to HALTIMERRST bit in the PMUCNTREG register within about four seconds to clear the HALTimer. If the HALTimer is not reset within about four seconds after the CPU core is activated or the RSTSW reset is canceled, the PMU resets all peripheral units except for RTC and PMU. Then the PMU resets (Cold Reset) the CPU core. In addition, TIMOUTRST bit in PMUINTREG register is set to 1. After the CPU core is restarted, TIMOUTRST bit must be checked and cleared to 0 by software. 10.4.2 Software shutdown When the HIBERNATE instruction is executed, the PMU checks for currently pending interrupt requests. If there are no pending interrupt requests, it stops the CPU core clock. It then resets all peripheral units except for the RTC, GIU, and the PMU. The PMU register contents do not change. 10.4.3 BATTINH shutdown If the BATTINH signal is asserted when the CPU core is going to be activated, the PMU stops CPU activation and resets all peripheral units except for the RTC, GIU, and the PMU. Then it resets the CPU core. In addition, BATTINH bit in the PMUINTREG register is set to 1. After the CPU core is restarted, BATTINH bit must be checked and cleared to 0 by software. For details of the timing of BATTINH shutdown, see 10.5 Power-on Control below.
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10.5 Power-on Control
The causes of CPU core activation (mode change from shutdown mode or Hibernate mode to Fullspeed mode) are called activation factors. There are twenty activation factors: a power switch interrupt (POWER), sixteen types of GPIO activation interrupts (GPIO(15:0)), a DCD interrupt (DCD#), a CompactFlash interrupt, and an ElapsedTime interrupt. Battery low detection (BATTINH/BATTINT# pin check) is a factor that prevents CPU core activation. The period (power-on wait time) in which the POWERON pin is active at power-on can be specified by using PMUWAITREG register. After RTCRST, by which the CPU core is initialized, the period is set as 343.75 ms. Poweron wait time can be specified when activation is caused by sources other than RTCRST. When MPOWER signal is at low level (Hibernate mode or during CPU core activation), to stop supplying voltage to the 2.5 V power-supply systems is recommended to reduce leak current. This means that this power supply can be 0 V while the MPOWER signal is inactive. The following operation will not be affected by supplying voltage of 2.3 V or more to this power supply within the period from when the MPOWER signal becomes active to when PLL starts oscillation. Caution When the CPU core enters the Hibernate mode by executing the HIBERNATE instruction, if an activation factor occurs simultaneously, the CPU core may be activated without asserting the POWERON signal after the MPOWER signal is once de-asserted. Moreover, if RSTSW#, which is not an activation factor of the Hibernate mode, is asserted at the same time a transition to the Hibernate mode by executing the HIBERNATE instruction occurs, the CPU core may be activated without asserting the POWERON signal after the MPOWER signal is de-asserted once.
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10.5.1 Activation via Power Switch interrupt request When the POWER signal is asserted, the PMU asserts the POWERON signal to provide an external notification that the CPU core is being activated. After asserting the POWERON signal, the PMU checks the BATTINH signal and then de-asserts the POWERON signal. If the BATTINH signal is at high level, the PMU cancels peripheral unit reset and starts the Cold Reset sequence to activate the CPU core. If the BATTINH signal is at low level, the PMU sets 1 to the BATTINH bit in the PMUINTREG register and then performs another shutdown. After the CPU core is restarted, the BATTINH bit must be checked and cleared to 0 by software. Remark Activation via Power Switch interrupt request never sets the POWERSWINTR bit in the PMUINTREG register to 1. Figure 10-3. Activation via Power Switch Interrupt Request (BATTINH = H)
RTC (Internal)
POWER (Input)
POWERON (Output)
MPOWER (Output) BATTINH/BATTINT# (Input) H
Figure 10-4. Activation via Power Switch Interrupt Request (BATTINH = L)
RTC (Internal)
POWER (Input)
POWERON (Output) MPOWER (Output) L
BATTINH/BATTINT# (Input)
L
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10.5.2 Activation via CompactFlash interrupt request When the CF_BUSY# signal is asserted, the PMU asserts the POWERON signal to provide an external notification that the CPU core is being activated. After asserting the POWERON signal, the PMU checks the BATTINH signal and then de-asserts the POWERON signal. If the BATTINH signal is at high level, the PMU cancels peripheral unit reset and starts the Cold Reset sequence to activate the CPU core. If the BATTINH signal is at low level, the PMU sets 1 to the BATTINH bit in the PMUINTREG register and then performs another shutdown. After the CPU core is restarted, the BATTINH bit must be checked and cleared to 0 by software. Figure 10-5. Activation via CompactFlash Interrupt Request (BATTINH = H)
RTC (Internal)
CF_BUSY# (Input)
POWERON (Output)
MPOWER (Output) BATTINH/BATTINT# (Input) H
Figure 10-6. Activation via CompactFlash Interrupt Request (BATTINH = L)
RTC (Internal)
CF_BUSY# (Input)
POWERON (Output) MPOWER (Output) L
BATTINH/BATTINT# (Input)
L
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10.5.3 Activation via GPIO activation interrupt request When any of the GPIO(15:0) signals are asserted, the PMU checks the GPIO(15:0) activation interrupt enable bits in the GIU. If GPIO(15:0) activation interrupts are enabled, the PMU asserts the POWERON signal to provide an external notification that the CPU core is being activated (since the GPIO(15:0) activation enable interrupt bits are cleared after an RTC reset, the GPIO(15:0) signal cannot be used for activation immediately after an RTC reset). After asserting the POWERON signal, the PMU checks the BATTINH signal and de-asserts the POWERON signal. If the BATTINH signal is at high level, the PMU cancels the peripheral unit reset and starts the Cold Reset sequence to activate the CPU core. If the BATTINH signal is at low level, the PMU sets 1 to the BATTINH bit in the PMUINTREG register and then performs another shutdown. After the CPU core is restarted, the BATTINH bit must be checked and cleared to 0 by software. The CPU core sets 1 to the GPWAKEUP bit in the PMUINTREG register regardless of whether activation succeeds or fails. Caution The changes in the GPIO signals are ignored while POWERON signal is active. Figure 10-7. Activation via GPIO Activation Interrupt Request (BATTINH = H)
RTC (Internal)
GPIO (15:0) (I/O) POWERON (Output)
MPOWER (Output) BATTINH/BATTINT# (Input)
H
Figure 10-8. Activation via GPIO Activation Interrupt Request (BATTINH = L)
RTC (Internal) GPIO (15:0) (I/O)
POWERON (Output)
MPOWER (Output)
L
BATTINH/BATTINT# (Input)
L
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10.5.4 Activation via DCD interrupt request When the DCD1# signal is asserted, the PMU asserts the POWERON signal to provide an external notification that the CPU core is being activated. After asserting the POWERON signal, the PMU checks the BATTINH signal and then de-asserts the POWERON signal. If the BATTINH signal is at high level, the PMU cancels the peripheral unit reset and starts the Cold Reset sequence to activate the CPU core. If the BATTINH signal is at low level, the PMU sets 1 to the BATTINH bit in the PMUINTREG register and then performs another shutdown. After the CPU core is restarted, the BATTINH bit must be checked and cleared to 0 by software. The DCDST bit in the PMUINTREG register does not indicate whether a DCD interrupt has occurred but instead reflects the current status of the DCD1# pin. Cautions1. The PMU cannot recognize changes in the DCD1# signal while the POWER signal is asserted. If the DCD1# state when the POWER signal is asserted is different from that when the POWER signal is deasserted, the change in the DCD1# signal is detected only after the POWER signal is deasserted. However, if the DCD1# state when the POWER signal is asserted is the same as that when the POWER signal is deasserted, any changes in the DCD1# signal that occur while the POWER signal is asserted are not detected. 2. The changes in the DCD1# signal are ignored while the POWERON signal is active. 3. There is no indicator which shows an activation via DCD interrupt, if DCD1# signal has already changed from active to inactive during power-on sequence. In other words, if software can not find activation factor and if the DCDST bit indicates that DCD1# signal is active, the above situation occurred.
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Figure 10-9. Activation via DCD Interrupt Request (BATTINH = H)
RTC (Internal)
DCD1# (Input) POWERON (Output)
MPOWER (Output) BATTINH/BATTINT# (Input) H
Figure 10-10. Activation via DCD Interrupt Request (BATTINH = L)
RTC (Internal) DCD1# (Input) POWERON (Output)
MPOWER (Output)
L
BATTINH/BATTINT# (Input)
L
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10.5.5 Activation via ElapsedTime (RTC alarm) interrupt request When the alarm (alarm_intr signal) generated from the ElapsedTime timer is asserted, the PMU asserts the POWERON signal to provide an external notification that the CPU core is being activated. After asserting the POWERON signal, the PMU checks the BATTINH signal and then de-asserts the POWERON signal. If the BATTINH signal is at high level, the PMU cancels the peripheral unit reset and starts the Cold Reset sequence to activate the CPU core. If the BATTINH signal is at low level, the PMU sets 1 to the BATTINH bit in the PMUINTREG register and then performs another shutdown. After the CPU core is restarted, the BATTINH bit must be checked and cleared to 0 by software. Caution The ElapsedTime interrupt is ignored while the POWERON signal is active. After the POWERON signal becomes inactive, the PMU is notified. Figure 10-11. Activation via ElapsedTime Interrupt Request (BATTINH = H)
RTC (Internal) alam_intr (Internal) POWERON (Output)
MPOWER (Output)
BATTINH/BATTINT# (Input)
H
Figure 10-12. Activation via ElapsedTime Interrupt Request (BATTINH = L)
RTC (Internal) alam_intr (Internal)
POWERON (Output)
MPOWER (Output)
L
BATTINH/BATTINT# (Input)
L
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10.6 DRAM Interface Control
The PMU provides a register to control the DRAM interface during Hibernate mode or Suspend mode. The DRAMHIBCTL register permits software to directly control the state of the DRAM interface pins prior to executing a HIBERNATE or SUSPEND instruction. The DRAMHIBCTL register also provides status indication of the memory controller. The software flow when entering and exiting Hibernate mode or Suspend mode is shown below. 10.6.1 Entering Hibernate mode (EDO DRAM) <1> Copy contents of all 2.5 V registers (i.e. DRAM type and configuration, ROM type and configuration, etc.) that must be preserved during Hibernate mode into the general-purpose registers, MISCREG(0:15), in the GIU or into external memory. Remark 3.3 V peripheral units: PMU, GIU, LED, and RTC 2.5 V peripheral units: all peripherals except PMU, GIU, LED, and RTC <2> Stop operations of the DMA controller and LCD controller. <3> Copy the codes for the Hibernate mode (<4> through <11> below) beginning at a 16-byte boundary into the cache by using a Fill operation of CACHE instruction, and jump to the cached codes. <4> Stop all peripheral clocks by writing zero to the CMUCLKMSK register in the MBA Host Bridge. <5> If DRAM can accept mixed use of burst and distributive CBR refresh, set a value that determines the refresh count to every 250 ns to the BCURFCNTREG register in the MBA Host Bridge. Then execute CBR refresh cycles for a specific time period (i.e. 0x3FFF x TClock period + burst refresh interval required by DRAM). <6> Set 0x3FF to the BCURFCNTREG register in the MBA Host Bridge that determines refresh interval to maximum to prevent an interruption of a Hibernate mode sequence. <7> Set the SUSPEND bit in the DRAMHIBCTL register to 1. If the BstRefr bit of the MEMCFG_REG register in the memory controller to 1, the memory controller performs a burst refresh cycle and then put the DRAM into self-refresh mode. <8> Poll the OK_STOP_CLK bit in the DRAMHIBCTL register to confirm that the memory controller completes a burst refresh cycle and put the DRAM into self-refresh mode. <9> Set the STOP_CLK bit in the DRAMHIBCTL register to 1 to stop supplying TClock to the memory controller. <10> Set the DRAM_EN bit in the DRAMHIBCTL register to 1 so that the DRAM interface signals are latched. <11> Execute a HIBERNATE instruction. <12> Stop applying 2.5 V power supply when the MPOWER signal becomes low level. Caution When entering Hibernate mode, set the BEV bit of the Status register in the CP0 of the CPU core to 1 to make sure that the vector of the exception handler points the ROM area.
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10.6.2 Entering Hibernate mode (SDRAM) <1> Copy contents of all 2.5 V registers (i.e. DRAM type and configuration, ROM type and configuration, etc.) that must be preserved during Hibernate mode into the general-purpose registers, MISCREG(0:15), in the GIU or into external memory. Remark 3.3 V peripheral units: PMU, GIU, LED, and RTC 2.5 V peripheral units: all peripherals except PMU, GIU, LED, and RTC <2> Stop operations of the DMA controller and LCD controller. <3> Copy the codes for the Hibernate mode (<4> through <12> below) beginning at a 16-byte boundary into the cache by using a Fill operation of CACHE instruction, and jump to the cached codes. <4> Stop all peripheral clocks by writing zero to the CMUCLKMSK register in the MBA Host Bridge. <5> Set the BCURFCNTREG register in the MBA Host Bridge to a value that determines refresh interval to maximum to prevent an interruption of a Hibernate mode sequence. <6> If burst refreshes are needed, set a value that determines the refresh count to every 250 ns to the BCURFCNTREG register in the MBA Host Bridge. Then execute CBR auto refresh cycles for a specific time period (i.e. 0x3FFF x TClock period + burst refresh interval required by DRAM). <7> Clear the BstRefr bit of the MEMCFG_REG register in the memory controller to 0 to disable a burst refresh. Then set SUSPEND bit in the DRAMHIBCTL register to 1 to put the DRAM into self-refresh mode. <8> Poll the OK_STOP_CLK bit in the DRAMHIBCTL register to confirm that the memory controller puts the DRAM into self-refresh mode. <9> Set the STOP_CLK bit in the DRAMHIBCTL register to 1 to stop supplying TClock to the memory controller. <10> Set the DRAM_EN bit in the DRAMHIBCTL register to 1 so that the DRAM interface signals are latched. <11> Clear the SUSPEND bit in the DRAMHIBCTL register to 0 after waiting for about 2 s. <12> Execute a HIBERNATE instruction. <13> Stop applying 2.5 V power supply when the MPOWER signal becomes low level. Caution When entering Hibernate mode, set the BEV bit of the Status register in the CP0 of the CPU core to 1 to make sure that the vector of the exception handler points the ROM area.
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10.6.3 Exiting Hibernate mode (EDO DRAM) <1> Generate a wake-up event such as a transition on the POWER pin, a DCD interrupt, etc. which causes the PMU to start a power-on sequence. <2> Apply 2.5 V power supply when the MPOWER signal becomes high level. The PMU waits until 3.3 V and 2.5 V power supply are stable, and then deasserts the reset signals to the VR4110 CPU core and on-chip peripheral units. <3> Software execution resumes at the Cold Reset exception vector (0x0BFC 0000). Initialize the cache tags, and the Config, Status, and WatchLo registers in the CP0. Reset the HALTimer by setting the HALTIMERRST bit in the PMUCNTREG register to 1. <4> Check and clear the TIMOUTRST bit in the PMUINTREG register in the case a HALTimer Shutdown had occurred. <5> Copy the codes for the restore (<6> through <12> below) beginning at a 16-byte boundary into the cache by using a Fill operation of CACHE instruction, and jump to the cached codes. These codes can be executed on ROM. <6> Poll the OK_STOP_CLK bit in the DRAMHIBCTL register until it is set to 1. <7> Reinitialize all the registers and peripherals during Hibernate mode and restore those registers saved in the general-purpose registers, MISCREG(0:15) which retain values during Hibernate mode, in the GIU or in external memory. Remark Software must wait until the OK_STOP_CLK bit in the DRAMHIBCTL register is set to 1 before reinitializing the memory controller registers. Otherwise unpredictable behavior of the memory controller could result. <8> Clear the DRAM_EN bit in the DRAMHIBCTL register to 0 so that the DRAM interface signals are again driven directly by the memory controller. <9> Clear SUSPEND bit in the DRAMHIBCTL register to 0 to exit self-refresh mode. <10> Set the EDOMCYTREG and MEMCFG_REG registers in the memory controller according to the DRAM type to be used. <11> If DRAM can accept mixed use of burst and distributive CBR refresh, set a value that determines the refresh count to every 250 ns to the BCURFCNTREG register in the MBA Host Bridge. Then execute CBR refresh cycles for a specific time period (i.e. 0x3FFF x TClock period + burst refresh interval required by DRAM). <12> Restore to the BCURFCNTREG register in the MBA Host Bridge a value that determines refresh interval satisfying the conditions of DRAM type to be used.
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10.6.4 Exiting Hibernate mode (SDRAM) <1> Generate a wake-up event such as a transition on the POWER pin, a DCD interrupt, etc. which causes the PMU to start a power-on sequence. <2> Apply 2.5 V power supply when the MPOWER signal becomes high level. The PMU waits until 3.3 V and 2.5 V power supply are stable, and then deasserts the reset signals to the VR4110 CPU core and on-chip peripheral units. <3> Software execution resumes at the Cold Reset exception vector (0x0BFC 0000). Initialize the cache tags, and the Config, Status, and WatchLo registers in the CP0. Reset the HALTimer by setting the HALTIMERRST bit in the PMUCNTREG register to 1. <4> Check and clear the TIMOUTRST bit in the PMUINTREG register in the case a HALTimer Shutdown had occurred. <5> Copy the codes for the restore (<6> through <12> below) beginning at a 16-byte boundary into the cache by using a Fill operation of CACHE instruction, and jump to the cached codes. These codes can be executed on ROM. <6> Reinitialize all the registers and peripherals during Hibernate mode and restore those registers saved in the general-purpose registers, MISCREG(0:15) which retain values during Hibernate mode, in the GIU or in external memory. <7> Clear the DRAM_EN bit in the DRAMHIBCTL register to 0 so that the DRAM interface signals are again driven directly by the memory controller. <8> SDRAM exits the self-refresh mode. <9> Set the MEMCFG_REG, MODE_REG, and SDTIMINGREG registers in the memory controller according to the SDRAM type to be used. <11> If burst refreshes are needed, set a value that determines the refresh count to every 250 ns to the BCURFCNTREG register in the MBA Host Bridge. Then execute CBR auto refresh cycles for a specific time period (i.e. 0x3FFF x TClock period + burst refresh interval required by DRAM). <12> Restore to the BCURFCNTREG register in the MBA Host Bridge a value that determines refresh interval satisfying the conditions of DRAM type to be used.
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10.6.5 Entering Suspend mode (EDO DRAM) <1> Stop operations of the DMA controller and LCD controller. <2> Set registers in the ICU and CP0 to allow notification of the interrupt requests used as wake-up events to Fullspeed mode to the CPU core. <3> Copy the codes for the Suspend mode (<4> through <11> below) beginning at a 16-byte boundary into the cache by using a Fill operation of CACHE instruction, and jump to the cached codes. <4> Stop all peripheral clocks by writing zero to the CMUCLKMSK register in the MBA Host Bridge. <5> If DRAM can accept mixed use of burst and distributive CBR refresh, set a value that determines the refresh count to every 250 ns to the BCURFCNTREG register in the MBA Host Bridge. Then execute CBR refresh cycles for a specific time period (i.e. 0x3FFF x TClock period + burst refresh interval required by DRAM). <6> Set 0x3FF to the BCURFCNTREG register in the MBA Host Bridge that determines refresh interval to maximum to prevent an interruption of a Suspend mode sequence. <7> Set the SUSPEND bit in the DRAMHIBCTL register to 1. If the BstRefr bit of the MEMCFG_REG register in the memory controller to 1, the memory controller performs a burst refresh cycle and then put the DRAM into self-refresh mode. <8> Poll the OK_STOP_CLK bit in the DRAMHIBCTL register to confirm that the memory controller completes a burst refresh cycle and put the DRAM into self-refresh mode. <9> Set the STOP_CLK bit in the DRAMHIBCTL register to 1 to stop supplying TClock to the memory controller. <10> Set the DRAM_EN bit in the DRAMHIBCTL register to 1 so that the DRAM interface signals are latched. <11> Execute a SUSPEND instruction. Caution When entering Suspend mode, set the BEV bit of the Status register in the CP0 of the CPU core to 1 to make sure that the vector of the exception handler points the ROM area.
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10.6.6 Entering Suspend mode (SDRAM) <1> Stop operations of the DMA controller and LCD controller. <2> Set registers in the ICU and CP0 to allow notification of the interrupt requests used as wake-up events to Fullspeed mode to the CPU core. <3> Copy the codes for the Suspend mode (<4> through <12> below) beginning at a 16-byte boundary into the cache by using a Fill operation of CACHE instruction, and jump to the cached codes. <4> Stop all peripheral clocks by writing zero to the CMUCLKMSK register in the MBA Host Bridge. <5> Set the BCURFCNTREG register in the MBA Host Bridge to a value that determines refresh interval to maximum to prevent an interruption of a Suspend mode sequence. <6> If burst refreshes are needed, set a value that determines the refresh count to every 250 ns to the BCURFCNTREG register in the MBA Host Bridge. Then execute CBR auto refresh cycles for a specific time period (i.e. 0x3FFF x TClock period + burst refresh interval required by DRAM). <7> Clear the BstRefr bit of the MEMCFG_REG register in the memory controller to 0 to disable a burst refresh. Then set SUSPEND bit in the DRAMHIBCTL register to 1 to put the DRAM into self-refresh mode. <8> Poll the OK_STOP_CLK bit in the DRAMHIBCTL register to confirm that the memory controller puts the DRAM into self-refresh mode. <9> Set the STOP_CLK bit in the DRAMHIBCTL register to 1 to stop supplying TClock to the memory controller. <10> Set the DRAM_EN bit in the DRAMHIBCTL register to 1 so that the DRAM interface signals are latched. <11> Clear the SUSPEND bit in the DRAMHIBCTL register to 0 after waiting for about 2 s. <12> Execute a SUSPEND instruction. Caution When entering Suspend mode, set the BEV bit of the Status register in the CP0 of the CPU core to 1 to make sure that the vector of the exception handler points the ROM area.
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10.6.7 Exiting Suspend mode (EDO DRAM) <1> Generate a wake-up event from Suspend mode such as a transition on the POWER pin, a DCD interrupt, etc. <2> Software execution resumes at the General exception vector (0x0BFC 0380 when BEV = 1). <3> Copy the codes for the restore (<4> through <8> below) beginning at a 16-byte boundary into the cache by using a Fill operation of CACHE instruction, and jump to the cached codes. These codes can be executed on ROM. <4> Poll the OK_STOP_CLK bit in the DRAMHIBCTL register until it is set to 1. Remark Software must wait until the OK_STOP_CLK bit in the DRAMHIBCTL register is set to 1 before reinitializing the memory controller registers. Otherwise unpredictable behavior of the memory controller could result. <5> Clear the DRAM_EN bit in the DRAMHIBCTL register to 0 so that the DRAM interface signals are again driven directly by the memory controller. <6> Clear SUSPEND bit in the DRAMHIBCTL register to 0 to exit self-refresh mode. <7> If DRAM can accept mixed use of burst and distributive CBR refresh, set a value that determines the refresh count to every 250 ns to the BCURFCNTREG register in the MBA Host Bridge. Then execute CBR refresh cycles for a specific time period (i.e. 0x3FFF x TClock period + burst refresh interval required by DRAM). <8> Restore to the BCURFCNTREG register in the MBA Host Bridge a value that determines refresh interval satisfying the conditions of DRAM type to be used. 10.6.8 Exiting Suspend mode (SDRAM) <1> Generate a wake-up event from Suspend mode such as a transition on the POWER pin, a DCD interrupt, etc. <2> Software execution resumes at the General exception vector (0x0BFC 0380 when BEV = 1). <3> Copy the codes for the restore (<4> through <7> below) beginning at a 16-byte boundary into the cache by using a Fill operation of CACHE instruction, and jump to the cached codes. These codes can be executed on ROM. <4> Clear the DRAM_EN bit in the DRAMHIBCTL register to 0 so that the DRAM interface signals are again driven directly by the memory controller. <5> SDRAM exits the self-refresh mode. <6> If burst refreshes are needed, set a value that determines the refresh count to every 250 ns to the BCURFCNTREG register in the MBA Host Bridge. Then execute CBR auto refresh cycles for a specific time period (i.e. 0x3FFF x TClock period + burst refresh interval required by DRAM). <7> Restore to the BCURFCNTREG register in the MBA Host Bridge a value that determines refresh interval satisfying the conditions of DRAM type to be used.
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10.7 Register Set
The PMU registers are listed below: Table 10-4. PMU Registers
Physical address 0x0B00 00A0 0x0B00 00A2 0x0B00 00A8 0x0B00 00AC 0x0B00 00B2 R/W R/W R/W R/W R/W R/W Register symbol PMUINTREG PMUCNTREG PMUWAITREG PMUDIVREG DRAMHIBCTL Function PMU interrupt status register PMU control register PMU wait counter register PMU Div mode register DRAM Hibernate mode control register
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10.7.1 PMUINTREG (0x0B00 00A0) (1/2)
Bit Name 15 Reserved 14 Reserved 13 Reserved 12 GP WAKEUP R/W 0 0 11 CF_INT 10 DCDST 9 RTCINTR 8 BATTINH
R/W RTCRST Other resets
R 0 0
R 0 0
R 0 0
R/W 0 0
R 0 0
R/W 0 0
R/W 0 0
Bit Name
7 Reserved
6 SDRAM
5 TIMOUT RST R/W 0 0
4 RTCRST
3 RSTSW
2 DMSRST
1 BATTINTR
0 POWER SWINTR R/W 0 0
R/W RTCRST Other resets
R/W 0 0
R/W 0 0
R/W 0 0
R/W 0 0
R/W 0 0
R/W 0 0
Bit 15 to 13 12 Reserved
Name 0 is returned when read
Function
GPWAKEUP
GPIO interrupt request detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected This bit must be checked and cleared to 0 after the CPU core is restarted.
11
CF_INT
CompactFlash interrupt request detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected This bit must be checked and cleared to 0 after the CPU core is restarted.
10
DCDST
DCD1# pin state 1 : High level (inactive) 0 : Low level (active)
9
RTCINTR
ElapsedTime (RTC alarm) interrupt request detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected This bit must be checked and cleared to 0 after the CPU core is restarted.
8
BATTINH
Battery low detection during activation. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected This bit must be checked and cleared to 0 after the CPU core is restarted.
7 6
Reserved SDRAM
Write 0 when write. 0 is returned when read. This bit determines whether the internal peripheral units are reset by RSTSW. This bit must be clear to 0 when EDO DRAM is used. 1 : Not reset (SDRAM data preserved during RSTSW) 0 : Reset (SDRAM data lost during RSTSW)
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(2/2)
Bit 5 Name TIMOUTRST Function HALTimer reset request detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected This bit must be checked and cleared to 0 after the CPU core is restarted. 4 RTCRST RTC reset detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected This bit must be checked and cleared to 0 after the CPU core is restarted. 3 RSTSW RSTSW interrupt request detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected This bit must be checked and cleared to 0 after the CPU core is restarted. 2 DMSRST Deadman's Switch interrupt request detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected This bit must be checked and cleared to 0 after the CPU core is restarted. 1 BATTINTR Battery low detection during normal operation. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected This bit must be checked and cleared to 0 after the CPU core is restarted. 0 POWERSWINTR Power Switch interrupt request detection. Cleared to 0 when 1 is written. 1 : Detected 0 : Not detected This bit must be checked and cleared to 0 after the CPU core is restarted.
This register indicates the statuses of power-on factors and interrupt requests. It also indicates the status of the DCD1# pin. The BATTINTR bit is set to 1 when the BATTINH/BATTINT# signal becomes low and a battery-low interrupt request occurs during modes other than the Hibernate mode (MPOWER = H). The POWERSWINTR bit is set to 1 when the POWER signal becomes high and a Power Switch interrupt request occurs during modes other than the Hibernate mode. However, this bit is not set to 1 when the POWER signal becomes high during the Hibernate mode (MPOWER = L).
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10.7.2 PMUCNTREG (0x0B00 00A2) (1/2)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name
7 STANDBY
6 Reserved
5 Selfrfresh
4 Suspend
3 Hibernate
2 HALTIMER RST R/W 0 0
1 Reserved
0 Reserved
R/W RTCRST Other resets
R/W 0 Note
R/W 0 0
R 0 0
R 0 0
R 0 0
R 0 0
R/W 0 0
Bit 15 to 8 7 Reserved STANDBY
Name 0 is returned when read
Function
Standby mode setting. This setting is performed only for software, and does not affect hardware in any way. 1 : Standby mode 0 : Normal mode
6 5
Reserved Selfrfresh
Write 0 when write. 0 is returned when read. Self refresh status 1 : Completed 0 : Not completed
4
Suspend
Suspend mode status (always 0 during Fullspeed mode) 1 : Suspend mode 0 : Other than Suspend mode
3
Hibernate
Hibernate mode status (always 0 during Fullspeed mode) 1 : Hibernate mode 0 : Other than Hibernate mode
Note Holds the value before reset.
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(2/2)
Bit 2 Name HALTIMERRST HALTimer reset 1 : Reset 0 : Set This bit is cleared to 0 automatically after reset of the HALTimer 1 0 Reserved Reserved 0 is returned when read Write 0 when write. 0 is returned when read.
Note1, 2
Function
.
Notes1. When the HALTIMERRST bit is cleared to 0 just after set to 1, the HALTimer may not be reset. Wait more than 6 RTC clock cycles from writing 1 to writing 0. 2. Verify that the HALTIMERRST bit is 0 before reset the HALTimer. When this bit is 1, the HALTimer is not reset even if write 1 to this bit. In this case, write 0 to this bit first, then write 1 after more than 6 RTC clock cycles. This register is used to set CPU core shutdown and overall system operations management. The HALTIMERRST bit must be reset within about four seconds after activation. Resetting of the HALTIMERRST bit indicates that the VR4181 itself has been activated normally. If the HALTIMERRST bit is not reset within about four seconds after activation, program execution is regarded as abnormal (possibly due to a runaway) and an automatic shutdown is performed.
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10.7.3 PMUWAITREG (0x0B00 00A8)
Bit Name 15 Reserved 14 Reserved 13 WCOUNT 13 R/W 1 Note 12 WCOUNT 12 R/W 0 Note 11 WCOUNT 11 R/W 1 Note 10 WCOUNT 10 R/W 1 Note 9 WCOUNT 9 R/W 0 Note 8 WCOUNT 8 R/W 0 Note
R/W RTCRST Other resets
R 0 0
R 0 0
Bit Name
7 WCOUNT 7 R/W 0 Note
6 WCOUNT 6 R/W 0 Note
5 WCOUNT 5 R/W 0 Note
4 WCOUNT 4 R/W 0 Note
3 WCOUNT 3 R/W 0 Note
2 WCOUNT 2 R/W 0 Note
1 WCOUNT 1 R/W 0 Note
0 WCOUNT 0 R/W 0 Note
R/W RTCRST Other resets
Bit 15, 14 13 to 0 Reserved
Name 0 is returned when read
Function
WCOUNT(13:0)
Activation wait time timer count value Activation wait time = WCOUNT(13:0) x (1/32.768) ms
Note Holds the value before reset This register is used to set the activation wait time when the CPU core is activated. This register is set to 0x2C00 (i.e. 343.75 ms activation wait time) after RTC reset. Therefore, the 343.75 ms wait time is always inserted as an activation wait time, when the CPU core is activated immediately after RTC reset. The activation wait time can be changed by setting this register for the CPU core activation from the Hibernate mode. When this register is set to 0x0, 0x1, 0x2, 0x3, or 0x4, the operation is not guaranteed. Software must set the value of this register to greater than 0x4 to assure reliable operation.
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10.7.4 PMUDIVREG (0x0B00 00AC)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 Reserved R 0 0
2 DIV2 R/W 0 Note
1 DIV1 R/W 0 Note
0 DIV0 R/W 0 Note
Bit 15 to 3 2 to 0 Reserved DIV(2:0)
Name 0 is returned when read Divide mode 111 : RFU 110 : RFU 101 : RFU 100 : RFU 011 : DIV3 mode 010 : DIV2 mode 001 : DIV1 mode 000 : Default mode (DIV2)
Function
Note Holds the value before reset This register is used to set CPU core's Div mode. The Div mode setting determines the division rate of the TClock in relation to the pipeline clock (PClock) frequency. Since the contents of this register are cleared to 0 during an RTC reset, the Div mode setting always DIV2 mode just after RTC reset. Though the Div mode has been set via this register, the setting does not become effective immediately in the processor's operations. In order to change Div mode, software has to put the CPU core into the Hibernate mode. The Div mode will change when the CPU core wakes up from the Hibernate mode.
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10.7.5 DRAMHIBCTL (0x0B00 00B2)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name
7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 OK_STOP _CLK R 0 Note
2 STOP _CLK R/W 0 Note
1 SUSPEND
0 DRAM_EN
R/W RTCRST Other resets
R 0 0
R 0 0
R 0 0
R Undefined Undefined
R/W 0 Note
R/W 0 Note
Bit 15 to 5 4 3 Reserved Reserved
Name 0 is returned when read
Function
An undefined value is returned when read Ready to stop clocks 1 : Ready (DRAM is in self refresh mode) 0 : Not ready (MEMC is busy to do burst refresh)
OK_STOP_CLK
2
STOP_CLK
Clock supply for MEMC 1 : Stop 0 : Supply
1
SUSPEND
Self refresh request. This bit is for software request to MEMC to perform burst refresh and enter self refresh mode 1 : Request 0 : Not request
0
DRAM_EN
DRAM interface operation enable 1 : Disabled 0 : Enabled (normal mode)
Note Holds the value before reset
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CHAPTER 11 REALTIME CLOCK UNIT (RTC)
This chapter describes the RTC unit's operations and register settings.
11.1 General
The RTC unit has a total of three timers, including the following two types. * RTCLong .......... This is a 24-bit programmable counter that counts down by 32.768 kHz clock cycle. Cycle interrupts can be occurred for up to every 512 seconds. The RTC unit of the VR4181 includes two RTCLong timers. * ElapsedTime..... This is a 48-bit up counter that counts up by 32.768 kHz clock cycle. It counts up to 272 years before returning to zero. It includes 48-bit comparator (ECMPLREG, ECMPMREG, and ECMPHREG) and 48-bit alarm time register (ETIMELREG, ETIMEMREG, and ETIMEHREG) to enable interrupts to occur at specified times.
11.2 Register Set
The RTC registers are listed below. Table 11-1. RTC Registers
Physical address 0x0B00 00C0 0x0B00 00C2 0x0B00 00C4 0x0B00 00C8 0x0B00 00CA 0x0B00 00CC 0x0B00 00D0 0x0B00 00D2 0x0B00 00D4 0x0B00 00D6 0x0B00 00D8 0x0B00 00DA 0x0B00 00DC 0x0B00 00DE 0x0B00 01DE R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R R R/W Register symbol ETIMELREG ETIMEMREG ETIMEHREG ECMPLREG ECMPMREG ECMPHREG RTCL1LREG RTCL1HREG RTCL1CNTLREG RTCL1CNTHREG RTCL2LREG RTCL2HREG RTCL2CNTLREG RTCL2CNTHREG RTCINTREG ElapsedTime L register ElapsedTime M register ElapsedTime H register ElapsedTime compare L register ElapsedTime compare M register ElapsedTime compare H register RTCLong1 L register RTCLong1 H register RTCLong1 count L register RTCLong1 count H register RTCLong2 L register RTCLong2 H register RTCLong2 count L register RTCLong2 count H register RTC interrupt register Function
Each register is described in detail below.
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11.2.1 ElapsedTime registers (1) ETIMELREG (0x0B00 00C0)
Bit Name R/W RTCRST Other resets 15 ETIME15 R/W 0 Note 14 ETIME14 R/W 0 Note 13 ETIME13 R/W 0 Note 12 ETIME12 R/W 0 Note 11 ETIME11 R/W 0 Note 10 ETIME10 R/W 0 Note 9 ETIME9 R/W 0 Note 8 ETIME8 R/W 0 Note
Bit Name R/W RTCRST Other resets
7 ETIME7 R/W 0 Note
6 ETIME6 R/W 0 Note
5 ETIME5 R/W 0 Note
4 ETIME4 R/W 0 Note
3 ETIME3 R/W 0 Note
2 ETIME2 R/W 0 Note
1 ETIME1 R/W 0 Note
0 ETIME0 R/W 0 Note
Bit 15 to 0
Name ETIME(15:0) ElapsedTime timer bits 15 to 0
Function
Note Continues counting. (2) ETIMEMREG (0x0B00 00C2)
Bit Name R/W RTCRST Other resets 15 ETIME31 R/W 0 Note 14 ETIME30 R/W 0 Note 13 ETIME29 R/W 0 Note 12 ETIME28 R/W 0 Note 11 ETIME27 R/W 0 Note 10 ETIME26 R/W 0 Note 9 ETIME25 R/W 0 Note 8 ETIME24 R/W 0 Note
Bit Name R/W RTCRST Other resets
7 ETIME23 R/W 0 Note
6 ETIME22 R/W 0 Note
5 ETIME21 R/W 0 Note
4 ETIME20 R/W 0 Note
3 ETIME19 R/W 0 Note
2 ETIME18 R/W 0 Note
1 ETIME17 R/W 0 Note
0 ETIME16 R/W 0 Note
Bit 15 to 0
Name ETIME(31:16) ElapsedTime timer bits 31 to 16
Function
Note Continues counting.
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(3) ETIMEHREG (0x0B00 00C4)
Bit Name R/W RTCRST Other resets 15 ETIME47 R/W 0 Note 14 ETIME46 R/W 0 Note 13 ETIME45 R/W 0 Note 12 ETIME44 R/W 0 Note 11 ETIME43 R/W 0 Note 10 ETIME42 R/W 0 Note 9 ETIME41 R/W 0 Note 8 ETIME40 R/W 0 Note
Bit Name R/W RTCRST Other resets
7 ETIME39 R/W 0 Note
6 ETIME38 R/W 0 Note
5 ETIME37 R/W 0 Note
4 ETIME36 R/W 0 Note
3 ETIME35 R/W 0 Note
2 ETIME34 R/W 0 Note
1 ETIME33 R/W 0 Note
0 ETIME32 R/W 0 Note
Bit 15 to 0
Name ETIME(47:32) ElapsedTime timer bits 47 to 32
Function
Note Continues counting These registers indicate the ElapsedTime timer's value. They count up by a 32.768 kHz clock cycle and when a match occurs with the ElapsedTime compare registers, an alarm (ElapsedTime interrupt) occurs (and the counting continues). A write operation is valid once values have been written to all registers (ETIMELREG, ETIMEMREG, and ETIMEHREG). These registers have no buffers for read. Therefore, an illegal data may be read if the timer value changes during a read operation. When using the read value as a data, be sure to read these registers twice and check that two read vales are the same. When setting these registers again, wait until at least 100 s (three cycles of 32.768 kHz clock) have elapsed after the first setting.
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11.2.2 ElapsedTime compare registers (1) ECMPLREG (0x0B00 00C8)
Bit Name R/W RTCRST Other resets 15 ECMP15 R/W 0 Note 14 ECMP14 R/W 0 Note 13 ECMP13 R/W 0 Note 12 ECMP12 R/W 0 Note 11 ECMP11 R/W 0 Note 10 ECMP10 R/W 0 Note 9 ECMP9 R/W 0 Note 8 ECMP8 R/W 0 Note
Bit Name R/W RTCRST Other resets
7 ECMP7 R/W 0 Note
6 ECMP6 R/W 0 Note
5 ECMP5 R/W 0 Note
4 ECMP4 R/W 0 Note
3 ECMP3 R/W 0 Note
2 ECMP2 R/W 0 Note
1 ECMP1 R/W 0 Note
0 ECMP0 R/W 0 Note
Bit 15 to 0
Name ECMP(15:0)
Function Value to be compared with ElapsedTime timer bits 15 to 0
Note Holds the value before reset. (2) ECMPMREG (0x0B00 00CA)
Bit Name R/W RTCRST Other resets 15 ECMP31 R/W 0 Note 14 ECMP30 R/W 0 Note 13 ECMP29 R/W 0 Note 12 ECMP28 R/W 0 Note 11 ECMP27 R/W 0 Note 10 ECMP26 R/W 0 Note 9 ECMP25 R/W 0 Note 8 ECMP24 R/W 0 Note
Bit Name R/W RTCRST Other resets
7 ECMP23 R/W 0 Note
6 ECMP22 R/W 0 Note
5 ECMP21 R/W 0 Note
4 ECMP20 R/W 0 Note
3 ECMP19 R/W 0 Note
2 ECMP18 R/W 0 Note
1 ECMP17 R/W 0 Note
0 ECMP16 R/W 0 Note
Bit 15 to 0
Name ECMP(31:16)
Function Value to be compared with ElapsedTime timer bits 31 to 16
Note Holds the value before reset.
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(3) ECMPHREG (0x0B00 00CC)
Bit Name R/W RTCRST Other resets 15 ECMP47 R/W 1 Note 14 ECMP46 R/W 0 Note 13 ECMP45 R/W 0 Note 12 ECMP44 R/W 0 Note 11 ECMP43 R/W 0 Note 10 ECMP42 R/W 0 Note 9 ECMP41 R/W 0 Note 8 ECMP40 R/W 0 Note
Bit Name R/W RTCRST Other resets
7 ECMP39 R/W 0 Note
6 ECMP38 R/W 0 Note
5 ECMP37 R/W 0 Note
4 ECMP36 R/W 0 Note
3 ECMP35 R/W 0 Note
2 ECMP34 R/W 0 Note
1 ECMP33 R/W 0 Note
0 ECMP32 R/W 0 Note
Bit 15 to 0
Name ECMP(47:32)
Function Value to be compared with ElapsedTime timer bits 47 to 32
Note Holds the value before reset. Use these registers to set the values to be compared with values in the ElapsedTime registers. A write operation is valid once values have been written to all registers (ECMPLREG, ECMPMREG, and ECMPHREG). When setting these registers again, wait until at least 100 s (three cycles of 32.768 kHz clock) have elapsed after the first setting.
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11.2.3 RTCLong1 registers (1) RTCL1LREG (0x0B00 00D0)
Bit Name R/W RTCRST Other resets 15 RTCL1P15 R/W 0 Note 14 RTCL1P14 R/W 0 Note 13 RTCL1P13 R/W 0 Note 12 RTCL1P12 R/W 0 Note 11 RTCL1P11 R/W 0 Note 10 RTCL1P10 R/W 0 Note 9 RTCL1P9 R/W 0 Note 8 RTCL1P8 R/W 0 Note
Bit Name R/W RTCRST Other resets
7 RTCL1P7 R/W 0 Note
6 RTCL1P6 R/W 0 Note
5 RTCL1P5 R/W 0 Note
4 RTCL1P4 R/W 0 Note
3 RTCL1P3 R/W 0 Note
2 RTCL1P2 R/W 0 Note
1 RTCL1P1 R/W 0 Note
0 RTCL1P0 R/W 0 Note
Bit 15 to 0
Name RTCL1P(15:0)
Function Bits 15 to 0 for RTCLong1 timer count cycle
Note Holds the value before reset.
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(2) RTCL1HREG (0x0B00 00D2)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 Note 14 Reserved R 0 Note 13 Reserved R 0 Note 12 Reserved R 0 Note 11 Reserved R 0 Note 10 Reserved R 0 Note 9 Reserved R 0 Note 8 Reserved R 0 Note
Bit Name R/W RTCRST Other resets
7 RTCL1P23 R/W 0 Note
6 RTCL1P22 R/W 0 Note
5 RTCL1P21 R/W 0 Note
4 RTCL1P20 R/W 0 Note
3 RTCL1P19 R/W 0 Note
2 RTCL1P18 R/W 0 Note
1 RTCL1P17 R/W 0 Note
0 RTCL1P16 R/W 0 Note
Bit 15 to 8 7 to 0 Reserved
Name 0 is returned when read
Function
RTCL1P(23:16)
Bits 23 to 16 for RTCLong1 timer count cycle
Note Holds the value before reset. Use these registers to set the RTCLong1 timer count cycle. The RTCLong1 timer begins its countdown at the value written to these registers. A write operation is valid once values have been written to both registers (RTCL1LREG and RTCL1HREG). When setting these registers again, wait until at least 100 s (three cycles of 32.768 kHz clock) have elapsed after the first setting. Cautions 1. The RTCLong1 timer is stopped when all zeros are written. 2. Any combined setting of "RTCL1HREG = 0x0000" and "RTCL1LREG = 0x0001, 0x0002, 0x0003, or 0x0004" is prohibited.
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11.2.4 RTCLong1 count registers (1) RTCL1CNTLREG (0x0B00 00D4)
Bit Name R/W RTCRST Other resets 15 RTCL1C15 R 0 Note 14 RTCL1C14 R 0 Note 13 RTCL1C13 R 0 Note 12 RTCL1C12 R 0 Note 11 RTCL1C11 R 0 Note 10 RTCL1C10 R 0 Note 9 RTCL1C9 R 0 Note 8 RTCL1C8 R 0 Note
Bit Name R/W RTCRST Other resets
7 RTCL1C7 R 0 Note
6 RTCL1C6 R 0 Note
5 RTCL1C5 R 0 Note
4 RTCL1C4 R 0 Note
3 RTCL1C3 R 0 Note
2 RTCL1C2 R 0 Note
1 RTCL1C1 R 0 Note
0 RTCL1C0 R 0 Note
Bit 15 to 0
Name RTCL1C(15:0) RTCLong1 timer bits 15 to 0
Function
Note Continues counting.
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(2) RTCL1CNTHREG (0x0B00 00D6)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 Note 14 Reserved R 0 Note 13 Reserved R 0 Note 12 Reserved R 0 Note 11 Reserved R 0 Note 10 Reserved R 0 Note 9 Reserved R 0 Note 8 Reserved R 0 Note
Bit Name R/W RTCRST Other resets
7 RTCL1C23 R 0 Note
6 RTCL1C22 R 0 Note
5 RTCL1C21 R 0 Note
4 RTCL1C20 R 0 Note
3 RTCL1C19 R 0 Note
2 RTCL1C18 R 0 Note
1 RTCL1C17 R 0 Note
0 RTCL1C16 R 0 Note
Bit 15 to 8 7 to 0 Reserved
Name 0 is returned when read RTCLong1 timer bits 23 to 16
Function
RTCL1C(23:16)
Note Continues counting. These registers indicate the RTCLong1 timer's values. It counts down by a 32.768 kHz clock cycle and begins counting at the value set to the RTCLong1 registers. An RTCLong1 interrupt occurs when the timer value reaches 0x00 0001 (at which point the timer returns to the start value and continues counting). These registers have no buffers for read. Therefore, an illegal data may be read if the timer value changes during a read operation. When using the read value as a data, be sure to read the registers twice and check that two read vales are the same.
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11.2.5 RTCLong2 registers (1) RTCL2LREG (0x0B00 00D8)
Bit Name R/W RTCRST Other resets 15 RTCL2P15 R/W 0 Note 14 RTCL2P14 R/W 0 Note 13 RTCL2P13 R/W 0 Note 12 RTCL2P12 R/W 0 Note 11 RTCL2P11 R/W 0 Note 10 RTCL2P10 R/W 0 Note 9 RTCL2P9 R/W 0 Note 8 RTCL2P8 R/W 0 Note
Bit Name R/W RTCRST Other resets
7 RTCL2P7 R/W 0 Note
6 RTCL2P6 R/W 0 Note
5 RTCL2P5 R/W 0 Note
4 RTCL2P4 R/W 0 Note
3 RTCL2P3 R/W 0 Note
2 RTCL2P2 R/W 0 Note
1 RTCL2P1 R/W 0 Note
0 RTCL2P0 R/W 0 Note
Bit 15 to 0
Name RTCL2P(15:0)
Function Bits 15 to 0 for RTCLong2 timer count cycle
Note Holds the value before reset.
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(2) RTCL2HREG (0x0B00 00DA)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 Note 14 Reserved R 0 Note 13 Reserved R 0 Note 12 Reserved R 0 Note 11 Reserved R 0 Note 10 Reserved R 0 Note 9 Reserved R 0 Note 8 Reserved R 0 Note
Bit Name R/W RTCRST Other resets
7 RTCL2P23 R/W 0 Note
6 RTCL2P22 R/W 0 Note
5 RTCL2P21 R/W 0 Note
4 RTCL2P20 R/W 0 Note
3 RTCL2P19 R/W 0 Note
2 RTCL2P18 R/W 0 Note
1 RTCL2P17 R/W 0 Note
0 RTCL2P16 R/W 0 Note
Bit 15 to 8 7 to 0 Reserved
Name 0 is returned when read
Function
RTCL2P(23:16)
Bits 23 to 16 for RTCLong2 timer count cycle
Note Holds the value before reset. Use these registers to set the RTCLong2 timer count cycle. The RTCLong2 timer begins its countdown at the value written to these registers. A write operation is valid once values have been written to both registers (RTCL2LREG and RTCL2HREG). When setting these registers again, wait until at least 100 s (three cycles of 32.768 kHz clock) have elapsed after the first setting. Cautions 1. The RTCLong2 timer is stopped when all zeros are written. 2. Any combined setting of "RTCL2HREG = 0x0000" and "RTCL2LREG = 0x0001, 0x0002, 0x0003, or 0x0004" is prohibited.
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11.2.6 RTCLong2 count registers (1) RTCL2CNTLREG (0x0B00 00DC)
Bit Name R/W RTCRST Other resets 15 RTCL2C15 R 0 Note 14 RTCL2C14 R 0 Note 13 RTCL2C13 R 0 Note 12 RTCL2C12 R 0 Note 11 RTCL2C11 R 0 Note 10 RTCL2C10 R 0 Note 9 RTCL2C9 R 0 Note 8 RTCL2C8 R 0 Note
Bit Name R/W RTCRST Other resets
7 RTCL2C7 R 0 Note
6 RTCL2C6 R 0 Note
5 RTCL2C5 R 0 Note
4 RTCL2C4 R 0 Note
3 RTCL2C3 R 0 Note
2 RTCL2C2 R 0 Note
1 RTCL2C1 R 0 Note
0 RTCL2C0 R 0 Note
Bit 15 to 0
Name RTCL2C(15:0) RTCLong2 timer bits 15 to 0
Function
Note Continues counting.
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(2) RTCL2CNTHREG (0x0B00 00DE)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 Note 14 Reserved R 0 Note 13 Reserved R 0 Note 12 Reserved R 0 Note 11 Reserved R 0 Note 10 Reserved R 0 Note 9 Reserved R 0 Note 8 Reserved R 0 Note
Bit Name R/W RTCRST Other resets
7 RTCL2C23 R 0 Note
6 RTCL2C22 R 0 Note
5 RTCL2C21 R 0 Note
4 RTCL2C20 R 0 Note
3 RTCL2C19 R 0 Note
2 RTCL2C18 R 0 Note
1 RTCL2C17 R 0 Note
0 RTCL2C16 R 0 Note
Bit 15 to 8 7 to 0 Reserved
Name 0 is returned when read RTCLong2 timer bits 23 to 16
Function
RTCL2C(23:16)
Note Continues counting. These registers indicate the RTCLong2 timer's values. It counts down by a 32.768 kHz clock cycle and begins counting at the value set to the RTCLong2 registers. An RTCLong2 interrupt occurs when the timer value reaches 0x00 0001 (at which point the timer returns to the start value and continues counting). These registers have no buffers for read. Therefore, an illegal data may be read if the timer value changes during a read operation. When using the read value as a data, be sure to read the registers twice and check that two read vales are the same.
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11.2.7 RTC interrupt register (1) RTCINTREG (0x0B00 01DE)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 Reserved R 0 0
2 RTCINTR2 R/W 0 Note
1 RTCINTR1 R/W 0 Note
0 RTCINTR0 R/W 0 Note
Bit 15 to 3 2 Reserved
Name 0 is returned when read
Function
RTCINTR2
RTCLong2 interrupt request. Cleared to 0 when 1 is written. 1 : Occurred 0 : Normal RTCLong1 interrupt request. Cleared to 0 when 1 is written. 1 : Occurred 0 : Normal ElapsedTime interrupt request. Cleared to 0 when 1 is written. 1 : Occurred 0 : Normal
1
RTCINTR1
0
RTCINTR0
Note Holds the value before reset. This register indicates the occurrences of interrupt requests of RTC.
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CHAPTER 12 DEADMAN'S SWITCH UNIT (DSU)
This chapter describes operations and register settings of the DSU (Deadman's Switch Unit).
12.1 General
The DSU detects runaway (endless loop) state of the VR4181 and resets the VR4181. Use of the DSU allows terminating runaway states that may occur due to software in earlier phase to minimize data loss.
12.2 Register Set
The DSU registers are listed below. Table 12-1. DSU Registers
Physical address 0x0B00 00E0 0x0B00 00E2 0x0B00 00E4 0x0B00 00E6 R/W R/W R/W W R/W Register symbol DSUCNTREG DSUSETREG DSUCLRREG DSUTIMREG DSU control register DSU cycle setting register DSU clear register DSU elapsed time register Function
Each register is described in detail below.
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12.2.1 DSUCNTREG (0x0B00 00E0)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 Reserved R 0 0
2 Reserved R 0 0
1 Reserved R 0 0
0 DSWEN R/W 0 0
Bit 15 to 1 0 Reserved DSWEN
Name 0 is returned when read Deadman's Switch function enable 1 : Enabled 0 : Disabled
Function
This register is used to enable use of the Deadman's Switch function.
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CHAPTER 12 DEADMAN'S SWITCH UNIT (DSU)
12.2.2 DSUSETREG (0x0B00 00E2)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 DEDTIME3 R/W 0 0
2 DEDTIME2 R/W 0 0
1 DEDTIME1 R/W 0 0
0 DEDTIME0 R/W 1 1
Bit 15 to 4 3 to 0 Reserved
Name 0 is returned when read Deadman's Switch cycle setting 1111 : 15 seconds 1110 : 14 seconds : 0010 : 2 seconds 0001 : 1 second 0000 : Setting prohibited
Function
DEDTIME(3:0)
This register is used to set the cycle for Deadman's Switch function. The Deadman's Switch cycle can be set in 1-second units in a range from 1 to 15 seconds. The DSWCLR bit in the DSUCLRREG register must be set by means of software within the cycle time specified in this register. The VR4181's operation is undefined when 0x0 has been set to DEDTIME(3:0).
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12.2.3 DSUCLRREG (0x0B00 00E4)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 Reserved R 0 0
2 Reserved R 0 0
1 Reserved R 0 0
0 DSWCLR W 0 0
Bit 15 to 1 0 Reserved DSWCLR
Name 0 is returned when read Deadman's Switch timer clear 1 : Clear (stops timer) 0 : Timer counting
Function
The Deadman's Switch timer is cleared by setting the DSWCLR bit in this register to 1. The VR4181 automatically enters in a Cold Reset status if 1 is not written to this register within the period specified in the DSUSETREG register. In order to restart operation of the timer, the DSWCLR bit in this register must be cleared to 0.
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CHAPTER 12 DEADMAN'S SWITCH UNIT (DSU)
12.2.4 DSUTIMREG (0x0B00 00E6)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 CRTTIME3 R/W 0 0
2 CRTTIME2 R/W 0 0
1 CRTTIME1 R/W 0 0
0 CRTTIME0 R/W 0 0
Bit 15 to 4 3 to 0 Reserved
Name 0 is returned when read
Function
CRTTIME(3:0)
Current Deadman's Switch timer value (elapsed time) 1111 : 15 seconds 1110 : 14 seconds : 0010 : 2 seconds 0001 : 1 second 0000 : Setting prohibited
This register indicates the elapsed time of the current Deadman's Switch timer.
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12.3 Register Setting Flow
The DSU register setting flow is described below. <1> Set the DSU timer count cycle (from 1 to 15 seconds). Register: DSUSETREG, address: 0x0B00 00E2, data: 0x000x The CPU core will be reset if the timer is not cleared (1 is not written to DSUCLRREG register) within this time period. <2> Enable the DSU. Register: DSUCNTREG, address: 0x0B00 00E0, data: 0x0001 <3> Clear the timer within the time period specified in step 1 above. Cancel the clearance of the timer to start another counting. Register: DSUCLRREG, address: 0x0B00 00E4, data: 0x0001 (timer clear) Register: DSUCLRREG, address: 0x0B00 00E4, data: 0x0000 (timer operation start) For normal use, repeat step 3. To obtain the current elapsed time, read the contents (4 bits) of the DSUTIMREG register (address: 0x0B00 00E6). <4> Disable the DSU during Suspend mode or a shutdown. Register: DSUCNTREG, address: 0x0B00 00E0, data: 0x0000
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CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU)
13.1 Overview
13.1.1 GPIO pins and alternate functions The VR4181 provides 32 general-purpose I/O divided into two groups of 16 pins each. The first group, GPIO(15:0) pins, are capable of supporting the following types of functions: * Clocked serial interface (CSI) * Serial interface channel 2 * Color LCD interface (upper 4-bit data) or CompactFlash Card Detect inputs * General-purpose outputs * Interrupt/wake-up inputs * Programmable chip selects * External ISA system clock output Any of GPIO(15:0) pins can be used as interrupt/wake-up inputs. The assignment of interface signals to particular GPIO pins is shown in the following table: Table 13-1. Alternate Functions of GPIO(15:0) Pins
GPIO pin Alternate signal 1 FPD7 FPD6 FPD5 FPD4 PCS1# FRM CTS2# DSR2# DTR2# RTS2# DCD2# - PCS0# SCK SO SI Alternate signal 2 CD2# CD1# - - - SYSCLK - - - - - - - - - - Definition
GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
Color LCD data bit output or Card Detect 2 input Color LCD data bit output or Card Detect 1 input Color LCD data bit output Color LCD data bit output Programmable chip select 1 output. CSI FRM input or SYSCLK output SIU2 CTS input SIU2 DSR input SIU2 DTR output SIU2 RTS output SIU2 DCD input - Programmable chip select 0 output. CSI serial clock input CSI serial data output CSI serial data input
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The second group, GPIO(31:16) pins, are capable of supporting the following types of functions: * External ISA I/O interface * External 16-bit bus sizing signal * ROM chip select * Serial interface channel 1 * General-purpose input * General-purpose output Remark GPIO(31:16) pins can not be used as interrupt/wake-up inputs. The assignment of interface signals to particular GPIO pins is shown in the following table: Table 13-2. Alternate Functions of GPIO(31:16) Pins
GPIO pin Alternate signal 1 DSR1# DTR1# DCD1# CTS1# RTS1# TxD1 RxD1 ROMCS2# ROMCS1# ROMCS0# RESET# UBE# IOCS16# IORDY IOWR# IORD# M - - - - Alternate signal 2 - - - - - - - - - - - SIU1 DSR input SIU1 DTR output SIU1 DCD input SIU1 CTS input SIU1 RTS output SIU1 transmit data output SIU1 receive data input ROM chip select for bank 2 ROM chip select for bank 1 ROM chip select for bank 0 External ISA reset External ISA upper byte enable or LCD modulation output External ISA I/O 16-bit bus sizing External ISA I/O channel ready External ISA I/O write strobe External ISA I/O read strobe Definition
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16
Note
Note This signal supports input only. The GPIO29/DCD1# pin can be used as an activation (wake-up) factor from Hibernate mode if enabled by software. The other pins listed above are only capable of providing general-purpose input or output, or the alternate function listed.
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CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU)
13.1.2 I/O direction control For each GPIO pin, the GIU provides register fields of one buffer enable, GPENn, one output data, GPOn, and one input data, GPIn. The function of each GPIO pin is decoded by 2 register bits in one of the GPIO Mode registers. The most significant bit, GPnMD1, controls the input/output direction of the GPIO pin while the system is powered (during Fullspeed, Standby, or Suspend mode). When this bit is set to 1, the GPIO pin is normally configured as an output. During Hibernate mode, the GPIO buffer enables are controlled by the GPHIBSTH and GPHIBSTL registers. Remark n = 0 to 31 13.1.3 General-purpose registers The GIU includes sixteen 16-bit general-purpose registers. Since the contents of these registers are preserved even during Hibernate mode, these registers can be used by system software to save the state of selected registers located in the 2.5 V block prior to entering Hibernate mode. Once the VR4181 has resumed from Hibernate mode, system software can then restore the state of those 2.5 V registers from the general-purpose registers. The general-purpose registers are located in the address range of 0x0B00 0330 to 0x0B00 034F.
13.2 Alternate Functions Overview
13.2.1 Clocked serial interface (CSI) The clocked serial interface is enabled by writing to the GPIO Mode registers and utilizes the following GPIO pins: Table 13-3. CSI Interface Signals
GPIO pin GPIO2 GPIO1 GPIO0 GPIO10 SCK SO SI FRM CSI signal Input Output Input Input Type
The GPIO10/FRM pin provides a multifunction control input option. In one mode, FRM determines data direction (transmit or receive). In the other mode, FRM prohibits transfer depending on its input level. This mode is set in bit 15, FRMEN, of the CSIMODE register (address: 0x0B00 0900) (see CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI)).
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13.2.2 Serial interface channels 1 and 2 The GIU also provides pin mapping for the serial interface (equivalent to 16550 UART) channels 1 and 2. The serial interface channel 1 (SIU1) is enabled by writing to the GPIO Mode registers. It utilizes the following GPIO pins: Table 13-4. Serial Interface Channel 1 (SIU1) Signals
GPIO pin GPIO26 GPIO25 GPIO31 GPIO30 GPIO28 GPIO27 GPIO29 TxD1 RxD1 DSR1# DTR1# CTS1# RTS1# DCD1# SIU1 signal Output Input Input Output Input Output Input Type
The GIU drives inputs to the serial interface channel 1 based on the settings in the GPIO Mode registers and bit 15, LOOPBK1, of the GPSICTL register (address: 0x0B00 031A) (for additional information, see 13.3.14 GPSICTL (0x0B00 031A)). When GPIO pins have been assigned to provide the serial interface channel 1 inputs, RxD1, DTR1#, RTS1#, and DCD1#, the GIU simply passes the signals driven on the GPIO pins to the corresponding serial interface channel 1 inputs. Otherwise, the GIU drives these signals based on the value programmed in the GPSICTL register as follows: Table 13-5. Serial Interface Channel 1 (SIU1) Loopback Control
LOOPBK1 bit value 0 Source for driving SIU1 input DSR1#: REGDSR1 (bit 9) value CTS1#: REGCTS1 (bit 10) value DCD1#: REGDCD1 (bit 8) value RxD1: REGRXD1 (bit 11) value DSR1#: DTR1# output CTS1#: RTS1# output DCD1#: REGDCD1 (bit 8) value RxD1: REGRXD1 (bit 11) value
1
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The serial interface channel 2 (SIU2) utilizes the dedicated IRDIN/RxD2 and IRDOUT/TxD2 pins. The line control signals, DTR2#, RTS2#, DCD2#, DSR2#, and CTS2#, are enabled by writing to the GPIO Mode registers and are utilized through the following GPIO pins: Table 13-6. Serial Interface Channel 2 (SIU2) Signals
GPIO pin GPIO9 GPIO8 GPIO6 GPIO5 GPIO7 CTS2# DSR2# RTS2# DCD2# DTR2# SIU2 signal Input Input Output Input Output Type
The transmit and receive data signals, TxD2 and RxD2, are enabled by writing to the SIUIRSEL_2 register in the SIU2. Control of the serial interface channel 2 line status inputs is identical to that of the serial interface channel 1. The GIU drives inputs to the serial interface channel 2 based on the settings in the GPIO Mode registers and bit 7, LOOPBK2, of the GPSICTL register (address: 0x0B00 031A) (for additional information, see 13.3.14 GPSICTL (0x0B00 031A)). When GPIO pins have been assigned to provide the serial interface channel 2 inputs, DTR2#, RTS2#, and DCD2#, the GIU simply passes the signals driven on the GPIO pins to the corresponding serial interface channel 2 inputs. Otherwise, the GIU drives these signals based on the value programmed in the GPSICTL register as follows: Table 13-7. Serial Interface Channel 2 (SIU2) Loopback Control
LOOPBK2 bit value 0 Source for driving SIU2 input DSR2#: REGDSR2 (bit 1) value CTS2#: REGCTS2 (bit 2) value DCD2#: REGDCD2 (bit 0) value DSR2#: DTR2# output CTS2#: RTS2# output DCD2#: REGDCD2 (bit 0) value
1
Note that the GIU does not drive the RxD2 input. This signal is always available to the serial interface as either IRDIN or RxD2.
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13.2.3 LCD interface The GIU supports two functions for the LCD interface. The first is pin mapping for 8-bit STN color LCD panel support. The second is pin mapping for support of an external LCD controller with integrated frame buffer RAM. For additional details about the LCD registers, see CHAPTER 21 LCD CONTROLLER. (1) STN color LCD interface pin mapping The color LCD panel interface is enabled by writing to the GPIO Mode registers and utilizes the following GPIO pins: Table 13-8. STN Color LCD Interface Signals
GPIO pin GPIO(15:12) FPD(7:4) LCD signal Output Type
(2) External LCD controller pin mapping An interface to an external LCD controller can be configured by setting the LCDGPEN bit of the LCDGPMODE register to 1. In this mode the following internal LCD controller pins are redefined to support the external LCD controller interface: Table 13-9. External LCD Controller Interface Signals
LCD pin SHCLK LOCLK VPLCD VPBIAS External LCD controller interface signal LCDCS# MEMCS16# General-purpose output (VPGPIO1) General-purpose output (VPGPIO0) Output Input Output Output Type
The LCDCS# output is generated by the address decode logic in the GIU. The address range can be specified by programming the LCDGPMODE register. The following address ranges are supported: (1) 0x1338 0000 to 0x133F FFFF (512KB) (2) 0x133C 0000 to 0x133F FFFF (256KB) (3) 0x133E 0000 to 0x133F FFFF (128KB) (4) 0x130A 0000 to 0x130A FFFF (64KB, the address space of the PC/AT Remark
TM
is assumed)
All memory cycles that access the external LCD controller address space are treated as 16-bit cycles.
The MEMCS16# input is provided to support external memory devices (besides the external LCD controller) which need accesses in 16-bit cycles. During an external memory cycle, if the MEMCS16# input is enabled and asserted, the ISA bridge will generate a 16-bit cycle.
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13.2.4 Programmable chip selects The GIU provides two programmable chip select signals, PCS(1:0)#. These chip select signals are available on the following GPIO pins: Table 13-10. Programmable Chip Select Signals
GPIO pin GPIO11 GPIO3 Programmable chip select PCS1# PCS0# Output Output Type
Each programmable chip select signal can be defined individually as memory- or I/O-mapped, 8- or 16-bit data width, and 1 to 64K bytes of address ranges. The chip selects can also be qualified with I/O or memory read strobes. 13.2.5 16-bit bus cycles The GIU generates two internal outputs (gpiocs16_l and gpmemcs16_l) to the internal ISA bus to signal the data width of the target of an external ISA cycle. The internal ISA bus uses these outputs as the IOCS16# and MEMCS16# signals that are AND'ed with the outputs from other internal ISA units. The gpiocs16_l output is controlled by either a programmable chip select set in the PCSMODE register (0x0B00 032C) or IOCS16#/GPIO19 pin. When one of the programmable chip selects has been defined as I/O mapped and 16-bit data width, the gpiocs16_l output is asserted while the I/O cycle address is within the range specified for the programmable chip select. When the IOCS16#/GPIO19 pin has been configured as IOCS16#, the gpiocs16_l output follows the state of the IOCS16# signal. The gpmemcs16_l output is controlled by a programmable chip select or the LOCLK/MEMCS16# pin. When one of the programmable chip selects has been defined as memory mapped and 16-bit data width, the gpmemcs16_l output is asserted while the memory cycle address is within the range specified for the programmable chip select. When the LOCLK/MEMCS16# pin has been configured as MEMCS16#, the gpmemcs16_l output follows the state of the MEMCS16# signal. 13.2.6 General purpose input/output Each one of the 32 GPIO pins can be defined as a general-purpose input or a general-purpose output. When a pin is configured as a general-purpose output, a corresponding value written to the GPDATLREG register or the GPDATHREG register appears on the GPIO pin. When a pin is configured as a general-purpose input, a value driven on the GPIO pin can be read from its corresponding data bit of the GPDATLREG or GPDATHREG register.
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13.2.7 Interrupt requests and wake-up events Each of the lower sixteen GPIO pins, GPIO(15:0), can be defined as an interrupt request input. The GIU provides a single asynchronous interrupt request output to the MBA Host Bridge, GPIOINTR. The MBA Host Bridge is responsible for synchronizing this interrupt request with the MasterOut clock (internal). The GIU provides a total of five registers to support GPIO interrupt requests. The interrupt enable register, GPINTEN, is used to enable interrupt requests on a particular GPIO pin. The interrupt mask register, GPINTMSK, permits temporary masking of an interrupt request for a particular GPIO pin. The interrupt type registers, GPINTTYPH and GPINTTYPL, define the interrupt trigger type (edge or level) and the level type (polarity) of the interrupt requests input to the GPIO pin. The interrupt status register, GPINTSTAT, allows software to determine the source of the GPIO interrupt request. The functions of the enable, mask, polarity, and type bits are shown in the following figure: Figure 13-1. GPIO(15:0) Interrupt Request Detecting Logic
Other GPIO interrupt requests Mask bit Level-triggered interrupt request GPIOINTR VDD
Note
MUX
Enable bit GPIO input Polarity bit Type bit
Note Edge-triggered interrupt request
During Hibernate mode, any one of the GPIO(15:0) inputs can be used as a wake-up event. Wake-up event notification is asynchronous and output on the GPWAKEUP signal (internal) following conditions must be met. (1) Interrupt requests to the GPIO pin must be enabled (set in the GPINTEN register). (2) Interrupt requests to the GPIO pin must be unmasked (set in the GPINTMSK register). (3) The GPIO pin must be enabled during Hibernate mode (set in the GPHIBSTL register). Note The state of this signal is displayed on the GPWAKEUP bit of the PMUINTREG register in the PMU.
Note
. To enable GPIO wake-up events, the
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13.3 Register Set
The GIU provides the following registers. Table 13-11. GIU Registers (1/2)
Physical address 0x0B00 0300 0x0B00 0302 0x0B00 0304 0x0B00 0306 0x0B00 0308 0x0B00 030A 0x0B00 030C 0x0B00 030E 0x0B00 0310 0x0B00 0312 0x0B00 0314 0x0B00 0316 0x0B00 0318 0x0B00 031A 0x0B00 031C 0x0B00 0320 0x0B00 0322 0x0B00 0324 0x0B00 0326 0x0B00 0328 0x0B00 032A 0x0B00 032C 0x0B00 032E R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register symbol GPMD0REG GPMD1REG GPMD2REG GPMD3REG GPDATHREG GPDATLREG GPINTEN GPINTMSK GPINTTYPH GPINTTYPL GPINTSTAT GPHIBSTH GPHIBSTL GPSICTL KEYEN PCS0STRA PCS0STPA PCS0HIA PCS1STRA PCS1STPA PCS1HIA PCSMODE LCDGPMODE GPIO Mode 0 register GPIO Mode 1 register GPIO Mode 2 register GPIO Mode 3 register GPIO data high register GPIO data low register GPIO interrupt enable register GPIO interrupt mask register GPIO interrupt type high register GPIO interrupt type low register GPIO interrupt status register GPIO Hibernate pin status high register GPIO Hibernate pin status low register GPIO serial interface control register Keyboard scan pin enable register Programmable chip select 0 start address register Programmable chip select 0 stop address register Programmable chip select 0 high address register Programmable chip select 1 start address register Programmable chip select 1 stop address register Programmable chip select 1 high address register Programmable chip select mode register LCD general-purpose mode register Function
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Table 13-11. GIU Registers (2/2)
Physical address 0x0B00 0330 0x0B00 0332 0x0B00 0334 0x0B00 0336 0x0B00 0338 0x0B00 033A 0x0B00 033C 0x0B00 033E 0x0B00 0340 0x0B00 0342 0x0B00 0344 0x0B00 0346 0x0B00 0348 0x0B00 034A 0x0B00 034C 0x0B00 034E R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register symbol MISCREG0 MISCREG1 MISCREG2 MISCREG3 MISCREG4 MISCREG5 MISCREG6 MISCREG7 MISCREG8 MISCREG9 MISCREG10 MISCREG11 MISCREG12 MISCREG13 MISCREG14 MISCREG15 General-purpose register Function
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13.3.1 GPMD0REG (0x0B00 0300) (1/2)
Bit Name R/W RTCRST Other resets 15 GP7MD1 R/W 0 Note 14 GP7MD0 R/W 0 Note 13 GP6MD1 R/W 0 Note 12 GP6MD0 R/W 0 Note 11 GP5MD1 R/W 0 Note 10 GP5MD0 R/W 0 Note 9 GP4MD1 R/W 0 Note 8 GP4MD0 R/W 0 Note
Bit Name R/W RTCRST Other resets
7 GP3MD1 R/W 0 Note
6 GP3MD0 R/W 0 Note
5 GP2MD1 R/W 0 Note
4 GP2MD0 R/W 0 Note
3 GP1MD1 R/W 0 Note
2 GP1MD0 R/W 0 Note
1 GP0MD1 R/W 0 Note
0 GP0MD0 R/W 0 Note
Bit 15, 14
Name GP7MD(1:0)
Function These bits control direction and function of the GPIO7 pin as follows: 00 : General-purpose input 01 : RFU 10 : General-purpose output 11 : SIU2 DTR2# output
13, 12
GP6MD(1:0)
These bits control direction and function of the GPIO6 pin as follows: 00 : General-purpose input 01 : RFU 10 : General-purpose output 11 : SIU2 RTS2# output
11, 10
GP5MD(1:0)
These bits control direction and function of the GPIO5 pin as follows: 00 : General-purpose input 01 : SIU2 DCD2# input 10 : General-purpose output 11 : RFU
9, 8
GP4MD(1:0)
These bits control direction and function of the GPIO4 pin as follows: 00 : General-purpose input 01 : RFU 10 : General-purpose output 11 : RFU
7, 6
GP3MD(1:0)
These bits control direction and function of the GPIO3 pin as follows: 00 : General-purpose input 01 : RFU 10 : General-purpose output 11 : Programmable chip select 0 output
Note Holds the value before reset
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Bit 5, 4 Name GP2MD(1:0) Function These bits control direction and function of the GPIO2 pin as follows: 00 : General-purpose input 01 : CSI SCK input 10 : General-purpose output 11 : RFU 3, 2 GP1MD(1:0) These bits control direction and function of the GPIO1 pin as follows: 00 : General-purpose input 01 : RFU 10 : General-purpose output 11 : CSI SO output 1, 0 GP0MD(1:0) These bits control direction and function of the GPIO0 pin as follows: 00 : General-purpose input 01 : CSI SI input 10 : General-purpose output 11 : RFU
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13.3.2 GPMD1REG (0x0B00 0302) (1/2)
Bit Name R/W RTCRST Other resets 15 GP15MD1 R/W 0 Note 14 GP15MD0 R/W 0 Note 13 GP14MD1 R/W 0 Note 12 GP14MD0 R/W 0 Note 11 GP13MD1 R/W 0 Note 10 GP13MD0 R/W 0 Note 9 GP12MD1 R/W 0 Note 8 GP12MD0 R/W 0 Note
Bit Name R/W RTCRST Other resets
7 GP11MD1 R/W 0 Note
6 GP11MD0 R/W 0 Note
5 GP10MD1 R/W 0 Note
4 GP10MD0 R/W 0 Note
3 GP9MD1 R/W 0 Note
2 GP9MD0 R/W 0 Note
1 GP8MD1 R/W 0 Note
0 GP8MD0 R/W 0 Note
Bit 15, 14
Name GP15MD(1:0)
Function These bits control direction and function of the GPIO15 pin as follows: 00 : General-purpose input 01 : CD2# input 10 : General-purpose output 11 : Color LCD FPD7 output
13, 12
GP14MD(1:0)
These bits control direction and function of the GPIO14 pin as follows: 00 : General-purpose input 01 : CD1# input 10 : General-purpose output 11 : Color LCD FPD6 output
11, 10
GP13MD(1:0)
These bits control direction and function of the GPIO13 pin as follows: 00 : General-purpose input 01 : RFU 10 : General-purpose output 11 : Color LCD FPD5 output
9, 8
GP12MD(1:0)
These bits control direction and function of the GPIO12 pin as follows: 00 : General-purpose input 01 : RFU 10 : General-purpose output 11 : Color LCD FPD4 output
7, 6
GP11MD(1:0)
These bits control direction and function of the GPIO11 pin as follows: 00 : General-purpose input 01 : RFU 10 : General-purpose output 11 : Programmable chip select 1 output
Note Holds the value before reset Remark When GPIO15 and GPIO14 pins are not defined as CD2# and CD1# signals respectively, the corresponding internal card detect signals to CompactFlash controller (ECU) are held to low level (active).
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Bit 5, 4 Name GP10MD(1:0) Function These bits control direction and function of the GPIO10 pin as follows: 00 : General-purpose input 01 : CSI FRM input 10 : General-purpose output 11 : SYSCLK output 3, 2 GP9MD(1:0) These bits control direction and function of the GPIO9 pin as follows: 00 : General-purpose input 01 : SIU2 CTS2# input 10 : General-purpose output 11 : RFU 1, 0 GP8MD(1:0) These bits control direction and function of the GPIO8 pin as follows: 00 : General-purpose input 01 : SIU2 DSR2# input 10 : General-purpose output 11 : RFU
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13.3.3 GPMD2REG (0x0B00 0304) (1/2)
Bit Name R/W RTCRST Other resets 15 GP23MD1 R/W 0 Note 14 GP23MD0 R/W 0 Note 13 GP22MD1 R/W 0 Note 12 GP22MD0 R/W 0 Note 11 GP21MD1 R/W 0 Note 10 GP21MD0 R/W 0 Note 9 GP20MD1 R/W 0 Note 8 GP20MD0 R/W 0 Note
Bit Name R/W RTCRST Other resets
7 GP19MD1 R/W 0 Note
6 GP19MD0 R/W 0 Note
5 GP18MD1 R/W 0 Note
4 GP18MD0 R/W 0 Note
3 GP17MD1 R/W 0 Note
2 GP17MD0 R/W 0 Note
1 GP16MD1 R/W 0 Note
0 GP16MD0 R/W 0 Note
Bit 15, 14
Name GP23MD(1:0)
Function These bits control direction and function of the GPIO23 pin as follows: 00 : General-purpose input 01 : RFU 10 : General-purpose output 11 : ROMCS1# output
13, 12
GP22MD(1:0)
These bits control direction and function of the GPIO22 pin as follows: 00 : General-purpose input 01 : RFU 10 : General-purpose output 11 : ROMCS0# output
11, 10
GP21MD(1:0)
These bits control direction and function of the GPIO21 pin as follows: 00 : General-purpose input 01 : RFU 10 : General-purpose output 11 : RESET# output
9, 8
GP20MD(1:0)
These bits control direction and function of the GPIO20 pin as follows: 00 : General-purpose input 01 : RFU 10 : LCD M output 11 : UBE# output
7, 6
GP19MD(1:0)
These bits control direction and function of the GPIO19 pin as follows: 00 : General-purpose input 01 : IOCS16# input 10 : General-purpose output 11 : RFU
Note Holds the value before reset Caution LCD M output can not be used in the VR4181 of Rev.1.0.
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Bit 5, 4 Name GP18MD(1:0) Function These bits control direction and function of the GPIO18 pin as follows: 00 : General-purpose input 01 : IORDY input 10 : General-purpose output 11 : RFU 3, 2 GP17MD(1:0) These bits control direction and function of the GPIO17 pin as follows: 00 : General-purpose input 01 : RFU 10 : General-purpose output 11 : IOWR# output 1, 0 GP16MD(1:0) These bits control direction and function of the GPIO16 pin as follows: 00 : General-purpose input 01 : RFU 10 : General-purpose output 11 : IORD# output
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13.3.4 GPMD3REG (0x0B00 0306) (1/2)
Bit Name R/W RTCRST Other resets 15 GP31MD1 R/W 0 Note 14 GP31MD0 R/W 0 Note 13 GP30MD1 R/W 0 Note 12 GP30MD0 R/W 0 Note 11 GP29MD1 R/W 0 Note 10 GP29MD0 R/W 0 Note 9 GP28MD1 R/W 0 Note 8 GP28MD0 R/W 0 Note
Bit Name R/W RTCRST Other resets
7 GP27MD1 R/W 0 Note
6 GP27MD0 R/W 0 Note
5 GP26MD1 R/W 0 Note
4 GP26MD0 R/W 0 Note
3 GP25MD1 R/W 0 Note
2 GP25MD0 R/W 0 Note
1 GP24MD1 R/W 0 Note
0 GP24MD0 R/W 0 Note
Bit 15, 14
Name GP31MD(1:0)
Function These bits control direction and function of the GPIO31 pin as follows: 00 : General-purpose input 01 : SIU1 DSR1# input 10 : General-purpose output 11 : RFU
13, 12
GP30MD(1:0)
These bits control direction and function of the GPIO30 pin as follows: 00 : General-purpose input 01 : RFU 10 : General-purpose output 11 : SIU1 DTR1# output
11, 10
GP29MD(1:0)
These bits control direction and function of the GPIO29 pin as follows: 00 : General-purpose input 01 : SIU1 DCD1# input 10 : General-purpose output 11 : RFU
9, 8
GP28MD(1:0)
These bits control direction and function of the GPIO28 pin as follows: 00 : General-purpose input 01 : SIU1 CTS1# input 10 : General-purpose output 11 : RFU
7, 6
GP27MD(1:0)
These bits control direction and function of the GPIO27 pin as follows: 00 : General-purpose input 01 : RFU 10 : General-purpose output 11 : SIU1 RTS1# output
Note Holds the value before reset
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Bit 5, 4 Name GP26MD(1:0) Function These bits control direction and function of the GPIO26 pin as follows: 00 : General-purpose input 01 : RFU 10 : General-purpose output 11 : SIU1 TxD1 output 3, 2 GP25MD(1:0) These bits control direction and function of the GPIO25 pin as follows: 00 : General-purpose input 01 : SIU1 RxD1 input 10 : General-purpose output 11 : RFU 1, 0 GP24MD(1:0) These bits control direction and function of the GPIO24 pin as follows: 00 : General-purpose input 01 : RFU 10 : General-purpose output 11 : ROMCS2# output
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13.3.5 GPDATHREG (0x0B00 0308)
Bit Name R/W RTCRST Other resets 15 GPDAT31 R/W 0 Note 14 GPDAT30 R/W 0 Note 13 GPDAT29 R/W 0 Note 12 GPDAT28 R/W 0 Note 11 GPDAT27 R/W 0 Note 10 GPDAT26 R/W 0 Note 9 GPDAT25 R/W 0 Note 8 GPDAT24 R/W 0 Note
Bit Name R/W RTCRST Other resets
7 GPDAT23 R/W 0 Note
6 GPDAT22 R/W 0 Note
5 GPDAT21 R/W 0 Note
4 GPDAT20 R/W 0 Note
3 GPDAT19 R/W 0 Note
2 GPDAT18 R/W 0 Note
1 GPDAT17 R/W 0 Note
0 GPDAT16 R/W 0 Note
Bit 15 to 0
Name GPDAT(31:16)
Function General-purpose data. There is a one-to-one correspondence between these bits and GPIO pins. When a GPIO pin is configured as a general-purpose input, the value of the pin can be read from this register. When the pin is defined as a general-purpose output, the value written to this register appears on the GPIO pin. When one of the GPIO(31:16) pins is configured as other function, the corresponding bit value in this register is invalid.
Note Holds the value before reset
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13.3.6 GPDATLREG (0x0B00 030A)
Bit Name R/W RTCRST Other resets 15 GPDAT15 R/W 0 Note 14 GPDAT14 R/W 0 Note 13 GPDAT13 R/W 0 Note 12 GPDAT12 R/W 0 Note 11 GPDAT11 R/W 0 Note 10 GPDAT10 R/W 0 Note 9 GPDAT9 R/W 0 Note 8 GPDAT8 R/W 0 Note
Bit Name R/W RTCRST Other resets
7 GPDAT7 R/W 0 Note
6 GPDAT6 R/W 0 Note
5 GPDAT5 R/W 0 Note
4 GPDAT4 R/W 0 Note
3 GPDAT3 R/W 0 Note
2 GPDAT2 R/W 0 Note
1 GPDAT1 R/W 0 Note
0 GPDAT0 R/W 0 Note
Bit 15 to 0
Name GPDAT(15:0)
Function General-purpose data. There is a one-to-one correspondence between these bits and GPIO pins. When a GPIO pin is configured as a general-purpose input, the value of the pin can be read from this register. When the pin is defined as a general-purpose output, the value written to this register appears on the GPIO pin. When one of the GPIO(15:0) pins is configured as other function, the corresponding bit value in this register is invalid.
Note Holds the value before reset
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13.3.7 GPINTEN (0x0B00 030C)
Bit Name R/W RTCRST Other resets 15 GIEN15 R/W 0 Note 14 GIEN14 R/W 0 Note 13 GIEN13 R/W 0 Note 12 GIEN12 R/W 0 Note 11 GIEN11 R/W 0 Note 10 GIEN10 R/W 0 Note 9 GIEN9 R/W 0 Note 8 GIEN8 R/W 0 Note
Bit Name R/W RTCRST Other resets
7 GIEN7 R/W 0 Note
6 GIEN6 R/W 0 Note
5 GIEN5 R/W 0 Note
4 GIEN4 R/W 0 Note
3 GIEN3 R/W 0 Note
2 GIEN2 R/W 0 Note
1 GIEN1 R/W 0 Note
0 GIEN0 R/W 0 Note
Bit 15 to 0 GIEN(15:0)
Name
Function GPIO interrupt enable. There is a one-to-one correspondence between these bits and GPIO pins. When one of the GPIO(15:0) pins is defined as a general-purpose input, the corresponding bit in this register enables interrupts for that pin as follows: 0 : Interrupt disabled 1 : Interrupt enabled
Note Holds the value before reset Remark About the relationship between the GPINTEN and GPINTMSK registers, refer to Figure 13-1. GPIO(15:0) Interrupt Request Detecting Logic.
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13.3.8 GPINTMSK (0x0B00 030E)
Bit Name R/W RTCRST Other resets 15 GIMSK15 R/W 1 Note 14 GIMSK14 R/W 1 Note 13 GIMSK13 R/W 1 Note 12 GIMSK12 R/W 1 Note 11 GIMSK11 R/W 1 Note 10 GIMSK10 R/W 1 Note 9 GIMSK9 R/W 1 Note 8 GIMSK8 R/W 1 Note
Bit Name R/W RTCRST Other resets
7 GIMSK7 R/W 1 Note
6 GIMSK6 R/W 1 Note
5 GIMSK5 R/W 1 Note
4 GIMSK4 R/W 1 Note
3 GIMSK3 R/W 1 Note
2 GIMSK2 R/W 1 Note
1 GIMSK1 R/W 1 Note
0 GIMSK0 R/W 1 Note
Bit 15 to 0
Name GIMSK(15:0)
Function GPIO interrupt mask. There is a one-to-one correspondence between these bits and GPIO pins. When a GPIO pin is defined as a general-purpose input and interrupts is enabled on that pin, the interrupt can be temporarily masked by setting the corresponding bit in this register as follows: 0 : Interrupt unmasked 1 : Interrupt masked
Note Holds the value before reset Remark About the relationship between the GPINTEN and GPINTMSK registers, refer to Figure 13-1. GPIO(15:0) Interrupt Request Detecting Logic.
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13.3.9 GPINTTYPH (0x0B00 0310) (1/2)
Bit Name R/W RTCRST Other resets 15 I15TYP1 R/W 0 Note 14 I15TYP0 R/W 0 Note 13 I14TYP1 R/W 0 Note 12 I14TYP0 R/W 0 Note 11 I13TYP1 R/W 0 Note 10 I13TYP0 R/W 0 Note 9 I12TYP1 R/W 0 Note 8 I12TYP0 R/W 0 Note
Bit Name R/W RTCRST Other resets
7 I11TYP1 R/W 0 Note
6 I11TYP0 R/W 0 Note
5 I10TYP1 R/W 0 Note
4 I10TYP0 R/W 0 Note
3 I9TYP1 R/W 0 Note
2 I9TYP0 R/W 0 Note
1 I8TYP1 R/W 0 Note
0 I8TYP0 R/W 0 Note
Bit 15, 14
Name I15TYP(1:0)
Function These bits define the type of interrupt generated when the GPIO15 pin is defined as a general-purpose input: 00 : Negative edge triggered interrupt 01 : Positive edge triggered interrupt 10 : Low level triggered interrupt 11 : High level triggered interrupt
13, 12
I14TYP(1:0)
These bits define the type of interrupt generated when the GPIO14 pin is defined as a general-purpose input: 00 : Negative edge triggered interrupt 01 : Positive edge triggered interrupt 10 : Low level triggered interrupt 11 : High level triggered interrupt
11, 10
I13TYP(1:0)
These bits define the type of interrupt generated when the GPIO13 pin is defined as a general-purpose input: 00 : Negative edge triggered interrupt 01 : Positive edge triggered interrupt 10 : Low level triggered interrupt 11 : High level triggered interrupt
9, 8
I12TYP(1:0)
These bits define the type of interrupt generated when the GPIO12 pin is defined as a general-purpose input: 00 : Negative edge triggered interrupt 01 : Positive edge triggered interrupt 10 : Low level triggered interrupt 11 : High level triggered interrupt
Note Holds the value before reset
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Bit 7, 6 Name I11TYP(1:0) Function These bits define the type of interrupt generated when the GPIO11 pin is defined as a general-purpose input: 00 : Negative edge triggered interrupt 01 : Positive edge triggered interrupt 10 : Low level triggered interrupt 11 : High level triggered interrupt 5, 4 I10TYP(1:0) These bits define the type of interrupt generated when the GPIO10 pin is defined as a general-purpose input: 00 : Negative edge triggered interrupt 01 : Positive edge triggered interrupt 10 : Low level triggered interrupt 11 : High level triggered interrupt 3, 2 I9TYP(1:0) These bits define the type of interrupt generated when the GPIO9 pin is defined as a general-purpose input: 00 : Negative edge triggered interrupt 01 : Positive edge triggered interrupt 10 : Low level triggered interrupt 11 : High level triggered interrupt 1, 0 I8TYP(1:0) These bits define the type of interrupt generated when the GPIO8 pin is defined as a general-purpose input: 00 : Negative edge triggered interrupt 01 : Positive edge triggered interrupt 10 : Low level triggered interrupt 11 : High level triggered interrupt
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13.3.10 GPINTTYPL (0x0B00 0312) (1/2)
Bit Name R/W RTCRST Other resets 15 I7TYP1 R/W 0 Note 14 I7TYP0 R/W 0 Note 13 I6TYP1 R/W 0 Note 12 I6TYP0 R/W 0 Note 11 I5TYP1 R/W 0 Note 10 I5TYP0 R/W 0 Note 9 I4TYP1 R/W 0 Note 8 I4TYP0 R/W 0 Note
Bit Name R/W RTCRST Other resets
7 I3TYP1 R/W 0 Note
6 I3TYP0 R/W 0 Note
5 I2TYP1 R/W 0 Note
4 I2TYP0 R/W 0 Note
3 I1TYP1 R/W 0 Note
2 I1TYP0 R/W 0 Note
1 I0TYP1 R/W 0 Note
0 I0TYP0 R/W 0 Note
Bit 15, 14 I7TYP(1:0)
Name
Function These bits define the type of interrupt generated when the GPIO7 pin is defined as a general-purpose input: 00 : Negative edge triggered interrupt 01 : Positive edge triggered interrupt 10 : Low level triggered interrupt 11 : High level triggered interrupt
13, 12
I6TYP(1:0)
These bits define the type of interrupt generated when the GPIO6 pin is defined as a general-purpose input: 00 : Negative edge triggered interrupt 01 : Positive edge triggered interrupt 10 : Low level triggered interrupt 11 : High level triggered interrupt
11, 10
I5TYP(1:0)
These bits define the type of interrupt generated when the GPIO5 pin is defined as a general-purpose input: 00 : Negative edge triggered interrupt 01 : Positive edge triggered interrupt 10 : Low level triggered interrupt 11 : High level triggered interrupt
9, 8
I4TYP(1:0)
These bits define the type of interrupt generated when the GPIO4 pin is defined as a general-purpose input: 00 : Negative edge triggered interrupt 01 : Positive edge triggered interrupt 10 : Low level triggered interrupt 11 : High level triggered interrupt
Note Holds the value before reset
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Bit 7, 6 I3TYP(1:0) Name Function These bits define the type of interrupt generated when the GPIO3 pin is defined as a general-purpose input: 00 : Negative edge triggered interrupt 01 : Positive edge triggered interrupt 10 : Low level triggered interrupt 11 : High level triggered interrupt 5, 4 I2TYP(1:0) These bits define the type of interrupt generated when the GPIO2 pin is defined as a general-purpose input: 00 : Negative edge triggered interrupt 01 : Positive edge triggered interrupt 10 : Low level triggered interrupt 11 : High level triggered interrupt 3, 2 I1TYP(1:0) These bits define the type of interrupt generated when the GPIO1 pin is defined as a general-purpose input: 00 : Negative edge triggered interrupt 01 : Positive edge triggered interrupt 10 : Low level triggered interrupt 11 : High level triggered interrupt 1, 0 I0TYP(1:0) These bits define the type of interrupt generated when the GPIO0 pin is defined as a general-purpose input: 00 : Negative edge triggered interrupt 01 : Positive edge triggered interrupt 10 : Low level triggered interrupt 11 : High level triggered interrupt
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13.3.11 GPINTSTAT (0x0B00 0314)
Bit Name R/W RTCRST Other resets 15 GISTS15 R/W 0 Note 14 GISTS14 R/W 0 Note 13 GISTS13 R/W 0 Note 12 GISTS12 R/W 0 Note 11 GISTS11 R/W 0 Note 10 GISTS10 R/W 0 Note 9 GISTS9 R/W 0 Note 8 GISTS8 R/W 0 Note
Bit Name R/W RTCRST Other resets
7 GISTS7 R/W 0 Note
6 GISTS6 R/W 0 Note
5 GISTS5 R/W 0 Note
4 GISTS4 R/W 0 Note
3 GISTS3 R/W 0 Note
2 GISTS2 R/W 0 Note
1 GISTS1 R/W 0 Note
0 GISTS0 R/W 0 Note
Bit 15 to 0
Name GISTS(15:0)
Function GPIO interrupt request status. There is a one-to-one correspondence between these bits and GPIO pins. When a GPIO pin is defined as a general-purpose input, these bits reflect the interrupt request status as follows: 0 : No Interrupt request pending 1 : Interrupt request pending
Note Holds the value before reset Interrupt request pending status is reflected regardless of the setting of the interrupt mask bits. Therefore, the status of an interrupt request can be returned as pending when this register is read even though the interrupt is masked. When a GPIO interrupt request is defined as an edge triggered type, the interrupt request is cleared by writing 1 to the corresponding bit of this register. For example, if GPIO11 is defined as an edge triggered interrupt request input, an interrupt request generated by this pin would be cleared by writing 1 to the bit 11 of this register.
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13.3.12 GPHIBSTH (0x0B00 0316)
Bit Name R/W RTCRST Other resets 15 GPHST31 R/W 0 Note 14 GPHST30 R/W 0 Note 13 GPHST29 R/W 0 Note 12 GPHST28 R/W 0 Note 11 GPHST27 R/W 0 Note 10 GPHST26 R/W 0 Note 9 GPHST25 R/W 0 Note 8 GPHST24 R/W 0 Note
Bit Name R/W RTCRST Other resets
7 GPHST23 R/W 0 Note
6 GPHST22 R/W 0 Note
5 GPHST21 R/W 0 Note
4 GPHST20 R/W 0 Note
3 GPHST19 R/W 0 Note
2 GPHST18 R/W 0 Note
1 GPHST17 R/W 0 Note
0 GPHST16 R/W 0 Note
Bit 15 to 0
Name GPHST(31:16)
Function GPIO Hibernate pin state control. There is a one-to-one correspondence between these bits and GPIO pins. These bits determine the state of GPIO(31:16) pins during Hibernate mode as follows: 0 : Output pin is in high impedance Input pin is ignored during Hibernate mode 1 : Output pin remains actively driven Input pin is monitored during Hibernate mode
Note Holds the value before reset Caution GPIO29 pin (DCD1#) can be input at high level and monitored during Hibernate mode and therefore the GPHST29 bit can be set to 1. The GPHST bits for all other GPIO pins configured as inputs should be reset to 0.
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13.3.13 GPHIBSTL (0x0B00 0318)
Bit Name R/W RTCRST Other resets 15 GPHST15 R/W 0 Note 14 GPHST14 R/W 0 Note 13 GPHST13 R/W 0 Note 12 GPHST12 R/W 0 Note 11 GPHST11 R/W 0 Note 10 GPHST10 R/W 0 Note 9 GPHST9 R/W 0 Note 8 GPHST8 R/W 0 Note
Bit Name R/W RTCRST Other resets
7 GPHST7 R/W 0 Note
6 GPHST6 R/W 0 Note
5 GPHST5 R/W 0 Note
4 GPHST4 R/W 0 Note
3 GPHST3 R/W 0 Note
2 GPHST2 R/W 0 Note
1 GPHST1 R/W 0 Note
0 GPHST0 R/W 0 Note
Bit 15 to 0
Name GPHST(15:0)
Function GPIO Hibernate pin state control. There is a one-to-one correspondence between these bits and GPIO pins. These bits determine the state of GPIO(15:0) pins during Hibernate mode as follows: 0 : Output pin is in high impedance Input pin is ignored during Hibernate mode 1 : Output pin remains actively driven Input pin is monitored during Hibernate mode
Note Holds the value before reset Remark In order to support wake-up events on one of the GPIO(15:0) pins, the associated GPHST bit must be set to 1.
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13.3.14 GPSICTL (0x0B00 031A) (1/2)
Bit Name R/W RTCRST Other resets 15 LOOPBK1 R/W 0 Note 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 REGRXD1 R/W 1 Note 10 REGCTS1 R/W 1 Note 9 REGDSR1 R/W 1 Note 8 REGDCD1 R/W 1 Note
Bit Name R/W RTCRST Other resets
7 LOOPBK2 R/W 0 Note
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 Reserved R 0 0
2 REGCTS2 R/W 1 Note
1 REGDSR2 R/W 1 Note
0 REGDCD2 R/W 1 Note
Bit 15 LOOPBK1
Name
Function Loopback enable for serial interface channel 1. When GPIO pins have not been allocated for the line status signals DSR1# and/or CTS1# of the serial interface channel 1, this bit can be set to 1 to allow the serial interface line status output signals to be connected to the line status input signals as follows: DTR1# output from serial interface drives the DSR1# input to serial interface RTS1# output from serial interface drives the CTS1# input to serial interface
14 to 12 11
Reserved REGRXD1
0 is returned when read RxD1 data. When a GPIO pin has not been enabled to provide RxD1, the RxD1 input to the serial interface channel 1 is driven with the value of this bit. CTS1# data. When the LOOPBK1 bit is reset to 0 and a GPIO pin has not been enabled to provide CTS1#, the CTS1# input to the serial interface channel 1 is driven with the value of this bit. DSR1# data. When the LOOPBK1 bit is reset to 0 and a GPIO pin has not been enabled to provide DSR1#, the DSR1# input to the serial interface channel 1 is driven with the value of this bit. DCD1# data. When a GPIO pin has not been enabled to provide DCD1#, the DCD1# input to the serial interface channel 1 is driven with the value of this bit.
10
REGCTS1
9
REGDSR1
8
REGDCD1
Note Holds the value before reset
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Bit 7 LOOPBK2 Name Function Loopback enable for serial interface channel 2. When GPIO pins have not be allocated for the line status signals DSR2# and/or CTS2# of the serial interface channel 2, this bit can be set to 1 to allow the serial interface line status output signals to be connected to the line status input signals as follows: DTR2# output from serial interface drives the DSR2# input to serial interface RTS2# output from serial interface drives the CTS2# input to serial interface 6 to 3 2 Reserved REGCTS2 0 is returned when read CTS2# data. When the LOOPBK2 bit is reset to 0 and a GPIO pin has not been enabled to provide CTS2#, the CTS2# input to the serial interface channel 2 is driven with the value of this bit. DSR2# data. When the LOOPBK2 bit is reset to 0 and a GPIO pin has not been enabled to provide DSR2#, the DSR2# input to the serial interface channel 2 is driven with the value of this bit. DCD2# data. When a GPIO pin has not been enabled to provide DCD2#, the DCD2# input to the serial interface channel 2 is driven with the value of this bit.
1
REGDSR2
0
REGDCD2
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13.3.15 KEYEN (0x0B00 031C)
Bit Name R/W RTCRST Other resets 15 KEYSEL R/W 0 Note 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 CFHIBEN R/W 0 Note
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 Reserved R 0 0
2 Reserved R 0 0
1 Reserved R 0 0
0 Reserved R 0 0
Bit 15 KEYSEL
Name
Function Keyboard scan pin enable. This bit causes the pins assigned to support the CompactFlash interface to be redefined to support the keyboard scan interface. 0 : CompactFlash interface enabled 1 : Keyboard scan interface enabled
14 to 8 7
Reserved CFHIBEN
0 is returned when read CompactFlash interface enable during Hibernate mode 0 : Disable 1 : Enable
6 to 0
Reserved
0 is returned when read
Note Holds the value before reset The GIU only provides an internal output signal (keysel) when the KEYSEL bit is set to 1. An external logic is responsible for multiplexing the pin inputs and pin outputs, and I/O buffer enable control from the ECU and the KIU. When the CompactFlash interface is enabled during Hibernate mode, a high-to-low transition on the CompactFlash CF_BUSY# pin will cause the VR4181 to wake up and return to Fullspeed mode.
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13.3.16 PCS0STRA (0x0B00 0320)
Bit Name 15 PCS0STRA 15 R/W 0 Note 14 PCS0STRA 14 R/W 0 Note 13 PCS0STRA 13 R/W 0 Note 12 PCS0STRA 12 R/W 0 Note 11 PCS0STRA 11 R/W 0 Note 10 PCS0STRA 10 R/W 0 Note 9 PCS0STRA 9 R/W 0 Note 8 PCS0STRA 8 R/W 0 Note
R/W RTCRST Other resets
Bit Name
7 PCS0STRA 7 R/W 0 Note
6 PCS0STRA 6 R/W 0 Note
5 PCS0STRA 5 R/W 0 Note
4 PCS0STRA 4 R/W 0 Note
3 PCS0STRA 3 R/W 0 Note
2 PCS0STRA 2 R/W 0 Note
1 PCS0STRA 1 R/W 0 Note
0 PCS0STRA 0 R/W 0 Note
R/W RTCRST Other resets
Bit 15 to 0
Name PCS0STRA(15:0)
Function Programmable chip select 0 start address. These bits determine the starting address for the memory or I/O chip select.
Note Holds the value before reset 13.3.17 PCS0STPA (0x0B00 0322)
Bit Name 15 PCS0STPA 15 R/W 0 Note 14 PCS0STPA 14 R/W 0 Note 13 PCS0STPA 13 R/W 0 Note 12 PCS0STPA 12 R/W 0 Note 11 PCS0STPA 11 R/W 0 Note 10 PCS0STPA 10 R/W 0 Note 9 PCS0STPA 9 R/W 0 Note 8 PCS0STPA 8 R/W 0 Note
R/W RTCRST Other resets
Bit Name
7 PCS0STPA 7 R/W 0 Note
6 PCS0STPA 6 R/W 0 Note
5 PCS0STPA 5 R/W 0 Note
4 PCS0STPA 4 R/W 0 Note
3 PCS0STPA 3 R/W 0 Note
2 PCS0STPA 2 R/W 0 Note
1 PCS0STPA 1 R/W 0 Note
0 PCS0STPA 0 R/W 0 Note
R/W RTCRST Other resets
Bit 15 to 0
Name PCS0STPA(15:0)
Function Programmable chip select 0 stop address. These bits determine the ending address for the memory or I/O chip select.
Note Holds the value before reset
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13.3.18 PCS0HIA (0x0B00 0324)
Bit Name 15 Reserved 14 Reserved 13 Reserved 12 Reserved 11 PCS0HIA 27 R/W 0 Note1 10 PCS0HIA 26 R/W 0 Note1 9 PCS0HIA 25 R/W 0 Note1 8 PCS0HIA 24 R/W 0 Note1
R/W RTCRST Other resets
R 0 0
R 0 0
R 0 0
R 0 0
Bit Name
7 PCS0HIA 23 R/W 0 Note1
6 PCS0HIA 22 R/W 0 Note1
5 PCS0HIA 21 R/W 0 Note1
4 PCS0HIA 20 R/W 0 Note1
3 PCS0HIA 19 R/W 0 Note1
2 PCS0HIA 18 R/W 0 Note1
1 PCS0HIA 17 R/W 0 Note1
0 PCS0HIA 16 R/W 0 Note1
R/W RTCRST Other resets
Bit 15 to 12 11 to 0 Reserved
Name 0 is returned when read
Function
PCS0HIA(27:16)
Programmable chip select 0 high address. A programmable chip select 0 will be generated when all of the following conditions have been met: * The system address bits A(15:0) are equal to or greater than PCS0STRA(15:0) Note2 and equal to or less than PCS0STPA(15:0) * The internal address bits A(27:16) are equal to PCS0HIA(27:16) * The read/write qualifier conditions specified by the PCSMODE register have been met.
Notes 1. Holds the value before reset 2. When the PCS0 has been defined as a 16-bit chip select, bit 0 of the address is ignored.
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13.3.19 PCS1STRA (0x0B00 0326)
Bit Name 15 PCS1STRA 15 R/W 0 Note 14 PCS1STRA 14 R/W 0 Note 13 PCS1STRA 13 R/W 0 Note 12 PCS1STRA 12 R/W 0 Note 11 PCS1STRA 11 R/W 0 Note 10 PCS1STRA 10 R/W 0 Note 9 PCS1STRA 9 R/W 0 Note 8 PCS1STRA 8 R/W 0 Note
R/W RTCRST Other resets
Bit Name
7 PCS1STRA 7 R/W 0 Note
6 PCS1STRA 6 R/W 0 Note
5 PCS1STRA 5 R/W 0 Note
4 PCS1STRA 4 R/W 0 Note
3 PCS1STRA 3 R/W 0 Note
2 PCS1STRA 2 R/W 0 Note
1 PCS1STRA 1 R/W 0 Note
0 PCS1STRA 0 R/W 0 Note
R/W RTCRST Other resets
Bit 15 to 0
Name PCS1STRA(15:0)
Function Programmable chip select 1 start address. These bits determine the starting address for the memory or I/O chip select.
Note Holds the value before reset 13.3.20 PCS1STPA (0x0B00 0328)
Bit Name 15 PCS1STPA 15 R/W 0 Note 14 PCS1STPA 14 R/W 0 Note 13 PCS1STPA 13 R/W 0 Note 12 PCS1STPA 12 R/W 0 Note 11 PCS1STPA 11 R/W 0 Note 10 PCS1STPA 10 R/W 0 Note 9 PCS1STPA 9 R/W 0 Note 8 PCS1STPA 8 R/W 0 Note
R/W RTCRST Other resets
Bit Name
7 PCS1STPA 7 R/W 0 Note
6 PCS1STPA 6 R/W 0 Note
5 PCS1STPA 5 R/W 0 Note
4 PCS1STPA 4 R/W 0 Note
3 PCS1STPA 3 R/W 0 Note
2 PCS1STPA 2 R/W 0 Note
1 PCS1STPA 1 R/W 0 Note
0 PCS1STPA 0 R/W 0 Note
R/W RTCRST Other resets
Bit 15 to 0
Name PCS1STPA(15:0)
Function Programmable chip select 1 stop address. These bits determine the ending address for the memory or I/O chip select.
Note Holds the value before reset
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13.3.21 PCS1HIA (0x0B00 032A)
Bit Name 15 Reserved 14 Reserved 13 Reserved 12 Reserved 11 PCS1HIA 27 R/W 0 Note1 10 PCS1HIA 26 R/W 0 Note1 9 PCS1HIA 25 R/W 0 Note1 8 PCS1HIA 24 R/W 0 Note1
R/W RTCRST Other resets
R 0 0
R 0 0
R 0 0
R 0 0
Bit Name
7 PCS1HIA 23 R/W 0 Note1
6 PCS1HIA 22 R/W 0 Note1
5 PCS1HIA 21 R/W 0 Note1
4 PCS1HIA 20 R/W 0 Note1
3 PCS1HIA 19 R/W 0 Note1
2 PCS1HIA 18 R/W 0 Note1
1 PCS1HIA 17 R/W 0 Note1
0 PCS1HIA 16 R/W 0 Note1
R/W RTCRST Other resets
Bit 15 to 12 11 to 0 Reserved
Name 0 is returned when read
Function
PCS1HIA(27:16)
Programmable chip select 1 high address. A programmable chip select 1 will be generated when all of the following conditions have been met: * The system address bits A(15:0) are equal to or greater than PCS1STRA(15:0) Note2 and equal to or less than PCS1STPA(15:0) * The internal address bits A(27:16) are equal to PCS1HIA(27:16) * The read/write qualifier conditions specified by the PCSMODE register have been met.
Notes 1. Holds the value before reset 2. When the PCS1 has been defined as a 16-bit chip select, bit 0 of the address is ignored.
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13.3.22 PCSMODE (0x0B00 032C)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 PCS1MIOB R/W 0 Note
6 PCS1DSIZE R/W 0 Note
5 PCS1MD1 R/W 0 Note
4 PCS1MD0 R/W 0 Note
3 PCS0MIOB R/W 0 Note
2 PCS0DSIZE R/W 0 Note
1 PCS0MD1 R/W 0 Note
0 PCS0MD0 R/W 0 Note
Bit 15 to 8 7 Reserved PCS1MIOB
Name 0 is returned when read
Function
Programmable chip select 1 target cycle 0 : Enabled only during I/O cycles 1 : Enabled only during memory cycles
6
PCS1DSIZE
Programmable chip select 1 data size 0 : Defined as an 8-bit device. During accesses to the address range specified for PCS1, 8-bit cycles will be generated unless MEMCS16# or IOCS16# is asserted. 1 : Defined as a 16-bit device. During accesses to the address range specified for PCS1 16-bit cycles will be generated.
5, 4
PCS1MD(1:0)
Programmable chip select 1 mode 00 : Disabled 01 : Qualified also with I/O or memory read strobe 10 : Qualified also with I/O or memory write strobe 11 : Based on address decode only
3
PCS0MIOB
Programmable chip select 0 target cycle 0 : Enabled only during I/O cycles 1 : Enabled only during memory cycles
2
PCS0DSIZE
Programmable chip select 0 data size 0 : Defined as an 8-bit device. During accesses to the address range specified for PCS0, 8-bit cycles will be generated unless MEMCS16# or IOCS16# is asserted. 1 : Defined as a 16-bit device. During accesses to the address range specified for PCS0 16-bit cycles will be generated.
1, 0
PCS0MD(1:0)
Programmable chip select 0 mode 00 : Disabled 01 : Qualified also with I/O or Memory read strobe 10 : Qualified also with I/O or Memory write strobe 11 : Based on address decode only
Note Holds the value before reset
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13.3.23 LCDGPMODE (0x0B00 032E)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 LCDGPEN R/W 0 Note
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 LCDCS1 R/W 0 Note
2 LCDCS0 R/W 0 Note
1 GPVPBIAS R/W 0 Note
0 GPVPLCD R/W 0 Note
Bit 15 to 8 7 Reserved LCDGPEN
Name 0 is returned when read Control unit of LCD interface signals
Function
0 : Controlled by internal LCD controller 1 : Controlled by external LCD controller SHCLK ... LCDCS# LOCLK ... MEMCS16# VPLCD ... driven by the GPVPLCD bit of this register VPBIAS ... driven by the GPVPBIAS bit of this register 6 to 4 3, 2 Reserved LCDCS(1:0) 0 is returned when read External LCD controller frame buffer address select. These bits determine the address range that will cause the LCDCS# signal to be asserted. 00 : 0x130A 0000 to 0x130A FFFF (64KB PC/AT compatible address space) 01 : 0x133E 0000 to 0x133F FFFF (128KB) 10 : 0x133C 0000 to 0x133F FFFF (256KB) 11 : 0x1338 0000 to 0x133F FFFF (512KB) 1 GPVPBIAS Output control for VPBIAS pin. When the LCDGPEN bit is set to 1, the VPBIAS pin is driven by the value of this bit. Output control for VPLCD pin. When the LCDGPEN bit is set to 1, the VPLCD pin is driven by the value of this bit.
0
GPVPLCD
Note Holds the value before reset
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13.3.24 MISCREGn (0x0B00 0330 to 0x0B00 034E) Remark n = 0 to 15 MISCREG0 (0x0B00 0330) MISCREG1 (0x0B00 0332) MISCREG2 (0x0B00 0334) MISCREG3 (0x0B00 0336) MISCREG4 (0x0B00 0338) MISCREG5 (0x0B00 033A) MISCREG6 (0x0B00 033C) MISCREG7 (0x0B00 033E)
Bit Name R/W RTCRST Other resets 15 MISCnD15 R/W 0 Note 14 MISCnD14 R/W 0 Note 13 MISCnD13 R/W 0 Note
MISCREG8 (0x0B00 0340) MISCREG9 (0x0B00 0342) MISCREG10 (0x0B00 0344) MISCREG11 (0x0B00 0346) MISCREG12 (0x0B00 0348) MISCREG13 (0x0B00 034A) MISCREG14 (0x0B00 034C) MISCREG15 (0x0B00 034E)
12 MISCnD12 R/W 0 Note 11 MISCnD11 R/W 0 Note 10 MISCnD10 R/W 0 Note 9 MISCnD9 R/W 0 Note 8 MISCnD8 R/W 0 Note
Bit Name R/W RTCRST Other resets
7 MISCnD7 R/W 0 Note
6 MISCnD6 R/W 0 Note
5 MISCnD5 R/W 0 Note
4 MISCnD4 R/W 0 Note
3 MISCnD3 R/W 0 Note
2 MISCnD2 R/W 0 Note
1 MISCnD1 R/W 0 Note
0 MISCnD0 R/W 0 Note
Bit 15 to 0
Name MISCnD(15:0) Miscellaneous data
Function
Note Holds the value before reset Remark n = 0 to 15
These registers are battery-backed, and its contents are retained even in Hibernate mode.
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14.1 General
The PIU uses the on-chip A/D converter to detect the X and Y coordinates of pen contact locations on a touch panel and to scan the general-purpose A/D input port. Since the touch panel control circuit and the A/D converter (conversion precision: 10 bits) are both incorporated, the touch panel is connected directly to the VR4181. The PIU's function, namely the detection of X and Y coordinates, is performed partly by hardware and partly by software. Hardware tasks: * Touch panel applied voltage control * Reception of coordinate data Software task: * Processing of coordinate data based on data sampled by hardware
Features of the PIU's hardware tasks are described below. * Can be directly connected to touch panel with four-pin resistance layers (on-chip touch panel driver) * Interface for on-chip A/D converter * Voltage detection at three general-purpose A/D ports and one audio input port * Operation of A/D converter based on various settings and control of voltage applied to touch panel * Sampling of X-coordinate and Y-coordinate data * Variable coordinate data sampling interval * Interrupt is triggered if pen touch occurs regardless of CPU operation mode (interrupts do not occur during Hibernate mode) * Four dedicated buffers with up to two pages each for coordinate data * Four buffers for A/D port scan * Auto/manual options for coordinate data sampling start/stop control Caution No clocks are supplied to the PIU, A/D converter, and D/A converter in the initial state. When using the PIU, set the MSKPIUPCLK, MSKADUPCLK, and MSKADU18M bits of the CMUCLKMSK register in the MBA Host Bridge to 1 in advance so that clocks are supplied.
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14.1.1 Block diagrams Figure 14-1. PIU Peripheral Block Diagram
VR4181
AUDIOIN Battery, etc. ADIN2 ADIN1 ADIN0 I/O Buffer
4
Selector
1 ADC
AIU
4
Touch panel TPY1 TPY0 TPX1 TPX0 I/O Buffer PIU
* Touch panel A set of four pins are located at the edges of the X-axis and Y-axis resistance layers, and the two layers have high resistance when there is no pen contact and low resistance when there is a pen contact. The resistance between the two edges of the resistance layers is about 1 k. When a voltage is applied to both edges of the Y-axis resistance layer, the voltage (VY1 and VY2 in the figure below) is measures at the X-axis resistance layer's pins to determine the Y coordinate. Similarly, when a voltage is applied to both edges of the X-axis resistance layer, the voltage (VX1 and VX2 in the figure below) is measures at the Y-axis resistance layer's pins to determine the X coordinate. For greater precision, voltages are again measured after switching plus and minus of the voltage applied to the resistance layer's pins. The obtained data is stored into the PIUPBnmREG register (n = 0 or 1, m = 0 to 3).
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Figure 14-2. Coordinate Detection Equivalent Circuits
(a) Y-coordinate detection
TPY1 pin: 3 V TPY1 pin: 0 V
VY2 TPX0 pin VY1 TPX0 pin
TPY0 pin: 0 V
TPY0 pin: 3 V
(b) X-coordinate detection
TPY0 pin VX1 TPY0 pin VX2
TPX0 pin: 3 V
TPX1 pin: 0 V
TPX0 pin: 0 V
TPX1 pin: 3 V
Figure 14-3. Internal Block Diagram of PIU
VR4181
PIU
Internal bus
Scan sequencer
Internal bus controller
PIU registers
Touch panel
Touch panel interface controller
A/D converter General-purpose A/D ports, Audio input port
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The PIU includes three blocks: the internal bus controller, the scan sequencer, and the touch panel interface controller. * Internal bus controller The internal bus controller controls the internal bus, the PIU registers, and interrupts, and communicates with the A/D converter. * Scan sequencer The scan sequencer is used for PIU state management. * Touch panel interface controller The touch panel interface controller is used to control the touch panel.
14.2 Scan Sequencer State Transition
Figure 14-4. Scan Sequencer State Transition Diagram
Disable
Reset = 1
PIUPWR = 0
PIUPWR = 1
PIUSEQEN = 0
ADPSSTART = 1 ADPScan PIUSEQEN = 1 & ADPSSTART = 1 PIUSEQEN = 0 ADPSSTART =1 Release & PADATSTOP = 1 Interval
auto
timeout
Standby PIUSEQEN = 1 & PADATSTART = 1 PIUSEQEN = 1 & PIUMODE = 01
WaitPenTouch
Touch
DataScan
Release
PIUSEQEN = 1 & PADSCANSTART = 1
CMDScan
PIUSEQEN = 0
PIUSEQEN = 0 or PADSCANSTOP = 1
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* Disable state In this state, the A/D converter is in standby status, the output pins are in touch detection status (no PIU interrupt), and the input pins are in mask status (to prevent misoperation when an undefined input is applied). * Standby state In this state, the PIU is in scan idle status. The touch panel is in low-power status (0 V voltage is applied to the touch panel and the A/D converter is in disable status). Normally, this is the state in which various mode settings are made. Caution Since a state transition occurs when the PIUSEQEN bit is active, the PIUSEQEN bit must be set as active after various mode settings have been completed. * ADPScan state This is the state in which voltage is measured at the A/D converter's three general-purpose ports and one audio input port. After the A/D converter is activated and voltage data is obtained, the data is stored in the PIU's internal data buffer (PIUABnREG, n = 0 to 3). After the four ports are scanned, an A/D port scan interrupt request occurs. After this interrupt occurs, the ADPSSTART bit is automatically set as inactive and the PIU enters the state in which the ADPSSTART bit has been set as active. * CMDScan state In this state, the A/D converter operates according to various settings. Voltage data from one port only is fetched based on a combination of the touch panel pin setting (TPX(1:0), TPY(1:0)) and the selection of an input port (TPX(1:0), TPY(1:0), AUDIOIN, ADIN(2:0)) to the A/D converter. Use PIUCMDREG register to make the touch panel pin setting and to select the input port. * WaitPenTouch state This is a standby state in which the PIU waits for a touch panel's "touch" status. When the PIU detects a touch panel's "touch" status, a touch panel contact status change interrupt request occurs inside the PIU. At this point, if the PADATSTART bit is active, the PIU enters the DataScan state. During the WaitPenTouch state, it is possible to enter Suspend mode because the panel state can be detected even while the TClock is stopped. * DataScan state This is the state in which touch panel coordinates are detected. The A/D converter is activated and four data for each coordinate are sampled. Caution If one complete set of coordinate data is not obtained during the interval between one set of coordinate data and the next coordinate data, a data lost interrupt request occurs. * Interval state This is the standby state in which the PIU waits for the next coordinate sampling period or the touch panel's "release" status. After the touch panel status is detected, the time period specified via PIUSIVLREG register elapses before the transition to the DataScan state. If the PIU detects the "release" status within the specified time period, a touch panel contact status change interrupt request occurs inside the PIU. At this point, the PIU enters the WaitPenTouch state if the PADATSTOP bit is active. If the PADATSTOP bit is inactive, it enters to the DataScan state after the specified time period has elapsed.
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14.3 Register Set
The PIU registers are listed below. Table 14-1. PIU Registers
Physical address 0x0B00 0122 0x0B00 0124 0x0B00 0126 0x0B00 0128 0x0B00 012A 0x0B00 0130 0x0B00 0132 0x0B00 013E 0x0B00 02A0 0x0B00 02A2 0x0B00 02A4 0x0B00 02A6 0x0B00 02A8 0x0B00 02AA 0x0B00 02AC 0x0B00 02AE 0x0B00 02B0 0x0B00 02B2 0x0B00 02B4 0x0B00 02B6 0x0B00 02BC 0x0B00 02BE R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register symbol PIUCNTREG PIUINTREG PIUSIVLREG PIUSTBLREG PIUCMDREG PIUASCNREG PIUAMSKREG PIUCIVLREG PIUPB00REG PIUPB01REG PIUPB02REG PIUPB03REG PIUPB10REG PIUPB11REG PIUPB12REG PIUPB13REG PIUAB0REG PIUAB1REG PIUAB2REG PIUAB3REG PIUPB04REG PIUPB14REG PIU Control register PIU Interrupt cause register PIU Data sampling interval register PIU A/D converter start delay register PIU A/D command register PIU A/D port scan register PIU A/D scan mask register PIU data sampling period count register PIU page 0 buffer 0 register PIU page 0 buffer 1 register PIU page 0 buffer 2 register PIU page 0 buffer 3 register PIU page 1 buffer 0 register PIU page 1 buffer 1 register PIU page 1 buffer 2 register PIU page 1 buffer 3 register PIU A/D scan buffer 0 register PIU A/D scan buffer 1 register PIU A/D scan buffer 2 register PIU A/D scan buffer 3 register PIU page 0 buffer 4 register PIU page 1 buffer 4 register Function
State of interrupt requests caused by the PIU is indicated and can be set in the following registers, which are included in the ICU (refer to CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) for details). Table 14-2. PIU Interrupt Registers
Physical address 0x0B00 0082 0x0B00 008E R/W R R/W Register symbol PIUINTREG MPIUINTREG Function PIU interrupt indication register PIU interrupt mask register
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14.3.1 PIUCNTREG (0x0B00 0122) (1/2)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 PENSTC R 0 0 12
PADSTATE2
11
PADSTATE1
10
PADSTATE0
9
PADATSTOP
8
PADATSTART
R 0 0
R 0 0
R 0 0
R/W 0 0
R/W 0 0
Bit Name
7 PADSCAN STOP R/W 0 0
6 PADSCAN START R/W 0 0
5 PADSCAN TYPE R/W 0 0
4 PIUMODE1
3 PIUMODE0
2 PIUSEQEN
1 PIUPWR
0 PADRST
R/W RTCRST Other resets
R/W 0 0
R/W 0 0
R/W 0 0
R/W 0 0
R/W 0 0
Bit 15, 14 13 Reserved PENSTC
Name 0 is returned when read
Function
Touch/release status when touch panel contact state changes 1 : Touch 0 : Release
12 to 10
PADSTATE(2:0)
Scan sequencer status 111 : 110 : 101 : 100 : 011 : 010 : 001 : 000 : CMDScan Interval DataScan WaitPenTouch RFU ADPScan Standby Disable
9
PADATSTOP
Sequencer auto stop setting during touch panel release status 1 : Auto stop after sampling data for one set of coordinates 0 : No auto stop
8
PADATSTART
Sequencer auto start setting during touch panel touch status 1 : Auto start 0 : No auto start
7
PADSCANSTOP
Forced stop setting for touch panel sequencer 1 : Forced stop after sampling data for one set of coordinates 0 : Do not stop
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(2/2)
Bit 6 Name PADSCANSTART Function Start setting for touch panel sequencer 1 : Forced start 0 : Do not start 5 PADSCANTYPE Touch pressure sampling enable 1: Enable 0: Disable 4, 3 PIUMODE(1:0) PIU mode setting 11 : 10 : 01 : 00 : 2 PIUSEQEN RFU RFU Operates A/D converter using any command Samples coordinate data
Scan sequencer operation enable 1 : Enable 0 : Disable
1
PIUPWR
PIU power mode setting 1 : Sets PIU output as active and puts into standby status 0 : Sets panel to touch detection status and set PIU operation stop enabled status
0
PADRST
PIU reset. Once the PADRST bit is set to 1, it is automatically cleared to 0 after four TClock cycles. 1 : Reset 0 : Do not reset
This register is used to make various settings for the PIU. The PENSTC bit indicates the touch panel contact status at the time when the PENCHGINTR bit of the PIUINTREG register is set to 1. This bit's state remains as it is until the PENCHGINTR bit is cleared to 0. Also, when the PENCHGINTR bit is cleared to 0, the PENSTC bit indicates the touch panel contact status at that time. However, the PENSTC bit does not change while the PENCHGINTR bit is set to 1, even if the touch panel contact status changes between release and touch. Some bits in this register cannot be set in a specific state of scan sequencer. The combination of the setting of this register and the sequencer state is as follows.
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Table 14-3. PIUCNTREG Bit Manipulation and States
PIUCNTREG bit manipulation Disable
Note1
Scan sequencer's state Standby Disable ? Disable WaitPenTouch ? - - - -
Note3
WaitPenTouch Disable x x ? Standby
Note2
DataScan Disable x x ? Standby x x x x x x
Note4
PADRST PIUPWR
01 01 10
- Standby ? x ? x x x x x x x x
PIUSEQEN
01 10
PADATSTART
01 10
DataScan - x x x x x x
PADATSTOP
01 10
PADSCANSTART
01 10
DataScan - - -
PADSCANSTOP
01 10
Standby -
PIUCNTREG bit manipulation Interval
Note1
Scan sequencer's state ADPScan Disable ? x ? Standby x x x x x x
Note4 Note4
CMDScan Disable ? x ? Standby x x x x x x
Note4
PADRST PIUPWR
01 01 10
Disable ? x ? Standby x x x x x x Standby ?
PIUSEQEN
01 10
PADATSTART
01 10
PADATSTOP
01 10
PADSCANSTART
01 10
PADSCANSTOP
01 10
Standby -
Standby -
Notes 1. 2. 3. 4.
After 1 is written, the bit is automatically cleared to 0 four TClock cycles later. State transition occurs during touch status. State transition occurs when the PIUSEQEN bit is set to 1. State transition occurs after one set of data is sampled. The PADSCANSTOP bit is cleared to 0 after the state transition occurs.
Remark
- : The bit change is retained but there is no state transition. x : Setting prohibited (operation not guaranteed) ? : Combination of state and bit status before setting does not exist.
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14.3.2 PIUINTREG (0x0B00 0124)
Bit Name R/W RTCRST Other resets 15 OVP R/W 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name
7 Reserved
6 PADCMD INTR R/W 0 0
5 PADADP INTR R/W 0 0
4 PADPAGE1 INTR R/W 0 0
3 PADPAGE0 INTR R/W 0 0
2 PADDLOST INTR R/W 0 0
1 Reserved
0 PENCHG INTR R/W 0 0
R/W RTCRST Other resets
R 0 0
R 0 0
Bit 15 OVP
Name Valid page ID bit (older valid page) 1 : Page 1 retains an older valid data 0 : Page 0 retains an older valid data
Function
14 to 7 6
Reserved PADCMDINTR
0 is returned when read PIU command scan interrupt request. This interrupt request occurs when a valid data is obtained during a command scan. Cleared to 0 when 1 is written. 1 : Occurred 0 : Not occurred
5
PADADPINTR
PIU A/D port scan interrupt request. This interrupt request occurs when a set of valid data is obtained during an A/D port scan. Cleared to 0 when 1 is written. 1 : Occurred 0 : Not occurred
4
PADPAGE1INTR
PIU data buffer page 1 interrupt request. This interrupt request occurs when a set of valid data is stored in the page 1 of the data buffer. Cleared to 0 when 1 is written. 1 : Occurred 0 : Not occurred
3
PADPAGE0INTR
PIU data buffer page 0 interrupt request. This interrupt request occurs when a set of valid data is stored in the page 0 of the data buffer. Cleared to 0 when 1 is written. 1 : Occurred 0 : Not occurred
2
PADDLOSTINTR
Data lost interrupt request. This interrupt request occurs when a set of data cannot be obtained during a specified time period. Cleared to 0 when 1 is written. 1 : Occurred 0 : Not occurred
1 0
Reserved PENCHGINTR
0 is returned when read Touch panel contact status change interrupt request. Cleared to 0 when 1 is written. 1 : Occurred 0 : Not occurred
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This register sets and indicates the interrupt request generation of the PIU. When the PENCHGINTR bit is set to1, the PENSTC bit of the PIUCNTREG register indicates the touch panel contact status (touch or release) when a contact status changes. The PENSTC bit's status remains until the PENCHGINTR bit is cleared to 0. Also, when the PENCHGINTR bit is cleared to 0, the PENSTC bit indicates the touch panel contact status. However, the PENSTC bit does not change while the PENCHGINTR bit is set to 1, even if the touch panel contact status changes between release and touch. Caution In the Hibernate mode, the VR4181 retains the touch panel status. Therefore, if the Hibernate mode has been entered while the touch panel is touched, the contact status may be mistakenly recognized as having changed, when the VR4181 returns to Fullspeed mode. If a touch panel status change interrupt request occurs immediately after the VR4181 returns from the Hibernate mode, the PENCHGINTR bit may be set to 1 due to a miss-recognition such as above. Similarly, other bits of the PIUINTREG register may be set to 1 on returning from the Hibernate mode. Therefore, set each bit of the PIUINTREG register to 1 to clear an interrupt request immediately after a restore from the Hibernate mode. 14.3.3 PIUSIVLREG (0x0B00 0126)
Bit Name 15 Reserved 14 Reserved 13 Reserved 12 Reserved 11 Reserved 10 SCAN INTVAL10 R/W 0 0 9 SCAN INTVAL9 R/W 0 0 8 SCAN INTVAL8 R/W 0 0
R/W RTCRST Other resets
R 0 0
R 0 0
R 0 0
R 0 0
R 0 0
Bit Name
7 SCAN INTVAL7 R/W 1 1
6 SCAN INTVAL6 R/W 0 0
5 SCAN INTVAL5 R/W 1 1
4 SCAN INTVAL4 R/W 0 0
3 SCAN INTVAL3 R/W 0 0
2 SCAN INTVAL2 R/W 1 1
1 SCAN INTVAL1 R/W 1 1
0 SCAN INTVAL0 R/W 1 1
R/W RTCRST Other resets
Bit 15 to 11 10 to 0 Reserved
Name 0 is returned when read
Function
SCANINTVAL(10:0)
Coordinate data scan sampling interval setting Interval = SCANINTVAL(10:0) x 30 s
This register sets the scan interval (sampling period) for coordinate data sampling. The sampling interval for one set of coordinate data is the value set via SCANINTVAL(10:0) multiplied by 30 s. Accordingly, the logical range of sampling intervals that can be set in 30 s units is from 0 s to about 60 ms. Actually, if the sampling interval setting is shorter than the time required for obtaining a set of coordinate data or ADPScan data, a data lost interrupt request will occur. If data lost interrupt requests occur frequently, set a longer interval time.
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Figure 14-5. Interval Times and States
State Operation
DataScan SASASASA
Interval ST
ADPScan AAAA
Interval T
DataScan SASASASA
Interval time
Remark
S: Voltage stabilization wait time (STABLE(5:0) in PIUSTBLREG) A: A/D converter conversion time (about 10 s) T: Touch/release detection
14.3.4 PIUSTBLREG (0x0B00 0128)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 STABLE5 R/W 0 0
4 STABLE4 R/W 0 0
3 STABLE3 R/W 0 0
2 STABLE2 R/W 1 1
1 STABLE1 R/W 1 1
0 STABLE0 R/W 1 1
Bit 15 to 6 5 to 0 Reserved
Name 0 is returned when read
Function
STABLE(5:0)
Touch panel voltage stabilization wait time (DataScan, CMDScan state) A/D scan timeout time (ADPScan state) Touch detection start wait time (Disable, WaitPenTouch, Interval state) Wait time = STABLE(5:0) x 30 s
The voltage stabilization wait time for the power applied to the touch panel can be set via the STABLE(5:0) bits in 30 s units between 0 s and 1,890 s.
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14.3.5 PIUCMDREG (0x0B00 012A) (1/2)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 STABLEON R/W 0 0 11 TPYEN1 R/W 0 0 10 TPYEN0 R/W 0 0 9 TPXEN1 R/W 0 0 8 TPXEN0 R/W 0 0
Bit Name R/W RTCRST Other resets
7 TPYD1 R/W 0 0
6 TPYD0 R/W 0 0
5 TPXD1 R/W 0 0
4 TPXD0 R/W 0 0
3 ADCMD3 R/W 1 1
2 ADCMD2 R/W 1 1
1 ADCMD1 R/W 1 1
0 ADCMD0 R/W 1 1
Bit 15 to 13 12 Reserved
Name 0 is returned when read
Function
STABLEON
Touch panel voltage stabilization wait time (STABLE(5:0) of PIUSTBLREG) enable during command scan 1 : Wait for panel voltage stabilization time 0 : Ignore panel voltage stabilization time (wait time = 0)
11, 10
TPYEN(1:0)
TPY port input/output switching during command scan 11 : 10 : 01 : 00 : TPY1 output, TPY0 output TPY1 output, TPY0 input TPY1 input, TPY0 output TPY1 input, TPY0 input
9, 8
TPXEN(1:0)
TPX port input/output switching during command scan 11 : 10 : 01 : 00 : TPX1 output, TPX0 output TPX1 output, TPX0 input TPX1 input, TPX0 output TPX1 input, TPX0 input
7, 6
TPYD(1:0)
TPY output level during command scan 11 : 10 : 01 : 00 : TPY1 = "H", TPY0 = "H" TPY1 = "H", TPY0 = "L" TPY1 = "L", TPY0 = "H" TPY1 = "L", TPY0 = "L"
5, 4
TPXD(1:0)
TPX output level during command scan 11 : 10 : 01 : 00 : TPX1 = "H", TPX0 = "H" TPX1 = "H", TPX0 = "L" TPX1 = "L", TPX0 = "H" TPX1 = "L", TPX0 = "L"
Remark
L: low level, H: high level
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Bit 3 to 0 Name ADCMD(3:0) Function A/D converter input port selection for command scan 1111 : A/D converter standby mode request 1110 : RFU : 1000 : 0111 : 0110 : 0101 : 0100 : 0011 : 0010 : 0001 : 0000 : RFU AUDIOIN port ADIN2 port ADIN1 port ADIN0 port TPY1 port TPY0 port TPX1 port TPX0 port
This register switches input/output and sets output level for each port during a command scanning operation. The setting of the TPYD bits are invalid when a port is set as input in the TPYEN bits. The setting of the TPXD bits are invalid when a port is set as input in the TPXEN bits.
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14.3.6 PIUASCNREG (0x0B00 0130)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name
7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 Reserved
2 Reserved
1 TPPSCAN
0 ADPS START R/W 0 0
R/W RTCRST Other resets
R 0 0
R 0 0
R 0 0
R 0 0
R 0 0
R 0 0
R/W 0 0
Bit 15 to 2 1 Reserved TPPSCAN
Name 0 is returned when read Port selection for ADPScan
Function
1 : Select TPX(1:0), TPY(1:0) (for touch panel) as A/D port 0 : Select ADIN(2:0) (general-purpose) as A/D port and AUDIOIN as audio input port 0 ADPSSTART ADPScan start 1 : Start ADPScan 0 : Do not perform ADPScan
This register is used for ADPScan setting. The ADPScan begins when the ADPSSTART bit is set. After the ADPScan is completed, the sequencer returns to the state when ADPScan was started, and the ADPSSTART bit is cleared to 0 automatically. If the ADPScan is not completed within the time period set via the STABLE bits of the PIUSTBLREG register, a data lost interrupt request occurs as a timeout interrupt. Caution Manipulation of the TPPSCAN bit is valid only in the standby state. In the other states, the operation is not guaranteed. Some bits in this register cannot be set in a specific state of scan sequencer. The combination of the setting of this register and the sequencer state is as follows.
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Table 14-4. PIUASCNREG Bit Manipulation and States
PIUASCNREG bit manipulation
Note1
Scan sequencer's state Disable x x - - Standby
Note2
WaitPenTouch
Note2
DataScan x x - -
ADPSSTART
01 10
ADPScan ? - - Scan sequencer's state
ADPScan ? - -
TPPSCAN
01 10
PIUCNTREG bit manipulation Interval
Note1
ADPScan
Note2 Note2
CMDScan x x x x
ADPSSTART
01 10
ADPScan ? x ?
ADPScan ? x x
TPPSCAN
01 10
Notes 1. Immediately after a transition to the ADPScan state, the bit is automatically cleared to 0. 2. After ADPScan is completed, the sequencer returns to the state in which the scan has started. Remark - : The bit change is retained but there is no state transition. x : Setting prohibited (operation not guaranteed) ? : Combination of state and bit status before setting does not exist.
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14.3.7 PIUAMSKREG (0x0B00 0132)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 ADINM3 R/W 0 0
6 ADINM2 R/W 0 0
5 ADINM1 R/W 0 0
4 ADINM0 R/W 0 0
3 TPYM1 R/W 0 0
2 TPYM0 R/W 0 0
1 TPXM1 R/W 0 0
0 TPXM0 R/W 0 0
Bit 15 to 8 7 Reserved ADINM3
Name 0 is returned when read Audio input port mask 1 : Mask 0 : Normal
Function
6 to 4
ADINM(2:0)
General-purpose A/D port mask 1 : Mask 0 : Normal
3, 2
TPYM(1:0)
Touch panel A/D port TPY mask 1 : Mask 0 : Normal
1, 0
TPXM(1:0)
Touch panel A/D port TPX mask 1 : Mask 0 : Normal
This register is used to set masking each A/D port. Each bit corresponds to one port. If masked, A/D conversions are not performed for data of the corresponding port. Settings in this register are valid only during the ADPScan state.
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14.3.8 PIUCIVLREG (0x0B00 013E)
Bit Name 15 Reserved 14 Reserved 13 Reserved 12 Reserved 11 Reserved 10 CHECK INTVAL10 R 0 0 9 CHECK INTVAL9 R 0 0 8 CHECK INTVAL8 R 0 0
R/W RTCRST Other resets
R 0 0
R 0 0
R 0 0
R 0 0
R 0 0
Bit Name
7 CHECK INTVAL7 R 1 1
6 CHECK INTVAL6 R 0 0
5 CHECK INTVAL5 R 1 1
4 CHECK INTVAL4 R 0 0
3 CHECK INTVAL3 R 0 0
2 CHECK INTVAL2 R 0 0
1 CHECK INTVAL1 R 0 0
0 CHECK INTVAL0 R 0 0
R/W RTCRST Other resets
Bit 15 to 11 10 to 0 Reserved
Name 0 is returned when read Interval count value.
Function
CHECKINTVAL(10:0)
This register indicates the value of an internal register that counts down based on the PIUSIVLREG register setting.
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14.3.9 PIUPBnmREG (0x0B00 02A0 to 0x0B00 02AE, 0x0B00 02BC to 0x0B00 02BE) Remark n = 0, 1, m = 0 to 4 PIUPB00REG (0x0B00 02A0) PIUPB01REG (0x0B00 02A2) PIUPB02REG (0x0B00 02A4) PIUPB03REG (0x0B00 02A6) PIUPB04REG (0x0B00 02BC)
Bit Name R/W RTCRST Other resets 15 VALID R/W 0 0 14 Reserved R 0 0 13 Reserved R 0 0
PIUPB10REG (0x0B00 02A8) PIUPB11REG (0x0B00 02AA) PIUPB12REG (0x0B00 02AC) PIUPB13REG (0x0B00 02AE) PIUPB14REG (0x0B00 02BE)
12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 PADDATA9 R/W 0 0 8 PADDATA8 R/W 0 0
Bit Name R/W RTCRST Other resets
7 PADDATA7 R/W 0 0
6 PADDATA6 R/W 0 0
5 PADDATA5 R/W 0 0
4 PADDATA4 R/W 0 0
3 PADDATA3 R/W 0 0
2 PADDATA2 R/W 0 0
1 PADDATA1 R/W 0 0
0 PADDATA0 R/W 0 0
Bit 15 VALID
Name Indicates validity of data in page buffer 1 : Valid 0 : Invalid
Function
14 to 10 9 to 0
Reserved PADDATA(9:0)
0 is returned when read A/D converter's sampling data
These registers are used to store coordinate data or touch pressure data. There are four coordinate data buffers and one touch pressure data buffer, each of which holds two pages of coordinate data or pressure data, and the addresses (register addresses) where the coordinate data or the pressure data is stored are fixed. Read coordinate data or pressure data from the corresponding register in a valid page. The VALID bit, which indicates whether the data is valid, is automatically rendered invalid when the page buffer interrupt source (the PADPAGE0INTR or PADPAGE1INTR bit in the PIUINTREG register) is cleared. Table 14-5 shows correspondences between the sampled data and the register in which the sampled data is stored. Table 14-5. Detected Data and Page Buffers
Detected data X- X+ Y- Y+ Z (Touch pressure) Page0 Buffer PIUPB00REG PIUPB01REG PIUPB02REG PIUPB03REG PIUPB04REG Page1 Buffer PIUPB10REG PIUPB11REG PIUPB12REG PIUPB13REG PIUPB14REG
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14.3.10 PIUABnREG (0x0B00 02B0 to 0x0B00 02B6) Remark n = 0 to 3 PIUAB0REG (0x0B00 02B0) PIUAB1REG (0x0B00 02B2) PIUAB2REG (0x0B00 02B4) PIUAB3REG (0x0B00 02B6)
Bit Name R/W RTCRST Other resets 15 VALID R/W 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 PADDATA9 R/W 0 0 8 PADDATA8 R/W 0 0
Bit Name R/W RTCRST Other resets
7 PADDATA7 R/W 0 0
6 PADDATA6 R/W 0 0
5 PADDATA5 R/W 0 0
4 PADDATA4 R/W 0 0
3 PADDATA3 R/W 0 0
2 PADDATA2 R/W 0 0
1 PADDATA1 R/W 0 0
0 PADDATA0 R/W 0 0
Bit 15 VALID
Name Indicates validity of data in buffer 1 : Valid 0 : Invalid
Function
14 to 10 9 to 0
Reserved PADDATA(9:0)
0 is returned when read A/D converter's sampling data
These registers are used to store sampling data of the general-purpose A/D port and audio input port or command scan data. There are four data buffers and the addresses (register address) where the data is stored are fixed. The VALID bit, which indicates whether the data is valid, is automatically rendered invalid when the page buffer interrupt source (the PADADPINTR bit in the PIUINTREG register) is cleared. Table 14-6 shows correspondences between the sampled data and the register in which the sampled data is stored. Table 14-6. A/D Ports and Data Buffers
Register During ADPScan TPPSCAN = 0 PIUAB0REG PIUAB1REG PIUAB2REG PIUAB3REG ADIN0 ADIN1 ADIN2 AUDIOIN TPPSCAN = 1 TPX0 TPX1 TPY0 TPY1 CMDScan data - - - During CMDScan
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14.4 State Transition Flow
Be sure to initialize the PIU before scan sequencer operation. Initialization via a reset sets particular values for the sequence interval, etc., which should be re-set to appropriate values. The following registers require initial settings.
SCANINTVAL(10:0) bit of PIUSIVLREG register STABLE(5:0) bit of PIUSTBLREG register
Interrupt mask cancellation settings are required for registers other than the PIU registers. Table 14-7. Mask Clear During Scan Sequencer Operation
Setting Interrupt mask clear ICU ICU Clock mask clear MBA Host Bridge Unit Register MSYSINT1REG MPIUINTREG CMUCLKMSK Bit MPIUINTR bits 6 to 0 MSKPIUPCLK 1 0x7F 1 Value
(1) Transition flow for voltage detection at A/D general-purpose ports and audio input port Standby, WaitPenTouch, or Interval state <1> PIUAMSKREG <2> PIUASCNREG ADPScan state <3> PIUASCNREG Standby, WaitPenTouch, or Interval state (2) Transition flow for auto scan coordinate detection Standby state <1> PIUCNTREG PIUMODE(1:0) = 00 PADATSTART = 1 PADATSTOP = 1 <2> PIUCNTREG WaitPenTouch state PIUSEQEN = 1 ADPSSTART = 0 Mask setting for A/D ports and audio input port ADPSSTART = 1
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(3) Transition flow for manual scan coordinate detection Disable state <1> PIUCNTREG Standby state <2> PIUCNTREG <3> PIUCNTREG DataScan state (4) Transition flow when entering Suspend mode transition Standby, WaitPenTouch, or Interval state <1> PIUCNTREG Standby state <2> PIUCNTREG Disable state (5) Transition flow when returning from Suspend mode Disable state <1> PIUCNTREG Standby state <2> PIUCNTREG PIUMODE(1:0) = 00 PADATSTART = 1 PADATSTOP = 1 <3> PIUCNTREG WaitPenTouch state Touch detected DataScan state (6) Transition flow for command scan Disable state <1> PIUCNTREG Standby state <2> PIUCNTREG <3> PIUCNTREG <4> PIUCNTREG CMDScan state PIUMODE(1:0) = 01 Setting of touch panel pins, selection of input port PIUSEQEN = 1 PIUPWR = 1 PIUSEQEN = 1 PIUPWR = 1 PIUPWR = 1 PIUSEQEN = 0 PIUMODE(1:0) = 00 PADSCANSTART = 1 PIUSEQEN = 1 PIUPWR = 1
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14.5 Relationships among TPX, TPY, ADIN, and AUDIOIN Pins and States
State PIU disable (pen status detection) Low-power standby Pen status detection Voltage detection at general-purpose AD0 port Voltage detection at general-purpose AD1 port Voltage detection at general-purpose AD2 port Voltage detection at audio input port Touch pressure detection (Z) TPY1=L, TPY0=H, TPX0=samp (X-) TPY1=H, TPY0=L, TPX0=samp (X+) TPX1=L, TPX0=H, TPY0=samp (Y-) TPX1=H, TPX0=L, TPY0=samp (Y+) PADSTATE(2:0) Disable
Note
TPX(1:0) HH 00 HH 00 00 00 00 HH -I -I LH HL
TPY(1:0) D- 00 D- 00 00 00 00 d- LH HL -I -I
AUDIOIN, ADIN(2:0) ---- ---- ---- ---I --I- -I-- I--- ---- ---- ---- ---- ----
Standby WaitPenTouch/Interval ADPScan ADPScan ADPScan ADPScan DataScan DataScan DataScan DataScan DataScan
Note The states of pins are not guaranteed if the PADSTATE(2:0) immediately before the CPU's SUSPEND or HIBERNATE instruction execution is in a state other then the Disable state. Remarks 0 1 L l d - : Low level input : High level input : Low level output : A/D converter input : No touch interrupt request input (with a pull-down resistor) : Don't care
H : High level output D : Touch interrupt request input (with a pull-down resistor)
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14.6 Timing
14.6.1 Touch/release detection timing Touch/release detection is not determined via the A/D converter but the voltage level of the TPY1 pin. The following figure shows a timing of touch/release detection and coordinate detection. Figure 14-6. Touch/Release Detection Timing
State
Standby
WaitPenTouch
DataScan
Interval
TPY(1:0), TPX(1:0) (PADSCANTYPE = 0) TPY(1:0), TPX(1:0) (PADSCANTYPE = 1)
Touch detected
Note
X-
X+
Y-
Y+
Release detected
Note
Touch detected
Note
Z
X-
X+
Y-
Y+
Release detected
Note
Note Determined according to the status of the TPY1 signal as follows. High level ... touched Low level ... released
14.6.2 A/D port scan timing During an A/D port scan, the four ports of A/D converter's input channel are sequentially scanned and the scanned data are stored in the data buffers dedicated to A/D port scanning. The following figure shows an A/D port scan timing diagram. Figure 14-7. A/D Port Scan Timing
State
XXX
ADPScan
XXX
AUDIOIN, ADIN(2:0) ADPSSTART bit (PIUASCNREG)
ADIN0
ADIN1
ADIN2
AUDIOIN
Remark
XXX: Standby, WaitPenTouch, or Interval
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14.7 Data Loss Conditions
The PIU issues a data lost interrupt request when any of the following four conditions exist. 1. Data for one coordinate has not been obtained within the interval period 2. The A/D port scan has not been completed within the time set via PIUSTBLREG register 3. Transfer of the next coordinate data starts while valid data for both pages remains in the buffer 4. The next data transfer starts while there is valid data in the ADPScan buffer Once a data lost interrupt request occurs, the sequencer is forcibly changed to the Standby state. The cause and response to each condition are as follows. (1) When data for one coordinate has not been obtained within the interval period Cause This condition occurs when the AIU has exclusive use of the A/D converter and the PIU is therefore unable to use the A/D converter. If this data loss condition occurs frequently, implement a countermeasure that temporarily prohibits the AIU's use of the A/D converter. Response After clearing the data lost interrupt request by setting the PADDLOSTINTR bit to 1, set the PADATSTART bit or PADSCANSTART bit of the PIUCNTREG register to restart the coordinate detection operation. Once the data lost interrupt request is cleared, the page in which the loss occurred becomes invalid. If the valid data prior to the data loss is needed, be sure to save the data that is being stored in the page buffer before clearing the data lost interrupt request. (2) When the A/D port scan has not been completed within the time set via PIUSTBLREG register Cause Same as cause of condition 1. Response After clearing the data lost interrupt request by setting the PADDLOSTINTR bit to 1, set the ADPSSTART bit of the PIUASCNREG register to restart the A/D port scan operation. Once the data lost interrupt request is cleared, the page in which the loss occurred becomes invalid. If the valid data prior to the data loss is needed, be sure to save the data that is being stored in the page buffer before clearing the data lost interrupt request.
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(3) When transfer of the next coordinate data starts while valid data for both pages remains in the buffer Cause This condition is caused when the data buffer contains two pages of valid data (both the data buffer page 1 and data buffer page 0 interrupt requests have occurred) but the valid data has not been processed. If the A/D converter is used frequently, the time from when both pages become full until when the data loss occurs may be shorter than that of the normal operation. Response In this case, valid data contained in the pages when the data lost interrupt request occurs is never overwritten. After two pages of valid data are processed, clear the three interrupt requests by writing 1 to the PADDLOSTINTR, PADPAGE1INTR, and PADPAGE0INTR bits in the PIUINTREG register. After clearing these interrupt requests, set the PADATSTART or PADSCANSTART bit of the PIUCNTREG register to restart the coordinate detection operation. (4) When the next data transfer starts while there is valid data in the ADPScan buffer Cause This condition is caused when valid data is not processed even while the ADPScan buffer holds valid data (A/D port scan interrupt request occurrence). Response In this case, valid data contained in the buffer when the data lost interrupt request occurs is never overwritten. After valid data in the buffer is processed, clear the two interrupt requests by writing 1 to the PADDLOSTINTR and PADADPINTR bits in the PIUINTREG register. After clearing these interrupt requests, set the ADPSSTART bit of the PIUASCNREG to restart the generalpurpose A/D port scan operation.
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CHAPTER 15 AUDIO INTERFACE UNIT (AIU)
15.1 General
The AIU controls the analog output (speaker output) processing of the internal D/A converter and the analog input (microphone input) processing of the internal A/D converter. It is also used to make settings related to the A/D and D/A converters. The main functions of the AIU are as follows: * Holding the digital value converted by the internal A/D converter * Holding the digital value to be converted by the internal D/A converter * Separating data being converted by the A/D or D/A converter and transfer data by using double buffers * Linking the update of the double buffers and the generation of DMA transfer requests with the data conversion rate Caution No clocks are supplied to the AIU, A/D converter, and D/A converter in the initial state. When using the AIU, set the MSKAIUPCLK, MSKADUPCLK, and MSKADU18M bits of the CMUCLKMSK register in the MBA Host Bridge to 1 in advance so that clocks are supplied.
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15.2 Register Set
The AIU registers are listed below. Table 15-1. AIU Registers
Physical address 0x0B00 0160 0x0B00 0162 0x0B00 0164 0x0B00 0166 0x0B00 0168 0x0B00 016E 0x0B00 0170 0x0B00 0172 0x0B00 0178 0x0B00 017A 0x0B00 017C 0x0B00 017E R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register symbol SDMADATREG MDMADATREG DAVREF_SETUP SODATREG SCNTREG SCNVC_END MIDATREG MCNTREG DVALIDREG SEQREG INTREG MCNVC_END Function Speaker DMA data register Microphone DMA data register D/A converter Vref setup register Speaker output data register Speaker output control register Speaker sample rate control register Microphone input data register Microphone input control register Data valid indication register Sequencer enable register Interrupt register Microphone sample rate control register
State of interrupt requests caused by AIU is indicated and can be set in the following registers, which are included in the ICU (refer to CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) for details). Table 15-2. AIU Interrupt Registers
Physical address 0x0B00 0084 0x0B00 0090 R R/W R/W Register symbol AIUINTREG MAIUINTREG Function AIU interrupt indication register AIU interrupt mask register
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15.2.1 SDMADATREG (0x0B00 0160)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 SDMA9 R/W 1 1 8 SDMA8 R/W 0 0
Bit Name R/W RTCRST Other resets
7 SDMA7 R/W 0 0
6 SDMA6 R/W 0 0
5 SDMA5 R/W 0 0
4 SDMA4 R/W 0 0
3 SDMA3 R/W 0 0
2 SDMA2 R/W 0 0
1 SDMA1 R/W 0 0
0 SDMA0 R/W 0 0
Bit 15 to 10 9 to 0 Reserved
Name 0 is returned when read Speaker output DMA data
Function
SDMA(9:0)
This register is used to store 10-bit DMA data for speaker output. When SODATREG register is empty, the data is transferred to the SODATREG register. Write is used for debugging and is enabled when the AIUSEN bit of the SEQREG register is set to 1. This register is initialized (0x0200) by resetting the AIUSEN bit of the SEQREG register to 0.
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15.2.2 MDMADATREG (0x0B00 0162)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 MDMA9 R/W 1 1 8 MDMA8 R/W 0 0
Bit Name R/W RTCRST Other resets
7 MDMA7 R/W 0 0
6 MDMA6 R/W 0 0
5 MDMA5 R/W 0 0
4 MDMA4 R/W 0 0
3 MDMA3 R/W 0 0
2 MDMA2 R/W 0 0
1 MDMA1 R/W 0 0
0 MDMA0 R/W 0 0
Bit 15 to 10 9 to 0 Reserved
Name 0 is returned when read Microphone input DMA data
Function
MDMA(9:0)
This register is used prior to DMA transfer to store 10-bit data that has been converted by the A/D converter and stored in the MIDATREG register. Write is used for debugging and is enabled when the AIUMEN bit of the SEQREG register is set to 1. This register is initialized (0x0200) by resetting the AIUMEN bit of the SEQREG register to 0. Therefore, if the AIUMEN bit is set to 0 during DMA transfer, invalid data may be transferred.
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15.2.3 DAVREF_SETUP (0x0B00 0164)
Bit Name R/W RTCRST Other resets 15 DAVREF15 R/W 0 0 14 DAVREF14 R/W 0 0 13 DAVREF13 R/W 0 0 12 DAVREF12 R/W 0 0 11 DAVREF11 R/W 0 0 10 DAVREF10 R/W 0 0 9 DAVREF9 R/W 0 0 8 DAVREF8 R/W 0 0
Bit Name R/W RTCRST Other resets
7 DAVREF7 R/W 0 0
6 DAVREF6 R/W 1 1
5 DAVREF5 R/W 1 1
4 DAVREF4 R/W 1 1
3 DAVREF3 R/W 1 1
2 DAVREF2 R/W 1 1
1 DAVREF1 R/W 0 0
0 DAVREF0 R/W 1 1
Bit 15 to 0
Name DAVREF(15:0) D/A converter Vref setup time.
Function
This register is used to select a Vref setup time for the D/A converter. The following expression is used to calculate the value set to this register. DAVREF(15:0) = 5 s x PCLK frequency For example, if the internal peripheral clock (PCLK) frequency is 25 MHz, the DAVREF(15:0) bits should be set to as follows; DAVREF(15:0) = 5 x 10 x 25 x 10 = 0x007D
-6
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15.2.4 SODATREG (0x0B00 0166)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 SODAT9 R/W 1 1 8 SODAT8 R/W 0 0
Bit Name R/W RTCRST Other resets
7 SODAT7 R/W 0 0
6 SODAT6 R/W 0 0
5 SODAT5 R/W 0 0
4 SODAT4 R/W 0 0
3 SODAT3 R/W 0 0
2 SODAT2 R/W 0 0
1 SODAT1 R/W 0 0
0 SODAT0 R/W 0 0
Bit 15 to 10 9 to 0 Reserved
Name 0 is returned when read Speaker output data
Function
SODAT(9:0)
This register is used to store 10-bit DMA data for speaker output. Data is received from the SDMADATREG register and is sent to the D/A converter. Write is used for debugging and is enabled when the AIUSEN bit of the SEQREG register is set to 1. This register is initialized (0x0200) by resetting the AIUSEN bit of the SEQREG register to 0.
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15.2.5 SCNTREG (0x0B00 0168)
Bit Name R/W RTCRST Other resets 15 DAENAIU R/W 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 SSTATE R 0 0
2 Reserved R 0 0
1 SSTOPEN R/W 0 0
0 Reserved R 0 0
Bit 15 DAENAIU
Name
Function Enables D/A converter operation (Vref connection). 1 : ON 0 : OFF
14 to 4 3
Reserved SSTATE
0 is returned when read Indicates speaker operation state. 1 : Operating 0 : Stopped
2 1
Reserved SSTOPEN
0 is returned when read Speaker output DMA transfer page boundary interrupt 1 : Stop DMA request at 1-page boundary 0 : Stop DMA request at 2-page boundary
0
Reserved
0 is returned when read
This register is used to control the AIU's speaker block. The DAENAIU bit controls the connection of VDD_AD and Vref input to ladder type resistors in the D/A converter. Setting this bit to 0 (OFF) allows low power consumption when not using the D/A converter. When using the D/A converter, this bit must be set following the sequence described in 15.3 Operation Sequence. The content of the SSTATE bit is valid only when the AIUSEN bit of the SEQREG register is set to 1.
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15.2.6 SCNVC_END (0x0B00 016E)
Bit Name R/W RTCRST Other resets 15 SCNVC15 R/W 0 0 14 SCNVC14 R/W 0 0 13 SCNVC13 R/W 0 0 12 SCNVC12 R/W 0 0 11 SCNVC11 R/W 1 1 10 SCNVC10 R/W 0 0 9 SCNVC9 R/W 0 0 8 SCNVC8 R/W 0 0
Bit Name R/W RTCRST Other resets
7 SCNVC7 R/W 1 1
6 SCNVC6 R/W 1 1
5 SCNVC5 R/W 0 0
4 SCNVC4 R/W 1 1
3 SCNVC3 R/W 1 1
2 SCNVC2 R/W 1 1
1 SCNVC1 R/W 0 0
0 SCNVC0 R/W 0 0
Bit 15 to 0
Name SCNVC(15:0) Speaker sample rate control
Function
This register is used to select a conversion rate for the D/A converter. The following expression is used to calculate the value set to this register. SCNVC(15:0) = PCLK frequency/sample rate For example, if the desired conversion rate is 8 ksps and internal peripheral clock (PCLK) frequency is 25 MHz, SCNVC(15:0) bits should be set to as follows; SCNVC(15:0) = 25 x 10 /8 x 10 = 0x0C35 Caution Set this register to a value that determines the conversion rate as 50 ksps or less.
6 3
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15.2.7 MIDATREG (0x0B00 0170)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 MIDAT9 R/W 1 1 8 MIDAT8 R/W 0 0
Bit Name R/W RTCRST Other resets
7 MIDAT7 R/W 0 0
6 MIDAT6 R/W 0 0
5 MIDAT5 R/W 0 0
4 MIDAT4 R/W 0 0
3 MIDAT3 R/W 0 0
2 MIDAT2 R/W 0 0
1 MIDAT1 R/W 0 0
0 MIDAT0 R/W 0 0
Bit 15 to 10 9 to 0 Reserved
Name 0 is returned when read Microphone input data
Function
MIDAT(9:0)
This register is used to store 10-bit speaker input data that has been converted by the A/D converter. Data is sent to the MDMADATREG register and is received from the A/D converter. Write is used for debugging and is enabled when the AIUMEN bit of the SEQREG register is set to 1. This register is initialized (0x0200) by resetting the AIUMEN bit of the SEQREG register to 0.
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15.2.8 MCNTREG (0x0B00 0172)
Bit Name R/W RTCRST Other resets 15 ADENAIU R/W 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 MSTATE R 0 0
2 Reserved R 0 0
1 MSTOPEN R/W 0 0
0 ADREQAIU R 0 0
Bit 15 ADENAIU
Name
Function Enables A/D converter operation (Vref connection). 1 : ON 0 : OFF
14 to 4 3
Reserved MSTATE
0 is returned when read Indicates microphone operation state 1 : Operating 0 : Stopped
2 1
Reserved MSTOPEN
0 is returned when read Microphone input DMA transfer page boundary interrupt 1 : Stop DMA request at 1-page boundary 0 : Stop DMA request at 2-page boundary
0
ADREQAIU
Request for use of A/D converter 1 : Requesting 0 : No request
This register is used to control the AIU's microphone block. The ADENAIU bit controls the connection of VDD_AD and Vref input to ladder type resistors in the A/D converter. Setting this bit to 0 (OFF) allows low power consumption when not using the A/D converter. When using the A/D converter, this bit must be set following the sequence described in 15.3 Operation Sequence. The content of the MSTATE bit is valid only when the AIUMEN bit of the SEQREG register is set to 1. The AIU has priority when a conflict occurs with the PIU in relation to A/D conversion requests.
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15.2.9 DVALIDREG (0x0B00 0178)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 SODATV R/W 0 0
2 SDMAV R/W 0 0
1 MIDATV R/W 0 0
0 MDMAV R/W 0 0
Bit 15 to 4 3 Reserved SODATV
Name 0 is returned when read
Function
This indicates whether valid data has been stored in SODATREG. 1 : Valid data exists 0 : No valid data
2
SDMAV
This indicates whether valid data has been stored in SDMADATREG. 1 : Valid data exists 0 : No valid data
1
MIDATV
This indicates whether valid data has been stored in MIDATREG. 1 : Valid data exists 0 : No valid data
0
MDMAV
This indicates whether valid data has been stored in MDMADATREG. 1 : Valid data exists 0 : No valid data
This register indicates whether valid data has been stored in the SODATREG, SDMADATREG, MIDATREG, or MDMADATREG register. If data has been written directly to the SODATREG, SDMADATREG, MIDATREG, or MDMADATREG register via software, the bits in this register are not set so that 1 must be written via software. Write is used for debugging and is enabled when the AIUSEN or AIUMEN bit of the SEQREG register is set to 1. If the AIUSEN bit = 0 or AIUMEN bit = 0 in the SEQREG register, then the SODATV bit = SDMAV bit = 0 or MIDATV bit = MDMAV bit = 0.
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15.2.10 SEQREG (0x0B00 017A)
Bit Name R/W RTCRST Other resets 15 AIURST R/W 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 AIUMEN R/W 0 0
3 Reserved R 0 0
2 Reserved R 0 0
1 Reserved R 0 0
0 AIUSEN R/W 0 0
Bit 15 AIURST
Name AIU reset via software 1 : Reset 0 : Normal
Function
14 to 5 4
Reserved AIUMEN
0 is returned when read Microphone block operation and DMA enable 1 : Enable 0 : Disable
3 to 1 0
Reserved AIUSEN
0 is returned when read Speaker block operation and DMA enable 1 : Enable 0 : Disable
This register is used to enable/disable the AIU's operation.
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15.2.11 INTREG (0x0B00 017C)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 MIDLEINTR R/W 0 0 8 MSTINTR R/W 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 Reserved R 0 0
2 Reserved R 0 0
1 SIDLEINTR R/W 0 0
0 Reserved R 0 0
Bit 15 to 10 9 Reserved
Name 0 is returned when read
Function
MIDLEINTR
Microphone idle interrupt request (receive data loss). Cleared to 0 when 1 is written. 1 : Occurred 0 : Normal
8
MSTINTR
Microphone receive completion interrupt request. Cleared to 0 when 1 is written. 1 : Occurred 0 : Normal
7 to 2 1
Reserved SIDLEINTR
0 is returned when read Speaker idle interrupt request (mute). Cleared to 0 when 1 is written. 1 : Occurred 0 : Normal
0
Reserved
0 is returned when read
This register indicates occurrence of various interrupt request of the AIU. When data is received from the A/D converter, the MIDLEINTR bit is set if valid data still exists in the MIDATREG register (MIDATV bit = 1). In this case, the MIDATREG register is overwritten. The MSTINTR bit is set when data is received in the MDMADATREG register. When data is passed to the D/A converter, the SIDLEINTR bit is set if there is no valid data in the SODATREG register (SODATV bit = 0). However, this interrupt request is valid only after AIUSEN bit = 1 in the SODATREG register, after which SODATV bit = 1 in the DVALIDREG register.
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15.2.12 MCNVC_END (0x0B00 017E)
Bit Name R/W RTCRST Other resets 15 MCNVC15 R/W 0 0 14 MCNVC14 R/W 0 0 13 MCNVC13 R/W 0 0 12 MCNVC12 R/W 0 0 11 MCNVC11 R/W 1 1 10 MCNVC10 R/W 0 0 9 MCNVC9 R/W 0 0 8 MCNVC8 R/W 0 0
Bit Name R/W RTCRST Other resets
7 MCNVC7 R/W 1 1
6 MCNVC6 R/W 1 1
5 MCNVC5 R/W 0 0
4 MCNVC4 R/W 1 1
3 MCNVC3 R/W 1 1
2 MCNVC2 R/W 1 1
1 MCNVC1 R/W 0 0
0 MCNVC0 R/W 0 0
Bit 15 to 0
Name MCNVC(15:0) Microphone sample rate control.
Function
This register is used to select a conversion rate for the A/D converter. The following expression is used to calculate the value set to this register. MCNVC(15:0) = PCLK frequency/sample rate For example, if the desired conversion rate is 11.025 ksps and internal peripheral clock (PCLK) frequency is 25 MHz, the MCNVC(15:0) bits should be set to as follows; MCNVC(15:0) = 25 x 10 /11.025 x 10 = 0x08DC Caution Set this register to a value that determines the conversion rate as 50 ksps or less.
6 3
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15.3 Operation Sequence
15.3.1 Output (speaker) 1. Set conversion rate (0x0B00 016E: SCNVC(15:0) = any value) 2. Set D/A converter Vref setup time (0x0B00 0164: any value to be DVAREF(15:0)/PCLK frequency = 5 s) 3. Enable DMA after setting DMA address in DCU 4. Set D/A converter's Vref to ON (0x0B00 0168: DAENAIU = 1) 5. Wait for Vref resistor stabilization time (about 5 s) (use the RTC counter) Even if speaker power is set to ON and speaker operation is enabled (AIUSEN = 1) without waiting for Vref resistor stabilization time, speaker output starts after the period calculated with the formula below. 5 + 1/conversion rate (44.1, 22.05, 11.025, or 8) (s) In this case, however, a noise may occur when speaker power is set to ON. 6. Set speaker power ON via GPIO. 7. Enable speaker operation (0x0B00 017A: AIUSEN = 1) DMA request Receive acknowledge and DMA data from DMA 0x0B00 0178: SDMAV = SODATV = 1 Output 10-bit data (0x0B00 0166: SODAT(9:0)) to D/A converter SODATV = 0, SDMAV = 1 Send SDMADATREG data to SODATREG. SODATV = 1, SDMAV = 0 Output DMA request and store the data after the next into SDMADATREG. SODATV = 1, SDMAV = 1 Update data at each conversion timing interval (becomes SIDLEINTR = 1 when DMA delays and SODATV = 0 during conversion timing interval, and (mute) interrupt request occurs) DMA page boundary interrupt request occurs at page boundary Clear the page interrupt request to continue output. 8. Disable speaker operation (0x0B00 017A: AIUSEN = 0) 9. Set speaker power OFF via GPIO. 10. Set D/A converter's Vref to OFF (0x0B00 0168: DAENAIU = 0) 11. Disable DMA in DCU Figure 15-1. Speaker Output and AUDIOOUT Pin
AUDIOOUT <1> <2> <3> <4> <5> <6> <7> <8><9><10> <11>
VDD/2
time
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15.3.2 Input (microphone) 1. Set conversion rate (0x0B00 017E: MCNVC(15:0) = any value) 2. Set D/A converter Vref setup time (0x0B00 0164: any value to be DVAREF(15:0)/PCLK frequency = 5 s) 3. Enable DMA after setting DMA address in DCU 4. Set A/D converter's Vref to ON (0x0B00 0172: ADENAIU = 1) Microphone power can be set ON and microphone operation can be enabled (AIUMEN = 1) without waiting for Vref resistor stabilization time (about 5 s). However, in such a case, sampling starts after the period calculated with the formula below. 5 + 1/conversion rate (44.1, 22.05, 11.025, or 8) (s) 5. Set microphone power ON via GPIO. 6. Enable microphone operation (0x0B00 017A: AIUMEN = 1) Output A/D request to A/D converter Acknowledge and 10-bit conversion data are returned from A/D converter. Store data in MIDATREG. 0x0B00 0178: MDMAV = 0, MIDATV = 1 Transfer data from MIDATREG to MDMADATREG. MDMAV = 1, MIDATV = 0 MSTINTR = 1 and an interrupt request (receive complete) occurs. Issue DMA request and store MDMADATREG data to memory. MDMAV = 0, MIDATV = 0 Issue an A/D request once per conversion timing interval and receive 10-bit data (becomes MIDLEINTR = 1 when DMA delays and MIDATV = 1 during conversion timing interval, and (data loss) interrupt request occurs) DMA page boundary interrupt request occurs at page boundary Clear the page interrupt request to continue output. 7. Disable microphone operation (0x0B00 017A: AIUMEN = 0) 8. Set microphone power OFF via GPIO. 9. Set A/D converter's Vref to OFF (0x0B00 0172: ADENAIU = 0) 10. Disable DMA in DCU Figure 15-2. AUDIOIN Pin and Microphone Operation
<1> to <3> <4> <5><6> AUDIOIN
<7> <8> <9> <10>
sampling
time
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CHAPTER 16 KEYBOARD INTERFACE UNIT (KIU)
16.1 General
The Keyboard Interface Unit (KIU) provides the interface between the VR4181 and an external matrix type keyboard. This unit supports key matrix of 8 x 8. The interface to the keyboard consists of SCANOUT (3-state output) and SCANIN (input) lines. The SCANOUT lines are used to search the matrix for pressed keys. The SCANIN lines are used to sense key press events and are read after each SCANOUT line being at low level to locate the pressed key. SCANOUT and SCANIN lines are allocated by programming CompactFlash pins to support this function during the power-on. If those pins are set as for keyboard interface, CompactFlash interface cannot be used.
16.2 Functional Description
When the keyboard is idle, the SCANOUT lines are all driven to 0 volts and the SCANIN lines are pulled to VDD by external 4.7 k resistors. When any key in the matrix is pressed, at least one SCANIN input is driven as low and signals a key press event to the KIU. Once the key press event has been detected, the KIU may be programmed to generate a key down interrupt request, and to begin scanning the keyboard automatically or to wait until software enables the scan operation. Keyboard scanning is performed by sequentially driving one SCANOUT line as low while the others remain high impedance, and reading the state of the SCANIN lines and storing into keyboard data registers inside the KIU. Once the last SCANOUT line has been driven as low and the SCANIN lines read the KIU may generate a Keyboard Data Ready interrupt request to inform system software that one keyboard scan operation has been completed. The KIU repeats this scan process until no further keys have been detected or until software disables the scan operation. At this point the KIU enters to the keyboard idle state or key press wait state.
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The following table illustrates the relationship between these bits: Table 16-1. Settings of Keyboard Scan Mode
ASTOP 0 X 0 ASTART 0 X X MSTART 0 X 1 MSTOP 0 1 0 Scanning disabled Scanning stopped Manual Scan mode. Scan operation starts as soon as a setting of the MSTART bit is detected by the scan sequencer and stops when the MSTOP bit is set to 1. Manual Scan with Auto Stop mode. Scan operation starts as soon as a setting of the MSTART bit is detected by the scan sequencer and stops when no valid keyboard data has been read for STPREP(5:0) times of consecutive scan cycles. Auto Scan with Manual Stop mode. Scan operation starts as soon as a key press is detected by the scan sequencer and stops when the MSTOP bit is set to 1. Auto Scan mode. Scan operation starts as soon as a key press is detected by the scan sequencer and stops when no valid keyboard data has been read for STPREP(5:0) times of consecutive scan cycles. Operation
1
X
1
0
0
1
0
0
1
1
0
0
16.2.1 Automatic keyboard scan mode (Auto Scan mode) Automatic Scan mode is enabled through the ASTART and ASTOP bits of the KIUSCANREP register. When the ASTART bit is set to 1, keyboard scanning starts automatically following a key down interrupt request. When the ASTOP bit is set to 1, keyboard scanning stops automatically after no valid keyboard data (i.e. all SCANIN lines are high level) has been read for the number of scan cycles specified by the STPREP(5:0) bits of the KIUSCANREP register. 16.2.2 Manual keyboard scan mode (Manual Scan mode) Manual Scan mode is enabled through the MSTART and MSTOP bits of the KIUSCANREP register. Software initiates a keyboard scan operation by setting the MSTART bit to 1 and terminates keyboard scanning by setting the MSTOP bit to 1. When software sets the MSTOP bit to 1, the KIU will complete the current scan operation before disabling the scan logic. 16.2.3 Key press detection All SCANIN lines are sampled by the KIU on the rising edge of the 32.768 kHz clock. When any SCANIN line is sampled as low during a period of time from a rising edge to a falling edge of the 32.768 kHz clock, a key down interrupt request is generated. If the ASTART bit of the KIUSCANREP register is set to 1 at this time, the KIU begins scanning the keyboard.
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16.2.4 Scan operation Scan operations are controlled by the T1CNT(4:0) and T3CNT(4:0) bits of the KIUWKS register and the WINTVL(9:0) bits of the KIUWKI register. The following diagram illustrates the relationship of these register bits to the scan operation: Figure 16-1. SCANOUT Signal Output Timing
T1CNT(4:0) + 1 SCANOUT0 Hi-Z (output) Hi-Z Hi-Z
T3CNT(4:0) SCANOUT1 Hi-Z (output) Hi-Z Hi-Z
SCANOUT2 Hi-Z (output)
Hi-Z
SCANOUT3 Hi-Z (output)
Hi-Z
SCANOUT4 Hi-Z (output)
Hi-Z
SCANOUT5 Hi-Z (output)
Hi-Z
SCANOUT6 Hi-Z (output)
Hi-Z WINTVL(9:0)
SCANOUT7 Hi-Z (output)
T3CNT(4:0)
Hi-Z
The T1CNT(4:0) bits specify the keyboard settling time and is expressed in 32.768 kHz clock cycles. Following the low level of one of the SCANOUT(7:0) pins, the KIU will wait for the time set in the T1CNT(4:0) bits before reading returned data to the SCANIN(7:0) pins. Actually the SCANOUT pins will be driven as low for (T1CNT(4:0) + 1) 32.768 kHz clock cycles. The T3CNT(4:0) bits specify the delay from driving one SCANOUT pin as high impedance to driving the next SCANOUT pin as low and is also expressed in 32.768 kHz clock cycles. When the SCANOUTn pin is driven as high impedance, the KIU will wait for the time set in the T3CNT(4:0) bits before driving the SCANOUTn+1 pin as low to allow the external pull-up resistors to return the SCANINn pin as high (n = 0 to 6). The WINTVL(9:0) bits specify the interval between one scan and another in 32.768 kHz clock cycles. After the last SCANOUT pin has been driven as high impedance and a time set in the T3CNT(4:0) bits has elapsed, the KIU will wait for the time set in the WINTVL(9:0) bits before driving SCANOUT0 as low to start the next scan sequence.
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16.2.5 Reading scanned data Scanned data is read from the SCANIN(7:0) pins. When a SCANOUT pin has been driven as low and the keyboard settling time specified by the T1CNT(4:0) bits has been elapsed, the KIU latches scanned data from the SCANIN pins and stores into one of the internal key data registers. 16.2.6 Interrupts and status reporting The KIU provides scan status indication that may be polled by the CPU core and may also generate interrupt requests to request keyboard servicing. Scan status indication is provided through the SSTAT(1:0) bits of the KIUSCANS register. These bits are decoded as follows:
SSTAT1 0 0 1 1 SSTAT0 0 1 0 1 Stopped Waiting for key press Scanning (T1CNT or T3CNT) During scan interval (WINTVL) KIU scan sequencer status
The KIU generates 3 types of maskable interrupt requests. KIU interrupt pending status is reported through the KDATLOST, KDATRDY, and KEYDOWN bits of the KIUINT register. All interrupt requests generated by the KIU should be considered asynchronous and must be externally qualified with TClock. The key data lost interrupt request (KDATLOST bit) signals that a data from the SCANIN line written to the key data register corresponding to the SCANOUT0 pin before the previous data value is read by the CPU core. This interrupt source can be masked through the MSKKDATLOST bit of the MKIUINTREG register. The key data ready interrupt request (KDATRDY bit) signals one complete scan operation has been completed. This interrupt request is generated during a write of a data from the SCANIN line to the key data register corresponding to the last SCANOUT pin. This interrupt request source can be masked through the MSKKDATRDY bit of the MKIUINTREG register. The key down interrupt request (KEYDOWN bit) signals a key press event has been detected. This interrupt request is generated in synchronization with the rising edge of the 32.768 kHz clock when the keyboard interface is idle and any SCANIN pin is sampled as low during a period of time from a rising edge to a falling edge of the 32.768 kHz clock. This interrupt request source can be masked through the MSKKDOWNINT bit of the MKIUINTREG register. The MSKKDATLOST, MSKKDATRDY, and MSKKDOWNINT bits only prevent interrupt requests from being generated on the kiuintr signal (internal). These mask bits do not disable interrupt request event detection nor do they disable interrupt status reporting in the KIUINT register.
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16.3 Register Set
The KIU registers are listed below. Table 16-2. KIU Registers
Physical address 0x0B00 0180 0x0B00 0182 0x0B00 0184 0x0B00 0186 0x0B00 0188 0x0B00 018A 0x0B00 018C 0x0B00 018E 0x0B00 0190 0x0B00 0192 0x0B00 0194 0x0B00 0196 0x0B00 0198 R R R R R R R R R/W R R/W R/W R/W R/W Register symbol KIUDAT0 KIUDAT1 KIUDAT2 KIUDAT3 KIUDAT4 KIUDAT5 KIUDAT6 KIUDAT7 KIUSCANREP KIUSCANS KIUWKS KIUWKI KIUINT Function Scan line 0 keyboard data register Scan line 1 keyboard data register Scan line 2 keyboard data register Scan line 3 keyboard data register Scan line 4 keyboard data register Scan line 5 keyboard data register Scan line 6 keyboard data register Scan line 7 keyboard data register Scan control register Scan status register Key scan stable time register Key scan interval time register Interrupt register
State of interrupt requests caused by KIU is indicated and can be set in the following registers, which are included in the ICU (refer to CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) for details). Table 16-3. KIU Interrupt Registers
Physical address 0x0B00 0086 0x0B00 0092 R/W R/W R/W Register symbol KIUINTREG MKIUINTREG Function KIU interrupt indication register KIU interrupt mask register
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16.3.1 KIUDATn (0x0B00 0180 to 0x0B00 018E) Remark n = 0 to 7 KIUDAT0 (0x0B00 0180) KIUDAT1 (0x0B00 0182) KIUDAT2 (0x0B00 0184) KIUDAT3 (0x0B00 0186)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0
KIUDAT4 (0x0B00 0188) KIUDAT5 (0x0B00 018A) KIUDAT6 (0x0B00 018C) KIUDAT7 (0x0B00 018E)
13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 RETDAT7 R 0 0
6 RETDAT6 R 0 0
5 RETDAT5 R 0 0
4 RETDAT4 R 0 0
3 RETDAT3 R 0 0
2 RETDAT2 R 0 0
1 RETDAT1 R 0 0
0 RETDAT0 R 0 0
Bit 15 to 8 7 to 0 Reserved
Name 0 is returned when read Scan data 1 : Key is released 0 : Key is pressed
Function
RETDAT(7:0)
These registers reflect the state of the returned signals for the selected SCANOUT pins. Each register corresponds to one SCANOUT pin as follows:
SCANOUT pin SCANOUT7 SCANOUT6 SCANOUT5 SCANOUT4 SCANOUT3 SCANOUT2 SCANOUT1 SCANOUT0 KIUDAT register KIUDAT7 KIUDAT6 KIUDAT5 KIUDAT4 KIUDAT3 KIUDAT2 KIUDAT1 KIUDAT0
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16.3.2 KIUSCANREP (0x0B00 0190)
Bit Name R/W RTCRST Other resets 15 KEYEN R/W 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 STPREP5 R/W 0 0 8 STPREP4 R/W 0 0
Bit Name R/W RTCRST Other resets
7 STPREP3 R/W 0 0
6 STPREP2 R/W 0 0
5 STPREP1 R/W 0 0
4 STPREP0 R/W 0 0
3 MSTOP R/W 0 0
2 MSTART R/W 0 0
1 ASTOP R/W 0 0
0 ASTART R/W 0 0
Bit 15 KEYEN
Name
Function KIU enable. This bit enables a KIU operation. When this bit is set to 0, the scan sequencer and all interrupt requests are disabled. 1 : Enable 0 : Disable
14 to 10 9 to 4
Reserved STPREP(5:0)
0 is returned when read Scan sequencer stop count. These bits select the number of scan operation performed after all keys have been released (0xFF is loaded to KIUDAT registers). 111111 : 63 times : 000001 : 1 time 000000 : 64 times
3
MSTOP
Scan stop (manual mode). This bit is sampled at the end of each scan operation and causes the scan sequencer to stop scanning when set to 1. 1 : Stop 0 : Operate
2
MSTART
Manual scan start (manual mode). When this bit is set to 1, the scan sequencer starts scanning the keyboard. 1 : Start 0 : Stop
1
ASTOP
Auto scan stop (auto mode). When this bit is set to 1, the scan sequencer stops scanning automatically when all keys have been released for the number of scan operation specified by the STPREP(5:0) bits. 1 : Auto stop 0 : Manual stop
0
ASTART
Auto Scan mode enable. When this bit is set to 1, the scan sequencer starts scanning automatically following a key press event. 1 : Enable 0 : Disable
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16.3.3 KIUSCANS (0x0B00 0192)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 Reserved R 0 0
2 Reserved R 0 0
1 SSTAT1 R 0 0
0 SSTAT0 R 0 0
Bit 15 to 2 1, 0 Reserved
Name 0 is returned when read Scan sequencer status 11 : During scan interval (WINTVL) 10 : Scanning (T1CNT or T3CNT) 01 : Waiting for key press 00 : Stopped
Function
SSTAT(1:0)
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16.3.4 KIUWKS (0x0B00 0194)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 T3CNT4 R/W 0 0 13 T3CNT3 R/W 0 0 12 T3CNT2 R/W 0 0 11 T3CNT1 R/W 0 0 10 T3CNT0 R/W 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 T1CNT4 R/W 0 0
3 T1CNT3 R/W 0 0
2 T1CNT2 R/W 0 0
1 T1CNT1 R/W 0 0
0 T1CNT0 R/W 0 0
Bit 15 14 to 10 Reserved
Name 0 is returned when read
Function
T3CNT(4:0)
Scan idle time. These bit determine the wait time the scan sequencer waits following a deassertion of one SCANOUT pin before an assertion of the next SCANOUT pin. 11111 : 960 s : (T3CNT(4:0) + 1) x 30 s 00001 : 60 s 00000 : Setting prohibited
9 to 5 4 to 0
Reserved T1CNT(4:0)
0 is returned when read Scan data stabilization time. These bits determine the time the scan sequencer waits following an assertion of a SCANOUT pin before return data is read. 11111 : 960 s : (T1CNT(4:0) + 1) x 30 s 00001 : 60 s 00000 : Setting prohibited
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CHAPTER 16 KEYBOARD INTERFACE UNIT (KIU)
16.3.5 KIUWKI (0x0B00 0196)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 WINTVL9 R/W 0 0 8 WINTVL8 R/W 0 0
Bit Name R/W RTCRST Other resets
7 WINTVL7 R/W 0 0
6 WINTVL6 R/W 0 0
5 WINTVL5 R/W 0 0
4 WINTVL4 R/W 0 0
3 WINTVL3 R/W 0 0
2 WINTVL2 R/W 0 0
1 WINTVL1 R/W 0 0
0 WINTVL0 R/W 0 0
Bit 15 to 10 9 to 0 Reserved
Name 0 is returned when read
Function
WINTVL(9:0)
Scan interval time. These bits determine the time the scan sequencer waits following completion of one scan operation before starting the next scan operation. 1111111111 : 30690 s : WINTVL(9:0) x 30 s 0000000001 : 30 s 0000000000 : No wait
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16.3.6 KIUINT (0x0B00 0198)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
D7 Reserved R 0 0
D6 Reserved R 0 0
D5 Reserved R 0 0
D4 Reserved R 0 0
D3 Reserved R 0 0
D2 KDATLOST R/W 0 0
D1 KDATRDY R/W 0 0
D0 KEYDOWN R/W 0 0
Bit 15 to 3 2 Reserved
Name 0 is returned when read
Function
KDATLOST
Key data lost interrupt request. This interrupt request occurs if the KIUDAT0 register is updated with the next key data prior to being read by the CPU core. 1 : Occurred 0 : Not occurred This bit is cleared by writing 1.
1
KDATRDY
Key data ready interrupt request. This interrupt request occurs when a set of scanning is completed and all the KIUDAT registers are updated. 1 : Occurred 0 : Not occurred This bit is cleared by writing 1.
0
KEYDOWN
Key down interrupt request. This interrupt request occurs when the KIU sequencer is idle and any of the SCANIN inputs has been sampled as low level. 1 : Occurred 0 : Not occurred This bit is cleared by writing 1.
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CHAPTER 17 COMPACTFLASH CONTROLLER (ECU)
17.1 General
The VR4181 provides an ExCA-compatible controller (ECU) supporting a single CompactFlash slot. The interface for this controller is shared with that of the keyboard interface unit. To use this interface for CompactFlash control, the KEYSEL bit of the KEYEN register in the GIU must be clear to 0. Also, to use CF_BUSY# signal as an activation factor, the CompactFlash interface must be enabled during Hibernate mode by writing 1 to the CFHIBEN bit of the KEYEN register.
17.2 Register Set Summary
This section provides details of the ECU registers. Two of the ECU registers are located in the I/O addressing space. These registers, as well as the Interrupt and Configuration registers, are shown in the following table. Table 17-1. ECU Control Registers
Physical address 0x0B00 08E0 0x0B00 08E1 0x0B00 08F8 0x0B00 08FA 0x0B00 08FE R/W R/W R/W R R/W R/W Register symbol ECUINDX ECUDATA INTSTATREG INTMSKREG CFG_REG_1 Index register (I/O space) Data register (I/O space) Interrupt status register Interrupt mask register Configuration register 1 Function
The remaining ECU registers listed below are all 8-bit width and accessed through the Index register and the Data register.
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Table 17-2. ECU Registers (1/2)
Index 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E 0x001F R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W Register symbol ID_REV_REG IF_STAT_REG PWRRSETDRV ITGENCTREG CDSTCHGREG CRDSTATREG ADWINENREG IOCTRL_REG IOADSLB0REG IOADSHB0REG IOSLB0REG IOSHB0REG IOADSLB1REG IOADSHB1REG IOSLB1REG IOSHB1REG SYSMEMSL0REG MEMWID0_REG SYSMEMEL0REG MEMSEL0_REG MEMOFFL0REG MEMOFFH0REG DTGENCLREG SYSMEMSL1REG MEMWID1_REG SYSMEMEL1REG MEMSEL1_REG MEMOFFL1REG MEMOFFH1REG GLOCTRLREG VOLTSENREG Function Identification and revision register Interface status register Power and RESETDRV control register Interrupt and general control register Card status change register Card status change interrupt configuration register Address window enable register I/O control register I/O start address 0 low byte register I/O start address 0 high byte register I/O stop address 0 low byte register I/O stop address 0 high byte register I/O start address 1 low byte register I/O start address 1 high byte register I/O stop address 1 low byte register I/O stop address 1 high byte register System memory 0 mapping start address low byte register System memory 0 mapping start address high byte register System memory 0 mapping stop address low byte register System memory 0 mapping stop address high byte register Card memory 0 offset address low byte register Card memory 0 offset address high byte register Card detect and general control register System memory 1 mapping start address low byte register System memory 1 mapping start address high byte register System memory 1 mapping stop address low byte register System memory 1 mapping stop address high byte register Card memory 1 offset address low byte register Card memory 1 offset address high byte register Global control register Card voltage sense register
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Table 17-2. ECU Registers (2/2)
Index 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0028 0x0029 0x002A 0x002B 0x002C 0x002D 0x002F 0x0030 0x0031 0x0032 0x0033 0x0034 0x0035 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register symbol SYSMEMSL2REG MEMWID2_REG SYSMEMEL2REG MEMSEL2_REG MEMOFFL2REG MEMOFFH2REG SYSMEMSL3REG MEMWID3_REG SYSMEMEL3REG MEMSEL3_REG MEMOFFL3REG MEMOFFH3REG VOLTSELREG SYSMEMSL4REG MEMWID4_REG SYSMEMEL4REG MEMSEL4_REG MEMOFFL4REG MEMOFFH4REG Function System memory 2 mapping start address low byte register System memory 2 mapping start address high byte register System memory 2 mapping stop address low byte register System memory 2 mapping stop address high byte register Card memory 2 offset address low byte register Card memory 2 offset address high byte register System memory 3 mapping start address low byte register System memory 3 mapping start address high byte register System memory 3 mapping stop address low byte register System memory 3 mapping stop address high byte register Card memory 3 offset address low byte register Card memory 3 offset address high byte register Card voltage select register System memory 4 mapping start address low byte register System memory 4 mapping start address high byte register System memory 4 mapping stop address low byte register System memory 4 mapping stop address high byte register Card memory 4 offset address low byte register Card memory 4 offset address high byte register
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17.3 ECU Control Registers
17.3.1 INTSTATREG (0x0B00 08F8)
Bit Name R/W Reset 15 IRQ15 R 0 14 IRQ14 R 0 13 Reserved R 0 12 IRQ12 R 0 11 IRQ11 R 0 10 IRQ10 R 0 9 IRQ9 R 0 8 Reserved R 0
Bit Name R/W Reset
7 IRQ7 R 0
6 Reserved R 0
5 IRQ5 R 0
4 IRQ4 R 0
3 IRQ3 R 0
2 Reserved R 0
1 Reserved R 0
0 Reserved R 0
Bit 15, 14 IRQ(15:14)
Name
Function Status of interrupt request 15 and 14 (internal) 0 : Invalid 1 : Valid
13 12 to 9
Reserved IRQ(12:9)
0 is returned when read Status of interrupt request 12, 11, 10 and 9 (internal) 0 : Invalid 1 : Valid
8 7
Reserved IRQ7
0 is returned when read Status of interrupt request 7 (internal) 0 : Invalid 1 : Valid
6 5 to 3
Reserved IRQ(5:3)
0 is returned when read Status of interrupt request 5, 4 and 3 (internal) 0 : Invalid 1 : Valid
2 to 0
Reserved
0 is returned when read
Remark
A single bit corresponds to each interrupt request.
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17.3.2 INTMSKREG (0x0B00 08FA)
Bit Name R/W Reset 15 IMSK015 R/W 0 14 IMSK014 R/W 0 13 Reserved R 0 12 IMSK012 R/W 0 11 IMSK011 R/W 0 10 IMSK010 R/W 0 9 IMSK09 R/W 0 8 Reserved R 0
Bit Name R/W Reset
7 IMSK07 R/W 0
6 Reserved R 0
5 IMSK05 R/W 0
4 IMSK04 R/W 0
3 IMSK03 R/W 0
2 Reserved R 0
1 Reserved R 0
0 Reserved R 0
Bit 15, 14
Name IMSK0(15:14)
Function Mask for interrupt request 15 and 14 (internal) 0 : Unmask 1 : Mask
13 12 to 9
Reserved IMSK0(12:9)
0 is returned when read Mask for interrupt request 12, 11, 10, and 9 (internal) 0 : Unmask 1 : Mask
8 7
Reserved IMSK07
0 is returned when read Mask for interrupt request 7 (internal) 0 : Unmask 1 : Mask
6 5 to 3
Reserved IMSK0(5:3)
0 is returned when read Mask for interrupt request 5, 4 and 3 (internal) 0 : Unmask 1 : Mask
2 to 0
Reserved
0 is returned when read
Remark
A single bit corresponds to each interrupt request.
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Figure 17-1. CompactFlash Interrupt Logic
IRQSEL(3:0) (Index 0x03) IRQ3 IRQ4 IREQ (CF_BUSY#) DMUX : : IRQ15 INTSTATREG (0x0B00 08F8) IRQ3 IRQ3 IRQ4 : : IRQ15 IRQ4 : : IRQ15 AND/ OR ecuint (to ICU)
CDSTCHGREG (Index 0x04) BATDEAD/STSCHG# (CF_STSCHG#) CD1#, CD2#/ SWCDINT bit RDY/BSY# (CF_BUSY#) Status change interrupt
SIRQ(3:0) (Index 0x05) IRQ3 IRQ4 : : IRQ15
OR
DMUX
INTMSKREG (0x0B00 08FA) IMSK3 IMSK4 : : IMSK15
Remark
All IRQ signals are ORed together to generate ecuint after ANDed with IMSK0n bits in the INTMSKREG register (n = 0 to 15).
17.3.3 CFG_REG_1 (0x0B00 08FE)
Bit Name R/W Reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 Reserved R 0
Bit Name R/W Reset
7 Reserved R 0
6 Reserved R 0
5 Reserved R 0
4 Reserved R 0
3 Reserved R 0
2 Reserved R 0
1 Reserved R 0
0 WSE R/W 1
Bit 15 to 1 0 Reserved WSE
Name 0 is returned when read
Function
Internal ISA cycle 1 wait state insertion enable. This bit controls wait insertion when accessing the ECU registers. Write 1 to this bit when write. 1 : Enable
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17.4 ECU Registers
17.4.1 ID_REV_REG (Index: 0x00)
Bit Name R/W Reset 7 IFTYP1 R 1 6 IFTYP0 R 0 5 Reserved R 0 4 Reserved R 0 3 REV3 R 0 2 REV2 R 0 1 REV1 R 1 0 REV0 R 1
Bit 7, 6 IFTYP(1:0)
Name
Function PCSC interface type These bits indicate 10 to reflect that both memory and I/O cards are supported. 0 is returned when read Revision level. 0011 is always displayed.
5, 4 3 to 0
Reserved REV(3:0)
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17.4.2 IF_STAT_REG (Index: 0x01)
Bit Name R/W Reset 7 Reserved R 1 6 PWRON R 0 5 RDY/BSY R Undefined 4 WP R Undefined 3 CD2 R 1 2 CD1 R 1 1 Reserved R 0 0 BVD1 R Undefined
Bit 7 6 Reserved PWRON
Name 1 is returned when read CompactFlash card power status 0 : Off 1 : On
Function
5
RDY/BSY
CompactFlash card ready/busy status. This bit indicates the current status of RDY/BSY# (CF_BUSY#) signal from a CompactFlash card. 0 : Busy 1 : Ready
4
WP
Memory write protect switch status. This bit indicates the current status of WP (CF_IOIS16#) signal from a CompactFlash card. 0 : Off 1 : On
3, 2
CD(2:1)
Complement of the values of CD1# and CD2# 11: Active (low level) 00 : Inactive (high level) Values other than above are not displayed.
Note
1 0
Reserved BVD1
0 is returned when read This bit indicates the current status of STSCHG# (CF_STSCHG#) signal from a CompactFlash card.
Note The card detect pins, CD1# and CD2#, alternate with GPIO pins. When the GPIO pins are not programmed as card detect input, the CD(2:1) bits of this register always return 11 (active). In this way, the CompactFlash interface can be used without the card detect pins. When the GPIO pins are programmed as card detect, the CD(2:1) bits are reflected in actual status of the CD1# and CD2# pins.
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17.4.3 PWRRSETDRV (Index: 0x02)
Bit Name R/W Reset 7 OE R/W 0 6 Reserved R 0 5 Reserved R 1 4 PWREN R/W 0 3 Reserved R 0 2 Reserved R 0 1 Reserved R/W 0 0 Reserved R 0
Bit 7 OE
Name
Function Output enable. If this bit is cleared to 0, the CompactFlash interface outputs from the VR4181 are driven to high impedance state and the CF_DEN# and CF_AEN# outputs are driven as high. Caution This bit should not be set until this register has been written to set the CompactFlash card power enable.
6 5 4
Reserved Reserved PWREN
0 is returned when read 1 is returned when read Card power enable 0 : Disabled (Vcc is 0 V) 1 : Enabled. Voltage selected in the VOLTSELREG register (0x2F) is applied. The power to the socked is turned on when a card is inserted and off when removed. Caution The VR4181 supports cards with the card voltage of 3.3 V only. Do not set this bit to 1 unless the contents of the VOTSELREG register are 0x01.
3, 2 1 0
Reserved Reserved Reserved
0 is returned when read Write 0 when write. 0 is returned when read. 0 is returned when read
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17.4.4 ITGENCTREG (Index: 0x03)
Bit Name R/W Reset 7 RI_EN R/W 0 6 CRDRST R/W 0 5 CRDTYP R/W 0 4 Reserved R 0 3 IRQSEL3 R/W 0 2 IRQSEL2 R/W 0 1 IRQSEL1 R/W 1 0 IRQSEL0 R/W 1
Bit 7 RI_EN
Name
Function Ring indicate enable. This bit is used to switch the function of the STSCHG#/RI# signal from the I/O card. The ring indicator function cannot be used in the VR4181 so that 0 must be written to this bit. 0 : Used as the STSCHG#. The current status of the signal is read from the IF_STAT_REG register if this signal is configures as a source for the card status change interrupt. 1 : Used as the RI# For memory PC Cards, this bit has no function.
6
CRDRST
Card reset. This bit is for a software reset to the PC Card to which the status of the CF_RESET signal is set. 0 : Active The CF_RESET signal will be active until this bit is set to 1. 1 : Inactive
5
CRDTYP
Card type 0 : Memory card 1 : I/O card
4 3 to 0
Reserved IRQSEL(3:0)
0 is returned when read Interrupt request steering for the I/O card IREQ (CF_BUSY#) signal 0000 : IRQ is not used 0001 : RFU 0010 : RFU 0011 : IRQ3 is used 0100 : IRQ4 is used 0101 : IRQ5 is used 0110 : RFU 0111 : IRQ7 is used 1000 : RFU 1001 : IRQ9 is used 1010 : IRQ10 is used 1011 : IRQ11 is used 1100 : IRQ12 is used 1101 : RFU 1110 : IRQ14 is used 1111 : IRQ15 is used
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17.4.5 CDSTCHGREG (Index: 0x04)
Bit Name R/W Reset 7 Reserved R 0 6 Reserved R 0 5 Reserved R 0 4 Reserved R 0 3 CD_CHG R/W 0 2 RDY_CHG R/W 0 1 Reserved R 0 0 BAT_DEAD R/W 0
Bit 7 to 4 3 Reserved CD_CHG
Name 0 is returned when read
Function
Card detect (CD1# and CD2# signals) status change 0 : Not changed 1 : Changed
2
RDY_CHG
Ready (CF_BUSY# signal) change 0 : No change or I/O card installed 1 : A low-to-high change has been detected indicating that the memory card is ready to accept a new data transfer
1 0
Reserved BAT_DEAD
0 is returned when read Battery not usable or status change detection (CF_STSCHG# signal status) 0 : For memory cards, battery is good. For I/O cards, the RI_EN bit of the ITGENCTREG register is set to 1, or the CF_STSCHG# signal is at high level. 1 : For memory cards, a battery dead condition has been detected. For I/O cards, the RI_EN bit of the ITGENCTREG register is cleared to 0 and the CF_STSCHG# signal is at low level. When this bit is set to 1, the system software then has to read the status change register in the I/O card to determine the cause of STSCHG. Caution CompactFlash cards do not support the BVD (battery status detection) signal so that the BVD2/SPKR signal of the ECU is internally fixed to low level.
This register indicates the source of the card status change interrupt request. Each source can be enabled to generate this interrupt request by setting the corresponding bit in the CRDSTATREG register. The bits in this register become 0 if their corresponding enable bits are cleared to 0. If the EXWRBK bit is set to 1 in the GLOCTRLREG register, sources for the card status change interrupt request is acknowledged when 1 is set to the CD_CHG bit in the CDSTCHGREG register though it has been already set to 1. Once acknowledged, the CD_CHG bit is cleared to 0. The interrupt request signal caused by the card status change, if any of the IRQ lines is enabled, remains active until all the bits in this register become 0. If the EXWRBK bit is not set to 1, the card status change interrupt request, when any of the IRQ lines are enabled, remains active until this register is read. In this mode, reading this register resets all status bits to 0, which has been set to 1.
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17.4.6 CRDSTATREG (Index: 0x05)
Bit Name R/W Reset 7 SIRQS3 R/W 0 6 SIRQS2 R/W 0 5 SIRQS1 R/W 0 4 SIRQS0 R/W 0 3 CD_EN R/W 0 2 RDY_EN R/W 0 1 Reserved R 0 0 BDEAD_EN R/W 0
Bit 7 to 4 SIRQS(3:0)
Name
Function Interrupt request steering for the I/O card STSCHG# (CF_BUSY#) signal. 0000 : IRQ is not used 0001 : RFU 0010 : RFU 0011 : IRQ3 is used 0100 : IRQ4 is used 0101 : IRQ5 is used 0110 : RFU 0111 : IRQ7 is used 1000 : RFU 1001 : IRQ9 is used 1010 : IRQ10 is used 1011 : IRQ11 is used 1100 : IRQ12 is used 1101 : RFU 1110 : IRQ14 is used 1111 : IRQ15 is used
3
CD_EN
Card detect enable. Enables a card status change interrupt request when a change has been detected on the CD1# or CD2# signals. 0 : Disable 1 : Enable
2
RDY_EN
Ready enable. Enables a card status change interrupt request when a transition has been detected on the CF_BUSY# signal. 0 : Disable 1 : Enable
1 0
Reserved BDEAD_EN
0 is returned when read Battery not usable or status change interrupt request enable. Enables a card status change interrupt request when a change has been detected on the CF_STSCHG# signal (battery unusable status for memory cards or status change detection for I/O cards). 0 : Disable 1 : Enable For I/O cards, the RI_EN bit of the ITGENCTREG register must be cleared to 0 in advance when using the interrupt request via the CF_STSCHG# signal.
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17.4.7 ADWINENREG (Index: 0x06)
Bit Name R/W Reset 7 IOWEN1 R/W 0 6 IOWEN0 R/W 0 5 Reserved R 0 4 MWEN4 R/W 0 3 MWEN3 R/W 0 2 MWEN2 R/W 0 1 MWEN1 R/W 0 0 MWEN0 R/W 0
Bit 7, 6
Name IOWEN(1:0)
Function I/O window enables. Generates the card enable signals to the card when an I/O access occurs within the corresponding I/O address window. 0 : Does not generate 1 : Generates I/O addresses are output from the system bus directly to the card. Caution The start and stop address register pairs must be set to values for the window to be used before setting these bits to 1.
5 4 to 0
Reserved MWEN(4:0)
0 is returned when read Memory window enables. Generates the card enable signals to the card when a memory access occurs within the corresponding memory address window. 0 : Does not generate 1 : Generates When the system address is within the window, the computed address is output to the card. Caution The start, stop, and offset address register pairs must be set to values for the window to be used before setting these bits to 1.
Remark
A single bit corresponds to each window.
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17.4.8 IOCTRL_REG (Index: 0x07)
Bit Name 7 IO1WT 6 W1_IOWS 5 IO1_CS16 MD R/W 0 4 IO1DSZ 3 IO0WT 2 W0_IOWS 1 IO0_CS16 MD R/W 0 0 IO0DSZ
R/W Reset
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
Bit 7 IO1WT
Name
Function I/O window 1 wait addition in 16-bit accesses 0 : No additional wait state 1 : Adds 1 wait state
6
W1_IOWS
I/O window 1 wait addition in 8-bit accesses 0 : No additional wait state 1 : Adds 1 wait state
5
IO1_CS16MD
I/O window 1 IOCS16 source 0 : Value of the IO1DSZ bit 1 : CF_IOIS16# signal from the card
4
IO1DSZ
I/O window 1 access data size 0 : 8 bits 1 : 16 bits This bit has no function when the IO1_CS16MD bit is set to 1.
3
IO0WT
I/O window 0 wait addition in 16-bit accesses 0 : Without additional wait state 1 : Adds 1 wait state
2
W0_IOWS
I/O window 0 wait addition in 8-bit accesses 0 : No additional wait state 1 : Adds 1 wait state
1
IO0_CS16MD
I/O window 0 IOCS16 source 0 : Value of the IO0DSZ bit 1 : CF_IOIS16# signal from the card
0
IO0DSZ
I/O window 0 access data size 0 : 8 bits 1 : 16 bits This bit has no function when the IO0_CS16MD bit is set to 1.
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17.4.9 IOADSLBnREG (Index: 0x08, 0x0C) Remark n = 0, 1 IOADSLB0REG (0x08): for Window 0 IOADSLB1REG (0x0C): for Window 1
Bit Name R/W Reset 7 STARTA7 R/W 0 6 STARTA6 R/W 0 5 STARTA5 R/W 0 4 STARTA4 R/W 0 3 STARTA3 R/W 0 2 STARTA2 R/W 0 1 STARTA1 R/W 0 0 STARTA0 R/W 0
Bit 7 to 0
Name STARTA(7:0) I/O window start address bits 7 to 0
Function
Low-order address bits used to determine the start address of an I/O address window. Minimum 1 byte can be specified for the I/O address window. 17.4.10 IOADSHBnREG (Index: 0x09, 0x0D) Remark n = 0, 1 IOADSHB0REG (0x09): for Window 0 IOADSHB1REG (0x0D): for Window 1
Bit Name R/W Reset 7 STARTA15 R/W 0 6 STARTA14 R/W 0 5 STARTA13 R/W 0 4 STARTA12 R/W 0 3 STARTA11 R/W 0 2 STARTA10 R/W 0 1 STARTA9 R/W 0 0 STARTA8 R/W 0
Bit 7 to 0
Name STARTA(15:8) I/O window start address bits 15 to 8
Function
High-order address bits used to determine the start address of an I/O address window. Remark Address bits 25 to 16 of an I/O window address are fixed to 0. Therefore, an I/O window is always mapped to the address space between 0x1400 0000 and 0x1400 FFFF, which is the first 64 KB of the ISA-IO space.
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17.4.11 IOSLBnREG (Index: 0x0A, 0x0E) Remark n = 0, 1 IOSLB0REG (0x0A): for Window 0 IOSLB1REG (0x0E): for Window 1
Bit Name R/W Reset 7 STOPA7 R/W 0 6 STOPA6 R/W 0 5 STOPA5 R/W 0 4 STOPA4 R/W 0 3 STOPA3 R/W 0 2 STOPA2 R/W 0 1 STOPA1 R/W 0 0 STOPA0 R/W 0
Bit 7 to 0
Name STOPA(7:0) I/O window stop address bits 7 to 0
Function
Low-order address bits used to determine the stop address of an I/O address window. 17.4.12 IOSHBnREG (Index: 0x0B, 0x0F) Remark n = 0, 1 IOSHB0REG (0x0B): for Window 0 IOSHB1REG (0x0F): for Window 1
Bit Name R/W Reset 7 STOPA15 R/W 0 6 STOPA14 R/W 0 5 STOPA13 R/W 0 4 STOPA12 R/W 0 3 STOPA11 R/W 0 2 STOPA10 R/W 0 1 STOPA9 R/W 0 0 STOPA8 R/W 0
Bit 7 to 0
Name STOPA(15:8) I/O window stop address bits 15 to 8
Function
High-order address bits used to determine the stop address of an I/O address window. Remark Address bits 25 to 16 of an I/O window address are fixed to 0. Therefore, an I/O window is always mapped to the address space between 0x1400 0000 and 0x1400 FFFF, which is the first 64 KB of the ISA-IO space.
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17.4.13 SYSMEMSLnREG (Index: 0x10, 0x18, 0x20, 0x28, 0x30) Remark n = 0 to 4 SYSMEMSL0REG (0x10): for Window 0 SYSMEMSL1REG (0x18): for Window 1 SYSMEMSL2REG (0x20): for Window 2
Bit Name 7 MWSTART A19 R/W 0 6 MWSTART A18 R/W 0 5 MWSTART A17 R/W 0 4 MWSTART A16 R/W 0 3 MWSTART A15 R/W 0 2 MWSTART A14 R/W 0 1 MWSTART A13 R/W 0 0 MWSTART A12 R/W 0
SYSMEMSL3REG (0x28): for Window 3 SYSMEMSL4REG (0x30): for Window 4
R/W Reset
Bit 7 to 0
Name MWSTARTA(19:12)
Function Memory window start address bits 19 to 12
Low-order address bits used to determine the start address of a memory address window. Minimum 4 KB can be specified for memory address window. 17.4.14 MEMWIDn_REG (Index: 0x11, 0x19, 0x21, 0x29, 0x31) Remark n = 0 to 4 MEMWID0_REG (0x11): for Window 0 MEMWID1_REG (0x19): for Window 1 MEMWID2_REG (0x21): for Window 2
Bit Name 7 DWIDTH 6 ZWSEN 5 MWSTART A25 R/W 0 4 MWSTART A24 R\W 0 3 MWSTART A23 R/W 0 2 MWSTART A22 R/W 0 1 MWSTART A21 R/W 0 0 MWSTART A20 R/W 0
MEMWID3_REG (0x29): for Window 3 MEMWID4_REG (0x31): for Window 4
R/W Reset
R/W 0
R/W 0
Bit 7 DWIDTH
Name Memory window data width 0 : 8 bits 1 : 16 bits
Function
6
ZWSEN
Zero wait state enable. This bit is used to set whether the zero wait state is requested to the ISA Bridge in memory accesses. 0 : Does not request 1 : Requests
5 to 0
MWSTARTA(25:20)
Memory window start address bits 25 to 20
This register is used to set the memory window data width, zero wait state enable, and high-order address bits used to determine the start address of a memory address window.
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17.4.15 SYSMEMELnREG (Index: 0x12, 0x1A, 0x22, 0x2A, 0x32) Remark n = 0 to 4 SYSMEMEL0REG (0x12): for Window 0 SYSMEMEL1REG (0x1A): for Window 1 SYSMEMEL2REG (0x22): for Window 2
Bit Name 7 MWSTOPA 19 R/W 0 6 MWSTOPA 18 R/W 0 5 MWSTOPA 17 R/W 0 4 MWSTOPA 16 R/W 0 3 MWSTOPA 15 R/W 0 2 MWSTOPA 14 R/W 0 1 MWSTOPA 13 R/W 0 0 MWSTOPA 12 R/W 0
SYSMEMEL3REG (0x2A): for Window 3 SYSMEMEL4REG (0x32): for Window 4
R/W Reset
Bit 7 to 0
Name MWSTOPA(19:12)
Function Memory window stop address bits 19 to 12
Low-order address bits used to determine the stop address of a memory address window. 17.4.16 MEMSELn_REG (Index: 0x13, 0x1B, 0x23, 0x2B, 0x33) Remark n = 0 to 4 MEMSEL0_REG (0x13): for Window 0 MEMSEL1_REG (0x1B): for Window 1 MEMSEL2_REG (0x23): for Window 2
Bit Name 7 M16W1 6 M16W0 5 MWSTOPA 25 R/W 0 4 MWSTOPA 24 R/W 0 3 MWSTOPA 23 R/W 0 2 MWSTOPA 22 R/W 0 1 MWSTOPA 21 R/W 0 0 MWSTOPA 20 R/W 0
MEMSEL3_REG (0x2B): for Window 3 MEMSEL4_REG (0x33): for Window 4
R/W Reset
R/W 0
R/W 0
Bit 7, 6 M16W(1:0)
Name
Function Memory window wait state select for 16-bit accesses 00 : No additional wait state 01 : 2 additional wait states 10 : 3 additional wait states 11 : 4 additional wait states
5 to 0
MWSTOPA(25:20)
Memory window stop address bits 25 to 20
The ECU automatically inserts wait states when memory windows are accessed in 16-bit width.
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17.4.17 MEMOFFLnREG (Index: 0x14, 0x1C, 0x24, 0x2C, 0x34) Remark n = 0 to 4 MEMOFFL0REG (0x14): for Window 0 MEMOFFL1REG (0x1C): for Window 1 MEMOFFL2REG (0x24): for Window 2
Bit Name 7 OFFSETA 19 R/W 0 6 OFFSETA 18 R/W 0 5 OFFSETA 17 R/W 0 4 OFFSETA 16 R/W 0 3 OFFSETA 15 R/W 0 2 OFFSETA 14 R/W 0 1 OFFSETA 13 R/W 0 0 OFFSETA 12 R/W 0
MEMOFFL3REG (0x2C): for Window 3 MEMOFFL4REG (0x34): for Window 4
R/W Reset
Bit 7 to 0
Name OFFSETA(19:12)
Function Card memory offset address bits 19 to 12
This register is defined to maintain compatibility with the ExCA. Settings in this register have no meaning in the VR4181. 17.4.18 MEMOFFHnREG (Index: 0x15, 0x1D, 0x25, 0x2D, 0x35) Remark n = 0 to 4 MEMOFFH0REG (0x15): for Window 0 MEMOFFH1REG (0x1D): for Window 1 MEMOFFH2REG (0x25): for Window 2
Bit Name 7 WP 6 REG 5 OFFSETA 25 R/W 0 4 OFFSETA 24 R/W 0 3 OFFSETA 23 R/W 0 2 OFFSETA 22 R/W 0 1 OFFSETA 21 R/W 0 0 OFFSETA 20 R/W 0
MEMOFFH3REG (0x2D): for Window 3 MEMOFFH4REG (0x35): for Window 4
R/W Reset
R/W 0
R/W 0
Bit 7 WP
Name
Function Write protect to the card through a memory window 0 : Write operation allowed 1 : Write operation prohibited
6
REG
REG# (CF_REG#) signal active of the CompactFlash. This bit is used to set which memory is to be used on accesses to the CompactFlash card. 0 : Common memory 1 : Attribute memory
5 to 0
OFFSETA(25:20)
Card memory offset address bits 25 to 20. Remark This is defined to maintain compatibility with the ExCA. Settings in these bits have no meaning in the VR4181.
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17.4.19 DTGENCLREG (Index: 0x16)
Bit Name R/W Reset 7 Reserved R 0 6 Reserved R 0 5 SWCDINT W 0 4 CDRSMEN R/W 0 3 Reserved R 0 2 Reserved R 0 1 CFGRSTEN R/W 0 0 DLY16INH R/W 0
Bit 7, 6 5 Reserved SWCDINT
Name 0 is returned when read
Function
Software card detect interrupt request 1 : Generates interrupt request This bit is valid when the CD_EN bit is set to 1 in the CRDSTATREG register. 0 is returned when read.
4
CDRSMEN
Card detect resume enable 1 : Enables notification of change on CD1# and CD2# inputs This bit is valid when the CD_EN bit is set to 1 in the CRDSTATREG register. 0 is returned when read.
3, 2 1
Reserved CFGRSTEN
0 is returned when read Configuration reset enable 1 : Enables initializing registers on high level of both CD1# and CD2# inputs The registers involved are all I/O registers, all memory registers, ITGENCTREG register, and ADWINENREG register.
0
DLY16INH
16-bit memory delay prohibit. This bit is used to set whether the falling edge of the WE# and OE# (CF_WE# and CF_OE#) signals of the CompactFlash is delayed in synchronization with SYSCLK when a memory window is set to be 16 bit in the DWIDTH bit of the MEMWIDn_REG register. 0 : Delayed 1 : Not delayed
The functionality and acknowledgment of this software interrupt request operate in the same way as those of the hardware-generated interrupt requests. The functionality and acknowledgement of the hardware card detect or card status change interrupt request are not affected by the setting of the SWCDINT bit. If card detect or card status change is signaled through the CD1# and CD2# inputs, a hardware card detect or card status change interrupt request is generated. When the CDRSMEN bit is set to 1, the RIO# signal (internal) goes from high level to low and the CD_CHG bit in the CDSTCHGREG register is set to 1. The RIO# signal remains low until either a read or a write of 1 to the CD_CHG bit (acknowledge cycle), which causes the CD_CHG bit to be reset to 0 and the RIO# signal to go from low level to high. If the card status change is routed to any of the IRQ signals, the setting of this bit to 1 prevents the IRQ signal from going active as a result of a hardware card detect status change. Once the software detects a card detect status change interrupt request from the RIO# signal by reading the CDSTCHGREG register, it must issue a software card detect change interrupt request so that the card detect change condition generates an active interrupt request on the IRQ signal.
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17.4.20 GLOCTRLREG (Index: 0x1E)
Bit Name R/W Reset 7 Reserved R 0 6 Reserved R 0 5 Reserved R 0 4 Reserved R 0 3 Reserved R 0 2 EXWRBK R/W 0 1 Reserved R 0 0 Reserved R 0
Bit 7 to 3 2 Reserved EXWRBK
Name 0 is returned when read
Function
Card status change interrupt request acknowledgement. 0 : Reading of the CDSTCHGREG register Each bit of the register is cleared after read. 1 : Writing 1 to the CDSTCHGREG register Each bit of the register is cleared after write of 1.
1, 0
Reserved
0 is returned when read
17.4.21 VOLTSENREG (Index: 0x1F)
Bit Name R/W Reset 7 Reserved R 0 6 Reserved R 0 5 Reserved R 0 4 Reserved R 0 3 Reserved R 0 2 Reserved R 0 1 VS2 R 1 0 VS1 R 0
Bit 7 to 2 1, 0 Reserved VS(2:1)
Name 0 is returned when read
Function
Voltage sense status These bits are read-only and hardwired to 10 binary since the VR4181 has no voltage sense pins.
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17.4.22 VOLTSELREG (Index: 0x2F)
Bit Name R/W Reset 7 Reserved R 0 6 Reserved R 0 5 Reserved R 0 4 Reserved R 0 3 Reserved R 0 2 Reserved R 0 1 VCCEN1 R/W 1 0 VCCEN0 R/W 0
Bit 7 to 2 1, 0 Reserved
Name 0 is returned when read Card connection status 01 : 3.3 V card connected 10 : No card connected
Function
VCCEN(1:0)
Caution Do not perform any write to this bit.
If the PWREN bit of the PWRRSETDRV register is set to 1 when the VCCEN(1:0) bits are 01, the CF_VCCEN# signal becomes active. Remark The VR4181 supports cards with the card voltage of 3.3 V only.
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CHAPTER 17 COMPACTFLASH CONTROLLER (ECU)
17.5 Memory Mapping of CompactFlash Card
(1) Memory window In the VR4181, memory windows can be placed at any address in the ISA memory space. The start address of a memory window is output without modification to the VR4181's ADD pins. However, spaces used for programmable chip select, LCD chip select, etc. must not be specified as a memory window. The CompactFlash memory space is 2 KB and the minimum memory window size is 4 KB. Accordingly, when using CompactFlash with the VR4181, the card's entire memory space is mapped to a single memory window. Mapping starts from the LSB. The remaining part of the memory window becomes a mirror area occupying the lower 2 KB. Figure 17-2. Mapping of CompactFlash Memory Space
VR4181 ISA memory space (internal) (64 MB) 0x13FF FFFF
VR4181 Space specified via ADD pins (4 MB) 0x3F FFFF
CompactFlash card Common memory space Attribute memory space (2 KB) 0x7FF
0x1sss s000 Memory window m 0x1rrr r000 0x1qqq q000 Memory window n 0x1ppp p000 Memory window n Memory window m
0x0000 0000
0x00 0000
0x000
Remark
m, n = 0 to 4 p, q, r, s = don't care
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(2) I/O window In the VR4181, the I/O window can be mapped to any address within the external ISA I/O space's lower 64 KB. The start address of a window is output without modification to the VR4181's ADD pins. When using the CompactFlash card, do not map a space for programmable chip select or another external device to the lower 64 KB within external ISA I/O space where I/O windows are assigned. Figure 17-3. Mapping of CompactFlash I/O Space
VR4181 ISA I/O space (internal) (64 MB) 0x17FF FFFF
VR4181 Space specified via ADD pins (4 MB) 0x3F FFFF
0x1401 0000
0x01 0000 0x7FF
CompactFlash card I/O space (2 KB)
I/O window m
I/O window m
I/O window m
I/O window n 0x1400 0000 0x00 0000
I/O window n 0x000
I/O window n
Remark
m, n = 0 or 1
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17.6 Controlling Bus When CompactFlash Card Is Used
Access to the CompactFlash card is made via the ISA bridge. The address, data, and command signals operate based on external ISA cycles. The operations of the signals that control the bus size and wait state (MEMCS16#, IOCS16#, and IORDY) can be set in the ECU. 17.6.1 Controlling bus size When the memory window is accessed, the data bus width is set in the DWIDTH bit of the MEMWIDn_REG register (n = 0 to 4). This setting is output from the ECU to the ISA bridge as the source of the MEMCS16# signal. When the I/O window is accessed, the source of the data width is selected from the CF_IOIS16# signal or IOnDSZ bit (n = 0 or 1) via the IOn_CS16MD bit (n = 0 or 1) of the IOCTRL_REG register. If the CF_IOIS16# signal is selected, its status is output from the ECU to the ISA bridge as the source of the IOCS16# signal. If the IOnDSZ bit is selected, the inverted setting of the IOnDSZ bit is output. 17.6.2 Controlling wait The number of wait states of the external ISA cycle can be selected from four types by using the MEMWS(1:0) and IOWS(1:0) bits of the XISACTL register of the ISA bridge, regardless of whether the memory or I/O is accessed. In addition, the ECU deasserts the IORDY signal and extends the bus cycle if the CF_WAIT# signal from the CompactFlash card is asserted. Additional wait states can be controlled by ECU settings. (1) Wait when memory window is accessed The zero wait state can be enabled or disabled via the ZWSEN bit of the MEMWIDn_REG register (n = 0 to 4). (a) If zero wait state is enabled A wait state is not added regardless of the bus size. Therefore, wait states are inserted only during the period set in the MEMWS(1:0) bits of the XISACTL register. (b) If zero wait state is disabled The number of wait states selected in the M16W(1:0) bits of the MEMSELn_REG register (n = 0 to 4) is added in the 16-bit access mode. In the 8-bit access mode, a 4 SYSCLK-cycle wait is added. (2) Wait when I/O window is accessed (a) 16-bit access A 2 SYSCLK-cycle wait is added if the IOnWT bit of the IOCTRL_REG register (n = 0 or 1) is set to 1. A 1 SYSCLK-cycle wait is added if the IOnWT bit of the IOCTRL_REG register (n = 0 or 1) is cleared to 0. (b) 8-bit access A 4 SYSCLK-cycle wait is added if the Wn_IOWS bit of the IOCTRL_REG register (n = 0 or 1) is set to 1. A 3 SYSCLK-cycle wait is added if the Wn_IOWS bit of the IOCTRL_REG register (n = 0 or 1) is cleared to 0.
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CHAPTER 18 LED CONTROL UNIT (LED)
18.1 General
This unit switches ON and OFF of LEDs at a regular interval. The interval can be set via software.
18.2 Register Set
The LED registers are listed below. Table 18-1. LED Registers
Physical address 0x0B00 0240 0x0B00 0242 0x0B00 0248 0x0B00 024A 0x0B00 024C R/W R/W R/W R/W R/W R/W Register symbol LEDHTSREG LEDLTSREG LEDCNTREG LEDASTCREG LEDINTREG Function LED ON time set register LED OFF time set register LED control register LED auto stop time setting register LED interrupt register
These registers are described in detail below.
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18.2.1 LEDHTSREG (0x0B00 0240)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 HTS4 R/W 1 Note
3 HTS3 R/W 0 Note
2 HTS2 R/W 0 Note
1 HTS1 R/W 0 Note
0 HTS0 R/W 0 Note
Bit 15 to 5 4 to 0 Reserved HTS(4:0)
Name 0 is returned when read LED ON time setting 11111 : 1.9375 seconds : 10000 : 1 second : 01000 : 0.5 seconds : 00100 : 0.25 seconds : 00010 : 0.125 seconds 00001 : 0.0625 seconds 00000 : Prohibited
Function
Note A value before reset is retained. This register is used to set the LED's ON time (high level width of LEDOUT). The ON time ranges from 0.0625 to 1.9375 seconds and can be set in 0.0625 second units. The initial setting is 1 second. This register must not be changed once the LEDENABLE bit of the LEDCNTREG register has been set to 1. The operation is not guaranteed if a change is made after that point.
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18.2.2 LEDLTSREG (0x0B00 0242)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 LTS6 R/W 0 Note
5 LTS5 R/W 1 Note
4 LTS4 R/W 0 Note
3 LTS3 R/W 0 Note
2 LTS2 R/W 0 Note
1 LTS1 R/W 0 Note
0 LTS0 R/W 0 Note
Bit 15 to 7 6 to 0 Reserved LTS(6:0)
Name 0 is returned when read LED OFF time setting 1111111 : 7.9375 seconds : 1000000 : 4 seconds : 0100000 : 2 seconds : 0010000 : 1 second : 0001000 : 0.5 seconds : 0000100 : 0.25 seconds : 0000010 : 0.125 seconds 0000001 : 0.0625 seconds 0000000 : Prohibited
Function
Note A value before reset is retained. This register is used to set the LED's OFF time (low level width of LEDOUT). The OFF time ranges from 0.0625 to 7.9375 seconds and can be set in 0.0625 second units. The initial setting is 2 seconds. This register must not be changed once the LEDENABLE bit of LEDCNTREG register has been set to 1. The operation is not guaranteed if a change is made after that point.
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18.2.3 LEDCNTREG (0x0B00 0248)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 Reserved R 0 0
2 LEDHLB R 0 0
1 LEDSTOP R/W 1 Note
0 LEDENABLE R/W 0 Note
Bit 15 to 3 2 Reserved LEDHLB
Name 0 is returned when read LED status indication 1 : ON 0 : OFF
Function
1
LEDSTOP
LED blink auto stop setting 1 : Automatically stops 0 : Does not stop automatically
0
LEDENABLE
LED blink setting 1 : Blinks 0 : Does not blink
Note A value before reset is retained. This register is used to make various LED settings. Caution When setting LED to blink, make sure that a value other than zero has already been set to the LEDHTSREG, LEDLTSREG, and LEDASTCREG registers. The operation is not guaranteed if zero is set to these registers.
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18.2.4 LEDASTCREG (0x0B00 024A)
Bit Name R/W RTCRST Other resets 15 ASTC15 R/W 0 0 14 ASTC14 R/W 0 0 13 ASTC13 R/W 0 0 12 ASTC12 R/W 0 0 11 ASTC11 R/W 0 0 10 ASTC10 R/W 1 1 9 ASTC9 R/W 0 0 8 ASTC8 R/W 0 0
Bit Name R/W RTCRST Other resets
7 ASTC7 R/W 1 1
6 ASTC6 R/W 0 0
5 ASTC5 R/W 1 1
4 ASTC4 R/W 1 1
3 ASTC3 R/W 0 0
2 ASTC2 R/W 0 0
1 ASTC1 R/W 0 0
0 ASTC0 R/W 0 0
Bit 15 to 0
Name ASTC(15:0) LED auto stop time count
Function
This register is used to set the number of ON/OFF times prior to automatic stopping of LED blink. The set value is read on a read. The initial setting is 1,200 times of ON/OFF pairs (i.e. one hour in which each time includes one second of ON time and two seconds of OFF time). The pair of operations in which the LED is switched ON once and OFF once is counted as "1" by this counter. The counter counts down from the set value and an LEDINT interrupt request occurs when it reaches zero. Caution Setting a zero to this register is prohibited. The operation is not guaranteed if zero is set to this register.
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18.2.5 LEDINTREG (0x0B00 024C)
Bit Name R/W RTCRST Other resets 15 Reserved R 0 0 14 Reserved R 0 0 13 Reserved R 0 0 12 Reserved R 0 0 11 Reserved R 0 0 10 Reserved R 0 0 9 Reserved R 0 0 8 Reserved R 0 0
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 Reserved R 0 0
2 Reserved R 0 0
1 Reserved R 0 0
0 LEDINT R/W 0 0
Bit 15 to 1 0 Reserved LEDINT
Name 0 is returned when read
Function
Auto stop interrupt request. Cleared to 0 when 1 is written. 1 : Occurred 0 : Not occurred
This register indicates when an auto stop interrupt request has occurred. An auto stop interrupt request occurs when 1 has already been set to both the LEDSTOP bit and the LEDENABLE bit of the LEDCNTREG register if LEDASTCREG register is cleared to 0. When this interrupt occurs, the LEDSTOP bit and the LEDENABLE bit of the LEDCNTREG register are both cleared to 0.
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18.3 Operation Flow
Start Register initial setting * LEDHTSREG: 0x0010 (LED ON time available) * LEDLTSREG: 0x0020 (LED OFF time available) * LEDCNTREG: 0x0002 * LEDASTCREG: 0x04B0
Register initial settingNote
Set LEDHTSREG
Set LEDLTSREG
LED blinking time setting * LEDHTSREG Set LED ON time. * LEDLTSREG Set LED OFF time. * LEDASTCREG Set number of LEDs blinking. Caution Setting these registers to 0 is prohibited because it may cause undefined operation. LED auto stop setting * LEDSTOP Set this bit to enable the LED blink auto stop function. This setting terminates LED blinking automatically after blinking time set above has elapaed. LED blinking operation start * LEDENABLE Set this bit to start LED blinking operation.
LEDs blinking operation start condition
Set LEDASTCREG
LEDCNTREG LEDSTOP = 1
LEDCNTREG LEDENABLE = 1 Software Hardware
LEDs blink
Auto stop counter = 0 Yes
No
LED blinking operation * Supervising the auto stop counter LED blinking terminates when the auto stop counter reaches 0. Caution Setting the LEDENABLE and LEDSTOP bits to 0 is prohibited because it may cause undefined operation.
LEDENABLE = 0 LEDSTOP = 0
LED blinking operation termination * LEDENABLE LED blinking operation is terminated by setting 0 to this bit. LED blinking operation terminate interrupt request generation * LEDINT An interrupt request to the ICU is generated when 1 is set to this bit.
LEDINT = 1
LEDs OFF
End
Note Initial setting for each register must be performed when a power is supplied to device for the first time, regardless whether LEDs blinking function is used or not.
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CHAPTER 19 SERIAL INTERFACE UNIT 1 (SIU1)
19.1 General
The SIU1 is a serial interface that conforms to the RS-232-C communication standard and is equipped with two one-channel interfaces, one for transmission and one for reception. This unit is functionally compatible with the NS16550 except for the additional clock control logic to permit the 16650 core clock source to be stopped. Figure 19-1. SIU1 Block Diagram
VR4181 SIU1 TxD1 UART1 RxD1 UART1_clock
RTS1# DCD1# DTR1#
Activity Timer 1 seclk_siu clk32k
Caution
No clock is supplied to the SIU1 in the initial state. When using the SIU1, set the MSKSIU18M bit of the CMUCLKMSK register in the MBA Host Bridge to 1 in advance so that the clock is supplied.
19.2 Clock Control Logic
The power of the 16550 core can be managed by monitoring activity on the modem status pins and writes to the transmit buffer. The clock control logic for the 16550 core monitors activity on the four serial interface input signals; RxD1, RTS1#, DCD1#, and DTR1#. It also monitors writes to the 16550 transmit buffer. Each source has an associated mask bit which prevents a source from causing reset of the Activity Timer. Activity on the RxD1, RTS1#, DCD1#, and DTR1# inputs is defined as any change of state (high to low or low to high). When no unmasked activity has been detected on any of the inputs, and no writes have occurred to the transmit buffer within the programmed time-out period specified in the Activity Timer block, the UART1_clock is stopped. The UART1_clock will remain stopped until any activity is detected on the monitored sources.
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19.3 Register Set
The SIU1 registers are listed below. Table 19-1. SIU1 Registers
Physical address 0x0C00 0010 LCR7 0 R W 1 0x0C00 0011 0 1 0x0C00 0012 0x0C00 0013 0x0C00 0014 0x0C00 0015 0x0C00 0016 0x0C00 0017 0x0C00 0019 0x0C00 001C 0x0C00 001E R/W R/W R/W R W R/W R/W R R/W R/W R/W R/W R/W R/W Register symbol SIURB_1 SIUTH_1 SIUDLL_1 SIUIE_1 SIUDLM_1 SIUIID_1 SIUFC_1 SIULC_1 SIUMC_1 SIULS_1 SIUMS_1 SIUSC_1 SIURESET_1 SIUACTMSK_1 SIUADTTMR_1 Function Receive buffer register (read) Transmit holding register (write) Divisor latch (least significant byte) register Interrupt enable register Divisor latch (most significant byte) register Interrupt identification register (read) FIFO control register (write) Line control register Modem control register Line status register Modem status register Scratch register SIU reset register SIU activity mask register SIU Activity Timer register
Remark
LCR7 is bit 7 of the SIULC_1 register.
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19.3.1 SIURB_1 (0x0C00 0010: LCR7 = 0, Read)
Bit Name R/W RTCRST Other resets 7 RXD7 R Undefined Undefined 6 RXD6 R Undefined Undefined 5 RXD5 R Undefined Undefined 4 RXD4 R Undefined Undefined 3 RXD3 R Undefined Undefined 2 RXD2 R Undefined Undefined 1 RXD1 R Undefined Undefined 0 RXD0 R Undefined Undefined
Bit 7 to 0 RXD(7:0)
Name Serial receive data
Function
This register stores receive data used in serial communications. To access this register, set the LCR7 bit (bit 7 of the SIULC_1 register) to 0. 19.3.2 SIUTH_1 (0x0C00 0010: LCR7 = 0, Write)
Bit Name R/W RTCRST Other resets 7 TXD7 W Undefined Undefined 6 TXD6 W Undefined Undefined 5 TXD5 W Undefined Undefined 4 TXD4 W Undefined Undefined 3 TXD3 W Undefined Undefined 2 TXD2 W Undefined Undefined 1 TXD1 W Undefined Undefined 0 TXD0 W Undefined Undefined
Bit 7 to 0 TXD(7:0)
Name Serial transmit data
Function
This register stores transmit data used in serial communications. To access this register, set the LCR7 bit (bit 7 of the SIULC_1 register) to 0. 19.3.3 SIUDLL_1 (0x0C00 0010: LCR7 = 1)
Bit Name R/W RTCRST Other resets 7 DLL7 R/W Undefined Undefined 6 DLL6 R/W Undefined Undefined 5 DLL5 R/W Undefined Undefined 4 DLL4 R/W Undefined Undefined 3 DLL3 R/W Undefined Undefined 2 DLL2 R/W Undefined Undefined 1 DLL1 R/W Undefined Undefined 0 DLL0 R/W Undefined Undefined
Bit 7 to 0 DLL(7:0)
Name Baud rate divisor (low-order byte)
Function
This register is used to set the divisor (division rate) for the baud rate generator. The data in this register and the data in the SIUDLM_1 register as upper 8 bits are together handled as 16-bit data. To access this register, set the LCR7 bit (bit 7 of the SIULC_1 register) to 1.
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19.3.4 SIUIE_1 (0x0C00 0011: LCR7 = 0)
Bit Name R/W RTCRST Other resets 7 Reserved R 0 0 6 Reserved R 0 0 5 Reserved R 0 0 4 Reserved R 0 0 3 IE3 R/W 0 0 2 IE2 R/W 0 0 1 IE1 R/W 0 0 0 IE0 R/W 0 0
Bit 7 to 4 3 Reserved IE3
Name 0 is returned when read Modem status interrupt 1 : Enable 0 : Prohibit
Function
2
IE2
Receive status interrupt 1 : Enable 0 : Prohibit
1
IE1
Transmit holding register empty interrupt 1 : Enable 0 : Prohibit
0
IE0
Receive data ready interrupt or character timeout interrupt in FIFO mode 1 : Enable 0 : Prohibit
This register is used to specify interrupt enable/prohibit settings for the five types of interrupt requests used in the SIU1. An interrupt is enabled by setting the corresponding bit to 1. Overall use of interrupt functions can be halted by setting bits 0 to 3 of this register to 0. When interrupts are prohibited, "pending" is not displayed in the IIR0 bit in the SIUIID_1 register even when interrupt conditions have been met. Other functions in the SIU1 are not affected even though interrupts are prohibited and the settings in the SIULS_1 register and SIUMS_1 register are valid. To access this register, set the LCR7 bit (bit 7 of the SIULC_1 register) to 0.
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19.3.5 SIUDLM_1 (0x0C00 0011: LCR7 = 1)
Bit Name R/W RTCRST Other resets 7 DLM7 R/W Undefined Undefined 6 DLM6 R/W Undefined Undefined 5 DLM5 R/W Undefined Undefined 4 DLM4 R/W Undefined Undefined 3 DLM3 R/W Undefined Undefined 2 DLM2 R/W Undefined Undefined 1 DLM1 R/W Undefined Undefined 0 DLM0 R/W Undefined Undefined
Bit 7 to 0 DLM(7:0)
Name Baud rate divisor (high-order byte)
Function
This register is used to set the divisor (division rate) for the baud rate generator. The data in this register and the data in the SIUDLL_1 register as lower 8 bits are together handled as 16-bit data. To access this register, set the LCR7 bit (bit 7 of the SIULC_1 register) to 1. The relationship between baud rates and the settings of the SIUDLL_1 and SIUDLM_1 registers are as follows.
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Table 19-2. Correspondence between Baud Rates and Divisors
Baud rate (bps) Divisor (DLM(7:0)||DLL(7:0)) 23040 15360 10473 8565 7680 3840 1920 960 640 576 480 320 240 160 120 60 30 20 10 9 8 6 5 4 3 2 1 1-clock width (s)
50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 128000 144000 192000 230400 288000 384000 576000 1152000
20000.00 13333.33 9090.91 7434.94 6666.67 3333.33 1666.67 833.33 555.56 500.00 416.67 277.78 208.33 138.89 104.17 52.08 26.04 17.36 8.68 7.81 6.94 5.21 4.34 3.47 2.60 1.74 0.868
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19.3.6 SIUIID_1 (0x0C00 0012: Read)
Bit Name R/W RTCRST Other resets 7 IIR7 R 0 0 6 IIR6 R 0 0 5 Reserved R 0 0 4 Reserved R 0 0 3 IIR3 R 0 0 2 IIR2 R 0 0 1 IIR1 R 0 0 0 IIR0 R 1 1
Bit 7, 6 5, 4 3 IIR(7:6) Reserved IIR3
Name Becomes 11 when FCR0 bit = 1 0 is returned when read
Function
Pending of the character timeout interrupt request (in FIFO mode) 1 : No pending 0 : Pending
2, 1
IIR(2:1)
Indicates the priority level of interrupts. See the following table. Pending interrupt requests 1 : No pending 0 : Pending
0
IIR0
This register indicates priority levels for interrupts and existence of pending interrupt requests. From highest to lowest priority, the involved interrupts are the receive line status, the receive data ready, the character timeout, the transmit holding register empty, and the modem status. The content of the IIR3 bit is valid only in the FIFO mode and it is always 0 in the 16450 mode. The IIR2 bit becomes 1 when the IIR3 bit is set to 1.
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Table 19-3. Interrupt Function
SIUIID_1 register Bit 3 0
Note
Interrupt set/reset function Priority level Interrupt type Interrupt source Overrun error, parity error, framing error, or break interrupt Receive data exists or has reached the trigger level. Interrupt reset control Read line status register
Bit 2 1 1
Bit 1
Highest (1st) Receive line status 2nd Receive data ready
0
1
0
Read the receive buffer register or lower the data in the FIFO than trigger level.
1
1
0
2nd
Character timeout
Read receive buffer During the time period for the four most recent characters, not one character has register been read from the receive FIFO nor has a character been input to the receive FIFO. During this period, at least one character has been held in the receive FIFO. Transmit register is empty Read IIR (if it is the interrupt source) or write to transmit holding register Read modem status register
0
0
1
3rd
Transmit holding register empty Modem status
0
0
0
4th
CTS1#, DSR1#, or DCD1#
Note FIFO mode only.
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19.3.7 SIUFC_1 (0x0C00 0012: Write)
Bit Name R/W RTCRST Other resets 7 FCR7 W 0 0 6 FCR6 W 0 0 5 Reserved R 0 0 4 Reserved R 0 0 3 FCR3 W 0 0 2 FCR2 W 0 0 1 FCR1 W 0 0 0 FCR0 W 0 0
Bit 7, 6 FCR(7:6)
Name Receive FIFO trigger level 11 : 10 : 01 : 00 : 14 bytes 8 bytes 4 bytes 0 bytes
Function
5, 4 3
Reserved FCR3
0 is returned when read Switch between 16450 mode and FIFO mode 1 : From 16450 mode to FIFO mode 0 : From FIFO mode to 16450 mode
2
FCR2
Transmit FIFO and its counter clear. Cleared to 0 when 1 is written. 1 : FIFO and its counter clear 0 : Normal
1
FCR1
Receive FIFO and its counter clear. Cleared to 0 when 1 is written. 1 : FIFO and its counter clear 0 : Normal
0
FCR0
Receive/Transmit FIFO enable. Cleared to 0 when 1 is written. 1 : Enable 0 : Disable
This register is used to control the FIFOs.
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* FIFO interrupt modes When receive FIFO is enabled and receive interrupt requests are enabled, receive interrupts can occur as described below. 1. When the FIFO is reached to the specified trigger level, a receive data ready interrupt request is notified to the CPU. This interrupt is cleared when the FIFO goes below the trigger level. 2. When the FIFO is reached to the specified trigger level, the SIUIID_1 register indicates a receive data ready interrupt request. Same as the interrupt above, the SUIID_1 register is cleared when the FIFO goes below the trigger level. 3. The receive line status interrupt is assigned to a higher priority level than the receive data ready interrupt. 4. When characters are transferred from the shift register to the receive FIFO, 1 is set to the LSR0 bit of the SIULS_1 register. The value of this bit returns to 0 when the FIFO becomes empty. When receive FIFO is enabled and receive interrupts are enabled, receive FIFO timeout interrupt requests can occur as described below. 1. Followings are the conditions under which FIFO timeout interrupt requests occur. * At least one character is being stored in the FIFO. * The time required for sending four characters has elapsed since the serial reception of the last character (includes the time for the second stop bit in cases where it is specified that two stop bits are required). * The time required for sending four characters has elapsed since the last read of the FIFO by the CPU. The time between receiving the last character and issuing a timeout interrupt request is a maximum of 160 ms when operating at 300 baud and receiving 12-bit data. 2. The transfer time for a character is calculated based on the baud rate clock for reception (internal) (which is why the elapsed time is in proportion to the baud rate). 3. Once a timeout interrupt request has occurred, the timeout interrupt is cleared and the timer is reset as soon as the CPU reads one character from the receive FIFO. 4. If no timeout interrupt request has occurred, the timer is reset when a new character is received or when the CPU reads the receive FIFO.
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When transmit FIFO is enabled and transmit interrupts are enabled, transmit interrupt requests can occur as described below. 1. When the transmit FIFO becomes empty, a transmit holding register empty interrupt request occurs. This interrupt request is cleared when a character is written to the transmit holding register (from one to 16 characters can be written to the transmit FIFO during servicing of this interrupt), or when the SIUIID_1 register is read. 2. If there are not at least two bytes of character data in the transmit FIFO between one time when the LSR5 bit = 1 (transmit FIFO is empty) in the SIULS_1 register and the next time when the LSR5 bit = 1, transmit FIFO empty status is reported to the IIR bits after a delay period calculated as "the time for one character - the time for the last stop bit(s)". When transmit interrupts are enabled, the first transmit interrupt request that occurs after the FCR0 bit (FIFO enable bit) in the SIUFC_1 register is overwritten is indicated immediately. The priority level of the character timeout interrupt and receive FIFO trigger level interrupt is the same as that of the receive data ready interrupt. The priority level of the transmit FIFO empty interrupt is the same as that of the transmit holding register empty interrupt. Whether data to be transmitted exists or not in the transmit FIFO and the transmit shift register, check the LSR6 bit of the SIULS_1 register. The LSR5 bit of the SIULS_1 register is used to check whether data to be transferred exists or not in the transmit FIFO only. Therefore, there may be data in the transmit shift register. * FIFO polling mode When the FCR0 bit = 1 (FIFO is enabled) in the SIUFC_1 register, if the value of any or all of the SIUIE_1 register bits 3 to 0 becomes 0, SIU1 enters FIFO polling mode. Because the transmit block and receive block are controlled separately, polling mode can be set for either or both blocks. When in this mode, the status of the transmit block and/or receive block can be checked by reading the SIULS_1 register via a user program. When in the FIFO polling mode, there is no notification when the trigger level is reached or when a timeout occurs, but the receive FIFO and transmit FIFO can still store characters as they normally do.
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19.3.8 SIULC_1 (0x0C00 0013)
Bit Name R/W RTCRST Other resets 7 LCR7 R/W 0 0 6 LCR6 R/W 0 0 5 LCR5 R/W 0 0 4 LCR4 R/W 0 0 3 LCR3 R/W 0 0 2 LCR2 R/W 0 0 1 LCR1 R/W 0 0 0 LCR0 R/W 0 0
Bit 7 LCR7
Name Divisor latch access register switching
Function
1 : Divisor latch access register 0 : Receive buffer, transmit holding register, interrupt enable register 6 LCR6 Break control 1 : Set break 0 : Clear break 5 LCR5 Parity fixing 1 : Fixed parity 0 : Parity not fixed 4 LCR4 Parity setting 1 : Even parity 0 : Odd parity 3 LCR3 Parity enable 1 : Create parity (during transmission) or check parity (during reception) 0 : No parity (during transmission) or no checking (during reception) 2 LCR2 Stop bit specification 1 : 1.5 bits (character length is 5 bits) 2 bits (character length is 6, 7, or 8 bits) 0 : 1 bit 1, 0 LCR(1:0) Specifies the length of one character (number of bits) 11 : 10 : 01 : 00 : 8 bits 7 bits 6 bits 5 bits
This register is used to specify the format for asynchronous data communication and exchange and to set the divisor latch access register. The LCR6 bit is used to send the break status to the receive side's UART. When the LCR6 bit = 1, the serial output (TxD1) is forcibly set to the spacing (0) state. The setting of the LCR5 bit becomes valid according to settings in the LCR4 and LCR3 bits.
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19.3.9 SIUMC_1 (0x0C00 0014)
Bit Name R/W RTCRST Other resets 7 Reserved R 0 0 6 Reserved R 0 0 5 Reserved R 0 0 4 MCR4 R/W 0 0 3 MCR3 R/W 0 0 2 MCR2 R/W 0 0 1 MCR1 R/W 0 0 0 MCR0 R/W 0 0
Bit 7 to 5 4 Reserved MCR4
Name 0 is returned when read
Function
Use of diagnostic testing (local loopback) 1 : Enable 0 : Disable
3
MCR3
OUT2 signal (internal) setting 1 : Low level 0 : High level
2
MCR2
OUT1 signal (internal) setting 1 : Low level 0 : High level
1
MCR1
RTS1# output control 1 : Low level 0 : High level
0
MCR0
DTR1# output control 1 : Low level 0 : High level
This register is used to control the interface with a modem or data set (or a peripheral device that emulates a modem). The settings of the MCR3 and MCR2 bits become valid only when the MCR4 bit is set to 1 (enable use of local loopback). * Local Loopback The local loopback can be used to test the transmit/receive data path in SIU1. The following operation (local loopback) is executed inside the SIU1 when the MCR4 bit = 1. The transmit block's serial output (TxD1) enters the marking state (1) and the serial input (RxD1) to the receive block is cut off. The transmit shift register's output is looped back to the receive shift register's input. The four modem control inputs (DSR1#, CTS1#, RI (internal), and DCD1#) are cut off and the four modem control outputs (DTR1#, RTS1#, OUT1 (internal), and OUT2 (internal)) are internally connected to the corresponding modem control inputs. The modem control output pins are forcibly set as inactive (high level). During this kind of loopback mode, transmitted data can be immediately and directly received. When in loopback mode, both transmit and receive interrupts can be used. The interrupt sources are external sources in relation to the transmit and receive blocks. Although modem control interrupts can be used, the loworder four bits of the modem control register can be used instead of the four modem control inputs as interrupt sources. As usual, each interrupt is controlled by an interrupt enable register.
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19.3.10 SIULS_1 (0x0C00 0015)
Bit Name R/W RTCRST Other resets 7 LSR7 R 0 0 6 LSR6 R 1 1 5 LSR5 R 1 1 4 LSR4 R 0 0 3 LSR3 R 0 0 2 LSR2 R 0 0 1 LSR1 R 0 0 0 LSR0 R 0 0
Bit 7 LSR7
Name Error detection (FIFO mode)
Function
1 : Parity error, framing error, or break is detected. 0 : No error 6 LSR6 Transmit block empty 1 : No data in transmit holding register and transmit shift register No data in transmit FIFO (during FIFO mode) 0 : Data exists in transmit holding register or transmit shift register Data exists in transmit FIFO (during FIFO mode) 5 LSR5 Transmit holding register empty 1 : Character is transferred to transmit shift register (during 16450 mode) Transmit FIFO is empty (during FIFO mode) 0 : Character is stored in transmit holding register (during 16450 mode) Transmit data exists in transmit FIFO (during FIFO mode) 4 LSR4 Break interrupt 1 : Detected 0 : No break 3 LSR3 Framing error 1 : Detected 0 : No error 2 LSR2 Parity error 1 : Detected 0 : No error 1 LSR1 Overrun error 1 : Detected (receive data is overwritten) 0 : No error 0 LSR0 Receive data ready 1 : Receive data exists in FIFO 0 : No receive data in FIFO
The CPU uses this register to get information related to data transfers. When LSR7 and LSR(4:1) bits are 1, reading this register clears these bits to 0. Caution The LSR0 bit (receive data ready bit) is set before the serial data reception is completed. Therefore, the LSR0 bit may not be cleared if the serial receive data is read from the SIURB_1 register immediately after this bit is set. When reading data from the SIURB_1 register, wait for the stop bit width time since the LSR0 bit is set.
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LSR7 bit is valid only in FIFO mode, and it indicates always 0 in 16450 mode. The value of LSR4 bit becomes 1 when the spacing status (0) of receive data input is held longer than the time required for transmission of one word (start bit + data bits + parity bit + stop bit). When in FIFO mode, if a break is detected for one character in the FIFO, the character is regarded as an error character and the CPU is notified of a break when that character reaches the highest position in the FIFO. When a break occurs, one "zero" character is sent to the FIFO. When the RxD1 enters marking status, and the next valid start bit is received, the next character can be transmitted. The value of LSR3 bit becomes 1 when a zero (spacing level) stop bit is detected following the final data bit or parity bit. When in FIFO mode, if a framing error is detected for one character in the FIFO, the character is regarded as an error character and the CPU is notified of a framing error when that character reaches the highest position in the FIFO. When a framing error occurs, the SIU1 prepares for synchronization again. The next start bit is assumed to be the cause of the framing error and the next data is not accepted until the next start bit has been sampled twice. The value of LSR2 bit becomes 1 when a received character does not satisfy the even or odd parity specified in the LCR4 bit. When in FIFO mode, if a parity error is detected for one character within the FIFO, the character is regarded as an error character and the CPU is notified of a parity error when that character reaches the highest position in the FIFO. The value of LSR1 bit becomes 1 when a character is transferred to the receive buffer register before reading by the CPU and the previous character is lost. When in FIFO mode, if the data continues to be transferred to the FIFO though it exceeds the trigger level, even after the FIFO becomes full an overrun error will not occur until all characters are stored in the shift register. The CPU is notified as soon as an overrun error occurs. The characters in the shift register are overwritten and are not transferred to the FIFO.
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19.3.11 SIUMS_1 (0x0C00 0016)
Bit Name R/W RTCRST Other resets 7 MSR7 R Undefined Undefined 6 MSR6 R Undefined Undefined 5 MSR5 R Undefined Undefined 4 MSR4 R Undefined Undefined 3 MSR3 R/W 0 0 2 MSR2 R/W 0 0 1 MSR1 R/W 0 0 0 MSR0 R/W 0 0
Bit 7 MSR7
Name DCD1# signal status 1 : Low level 0 : High level
Function
6
MSR6
RI signal (internal) status 1 : Low level 0 : High level
5
MSR5
DSR1# input status 1 : Low level 0 : High level
4
MSR4
CTS1# input status 1 : Low level 0 : High level
3
MSR3
DCD1# signal change 1 : Changed 0 : No change
2
MSR2
RI signal (internal) change 1 : Changed 0 : No change
1
MSR1
DSR1# signal change 1 : Changed 0 : No change
0
MSR0
CTS1# signal change 1 : Changed 0 : No change
This register indicates the current status and change in status of various control signals that are input to the CPU from a modem or other peripheral device. The MSR(3:0) bits are cleared to 0 if they are read when they are set to 1.
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19.3.12 SIUSC_1 (0x0C00 0017)
Bit Name R/W RTCRST Other resets 7 SCR7 R/W Undefined Undefined 6 SCR6 R/W Undefined Undefined 5 SCR5 R/W Undefined Undefined 4 SCR4 R/W Undefined Undefined 3 SCR3 R/W Undefined Undefined 2 SCR2 R/W Undefined Undefined 1 SCR1 R/W Undefined Undefined 0 SCR0 R/W Undefined Undefined
Bit 7 to 0 SCR(7:0)
Name General-purpose data
Function
This register is a readable/writable 8-bit register, and can be used freely by users. It does not affect control of the SIU1. 19.3.13 SIURESET_1 (0x0C00 0019)
Bit Name 7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 SIU RESET R/W 0 0
R/W RTCRST Other resets
R 0 0
R 0 0
R 0 0
R 0 0
R 0 0
R 0 0
R 0 0
Bit 7 to 1 0 Reserved
Name 0 is returned when read SIU1 reset 1 : Reset 0 : Release reset
Function
SIURESET
This register is used to reset SIU1 forcibly.
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19.3.14 SIUACTMSK_1 (0x0C00 001C)
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 RxDMSK R/W 0 0
4 RTSMSK R/W 0 0
3 DCDMSK R/W 0 0
2 DTRMSK R/W 0 0
1 Reserved R/W 0 0
0 TxWRMSK R/W 0 0
Bit 7, 6 5 Reserved RxDMSK
Name 0 is returned when read
Function
Mask for notification of change on RxD1 1 : Mask 0 : Unmask
4
RTSMSK
Mask for notification of change on RTS1# 1 : Mask 0 : Unmask
3
DCDMSK
Mask for notification of change on DCD1# 1 : Mask 0 : Unmask
2
DTRMSK
Mask for notification of change on DTR1# 1 : Mask 0 : Unmask
1 0
Reserved TxWRMSK
Write 0 when write. 0 is returned when read Mask for notification of transmit buffer write 1 : Mask 0 : Unmask
This register is used to set masks for notification of operation statuses to the Activity Timer of the SIU1. When 1 is set in this register, state transition of the corresponding signals or write to transmit buffer is not notified to the Activity Timer.
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19.3.15 SIUACTTMR_1 (0x0C00 001E)
Bit Name R/W RTCRST Other resets 7 SIUTMO7 R/W 0 0 6 SIUTMO6 R/W 0 0 5 SIUTMO5 R/W 0 0 4 SIUTMO4 R/W 0 0 3 SIUTMO3 R/W 0 0 2 SIUTMO2 R/W 0 0 1 SIUTMO1 R/W 0 0 0 SIUTMO0 R/W 0 0
Bit 7 to 0
Name SIUTMO(7:0) SIU activity timeout period 11111111 : 255 x 30.5 s 11111110 : 254 x 30.5 s : 01111111 : 127 x 30.5 s : 00000001 : 30.5 s 00000000 : Activity Timer disabled
Function
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CHAPTER 20 SERIAL INTERFACE UNIT 2 (SIU2)
20.1 General
The SIU2 is a serial interface that conforms to the RS-232-C communication standard and is equipped with two one-channel interfaces, one for transmission and one for reception. This unit can be also used as an interface in the IrDA format by means of register setting. This unit is functionally compatible with the NS16550 except for the additional clock control logic to permit the 16650 core clock source to be stopped. Figure 20-1. SIU2 Block Diagram
VR4181 SIU2 IRDOUT/TxD2 UART2 IRDIN/RxD2 UART2_clock
RTS2# DCD2# DTR2#
Activity Timer 2 seclk_siu clk32k
Caution
No clock is supplied to the SIU2 in the initial state. When using the SIU2, set the MSKSIU18M bit of the CMUCLKMSK register in the MBA Host Bridge to 1 in advance so that the clock is supplied.
20.2 Clock Control Logic
The power of the 16550 core can be managed by monitoring activity on the modem status pins and writes to the transmit buffer. The clock control logic for the 16550 core monitors activity on the four serial interface input signals; RxD2, RTS2#, DCD2#, and DTR2#. It also monitors writes to the 16550 transmit buffer. Each source has an associated mask bit which prevents a source from causing reset of the Activity Timer. Activity on the RxD2, RTS2#, DCD2# and DTR2# inputs is defined as any change of state (high to low or low to high). When no unmasked activity has been detected on any of the inputs, and no writes have occurred to the transmit buffer within the programmed time-out period specified in the Activity Timer block, the UART2_clock is stopped. The UART2_clock will remain stopped until the activity is detected on the monitored sources.
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20.3 Register Set
The SIU2 registers are listed below. Table 20-1. SIU2 Registers
Physical address 0x0C00 0000 LCR7 0 R W 1 0x0C00 0001 0 1 0x0C00 0002 0x0C00 0003 0x0C00 0004 0x0C00 0005 0x0C00 0006 0x0C00 0007 0x0C00 0008 0x0C00 0009 0x0C00 000A 0x0C00 000C 0x0C00 000E R/W R/W R/W R W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W Register symbol SIURB_2 SIUTH_2 SIUDLL_2 SIUIE_2 SIUDLM_2 SIUIID_2 SIUFC_2 SIULC_2 SIUMC_2 SIULS_2 SIUMS_2 SIUSC_2 SIUIRSEL_2 SIURESET_2 SIUCSEL_2 SIUACTMSK_2 SIUADTTMR_2 Function Receive buffer register (read) Transmit holding register (write) Divisor latch (least significant byte) register Interrupt enable register Divisor latch (most significant byte) register Interrupt identification register (read) FIFO control register (write) Line control register Modem control register Line status register Modem status register Scratch register SIU IrDA select register SIU reset register SIU echo back control register SIU activity mask register SIU Activity Timer register
Remark
LCR7 is bit 7 of the SIULC_2 register.
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20.3.1 SIURB_2 (0x0C00 0000: LCR7 = 0, Read)
Bit Name R/W RTCRST Other resets 7 RXD7 R Undefined Undefined 6 RXD6 R Undefined Undefined 5 RXD5 R Undefined Undefined 4 RXD4 R Undefined Undefined 3 RXD3 R Undefined Undefined 2 RXD2 R Undefined Undefined 1 RXD1 R Undefined Undefined 0 RXD0 R Undefined Undefined
Bit 7 to 0 RXD(7:0)
Name Serial receive data
Function
This register stores receive data used in serial communications. To access this register, set the LCR7 bit (bit 7 of the SIULC_2 register) to 0. 20.3.2 SIUTH_2 (0x0C00 0000: LCR7 = 0, Write)
Bit Name R/W RTCRST Other resets 7 TXD7 W Undefined Undefined 6 TXD6 W Undefined Undefined 5 TXD5 W Undefined Undefined 4 TXD4 W Undefined Undefined 3 TXD3 W Undefined Undefined 2 TXD2 W Undefined Undefined 1 TXD1 W Undefined Undefined 0 TXD0 W Undefined Undefined
Bit 7 to 0 TXD(7:0)
Name Serial transmit data
Function
This register stores transmit data used in serial communications. To access this register, set the LCR7 bit (bit 7 of the SIULC_2 register) to 0. 20.3.3 SIUDLL_2 (0x0C00 0000: LCR7 = 1)
Bit Name R/W RTCRST Other resets 7 DLL7 R/W Undefined Undefined 6 DLL6 R/W Undefined Undefined 5 DLL5 R/W Undefined Undefined 4 DLL4 R/W Undefined Undefined 3 DLL3 R/W Undefined Undefined 2 DLL2 R/W Undefined Undefined 1 DLL1 R/W Undefined Undefined 0 DLL0 R/W Undefined Undefined
Bit 7 to 0 DLL(7:0)
Name Baud rate divisor (low-order byte)
Function
This register is used to set the divisor (division rate) for the baud rate generator. The data in this register and the data in SIUDLM_2 register as upper 8 bits are together handled as 16-bit data. To access this register, set the LCR7 bit (bit 7 of the SIULC_2 register) to 1.
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20.3.4 SIUIE_2 (0x0C00 0001: LCR7 = 0)
Bit Name R/W RTCRST Other resets 7 Reserved R 0 0 6 Reserved R 0 0 5 Reserved R 0 0 4 Reserved R 0 0 3 IE3 R/W 0 0 2 IE2 R/W 0 0 1 IE1 R/W 0 0 0 IE0 R/W 0 0
Bit 7 to 4 3 Reserved IE3
Name 0 is returned when read Modem status interrupt 1 : Enable 0 : Prohibit
Function
2
IE2
Receive status interrupt 1 : Enable 0 : Prohibit
1
IE1
Transmit holding register empty interrupt 1 : Enable 0 : Prohibit
0
IE0
Receive data ready interrupt or character timeout interrupt in FIFO mode 1 : Enable 0 : Prohibit
This register is used to specify interrupt enable/prohibit settings for the five types of interrupt requests used in the SIU2. An interrupt is enabled by setting the corresponding bit to 1. Overall use of interrupt functions can be halted by setting bits 0 to 3 of this register to 0. When interrupts are prohibited, "pending" is not displayed in the IIR0 bit in the SIUIID_2 register even when interrupt conditions have been met. Other functions in the SIU2 are not affected even though interrupts are prohibited and the settings in the SIULS_2 register and SIUMS_2 register are valid. To access this register, set the LCR7 bit (bit 7 of the SIULC_2 register) to 0.
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20.3.5 SIUDLM_2 (0x0C00 0001: LCR7 = 1)
Bit Name R/W RTCRST Other resets 7 DLM7 R/W Undefined Undefined 6 DLM6 R/W Undefined Undefined 5 DLM5 R/W Undefined Undefined 4 DLM4 R/W Undefined Undefined 3 DLM3 R/W Undefined Undefined 2 DLM2 R/W Undefined Undefined 1 DLM1 R/W Undefined Undefined 0 DLM0 R/W Undefined Undefined
Bit 7 to 0 DLM(7:0)
Name Baud rate divisor (high-order byte)
Function
This register is used to set the divisor (division rate) for the baud rate generator. The data in this register and the data in SIUDLL_2 register as lower 8 bits are together handled as 16-bit data. To access this register, set the LCR7 bit (bit 7 of the SIULC_2 register) to 1. The relationship between baud rates and the settings of the SIUDLL_2 and SIUDLM_2 registers are as follows.
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Table 20-2. Correspondence between Baud Rates and Divisors
Baud rate (bps) Divisor (DLM(7:0)||DLL(7:0)) 23040 15360 10473 8565 7680 3840 1920 960 640 576 480 320 240 160 120 60 30 20 10 9 8 6 5 4 3 2 1 1-clock width (s)
50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200 128000 144000 192000 230400 288000 384000 576000 1152000
20000.00 13333.33 9090.91 7434.94 6666.67 3333.33 1666.67 833.33 555.56 500.00 416.67 277.78 208.33 138.89 104.17 52.08 26.04 17.36 8.68 7.81 6.94 5.21 4.34 3.47 2.60 1.74 0.868
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20.3.6 SIUIID_2 (0x0C00 0002: Read)
Bit Name R/W RTCRST Other resets 7 IIR7 R 0 0 6 IIR6 R 0 0 5 Reserved R 0 0 4 Reserved R 0 0 3 IIR3 R 0 0 2 IIR2 R 0 0 1 IIR1 R 0 0 0 IIR0 R 1 1
Bit 7, 6 5, 4 3 IIR(7:6) Reserved IIR3
Name Becomes 11 when FCR0 bit = 1 0 is returned when read
Function
Pending of the character timeout interrupt request (in FIFO mode) 1 : No pending 0 : Pending
2, 1
IIR(2:1)
Indicates the priority level of interrupts. See the following table. Pending interrupt requests 1 : No pending 0 : Pending
0
IIR0
This register indicates priority levels for interrupts and existence of pending interrupt requests. From highest to lowest priority, the involved interrupts are the receive line status, the receive data ready, the character timeout, the transmit holding register empty, and the modem status. The content of the IIR3 bit is valid only in the FIFO mode and it is always 0 in the 16450 mode. The IIR2 bit becomes 1 when the IIR3 bit is set to 1.
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Table 20-3. Interrupt Function
SIUIID_2 register Bit 3 0
Note
Interrupt set/reset function Priority level Interrupt type Interrupt source Overrun error, parity error, framing error, or break Receive data exists or has reached the trigger level. Interrupt reset control Read line status register
Bit 2 1 1
Bit 1
Highest (1st) Receive line status 2nd Receive data ready
0
1
0
Read the receive buffer register or lower the data in the FIFO than trigger level.
1
1
0
2nd
Character timeout
Read receive buffer During the time period for the four most recent characters, not one character has register been read from the receive FIFO nor has a character been input to the receive FIFO. During this period, at least one character has been held in the receive FIFO. Transmit register is empty Read IIR (if it is the interrupt source) or write to transmit holding register Read modem status register
0
0
1
3rd
Transmit holding register empty Modem status
0
0
0
4th
CTS2#, DSR2#, or DCD2#
Note FIFO mode only.
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20.3.7 SIUFC_2 (0x0C00 0002: Write)
Bit Name R/W RTCRST Other resets 7 FCR7 W 0 0 6 FCR6 W 0 0 5 Reserved R 0 0 4 Reserved R 0 0 3 FCR3 W 0 0 2 FCR2 W 0 0 1 FCR1 W 0 0 0 FCR0 W 0 0
Bit 7, 6 FCR(7:6)
Name Receive FIFO trigger level 11 : 10 : 01 : 00 : 14 bytes 8 bytes 4 bytes 0 bytes
Function
5, 4 3
Reserved FCR3
0 is returned when read Switch between 16450 mode and FIFO mode 1 : From 16450 mode to FIFO mode 0 : From FIFO mode to 16450 mode
2
FCR2
Transmit FIFO and its counter clear. Cleared to 0 when 1 is written. 1 : FIFO and its counter clear 0 : Normal
1
FCR1
Receive FIFO and its counter clear. Cleared to 0 when 1 is written. 1 : FIFO and its counter clear 0 : Normal
0
FCR0
Receive/Transmit FIFO enable. Cleared to 0 when 1 is written. 1 : Enable 0 : Disable
This register is used to control the FIFOs.
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* FIFO interrupt modes When receive FIFO is enabled and receive interrupt requests are enabled, receive interrupts can occur as described below. 1. When the FIFO is reached to the specified trigger level, a receive data ready interrupt request is notified to the CPU. This interrupt is cleared when the FIFO goes below the trigger level. 2. When the FIFO is reached to the specified trigger level, the SIUIID_2 register indicates a receive data ready interrupt request. Same as the interrupt above, the SUIID_2 register is cleared when the FIFO goes below the trigger level. 3. The receive line status interrupt is assigned to a higher priority level than the receive data ready interrupt. 4. When characters are transferred from the shift register to the receive FIFO, 1 is set to the LSR0 bit of the SIULS_2 register. The value of this bit returns to 0 when the FIFO becomes empty. When receive FIFO is enabled and receive interrupts are enabled, receive FIFO timeout interrupt requests can occur as described below. 1. Followings are the conditions under which FIFO timeout interrupt requests occur. * At least one character is being stored in the FIFO. * The time required for sending four characters has elapsed since the serial reception of the last character (includes the time for the second stop bit in cases where it is specified that two stop bits are required). * The time required for sending four characters has elapsed since the last read of the FIFO by the CPU. The time between receiving the last character and issuing a timeout interrupt request is a maximum of 160 ms when operating at 300 baud and receiving 12-bit data. 2. The transfer time for a character is calculated based on the baud rate clock for reception (internal) (which is why the elapsed time is in proportion to the baud rate). 3. Once a timeout interrupt request has occurred, the timeout interrupt is cleared and the timer is reset as soon as the CPU reads one character from the receive FIFO. 4. If no timeout interrupt request has occurred, the timer is reset when a new character is received or when the CPU reads the receive FIFO.
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When transmit FIFO is enabled and transmit interrupts are enabled, transmit interrupt requests can occur as described below. 1. When the transmit FIFO becomes empty, a transmit holding register empty interrupt request occurs. This interrupt request is cleared when a character is written to the transmit holding register (from one to 16 characters can be written to the transmit FIFO during servicing of this interrupt), or when the SIUIID_2 register is read. 2. If there are not at least two bytes of character data in the transmit FIFO between one time when the LSR5 bit = 1 (transmit FIFO is empty) in the SIULS_2 register and the next time when the LSR5 bit = 1, transmit FIFO empty status is reported to the IIR bits after a delay period calculated as "the time for one character - the time for the last stop bit(s)". When transmit interrupts are enabled, the first transmit interrupt request that occurs after the FCR0 bit (FIFO enable bit) in the SIUFC_2 register is overwritten is indicated immediately. The priority level of the character timeout interrupt and receive FIFO trigger level interrupt is the same as that of the receive data ready interrupt. The priority level of the transmit FIFO empty interrupt is the same as that of the transmit holding register empty interrupt. Whether data to be transmitted exists or not in the transmit FIFO and the transmit shift register, check the LSR6 bit of the SIULS_2 register. The LSR5 bit of the SIULS_2 register is used to check whether data to be transferred exists or not in the transmit FIFO only. Therefore, there may be data in the transmit shift register. * FIFO polling mode When the FCR0 bit = 1 (FIFO is enabled) in the SIUFC_2 register, if the value of any or all of the SIUIE_2 register bits 3 to 0 becomes 0, SIU2 enters FIFO polling mode. Because the transmit block and receive block are controlled separately, polling mode can be set for either or both blocks. When in this mode, the status of the transmit block and/or receive block can be checked by reading the SIULS_2 register via a user program. When in the FIFO polling mode, there is no notification when the trigger level is reached or when a timeout occurs, but the receive FIFO and transmit FIFO can still store characters as they normally do.
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20.3.8 SIULC_2 (0x0C00 0003)
Bit Name R/W RTCRST Other resets 7 LCR7 R/W 0 0 6 LCR6 R/W 0 0 5 LCR5 R/W 0 0 4 LCR4 R/W 0 0 3 LCR3 R/W 0 0 2 LCR2 R/W 0 0 1 LCR1 R/W 0 0 0 LCR0 R/W 0 0
Bit 7 LCR7
Name Divisor latch access register switching
Function
1 : Divisor latch access register 0 : Receive buffer, transmit holding register, interrupt enable register 6 LCR6 Break control 1 : Set break 0 : Clear break 5 LCR5 Parity fixing 1 : Fixed parity 0 : Parity not fixed 4 LCR4 Parity setting 1 : Even parity 0 : Odd parity 3 LCR3 Parity enable 1 : Create parity (during transmission) or check parity (during reception) 0 : No parity (during transmission) or no checking (during reception) 2 LCR2 Stop bit specification 1 : 1.5 bits (character length is 5 bits) 2 bits (character length is 6, 7, or 8 bits) 0 : 1 bit 1, 0 LCR(1:0) Specifies the length of one character (number of bits) 11 : 10 : 01 : 00 : 8 bits 7 bits 6 bits 5 bits
This register is used to specify the format for asynchronous data communication and exchange and to set the divisor latch access register. The LCR6 bit is used to send the break status to the receive side's UART. When the LCR6 bit = 1, the serial output (TxD2) is forcibly set to the spacing (0) state. The setting of the LCR5 bit becomes valid according to settings in the LCR4 and LCR3 bits.
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20.3.9 SIUMC_2 (0x0C00 0004)
Bit Name R/W RTCRST Other resets 7 Reserved R 0 0 6 Reserved R 0 0 5 Reserved R 0 0 4 MCR4 R/W 0 0 3 MCR3 R/W 0 0 2 MCR2 R/W 0 0 1 MCR1 R/W 0 0 0 MCR0 R/W 0 0
Bit 7 to 5 4 Reserved MCR4
Name 0 is returned when read
Function
Use of diagnostic testing (local loopback) 1 : Enable 0 : Disable
3
MCR3
OUT2 signal (internal) setting 1 : Low level 0 : High level
2
MCR2
OUT1 signal (internal) setting 1 : Low level 0 : High level
1
MCR1
RTS2# output control 1 : Low level 0 : High level
0
MCR0
DTR2# output control 1 : Low level 0 : High level
This register is used to control the interface with a modem or data set (or a peripheral device that emulates a modem). The settings of the MCR3 and MCR2 bits become valid only when the MCR4 bit is set to 1 (enable use of local loopback). * Local Loopback The local loopback can be used to test the transmit/receive data path in SIU2. The following operation (local loopback) is executed inside the SIU2 when the MCR4 bit = 1. The transmit block's serial output (TxD2) enters the marking state (1) and the serial input (RxD2) to the receive block is cut off. The transmit shift register's output is looped back to the receive shift register's input. The four modem control inputs (DSR2#, CTS2#, RI (internal), and DCD2#) are cut off and the four modem control outputs (DTR2#, RTS2#, OUT1 (internal), and OUT2 (internal)) are internally connected to the corresponding modem control inputs. The modem control output pins are forcibly set as inactive (high level). During this kind of loopback mode, transmitted data can be immediately and directly received. When in loopback mode, both transmit and receive interrupts can be used. The interrupt sources are external sources in relation to the transmit and receive blocks. Although modem control interrupts can be used, the loworder four bits of the modem control register can be used instead of the four modem control inputs as interrupt sources. As usual, each interrupt is controlled by an interrupt enable register.
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20.3.10 SIULS_2 (0x0C00 0005)
Bit Name R/W RTCRST Other resets 7 LSR7 R 0 0 6 LSR6 R 1 1 5 LSR5 R 1 1 4 LSR4 R 0 0 3 LSR3 R 0 0 2 LSR2 R 0 0 1 LSR1 R 0 0 0 LSR0 R 0 0
Bit 7 LSR7
Name Error detection (FIFO mode)
Function
1 : Parity error, framing error, or break is detected. 0 : No error 6 LSR6 Transmit block empty 1 : No data in transmit holding register and transmit shift register No data in transmit FIFO (during FIFO mode) 0 : Data exists in transmit holding register or transmit shift register Data exists in transmit FIFO (during FIFO mode) 5 LSR5 Transmit holding register empty 1 : Character is transferred to transmit shift register (during 16450 mode) Transmit FIFO is empty (during FIFO mode) 0 : Character is stored in transmit holding register (during 16450 mode) Transmit data exists in transmit FIFO (during FIFO mode) 4 LSR4 Break interrupt 1 : Detected 0 : No break 3 LSR3 Framing error 1 : Detected 0 : No error 2 LSR2 Parity error 1 : Detected 0 : No error 1 LSR1 Overrun error 1 : Detected (receive data is overwritten) 0 : No error 0 LSR0 Receive data ready 1 : Receive data exists in FIFO 0 : No receive data in FIFO
The CPU uses this register to get information related to data transfers. When LSR7 and LSR(4:1) bits are 1, reading this register clears these bits to 0. Caution The LSR0 bit (receive data ready bit) is set before the serial data reception is completed. Therefore, the LSR0 bit may not be cleared if the serial receive data is read from the SIURB_2 register immediately after this bit is set. When reading data from the SIURB_2 register, wait for the stop bit width time since the LSR0 bit is set.
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LSR7 bit is valid only in FIFO mode, and it indicates always 0 in 16450 mode. The value of LSR4 bit becomes 1 when the spacing status (0) of receive data input is held longer than the time required for transmission of one word (start bit + data bits + parity bit + stop bit). When in FIFO mode, if a break is detected for one character in the FIFO, the character is regarded as an error character and the CPU is notified of a break when that character reaches the highest position in the FIFO. When a break occurs, one "zero" character is sent to the FIFO. When the RxD2 enters marking status, and the next valid start bit is received, the next character can be transmitted. The value of LSR3 bit becomes 1 when a zero (spacing level) stop bit is detected following the final data bit or parity bit. When in FIFO mode, if a framing error is detected for one character in the FIFO, the character is regarded as an error character and the CPU is notified of a framing error when that character reaches the highest position in the FIFO. When a framing error occurs, the SIU2 prepares for synchronization again. The next start bit is assumed to be the cause of the framing error and the next data is not accepted until the next start bit has been sampled twice. The value of LSR2 bit becomes 1 when a received character does not satisfy the even or odd parity specified in the LCR4 bit. When in FIFO mode, if a parity error is detected for one character within the FIFO, the character is regarded as an error character and the CPU is notified of a parity error when that character reaches the highest position in the FIFO. The value of LSR1 bit becomes 1 when a character is transferred to the receive buffer register before reading by the CPU and the previous character is lost. When in FIFO mode, if the data continues to be transferred to the FIFO though it exceeds the trigger level, even after the FIFO becomes full an overrun error will not occur until all characters are stored in the shift register. The CPU is notified as soon as an overrun error occurs. The characters in the shift register are overwritten and are not transferred to the FIFO.
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20.3.11 SIUMS_2 (0x0C00 0006)
Bit Name R/W RTCRST Other resets 7 MSR7 R Undefined Undefined 6 MSR6 R Undefined Undefined 5 MSR5 R Undefined Undefined 4 MSR4 R Undefined Undefined 3 MSR3 R/W 0 0 2 MSR2 R/W 0 0 1 MSR1 R/W 0 0 0 MSR0 R/W 0 0
Bit 7 MSR7
Name DCD2# signal status 1 : Low level 0 : High level
Function
6
MSR6
RI signal (internal) status 1 : Low level 0 : High level
5
MSR5
DSR2# input status 1 : Low level 0 : High level
4
MSR4
CTS2# input status 1 : Low level 0 : High level
3
MSR3
DCD2# signal change 1 : Changed 0 : No change
2
MSR2
RI signal (internal) change 1 : Changed 0 : No change
1
MSR1
DSR2# signal change 1 : Changed 0 : No change
0
MSR0
CTS2# signal change 1 : Changed 0 : No change
This register indicates the current status and change in status of various control signals that are input to the CPU from a modem or other peripheral device. The MSR(3:0) bits are cleared to 0 if they are read when they are set to 1.
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20.3.12 SIUSC_2 (0x0C00 0007)
Bit Name R/W RTCRST Other resets 7 SCR7 R/W Undefined Undefined 6 SCR6 R/W Undefined Undefined 5 SCR5 R/W Undefined Undefined 4 SCR4 R/W Undefined Undefined 3 SCR3 R/W Undefined Undefined 2 SCR2 R/W Undefined Undefined 1 SCR1 R/W Undefined Undefined 0 SCR0 R/W Undefined Undefined
Bit 7 to 0 SCR(7:0)
Name General-purpose data
Function
This register is a readable/writable 8-bit register, and can be used freely by users. It does not affect control of the SIU2. 20.3.13 SIUIRSEL_2 (0x0C00 0008)
Bit Name R/W RTCRST Other resets 7 Reserved R 0 0 6 Reserved R 0 0 5 Reserved R/W 0 0 4 Reserved R 0 0 3 Reserved R/W 0 0 2 Reserved R/W 0 0 1 Reserved R 0 0 0 SIRSEL R/W 0 0
Bit 7, 6 5 4 3, 2 1 0 Reserved Reserved Reserved Reserved Reserved SIRSEL
Name 0 is returned when read
Function
Write 0 when write. 0 is returned when read. 0 is returned when read Write 0 when write. 0 is returned when read. 0 is returned when read Selects communication format 1 : IrDA 0 : RS-232-C
This register is used to set the SIU2's communication format (IrDA or RS-232-C). To use the IrDA format, an external IrDA module must be connected.
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20.3.14 SIURESET_2 (0x0C00 0009)
Bit Name 7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 SIU RESET R/W 0 0
R/W RTCRST Other resets
R 0 0
R 0 0
R 0 0
R 0 0
R 0 0
R 0 0
R 0 0
Bit 7 to 1 0 Reserved
Name 0 is returned when read SIU2 reset 1 : Reset 0 : Release reset
Function
SIURESET
This register is used to reset SIU2 forcibly. 20.3.15 SIUCSEL_2 (0x0C00 000A)
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 Reserved R 0 0
4 Reserved R 0 0
3 Reserved R 0 0
2 Reserved R 0 0
1 Reserved R 0 0
0 SIUCSEL R/W 0 0
Bit 7 to 1 0 Reserved SIUCSEL
Name 0 is returned when read Mask for echo back of IrDA 1 : Mask disabled 0 : Mask enabled (echo-back mode)
Function
This register is used to specify whether the use of echo back function on IrDA transmission and reception is enabled.
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20.3.16 SIUACTMSK_2 (0x0C00 000C)
Bit Name R/W RTCRST Other resets
7 Reserved R 0 0
6 Reserved R 0 0
5 RxDMSK R/W 0 0
4 RTSMSK R/W 0 0
3 DCDMSK R/W 0 0
2 DTRMSK R/W 0 0
1 Reserved R/W 0 0
0 TxWRMSK R/W 0 0
Bit 7, 6 5 Reserved RxDMSK
Name 0 is returned when read
Function
Mask for notification of change on RxD2 1 : Mask 0 : Unmask
4
RTSMSK
Mask for notification of change on RTS2# 1 : Mask 0 : Unmask
3
DCDMSK
Mask for notification of change on DCD2# 1 : Mask 0 : Unmask
2
DTRMSK
Mask for notification of change on DTR2# 1 : Mask 0 : Unmask
1 0
Reserved TxWRMSK
Write 0 when write. 0 is returned when read Mask for notification of transmit buffer write 1 : Mask 0 : Unmask
This register is used to set masks for notification of operation statuses to the Activity Timer of the SIU2. When 1 is set in this register, state transition of the corresponding signals or write to transmit buffer is not notified to the Activity Timer.
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20.3.17 SIUACTTMR_2 (0x0C00 000E)
Bit Name R/W RTCRST Other resets 7 SIUTMO7 R/W 0 0 6 SIUTMO6 R/W 0 0 5 SIUTMO5 R/W 0 0 4 SIUTMO4 R/W 0 0 3 SIUTMO3 R/W 0 0 2 SIUTMO2 R/W 0 0 1 SIUTMO1 R/W 0 0 0 SIUTMO0 R/W 0 0
Bit 7 to 0
Name SIUTMO(7:0) SIU activity timeout period 11111111 : 255 x 30.5 s 11111110 : 254 x 30.5 s : 01111111 : 127 x 30.5 s : 00000001 : 30.5 s 00000000 : Activity Timer disabled
Function
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21.1 Overview
The VR4181 includes an LCD control module that operates on the MBA bus under the Unified Memory Architecture (UMA) conventions. The frame buffer resides in the main DRAM memory. This module supports an STN LCD panel. 21.1.1 LCD interface The VR4181 LCD controller is a UMA based controller and uses a part of DRAM memory as a frame buffer. The LCD controller supports monochrome STN LCD panels having 4-bit data bus interfaces and color STN LCD panels having 8-bit data bus interfaces. When interfacing to a color LCD panel, GPIO pins must be allocated to provide the upper nibble of the 8-bit LCD data bus. In monochrome mode, the LCD controller supports 1-bpp (bit per pixel) mode (mono), 2-bpp mode (4 gray levels) and 4-bpp mode (16 gray levels). In color mode, the LCD controller supports 4-bpp mode (16 colors) and 8-bpp mode (256 colors). The LCD controller includes a 256-entry x 18-bit color pallet. In color 8-bpp mode, the pallet is used to select 256 colors out of possible 262,144 colors. The LCD controller can support up to 320 x 320 pixels, and typical LCD panel horizontal/vertical resolutions are as follows. Table 21-1. LCD Panel Resolutions (in Pixels, TYP.)
Horizontal resolution 320 320 320 240 240 240 160 160 160 Vertical resolution 320 240 160 320 240 160 320 240 160
The LCD controller also provides power-on and power-down sequence control for the LCD panel via the VPLCD pin, which is for LCD logic power control, and VPBIAS pin, which is for LCD bias power control. Power sequencing is provided to prevent latch-up damage to the panel. The LCD controller may be disabled to allow connection of an external LCDC with integrated frame buffer RAM such as NEC Electronics' PD16661. When the internal LCD controller is disabled by setting the LCDGPMODE register in the GIU, the SHCLK, LOCLK, VPLCD, and VPBIAS pins are redefined as follows:
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Table 21-2. Redefining LCD Interface Pins When LCD Controller Is Disabled
Redefined function LCDCS# MEMCS16# VPGPIO1 VPGPIO0 Default function SHCLK LOCLK VPLCD VPBIAS
21.2 LCD Module Features
* Resolutions Horizontal: Vertical: Color: Monochrome: Color Palette: Up to 320 pixels (the number of pixels must be multiplies of 8) Up to 320 pixels 4 bpp, 8 bpp (up to 256 colors) 1 bpp, 2 bpp, 4 bpp (up to 16 gray scale) 18 bits
* High vertical refresh rates for flicker-free LCD frame modulation The following is a block diagram of the LCD controller.
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Figure 21-1. LCD Controller Block Diagram
32
MBA memory controller
16
Bus interface unit
16 RAM
MGCLK
32 LCD Controller
MBAGP interface MGCLK 32 6R FIFOs Color lookup 6G 6B Pixel modulation 1R 1G 1B Pixel packing
18 MBA slave interface
Data (8 bits)
32
LCD registers
256 x 18 palette
Data (4 bits) Shift clock MBA clock Timing generator Load clock FLM GPU Data (4 bits) Shift clock Load clock FLM
Data (4 bits)
I/O pins
LCD interrupt request
The LCD controller is a slave module of the MBA bus. Its registers can be accessed via the MBA slave interface. The frame data are read from main memory via the memory controller and the MBAGP (MBA Graphic port).
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21.3 LCD Controller Specification
21.3.1 Panel configuration and interface (1) View rectangle and horizontal/vertical blank Most parameters of the LCD controller are described using a coordinate system. The x coordinate increases as a point moves to the right. The y coordinate increases as a point moves down. The origin is (0, 0). The size of the bounding box is specified by Vtotal and Htotal. The point (Vtotal-1, Htotal-1) is the box's lower right corner and includes the horizontal and vertical blanks. Vvisible and Hvisible define the view rectangle, and outside of the view rectangle are the horizontal blank and vertical blank. Figure 21-2. View Rectangle and Horizontal/Vertical Blank
Origin (0, 0)
(Hvisible-1, 0)
X
View rectangle (LCD panel)
Horizontal blank
(0, Vvisible-1) Vertical blank
(Hvisible-1, Vvisible-1)
(Htotal-1, Vtotal-1)
Y
Each parameter is defined using bit values in the LCD controller registers as follows: * Vtotal = Vtot(8:0) * Vvisible = Vact(8:0) * Htotal = Htot(7:0) x 2 * Hvisble = Hact(5:0) x 8 Caution VRTOTALREG (0x0A00 0408) VRVISIBREG (0x0A00 040A) HRTOTALREG (0x0A00 0400) HRVISIBREG (0x0A00 0402)
The following expressions must be satisfied. 1. Vtotal Vvisible 2. Htotal Hvisible + 6
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(2) Load clock The edge positions of the load clock, LOCLK, are programmable. Each row in the rectangle specified with (0, 0) and (Htotal-1, Vvisible-1) must have two LOCLK edges. The remaining rows in the frame rectangle form the vertical blank. These rows also have two LOCLK edges if the DummyL bit of the VRVISIBREG register is 1, or none if DummyL bit is 0. The first LOCLK edge is defined by the LCS(7:0) bits of the LDCLKSTREG register. The second edge is defined by the LCE(7:0) bits of the LDCLKENDREG register, and is usually inside the horizontal blank. The LPPOL bit of the LCDCTRLREG register controls the directions of toggles. If the LPPOL bit is 0, the first LOCLK edge is positive and the second is negative. If the LPPOL bit is 1, the reverse is true. Figure 21-3. Position of Load Clock (LOCLK)
Origin (0, 0)
(Hvisible-1, 0)
(Htotal-1, 0)
X
View rectangle
Horizontal blank
(0, Vvisible-1) Vertical blank (0, Vtotal-1)
Y (X = LCS x 2) LOCLK 1st edge 2nd edge (X = LCE x 2)
Caution
The following expression must be satisfied. 1. Htotal > LCE(7:0) x 2 > LCS(7:0) x 2
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(3) Frame clock The edge positions of the frame clock, FLM, are also programmable. There must be exactly two FLM edges inside the bounding box. The first FLM edge is defined by the FLMHS(7:0) bits of the FHSTARTREG register and the FLMS(8:0) bits of the FVSTARTREG register. The location of the first edge is at (FLMHS x 2, FLMS). The second FLM edge is defined by the FLMHE(7:0) bits of the FHENDREG register and the FLME(8:0) bits of the FVENDREG register. The location of second edge is at (FLMHE x 2, FLME). If the FLMPOL bit of the LCDCTRLREG register is 0, the first FLM edge is positive and the second is negative. If the FLMPOL bit is 1, the reverse is true. Figure 21-4. Position of Frame Clock (FLM)
Origin (0, 0)
(Hvisible-1, 0)
(Htotal-1, 0)
X
View rectangle
Horizontal blank
(0, Vvisible-1) Vertical blank (0, Vtotal-1)
(FLMHS x 2, FLMS) (FLMHE x 2, FLME)
Y
FLM 1st edge 2nd edge
Caution
The following expressions must be satisfied. 1. Htotal > FLMHE(7:0) x 2 > FLMHS(7:0) x 2 2. Vtotal > FLME(8:0), Vtotal > FLMS(8:0)
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(4) Shift clock The shift clock (SHCLK) edges can be programmed only indirectly. The SHCLK is also output in rows of the vertical blank if the DummyL bit of the VRVISIBREG register is 1. The position of SHCLK edges are controlled by the Panelcolor and PanDbus bits of the LCDCFGREG0 register. The SCLKPOL bit of the LCDCTRLREG register determines whether data is latched into the panel on the rising or falling edges. If the SCLKPOL bit is 0, data is latched on the falling edges. (5) M signal Some panels also need a modulation signal, M, to operate properly. The modulation rate is controlled by MOD(7:0) bits of the LCDCFGREG0 register. If the MOD field is 0, the M signal toggles once per frame. If the MOD field is not 0, then the M signal toggles once every rows set in the MOD field. The M signal toggles at the position specified in the LCE field, the same time as the second LOCLK edge. When the MOD field is 0, the M signal toggles when the LOCLK latches the FLM. (6) Vertical retrace interrupt When the LCD controller goes through the vertical blank, a status signal bit VIReq of the LCDINRQREG register becomes 1. This signal can be configured to be polled or to generate an interrupt request. To enable the interrupt, set the MVIReq bit of the LCDIMSKREG register to 1. Once an interrupt request is generated, writing to the VIReq bit clears the interrupt request. However, the state of the VIReq bit changes to 0 only after the controller returns to top left corner. Note that there is some delay between the controller's entering or leaving the vertical blank and the changes in the VIReq bit. 21.3.2 Controller clocks All LCD controller timing is based on the internal clock hpck. The hpck is derived from the gclk, which is derived from the MBA clock (TClock). The frequency of gclk can be equal to, one-half of, or one-quarter of that of the MBA clock, depending on the Pre-scal(1:0) bits of the LCDCFGREG0 register and the MBA clock frequency. The hpck frequency is programmable. In each cycle the hpck is at high level for cycles set in the HpckH(5:0) bits of the LCDCFGREG1 register, and at low level for cycles set in the HpckL(5:0) bits of the LCDCFGREG1 register. The values in HpckH and HpckL fields are not arbitrary. Their sum must be at least 5, and the following condition must be satisfied: f-hpck Htotal x Vtotal x f-refresh Both the hpck and the gclk can be turned off when the panel is inactive. Setting the ContCkE bit of the LCDCTRLREG register to 1 initializes the LCD controller and turns on both clocks, or 0 turns them off.
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21.3.3 Palette The Col(1:0) bits of the LCDCFGREG0 register indicate the desired color depth. If they are set to 0, then a monochrome image can be displayed on a monochrome panel. If they are set 1, then a 4-shade gray scale image can be displayed on a monochrome panel. If they are set to 2 or 3, then a palette is enabled, and a color panel can be used. The palette has 256 entries. Each entry has 18 bits and is 6-6-6 format for the RGB color. To access an entry first store its index in the PalIndex(7:0) bits of the CPINDCTREG register, then read from or write to the PalData(17:0) bits of the CPALDATREG register. To accelerate continuous accesses, the PalRDI bit or the PalWRI bit of the CPINDCTREG register can be set to 1. When the PalRDI bit is set to 1, the LCD controller automatically adds 1 to the PalIndex(7:0) bits of the CPINDCTREG register after reading from the PalData field; when the PalWRI bit is set to 1, the LCD controller automatically adds 1 to the PalIndex(7:0) bits after writing to the PalData field. If the Col field is set to 2, then the pixel data provides only the lower half of the palette index. The upper half is provided by the PalPage(3:0) bits of the CPINDCTREG register. Together they specify one entry in the palette. Finally, the hpck and the gclk must be turned on before the palette is accessed. 21.3.4 Frame buffer memory and FIFO The frame buffer is linear and supports a packed pixel format. The length of a scan line must be a multiple of 32. The last double word of a scan line need not be completely filled. The pixels are stored in double words. The data format of each double word depends on the color depth, as shown in the following table.
Bit 31 Bit 0
18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 14 15 16 17 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07 0C 06 03 0D 0E 07 0F 08 04 02 09 0A 05 0B 04 02 01 05 06 03 07 00 00 00 01 02 01 03
The frame buffer memory starts from the 32-bit address specified by the FBSA(31:0) bits of the FBSTADREG1 and FBSTADREG2 registers, and ends at the address specified by the FBEA(31:0) bits of the FBENDADREG1 and FBENDADREG2 registers. The FBEA field does not necessarily show where the last pixel is stored; but it is the address of the first 32-byte page boundary that follows the memory location where the last pixel is stored, starting from the address set in the FBSA field. For example, if FBSA field is 0x0B00 0408, and the frame buffer occupies 235 bytes, then the FBEA field is 0x0B00 0508 (FBSA plus the ceiling of 235/32). Data from the frame buffer is burst into the FIFO to conserve memory bandwidth. Each burst transfers 32 bytes. The FIFO is divided into three arrays, and each burst fills exactly one array. Bursts can not cross array borders, nor can read from and write to the same array at the same time. When the memory bandwidth is low, the FIFO bursts only when there are only the number of double words left to be read that is displayed in the FIFOC(2:0) bits of the LCDCTRLREG register. If the burst is not fast enough in relation to the refresh rate of the panel image, irreversible image degradation occurs due to a lack of data to be displayed, and an interrupt request is generated. This interrupt request can be polled from the FIFOOVERR bit of the LCDINRQREG register. It can be cleared only by stopping and then restarting controller clocks. Because image degradation is a serious problem, the value set to the FIFOC field should be carefully selected during development.
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21.3.5 Panel power ON/OFF sequence Some panels use several power supplies, and these supplies and interface logic signals must be turn on or off in sequences specified by the manufacturers. The LCD controller has signals to control these power supplies. Each power supply is controlled via the VPBIAS or VPLCD pin. These pins are connected to a pull-up or pull-down resistor in addition to the power supply. When the power is off, these pins are placed into high impedance, so that the resistor pulls the power supply on/off input to the off state. The power-on/off sequence is started by setting the PowerC bit of the PWRCONREG2 register. Setting this bit to 1 starts the power-on sequence. In the power-on sequence the power supply control pins are brought out of high impedance to a programmed state at a programmed time, and the panel interface signals become active at a programmed time. The following table lists the control pins and the programming register bits.
Pin VPBIAS VPLCD LCD Interface Power-on time bit Biason(4:0) Vccon(4:0) I/Fon(4:0) Power-on state bit BiasCon VccC - (active)
For example, storing 1 in the BiasCon bit and 3 in the Biason field brings the LCD controller to make the VPBIAS signal from high impedance to high level three frames after the PowerC bit is set to 1, not counting the frame in which the PowerC bit is changed. Setting the PowerC bit to 0 starts the power-off sequence. In the power-off sequence the control pins are put into high impedance, so that the power supply is turned off. The pins enter high impedance in the reverse order of the power-on sequence, but the time delay between the two control pins remains the same.
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21.3.6 Operation of LCD controller Figure 21-5. Monochrome Panel
LOCLK (Output) SHCLK (Output) FPD3 (Output) FPD2 (Output) FPD1 (Output) FPD0 (Output)
W-4
0
4
8
W-4
0
4
W-3
1
5
9
W-3
1
5
W-2
2
6
10
W-2
2
6
W-1
3
7
11
W-1
3
7
SHCLK x W/4 pulses
Remark W: panel width (Hact(5:0) x 8)
The polarity (order of rising and falling edges) of the LOCLK and the SHCLK are programmable via the LPPOL and SCLKPOL bits.
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Figure 21-6. Color Panel in 8-Bit Data Bus
LOCLK (Output) SHCLK (Output) FPD3 (Output) FPD2 (Output) FPD1 (Output) FPD0 (Output) FPD7 (Output) FPD6 (Output) FPD5 (Output) FPD4 (Output)
W-3G
0R
2B
5G
W-3G
0R
2B
W-3B
0G
3R
5B
W-3B
0G
3R
W-2R
0B
3G
6R
W-2R
0B
3G
W-2G
1R
3B
6G
W-2G
1R
3B
W-2B
1G
4R
6B
W-2B
1G
4R
W-1R
1B
4G
7R
W-1R
1B
4G
W-1G
2R
4B
7G
W-1G
2R
4B
W-1B
2G
5R
7B
W-1B
2G
5R
SHCLK x W x 3/8 pulses
Remark W: panel width (Hact(5:0) x 8)
The polarity (order of rising and falling edges) of the LOCLK and the SHCLK are programmable via the LPPOL and SCLKPOL bits. Remark In the color 8-bit data bus mode, FPD(3:0) are for upper 4 bits of the LCD data bus, and FPD(7:4) are for lower 4 bits of the LCD data bus.
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Figure 21-7. Load Clock (LOCLK)
LOCLK (Output)
Pixel row
TH-1
0
1
H-1
H
TH-1
0
LOCLK x H pulses
LOCLK x (TH-H) pulses
Remark
H: panel height (Vact) TH: panel height + dummy lines (Vtotal)
Remark
Dummy lines are inserted when needed. For example, some panels can display only 240 lines, but has 242 line cycles. Load clock can be deactivated during the dummy lines (see DummyL bit description in 21.4.6). Figure 21-8. Frame Clock (FLM)
FLM (Output)
Pixel row
TH-1
0
YE
YS
TH-1
0
XE
XS
Remark
YS: Y-Coordinates of the second FLM edge (FLMS) YE: Y-Coordinates of the first FLM edge (FLME)
The polarity (order of rising and falling edges) of the FLM is programmable via the FLMPOL bit.
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Figure 21-9. LCD Timing Parameters
LOCLK (Output)
T6 T7 FLM (Output)
T8 T9 SHCLK (Output) T1 T2 T5 FPD(7:0) (Output) 0 1 ... W-2, W-1 Invalid 0
T3
T4
The polarity of the FLM is programmable through the FLMPOL bit. In this diagram the first edge is a rising edge. The two FLM edges are on the same row in this diagram, but they need not be. The active edge of the LOCLK is programmable through the LPPOL bit. In this diagram, the first edge is a rising edge (the falling edge is the active edge). The polarity of the SHCLK is programmable through the SCLKPOL bit. In this diagram, the first edge is a rising edge (the falling edge is the active edge). Figure 21-10. FLM Period
FLM (Output) T10
The definitions of parameters shown in the figures are given in the table below.
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Table 21-3. LCD Controller Parameters
Symbol Tg Definition gclk period This parameter is not one of the timing parameters, but all timing parameters is calculated based on this. gclk is controlled by the Pre-scal field. Tg = 1 / (frequency of gclk) T1 Shift clock high level width Color: T1 = Tg x HpckH 4-bit bus monochrome: T1 = Tg x (HpckH + HpckL) T2 Shift clock cycle Color: T2 = Tg x (HpckH + HpckL) 4-bit bus monochrome: T2 = Tg x (HpckH + HpckL) x 2 T3 Panel data setup time Color : T3 = Tg x HpckH 4-bit bus monochrome: T3 = Tg x (HpckH + HpckL) T4 Panel data hold time Color: T4 = Tg x HpckL 4-bit bus monochrome: T4 = Tg x (HpckH + HpckL) T5 Row cycle time T5 = Tg x (HpckH + HpckL) x Htot T6 Load clock start time T6 = Tg x (HpckH + HpckL) x LCS T7 Load clock end time T7 = Tg x (HpckH + HpckL) x LCE T8 FLM horizontal start time T8 = Tg x (HpckH + HpckL) x FLMHS T9 FLM horizontal end time T9 = Tg x (HpckH + HpckL) x FLMHE T10 Panel frame period T10 = Tg x (HpckH + HpckL) x Htot x Vtot
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21.4 Register Set
Table 21-4. LCD Controller Registers
Physical address 0x0A00 0400 0x0A00 0402 0x0A00 0404 0x0A00 0406 0x0A00 0408 0x0A00 040A 0x0A00 040C 0x0A00 040E 0x0A00 0410 0x0A00 0412 0x0A00 0414 0x0A00 0416 0x0A00 0418 0x0A00 041A 0x0A00 0420 0x0A00 0422 0x0A00 0424 0x0A00 0426 0x0A00 0430 0x0A00 0432 0x0A00 0434 0x0A00 047E 0x0A00 0480 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register symbol HRTOTALREG HRVISIBREG LDCLKSTREG LDCLKENDREG VRTOTALREG VRVISIBREG FVSTARTREG FVENDREG LCDCTRLREG LCDINRQREG LCDCFGREG0 LCDCFGREG1 FBSTADREG1 FBSTADREG2 FBENDADREG1 FBENDADREG2 FHSTARTREG FHENDREG PWRCONREG1 PWRCONREG2 LCDIMSKREG CPINDCTREG CPALDATREG Horizontal total register Horizontal visible register Load clock start register Load clock end register Vertical total register Vertical visible register FLM vertical start register FLM vertical end register LCD control register LCD interrupt request register LCD configuration register 0 LCD configuration register 1 Frame buffer start address 1 register Frame buffer start address 2 register Frame buffer end address 1 register Frame buffer end address 2 register FLM horizontal start register FLM horizontal end register Power control register 1 Power control register 2 LCD interrupt mask register Color palette index and control register Color palette data register (32 bits wide) Function
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21.4.1 HRTOTALREG (0x0A00 0400)
Bit Name R/W Reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 Reserved R 0
Bit Name R/W Reset
7 Htot7 R/W 0
6 Htot6 R/W 0
5 Htot5 R/W 0
4 Htot4 R/W 0
3 Htot3 R/W 0
2 Htot2 R/W 0
1 Htot1 R/W 0
0 Htot0 R/W 0
Bit 15 to 8 7 to 0 Reserved Htot(7:0)
Name 0 is returned when read
Function
Number of horizontal total columns. Set this register to a value one half of the horizontal total. Horizontal total = horizontal visible width + horizontal blank
21.4.2 HRVISIBREG (0x0A00 0402)
Bit Name R/W Reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 Reserved R 0
Bit Name R/W Reset
7 Reserved R 0
6 Reserved R 0
5 Hact5 R/W 0
4 Hact4 R/W 0
3 Hact3 R/W 0
2 Hact2 R/W 0
1 Hact1 R/W 0
0 Hact0 R/W 0
Bit 15 to 6 5 to 0 Reserved Hact(5:0)
Name 0 is returned when read
Function
Number of horizontal visible pixels. Set this register to a value one eighth of the horizontal visible pixels.
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21.4.3 LDCLKSTREG (0x0A00 0404)
Bit Name R/W Reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 Reserved R 0
Bit Name R/W Reset
7 LCS7 R/W 0
6 LCS6 R/W 0
5 LCS5 R/W 0
4 LCS4 R/W 0
3 LCS3 R/W 0
2 LCS2 R/W 0
1 LCS1 R/W 0
0 LCS0 R/W 0
Bit 15 to 8 7 to 0 Reserved LCS(7:0)
Name 0 is returned when read
Function
X coordinate of the first edge of the LOCLK. Set this register to a value one half of the first edge of the LOCLK.
21.4.4 LDCLKENDREG (0x0A00 0406)
Bit Name R/W Reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 Reserved R 0
Bit Name R/W Reset
7 LCE7 R/W 0
6 LCE6 R/W 0
5 LCE5 R/W 0
4 LCE4 R/W 0
3 LCE3 R/W 0
2 LCE2 R/W 0
1 LCE1 R/W 0
0 LCE0 R/W 0
Bit 15 to 8 7 to 0 Reserved LCE(7:0)
Name 0 is returned when read
Function
X coordinate of the second edge of the LOCLK. Set this register to a value one half of the second edge of the LOCLK.
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21.4.5 VRTOTALREG (0x0A00 0408)
Bit Name R/W Reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 Vtot8 R/W 0
Bit Name R/W Reset
7 Vtot7 R/W 0
6 Vtot6 R/W 0
5 Vtot5 R/W 0
4 Vtot4 R/W 0
3 Vtot3 R/W 0
2 Vtot2 R/W 0
1 Vtot1 R/W 0
0 Vtot0 R/W 0
Bit 15 to 9 8 to 0 Reserved Vtot(8:0)
Name 0 is returned when read
Function
Vertical total number of lines including vertical retrace period
21.4.6 VRVISIBREG (0x0A00 040A)
Bit Name R/W Reset 15 DummyL R/W 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 Vact8 R/W 0
Bit Name R/W Reset
7 Vact7 R/W 0
6 Vact6 R/W 0
5 Vact5 R/W 0
4 Vact4 R/W 0
3 Vact3 R/W 0
2 Vact2 R/W 0
1 Vact1 R/W 0
0 Vact0 R/W 0
Bit 15 DummyL
Name Dummy line inserting position
Function
0 : Immediately before vertical blank 1 : Anywhere in vertical blank 14 to 9 8 to 0 Reserved Vact(8:0) 0 is returned when read Vertical visible number of lines
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21.4.7 FVSTARTREG (0x0A00 040C)
Bit Name R/W Reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 FLMS8 R/W 0
Bit Name R/W Reset
7 FLMS7 R/W 0
6 FLMS6 R/W 0
5 FLMS5 R/W 0
4 FLMS4 R/W 0
3 FLMS3 R/W 0
2 FLMS2 R/W 0
1 FLMS1 R/W 0
0 FLMS0 R/W 0
Bit 15 to 9 8 to 0 Reserved FLMS(8:0)
Name 0 is returned when read Y coordinate of the first FLM edge
Function
21.4.8 FVENDREG (0x0A00 040E)
Bit Name R/W Reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 FLME8 R/W 0
Bit Name R/W Reset
7 FLME7 R/W 0
6 FLME6 R/W 0
5 FLME5 R/W 0
4 FLME4 R/W 0
3 FLME3 R/W 0
2 FLME2 R/W 0
1 FLME1 R/W 0
0 FLME0 R/W 0
Bit 15 to 9 8 to 0 Reserved FLME(8:0)
Name 0 is returned when read
Function
Y coordinate of the second FLM edge
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21.4.9 LCDCTRLREG (0x0A00 0410)
Bit Name R/W Reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 Reserved R 0
Bit Name R/W Reset
7 FIFOC2 R/W 0
6 FIFOC1 R/W 0
5 FIFOC0 R/W 0
4 Reserved R 0
3 ContCkE R/W 0
2 LPPOL R/W 0
1 FLMPOL R/W 0
0 SCLKPOL R/W 0
Bit 15 to 8 7 to 5 Reserved FIFOC(2:0)
Name 0 is returned when read
Function
FIFO control. A FIFO transfer is performed when only the number of double words set here is left in the FIFO. 0 is returned when read LCD controller clock enable 0 : OFF 1 : ON
4 3
Reserved ContCkE
2
LPPOL
LOCLK clock polarity 0 : Leading edge is rising 1 : Leading edge is falling
1
FLMPOL
FLM clock polarity 0 : Leading edge is rising 1 : Leading edge is falling
0
SCLKPOL
Shift clock polarity 0 : Leading edge is rising (active edge is falling) 1 : Leading edge is falling (active edge is rising)
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21.4.10 LCDINRQREG (0x0A00 0412)
Bit Name R/W Reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 Reserved R 0
Bit Name
7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 Reserved
2 VIReq
1 FIFOOV ERR R/W 0
0 Reserved
R/W Reset
R 0
R 0
R 0
R 0
R 0
R/W 0
R 0
Bit 15 to 3 2 Reserved VIReq
Name 0 is returned when read Vertical retrace interrupt request
Function
0 : No request (outside vertical blank) 1 : Requested (vertical blank) 1 FIFOOVERR FIFO overrun interrupt request 0 : No request 1 : Requested 0 Reserved 0 is returned when read
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21.4.11 LCDCFGREG0 (0x0A00 0414)
Bit Name R/W Reset 15 MOD7 R/W 0 14 MOD6 R/W 0 13 MOD5 R/W 0 12 MOD4 R/W 0 11 MOD3 R/W 0 10 MOD2 R/W 0 9 MOD1 R/W 0 8 MOD0 R/W 0
Bit Name R/W Reset
7 Softreset R/W 0
6 Reserved R 0
5 Pre-scal1 R/W 0
4 Pre-scal0 R/W 0
3 Col1 R/W 0
2 Col0 R/W 0
1 Panelcolor R/W 0
0 PanDbus R/W 0
Bit 15 to 8 MOD(7:0)
Name
Function LCD M signal configuration. These bits specify the number of lines between M toggles. 0 : Once per frame 1 : After every line 2 : After every 2 lines : 255 : After every 255 lines
7
Softreset
Software reset for LCD controller. The software reset is active only in test mode. 0 : Normal operation 1 : Reset
6 5, 4
Reserved Pre-scal(1:0)
0 is returned when read gclk (clock for LCD controller) pre-scalar mode to the MBA clock 00 : Divide by 1 01 : Divide by 2 10 : Divide by 4 11 : RFU
3, 2
Col(1:0)
Color depth selection 00 : 1 bit (black and white for monochrome panel) 01 : 2 bits (4 gray scale for monochrome panel) 10 : 4 bits (16 gray scale for monochrome or 16 colors for color panel) 11 : 8 bits (256 colors for color panel)
1
Panelcolor
Color/monochrome selection 0 : Color 1 : Monochrome
0
PanDbus
Panel data width 0 : 4 bits 1 : 8 bits (for dual scan panel or for 8-bit high scan)
Remark
In the 4 bpp mode (16 gray scale) for monochrome panels, the Blue area of the color palette is used for displaying. The palette is not used in the other modes (1 bpp and 2 bpp) for monochrome panels.
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21.4.12 LCDCFGREG1 (0x0A00 0416)
Bit Name R/W Reset 15 Reserved R 0 14 Reserved R 0 13 HpckL5 R/W 0 12 HpckL4 R/W 0 11 HpckL3 R/W 0 10 HpckL2 R/W 0 9 HpckL1 R/W 0 8 HpckL0 R/W 0
Bit Name R/W Reset
7 Reserved R 0
6 Reserved R 0
5 HpckH5 R/W 0
4 HpckH4 R/W 0
3 HpckH3 R/W 0
2 HpckH2 R/W 0
1 HpckH1 R/W 0
0 HpckH0 R/W 0
Bit 15, 14 13 to 8 7, 6 5 to 0 Reserved HpckL(5:0) Reserved HpckH(5:0)
Name 0 is returned when read
Function
Number of gclk cycles for hpck low level width 0 is returned when read Number of gclk cycles for hpck high level width
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21.4.13 FBSTADREG1 (0x0A00 0418)
Bit Name R/W Reset 15 FBSA15 R/w 0 14 FBSA14 R/W 0 13 FBSA13 R/W 0 12 FBSA12 R/W 0 11 FBSA11 R/W 0 10 FBSA10 R/W 0 9 FBSA9 R/W 0 8 FBSA8 R/W 0
Bit Name R/W Reset
7 FBSA7 R/W 0
6 FBSA6 R/W 0
5 FBSA5 R/W 0
4 FBSA4 R/W 0
3 FBSA3 R/W 0
2 FBSA2 R/W 0
1 FBSA1 R/W 0
0 FBSA0 R/W 0
Bit 15 to 0
Name FBSA(15:0)
Function Frame buffer start address (lower 16 bits)
Caution
FBSA(2:0) bits must be cleared to 0.
21.4.14 FBSTADREG2 (0x0A00 041A)
Bit Name R/W Reset 15 FBSA31 R 0 14 FBSA30 R 0 13 FBSA29 R 0 12 FBSA28 R/W 0 11 FBSA27 R/W 0 10 FBSA26 R/W 0 9 FBSA25 R/W 0 8 FBSA24 R/W 0
Bit Name R/W Reset
7 FBSA23 R/W 0
6 FBSA22 R/W 0
5 FBSA21 R/W 0
4 FBSA20 R/W 0
3 FBSA19 R/W 0
2 FBSA18 R/W 0
1 FBSA17 R/W 0
0 FBSA16 R/W 0
Bit 15 to 0
Name FBSA(31:16)
Function Frame buffer start address (upper 16 bits) FBSA(31:29) are always 0 when read.
The FBSTADREG1 and FBSTADREG2 registers are used to specify the frame buffer starting address. The frame buffer is linear and the pixels are packed. This address corresponds to the first, top left pixel of the screen.
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21.4.15 FBENDADREG1 (0x0A00 0420)
Bit Name R/W Reset 15 FBEA15 R/W 0 14 FBEA14 R/W 0 13 FBEA13 R/W 0 12 FBEA12 R/W 0 11 FBEA11 R/W 0 10 FBEA10 R/W 0 9 FBEA9 R/W 0 8 FBEA8 R/W 0
Bit Name R/W Reset
7 FBEA7 R/W 0
6 FBEA6 R/W 0
5 FBEA5 R/W 0
4 FBEA4 R/W 0
3 FBEA3 R/W 0
2 FBEA2 R/W 0
1 FBEA1 R/W 0
0 FBEA0 R/W 0
Bit 15 to 0
Name FBEA(15:0)
Function Frame buffer end address (lower 16 bits)
21.4.16 FBENDADREG2 (0x0A00 0422)
Bit Name R/W Reset 15 FBEA31 R 0 14 FBEA30 R 0 13 FBEA29 R 0 12 FBEA28 R/W 0 11 FBEA27 R/W 0 10 FBEA26 R/W 0 9 FBEA25 R/W 0 8 FBEA24 R/W 0
Bit Name R/W Reset
7 FBEA23 R/W 0
6 FBEA22 R/W 0
5 FBEA21 R/W 0
4 FBEA20 R/W 0
3 FBEA19 R/W 0
2 FBEA18 R/W 0
1 FBEA17 R/W 0
0 FBEA16 R/W 0
Bit 15 to 0
Name FBEA(31:16)
Function Frame buffer end address (upper 16 bits) FBEA(31:29) are always 0 when read.
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21.4.17 FHSTARTREG (0x0A00 0424)
Bit Name R/W Reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 Reserved R 0
Bit Name R/W Reset
7 FLMHS7 R/W 0
6 FLMHS6 R/W 0
5 FLMHS5 R/W 0
4 FLMHS4 R/W 0
3 FLMHS3 R/W 0
2 FLMHS2 R/W 0
1 FLMHS1 R/W 0
0 FLMHS0 R/W 0
Bit 15 to 8 7 to 0 Reserved
Name 0 is returned when read
Function
FLMHS(7:0)
X coordinate of the first FLM edge. Set this register to a value one half of the first edge of FLM.
21.4.18 FHENDREG (0x0A00 0426)
Bit Name R/W Reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 Reserved R 0
Bit Name R/W Reset
7 FLMHE7 R/W 0
6 FLMHE6 R/W 0
5 FLMHE5 R/W 0
4 FLMHE4 R/W 0
3 FLMHE3 R/W 0
2 FLMHE2 R/W 0
1 FLMHE1 R/W 0
0 FLMHE0 R/W 0
Bit 15 to 8 7 to 0 Reserved
Name 0 is returned when read
Function
FLMHE(7:0)
X coordinate of the second FLM edge. Set this register to a value one half of the second edge of FLM.
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21.4.19 PWRCONREG1 (0x0A00 0430)
Bit Name R/W Reset 15 Reserved R 0 14 Reserved R/W 0 13 Reserved R/W 0 12 Reserved R/W 0 11 Reserved R/W 0 10 Reserved R/W 0 9 Reserved R/W 0 8 Reserved R/W 0
Bit Name R/W Reset
7 Reserved R/W 0
6 Reserved R/W 0
5 Reserved R/W 0
4 Biason4 R/W 0
3 Biason3 R/W 0
2 Biason2 R/W 0
1 Biason1 R/W 0
0 Biason0 R/W 0
Bit 15 14 to 5 4 to 0 Reserved Reserved Biason(4:0)
Name 0 is returned when read
Function
Write 0 when write. 0 is returned when read Frame at which the bias voltage is turned on
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CHAPTER 21 LCD CONTROLLER
21.4.20 PWRCONREG2 (0x0A00 0432)
Bit Name R/W Reset 15 Testmode R/W 0 14 VccC R/W 0 13 Reserved R/W 0 12 Reserved R/W 0 11 BiasCon R/W 0 10 PowerC R/W 0 9 I/Fon4 R/W 0 8 I/Fon3 R/W 0
Bit Name R/W Reset
7 I/Fon2 R/W 0
6 I/Fon1 R/W 0
5 I/Fon0 R/W 0
4 Vccon4 R/W 0
3 Vccon3 R/W 0
2 Vccon2 R/W 0
1 Vccon1 R/W 0
0 Vccon0 R/W 0
Bit 15 Testmode
Name Test mode enable 0 : Normal operation 1 : Enters test mode
Function
14
VccC
Vcc (VPLCD) signal polarity control 0 : Active low 1 : Active high
13, 12 11
Reserved BiasCon
Write 0 when write. 0 is returned when read Bias (VPBIAS) signal polarity control 0 : Active low 1 : Active high
10
PowerC
Power control 0 : Off 1 : On
9 to 5 4 to 0
I/Fon(4:0) Vccon(4:0)
Frame at which the panel logic interface signals are turned on Frame at which the panel Vcc is turned on
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21.4.21 LCDIMSKREG (0x0A00 0434)
Bit Name R/W Reset 15 Reserved R 0 14 Reserved R 0 13 Reserved R 0 12 Reserved R 0 11 Reserved R 0 10 Reserved R 0 9 Reserved R 0 8 Reserved R 0
Bit Name
7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 Reserved
2 MVIReq
1 MFIFO OVERR R/W 0
0 Reserved
R/W Reset
R 0
R 0
R 0
R 0
R 0
R/W 0
R 0
Bit 15 to 3 2 Reserved MVIReq
Name 0 is returned when read Vertical retrace interrupt mask 0 : Mask 1 : Unmask
Function
1
MFIFOOVERR
FIFO overrun interrupt mask 0 : Mask 1 : Unmask
0
Reserved
0 is returned when read
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21.4.22 CPINDCTREG (0x0A00 047E)
Bit Name R/W Reset 15 PalPage3 R/W 0 14 PalPage2 R/W 0 13 PalPage1 R/W 0 12 PalPage0 R/W 0 11 Reserved R 0 10 Reserved R 0 9 PalRDI R/W 0 8 PalWRI R/W 0
Bit Name R/W Reset
7 PalIndex7 R/W 0
6 PalIndex6 R/W 0
5 PalIndex5 R/W 0
4 PalIndex4 R/W 0
3 PalIndex3 R/W 0
2 PalIndex2 R/W 0
1 PalIndex1 R/W 0
0 PalIndex0 R/W 0
Bit 15 to 12 11, 10 9
Name PalPage(3:0) Reserved PalRDI
Function Palette page select used in 4 bpp mode 0 is returned when read Palette index read status 0 : No change after read 1 : Incremented by 1 after read
8
PalWRI
Palette index write status 0 : No change after write 1 : Incremented by 1 after write
7 to 0
PalIndex(7:0)
Palette index
Remark
In the 4 bpp mode (16 gray scale) for monochrome panels, the Blue area of the color palette is used for displaying. The palette is not used in the other modes (1 bpp and 2 bpp) for monochrome panels.
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21.4.23 CPALDATREG (0x0A0 0480)
Bit Name R/W Reset 31 Reserved R 0 30 Reserved R 0 29 Reserved R 0 28 Reserved R 0 27 Reserved R 0 26 Reserved R 0 25 Reserved R 0 24 Reserved R 0
Bit Name R/W Reset
23 Reserved R 0
22 Reserved R 0
21 Reserved R 0
20 Reserved R 0
19 Reserved R 0
18 Reserved R 0
17 PalData17 R/W Undefined
16 PalData16 R/W Undefined
Bit Name R/W Reset
15 PalData15 R/W Undefined
14 PalData14 R/W Undefined
13 PalData13 R/W Undefined
12 PalData12 R/W Undefined
11 PalData11 R/W Undefined
10 PalData10 R/W Undefined
9 PalData9 R/W Undefined
8 PalData8 R/W Undefined
Bit Name R/W Reset
7 PalData7 R/W Undefined
6 PalData6 R/W Undefined
5 PalData5 R/W Undefined
4 PalData4 R/W Undefined
3 PalData3 R/W Undefined
2 PalData2 R/W Undefined
1 PalData1 R/W Undefined
0 PalData0 R/W Undefined
Bit 31 to 18 17 to 0 Reserved
Name 0 is returned when read Color palette data (6-6-6 format)
Function
PalData(17:0)
Caution
Do not change palette data during LCD display.
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CHAPTER 22 PLL PASSIVE COMPONENTS
The VR4181 requires several external passive components for proper operation, which are connected to VDD_PLL as illustrated in Figure 22-1. Figure 22-1. Example of Connection of PLL Passive Components
VDD_LOGIC
R VDD_PLL
VR4181
C1
C2
GND_PLL
GND_LOGIC
Remarks 1. Capacitors C1 and C2 and resistor R are mounted on the printed circuit board. 2. Since the value for the components depends upon the application system, the optimum values for each system should be decided after repeated experimentation.
It is essential to isolate the analog power and ground for the PLL circuit (VDD_PLL, GND_PLL) from the regular power and ground (VDD_LOGIC, GND_LOGIC). The following values are an example for each component. R = 100 C1 = 0.1 F C2 = 1.0 F
Since the optimum values for the filter components depend upon the application and the system noise environment, these values should be considered as starting points for further experimentation within your specific application. In addition, the choke (inductor: L) can be considered for use as an alternative to the resistor (R) for use in filtering the power supply.
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CHAPTER 23 COPROCESSOR 0 HAZARDS
The VR4110 CPU core avoids contention of its internal resources by causing a pipeline interlock in such cases as when the contents of the destination register of an instruction are used as a source in the succeeding instruction. Therefore, instructions such as NOP must not be inserted between instructions. However, interlocks do not occur on the operations related to the CP0 registers and the TLB. Therefore, contention of internal resources should be considered when composing a program that manipulates the CP0 registers or the TLB. The CP0 hazards define the number of NOP instructions that is required to avoid contention of internal resources, or the number of instructions unrelated to contention. This chapter describes the CP0 hazards. The CP0 hazards of the VR4110 CPU core are as or less stringent than those of the VR4000. Table 23-1 lists the Coprocessor 0 hazards of the VR4110 CPU core. Code that complies with these hazards will run without modification on the VR4000. The contents of the CP0 registers or the bits in the "Source" column of this table can be used as a source after they are fixed. The contents of the CP0 registers or the bits in the "Destination" column of this table can be available as a destination after they are stored. Based on this table, the number of NOP instructions required between instructions related to the TLB is computed by the following formula, and so is the number of instructions unrelated to contention: (Destination Hazard number of A) - [(Source Hazard number of B) + 1] As an example, to compute the number of instructions required between an MTC0 and a subsequent MFC0 instruction, this is: 5 - (3 + 1) = 1 instruction The CP0 hazards do not generate interlocks of pipeline. Therefore, the required number of instruction must be controlled by program.
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CHAPTER 23 COPROCESSOR 0 HAZARDS
Table 23-1. Coprocessor 0 Hazards
Operation Source Source name - CPU general-purpose register Index, TLB 3 2 No. of cycles Destination Destination name No. of cycles 5
MTC0 MFC0 TLBR
CPU general-purpose register - PageMask, EntryHi, EntryLo0, EntryLo1 TLB
5
TLBWI TLBWR TLBP ERET
Index or Random, PageMask, EntryHi, EntryLo0, EntryLo1 PageMask, EntryHi EPC or ErrorEPC, TLB Status
2
5
2 2 2 -
Index Status[EXL], Status[ERL]
6 4
CACHE Index Load Tag CACHE Index Store Tag CACHE Hit operations Coprocessor usable test Instruction fetch TagLo, TagHi, PErr
TagLo, TagHi, PErr - cache line - -
5
3
cache line Status[CU], [KSU], [EXL], [ERL] EntryHi[ASID], Status[KSU], [EXL], [ERL], [RE], Config[K0] TLB
3 2
5
2
2 - EPC, Status Cause, BadVAddr, Context, XContext 4 5
Instruction fetch exception
Interrupts
Cause[IP], Status[IM], [IE], [EXL], [ERL] EntryHi[ASID], Status[KSU], [EXL], [ERL], [RE], Config[K0], TLB Config[AD], [EP] WatchHi, WatchLo
2
- -
Load/Store
3
3 3 - - EPC, Status, Cause, BadVAddr, Context, XContext Status[TS] 5
Load/Store exception
TLB shutdown
2 (Inst.), 4 (Data)
Remark
Brackets indicate a bit name or a field name of registers.
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Cautions 1. If the setting of the K0 bit in the Config register is changed by executing an MTC0 instruction within the kseg0 or ckseg0 area, the change is reflected one to three instructions later from the MTC0 instruction. 2. The instruction following an MTC0 instruction must not be an MFC0 instruction. 3. The five instructions following an MTC0 instruction for the Status register that changes the KSU bit and sets the EXL and ERL bits may be executed in the new mode, and not kernel mode. This can be avoided by setting the EXL bit first, leaving the KSU bit set to kernel, and later changing the KSU bit. 4. If interrupts are disabled by setting the EXL bit in the Status register with an MTC0 instruction, an interrupt may occur immediately after the MTC0 instruction without change of the contents of the EPC register. This can be avoided by clearing the IE bit first, and later setting the EXL bit. 5. There must be two non-load, non-CACHE instructions between a store and a CACHE instruction directed to the same cache line to be stored. The status during execution of the following instruction for which CP0 hazards must be considered is described below. (1) MTC0 Destination: The completion of writing to a destination register (CP0) of MTC0. (2) MFC0 Source: (3) TLBR Source: The confirmation of the status of TLB and the Index register before the execution of TLBR. Destination: The completion of writing to a destination register (CP0) of TLBR. (4) TLBWI, TLBWR Source: The confirmation of a source register of these instructions and registers used to specify a TLB entry. Destination: The completion of writing to TLB by these instructions. (5) TLBP Source: The confirmation of the PageMask register and the EntryHi register before the execution of TLBP. Destination: The completion of writing the result of execution of TLBP to the Index register. (6) ERET Source: The confirmation of registers containing information necessary for executing ERET. Destination: The completion of the processor state transition by the execution of ERET. (7) CACHE Index Load Tag Destination: The completion of writing the results of execution of this instruction to the related registers. The confirmation of a source register (CP0) of MFC0.
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CHAPTER 23 COPROCESSOR 0 HAZARDS
(8) CACHE Index Store Tag Source: The confirmation of registers containing information necessary for executing this instruction.
(9) Coprocessor usable test Source: The confirmation of modes set by the bits of the CP0 registers in the "Source" column.
Examples 1. After the contents of the CU0 bit of the Status register are modified, when accessing the CP0 registers in User mode or when executing an instruction such as TLB instructions, CACHE instructions, or branch instructions that use the resource of the CP0. 2. When accessing the CP0 registers in the operating mode set in the Status register after the KSU, EXL, and ERL bits of the Status register are modified. (10) Instruction fetch Source: The confirmation of the operating mode and TLB necessary for instruction fetch.
Examples 1. When changing the operating mode from User to Kernel and fetching instructions after the KSU, EXL, and ERL bits of the Status register are modified. 2. When fetching instructions using the modified TLB entry after TLB modification. (11) Instruction fetch exception Destination: The completion of writing to registers containing information related to the exception when an exception occurs on instruction fetch. (12) Interrupts Source: The confirmation of registers judging the condition of occurrence of interrupt when an interrupt factor is detected. (13) Loads/sores Source: The confirmation of the operating mode related to the address generation of Load/Store instructions, TLB entries, the cache mode set in the K0 bit of the Config register, and the registers setting the condition of occurrence of a Watch exception. Example When Loads/Stores are executed in the kernel field after changing the mode from User to Kernel.
(14) Load/store exception Destination: The completion of writing to registers containing information related to the exception when an exception occurs on load or store operation. (15) TLB shutdown Destination: The completion of writing to the TS bit of the Status register when a TLB shutdown occurs.
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Table 23-2 indicates examples of calculation. Table 23-2. Calculation Example of CP0 Hazard and Number of Instructions Inserted
Contending internal resource TLB Entry TLB Entry TLB Entry Status [CU] Number of instructions inserted 2 1 2 2
Destination
Source
Formula
TLBWR/TLBWI TLBWR/TLBWI TLBWR/TLBWI MTC0, Status [CU]
TLBP Load or store using newly modified TLB Instruction fetch using newly modified TLB Coprocessor instruction that requires the setting of CU MFC0 EntryHi TLBWR/TLBWI MFC0 Index TLBP ERET ERET
Note
5 - (2 + 1) 5 - (3 + 1) 5 - (2 + 1) 5 - (2 + 1)
TLBR MTC0 EntryLo0 TLBP MTC0 EntryHi MTC0 EPC MTC0 Status MTC0 Status [IE]
EntryHi EntryLo0 Index EntryHi EPC Status Status [IE]
1 2 2 2 2 2 2
5 - (3 + 1) 5 - (2 + 1) 6 - (3 + 1) 5 - (2 + 1) 5 - (2 + 1) 5 - (2 + 1) 5 - (2 + 1)
Instruction that causes an interrupt
Note The number of hazards is undefined if the instruction execution sequence is changed by exceptions. In such a case, the minimum number of hazards until the IE bit value is confirmed may be the same as the maximum number of hazards until an interrupt request occurs that is pending and enabled. Remark Brackets indicate a bit name or a field name of registers.
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APPENDIX A RESTRICTIONS ON VR4181
A.1 RSTSW# During HALTimer Operation
The VR4181 ignores the RSTSW# signal even if it is asserted while the HALTimer is operating (counting). If the VR4181 is started while the RSTSW# signal is low, the RSTSW reset sequence is not executed and the VR4181 continues operating until the HALTimer is reset. Consequently, the operation of the VR4181 may differ from the operation of the external peripheral circuits when the RSTSW# signal is used as a reset signal to the external peripheral circuits. Particularly, when the reset signal to a flash memory that includes a boot vector and the RSTSW# signal are shared, the VR4181 may not be able to read the correct program and hang up for 4 seconds between when the VR4181 is started and when the HALTimer is shut down. [Workaround] Do not share the reset signal to the external peripheral circuits with the RSTSW# signal. However, if it is necessary to do so, insert a circuit like the one shown in the figure below to mask the RSTSW# signal between when the VR4181 is started and when the HALTimer is cleared, by using the GPIO pin. Figure A-1. Mask Circuit for RSTSW# Signal
Mask control (GPIO, etc.)
RSTSW# signal (original)
RSTSW# signal (for actual use)
To the VR4181, flash memory, and external peripheral circuits
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A.2 RSTSW# in Hibernate Mode
The VR4181 may release the self-refresh mode of DRAM when the RSTSW# signal is asserted in the Hibernate mode. As a result, the DRAM data may be lost. (1) With EDO DRAM When the RSTSW# signal goes low, the RAS# and CAS# signals go high and the self-refresh mode is released. After that DRAM returns to the self-refresh mode. At this time, the following phenomena may occur, and the DRAM data may be lost. * DRAM is in the normal operation mode while the RAS# signal is high ((a) in Figure A-2) but a CBR refresh is not executed. * The high-level output of the CAS# signal ((b) in Figure A-2) may be a spike. Figure A-2. Release of Self-Refresh Mode by RSTSW# Signal (EDO DRAM)
RTC (internal)
RSTSW# (input)
RAS(1:0)# (output) (a) LCAS#, UCAS# (output) (b) (c)
Exit self-refresh mode
Resume self-refresh mode
Pulse width: (a) 30 to 60 s (b) 0 (spike) to 30 s (c) 30 s
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(2) With SDRAM When the RSTSW# signal goes low, the CLKEN (CKE) signal goes high. While the CLKEN signal is high, the self-refresh mode of SDRAM may be released. However, because the SDCLK signal is kept low, this problem does not occur in SDRAM that requires the rising edge of the SDCLK signal to release the self-refresh mode. Figure A-3. Release of Self-Refresh Mode by RSTSW# Signal (SDRAM)
RTC (internal)
RSTSW# (input)
CLKEN (output)
SDCLK (output)
L
SDCS(1:0)# (output)
SDRAS# (output)
CAS# (output)
[Workaround] Mask the RSTSW# signal via an external circuit using the MPOWER signal and GPIO pin, so that the RSTSW# signal does not go low in the Hibernate mode.
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APPENDIX B INDEX
Numerics
16450 mode ......................................368, 373, 387, 392
C
cache.................................................................. 44, 106 cache algorithm .......................................................... 71 Cache Error register ................................................... 87 card (CompactFlash)........................................ 350, 352 detection ....................................................... 338, 347 status change ............................................... 338, 347 Cause register ............................................................ 79 CDSTCHGREG ........................................................ 338 CFG_REG_1 ............................................................ 333 CLKSPEEDREG....................................................... 117 clock control ..................................................... 360, 379 clock interface ............................................................ 47 clock interface signals ................................................ 55 clock oscillator............................................................ 48 clock supply.............................................................. 106 clocked serial interface unit.............................. 156, 238 CMUCLKMSK........................................................... 112 Cold Reset................................................................ 104 color panel........................................................ 409, 420 CompactFlash controller .......................................... 328 CompactFlash interface signals ................................. 56 Compare register........................................................ 76 Config register ............................................................ 83 Context register .......................................................... 71 conversion rate................................................. 308, 314 Coprocessor 0 .................................................... 67, 106 Coprocessor 0 hazards ............................................ 431 Count register............................................................. 74 CP0 ............................................................................ 67 CP0 registers........................................................ 43, 67 CPALDATREG ......................................................... 429 CPINDCTREG.......................................................... 428 CPU core.............................................................. 31, 35 CPU registers ............................................................. 37 CRDSTATREG......................................................... 339 CSI ................................................................... 156, 238 CSI registers............................................................. 160 CSI transfer timing.................................................... 157 CSI transfer type ...................................................... 159 CSIINTMSK.............................................................. 166 CSIINTSTAT ............................................................ 167 CSILSTAT ................................................................ 164 CSIMODE................................................................. 161 CSIRXBLEN ............................................................. 170
A
activation factor.................................................194, 328 CompactFlash interrupt request............................196 DCD interrupt request ...........................................198 ElapsedTime interrupt request ..............................200 GPIO activation interrupt request..........................197 power switch interrupt request ..............................195 A/D converter ....................................................275, 301 A/D port scan ............................................................298 address spaces...................................................92, 109 addressing ..................................................................40 addressing modes.......................................................78 ADWINENREG .........................................................340 AIU ............................................................................301 operation sequence...............................................315 AIU registers .............................................................302 AIUDMAMSKREG.....................................................149 AIUINTREG ..............................................................183 alternate functions ....................................106, 236, 238 audio interface signals ................................................56 audio interface unit ...................................................301 auto-load mode .........................................................142 auto scan mode ........................................................318 auto-stop mode .........................................................142
B
BadVAddr register.......................................................74 battery monitor interface signals .................................55 BATTINH shutdown ..................................................193 baud rate...........................................................365, 384 BCUCNTREG1 .........................................................111 BCURFCNTREG.......................................................115 BCUSPEEDREG.......................................................113 bpp ......................................................................34, 399 bus control ................................................................108 bus control registers .................................................110 bus cycles (16 bits) ...................................................242 bus interface ...............................................................31 bus size.....................................................................352
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CSIRXDATA............................................................. 163 CSITXBLEN ............................................................. 169 CSITXDATA ............................................................. 163
EPC register ............................................................... 81 ErrorEPC register ....................................................... 89 ETIMEHREG ............................................................ 218 ETIMELREG ............................................................. 217 ETIMEMREG ............................................................ 217 ExCA ........................................................................ 328 exception code ........................................................... 80 external ROM connection ............................................................ 119 cycle...................................................................... 125 memory map ......................................................... 118 external system bus space ......................................... 93
D
D/A converter ........................................................... 301 data formats ............................................................... 40 data loss................................................................... 299 DAVREF_SETUP..................................................... 305 DCU ......................................................................... 142 DCU registers........................................................... 144 Deadman's Switch reset .................................... 99, 192 Deadman's Switch unit............................................. 230 DMA control unit....................................................... 142 DMA priority ............................................................. 143 DMACTLREG........................................................... 154 DMAITMKREG ......................................................... 155 DMAITRQREG ......................................................... 153 DMARSTREG .......................................................... 149 doubleword................................................................. 42 DRAM data preservation.......................................... 192 DRAM interface................................................ 128, 201 DRAM space .............................................................. 95 DRAMHIBCTL .......................................................... 215 DSU.......................................................................... 230 register setting flow .............................................. 235 DSU registers........................................................... 230 DSUCLRREG........................................................... 233 DSUCNTREG........................................................... 231 DSUSETREG ........................................................... 232 DSUTIMREG............................................................ 234 DTGENCLREG ........................................................ 347 dummy line............................................................... 410 DVALIDREG............................................................. 311
F
FBENDADREG1....................................................... 423 FBENDADREG2....................................................... 423 FBSTADREG1.......................................................... 422 FBSTADREG2.......................................................... 422 FHENDREG.............................................................. 424 FHSTARTREG ......................................................... 424 FIFO mode ....................................... 368, 373, 387, 392 flash memory ............................................ 123, 124, 127 FLM .......................................................... 404, 410, 411 frame buffer .............................................................. 406 frame clock ....................................................... 404, 410 Fullspeed mode .................................................. 45, 190 FVENDREG.............................................................. 417 FVSTARTREG.......................................................... 417
G
general-purpose I/O.................................................... 33 general-purpose I/O signals ....................................... 58 general-purpose I/O unit........................................... 236 general-purpose register .................................... 37, 238 GIU ........................................................................... 236 GIU register .............................................................. 244 GLOCTRLREG ......................................................... 348 GND signal ................................................................. 59 GPDATHREG ........................................................... 254 GPDATLREG............................................................ 255 GPHIBSTH ............................................................... 263 GPHIBSTL................................................................ 264 GPINTEN.................................................................. 256 GPINTMSK ............................................................... 257 GPINTSTAT ............................................................. 262 GPINTTYPH ............................................................. 258 GPINTTYPL.............................................................. 260 GPMD0REG ............................................................. 246
E
ECMPHREG............................................................. 220 ECMPLREG ............................................................. 219 ECMPMREG ............................................................ 219 ECU.......................................................................... 328 ECU control registers ............................................... 331 ECU registers........................................................... 334 EDO DRAM ...... 128, 129, 192, 201, 203, 205, 207, 437 EDOMCYTREG........................................................ 131 ElapsedTime timer ................................................... 216 endian ........................................................................ 40 EntryHi register .......................................................... 75 EntryLo register.......................................................... 70
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GPMD1REG..............................................................248 GPMD2REG..............................................................250 GPMD3REG..............................................................252 GPSICTL...................................................................265
ITGENCTREG .......................................................... 337
K
key press.......................................................... 317, 318 keyboard interface signals ......................................... 56 keyboard interface unit............................................. 317 KEYEN ..................................................................... 267 KIU ........................................................................... 317 KIU register .............................................................. 321 KIUDATn (n = 0 to 7)................................................ 322 KIUINT...................................................................... 327 KIUINTREG.............................................................. 184 KIUSCANREP .......................................................... 323 KIUSCANS ............................................................... 324 KIUWKI..................................................................... 326 KIUWKS ................................................................... 325
H
halfword ......................................................................42 HALTimer..........................................................106, 436 HALTimer shutdown .........................................101, 193 HI register ...................................................................37 Hibernate mode ..........................................45, 191, 437 entering .........................................................201, 202 exiting............................................................203, 204 horizontal blank.........................................................402 HRTOTALREG..........................................................414 HRVISIBREG ............................................................414
I
ICU............................................................................171 ICU register...............................................................173 ID_REV_REG ...........................................................334 IF_STAT_REG..........................................................335 Index register ..............................................................69 initialization interface ..................................................96 initialization interface signals ......................................55 instruction sets ......................................................38, 46 internal bus clock ........................................................31 internal I/O space........................................................94 interrupt control .........................................................172 interrupt control unit ..................................................171 interrupt request................................................171, 243 interval time...............................................285, 286, 326 INTMSKREG.............................................................332 INTREG ....................................................................313 INTSTATREG ...........................................................331 I/O card .............................................................337, 338 I/O direction control (GIU) .........................................238 I/O window ................................................................351 IOADSHBnREG (n = 0 or 1) .....................................342 IOADSLBnREG (n = 0 or 1) ......................................342 IOCTRL_REG ...........................................................341 IOSHBnREG (n = 0 or 1) ..........................................343 IOSLBnREG (n = 0 or 1) ...........................................343 IrDA.............................................................32, 395, 396 IrDA interface signals..................................................58 ISA Bridge.................................................................137 ISABRGCTL..............................................................138 ISABRGSTS .............................................................139
L
LCD controller .......................................................... 399 LCD controller registers............................................ 413 LCD interface ............................................. 34, 241, 399 LCD interface signals ................................................. 54 LCD panel .......................................................... 34, 399 LCDCFGREG0 ......................................................... 420 LCDCFGREG1 ......................................................... 421 LCDCTRLREG ......................................................... 418 LCDGPMODE .......................................................... 273 LCDIMSKREG.......................................................... 427 LCDINRQREG.......................................................... 419 LDCLKENDREG....................................................... 415 LDCLKSTREG ......................................................... 415 LED .......................................................................... 353 operation flow ....................................................... 359 LED control unit........................................................ 353 LED interface signals ................................................. 56 LED registers............................................................ 353 LEDASTCREG ......................................................... 357 LEDCNTREG ........................................................... 356 LEDHTSREG ........................................................... 354 LEDINTREG............................................................. 358 LEDLTSREG ............................................................ 355 little endian ................................................................. 40 LLAddr register........................................................... 84 LO register.................................................................. 37 load clock ......................................................... 403, 410 local loopback .................................................. 372, 391 LOCLK.............................................................. 403, 410
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M
M signal.................................................................... 405 MAIUINTREG........................................................... 186 manual scan mode................................................... 318 MBA address space ................................................. 109 MBA bus................................................................... 108 Host Bridge........................................................... 108 MCNTREG ............................................................... 310 MCNVC_END........................................................... 314 MDMADATREG ....................................................... 304 MEMCFG_REG........................................................ 133 MEMOFFHnREG (n = 0 to 4) ................................... 346 MEMOFFLnREG (n = 0 to 4).................................... 346 memory card .................................................... 337, 338 memory controller ............................................ 106, 131 memory management .......................................... 44, 91 memory mapping ............................................. 118, 350 memory window ....................................................... 350 MEMSELnREG (n = 0 to 4) ...................................... 345 MEMWIDnREG (n = 0 to 4)...................................... 344 MICDEST1REG1 ..................................................... 145 MICDEST1REG2 ..................................................... 145 MICDEST2REG1 ..................................................... 146 MICDEST2REG2 ..................................................... 146 MICDMACFGREG ................................................... 151 MICRCLENREG....................................................... 150 microphone ...................................................... 301, 316 MIDATREG .............................................................. 309 MIPS III instructions ................................................... 38 MIPS16 instructions ................................................... 39 MISCREGn (n = 0 to 15) .......................................... 274 mixed memory mode................................................ 129 MKIUINTREG........................................................... 187 MODE_REG............................................................. 135 monochrome panel .......................................... 408, 420 MPIUINTREG........................................................... 185 MSYSINT1REG........................................................ 176 MSYSINT2REG........................................................ 181
P
PageROM......................................... 114, 121, 122, 126 page sizes .................................................................. 72 PageMask register...................................................... 72 palette....................................................... 406, 428, 429 Parity Error register .................................................... 87 PC............................................................................... 37 PCLK .................................................................. 47, 138 PClock .................................................... 31, 47, 57, 117 PCS0HIA .................................................................. 269 PCS0STPA............................................................... 268 PCS0STRA............................................................... 268 PCS1HIA .................................................................. 271 PCS1STPA............................................................... 270 PCS1STRA............................................................... 270 PCSMODE................................................................ 272 physical address......................................................... 92 pin functions ............................................................... 52 configuration ........................................................... 50 connection .............................................................. 63 I/O circuit........................................................... 63, 66 status ...................................................................... 60 pipeline ....................................................................... 44 pipeline clock.............................................................. 31 PIU............................................................................ 275 PIU registers............................................................. 280 PIUABnREG (n = 0 to 3)........................................... 294 PIUAMSKREG.......................................................... 291 PIUASCNREG .......................................................... 289 PIUCIVLREG ............................................................ 292 PIUCMDREG............................................................ 287 PIUCNTREG............................................................. 281 PIUINTREG .............................................................. 284 PIUPBnmREG (n = 0 or 1, m = 0 to 4) ..................... 293 PIUSIVLREG ............................................................ 285 PIUSTBLREG ........................................................... 286 pixel .................................................................... 34, 399 PLL passive component ........................................... 430 PMU.......................................................................... 188 PMU registers........................................................... 208 PMUCNTREG........................................................... 211 PMUDIVREG ............................................................ 214 PMUINTREG ............................................................ 209 PMUWAITREG ......................................................... 213 polling mode ..................................................... 370, 389 power management unit ........................................... 188 power modes ................................................ 31, 45, 188 transition ............................................................... 189
N
NMIREG ................................................................... 178
O
operating modes ........................................................ 78 ordinary ROM........................................... 114, 120, 125
442
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APPENDIX B INDEX
power-on control .......................................................194 power-on sequence ..........................................102, 407 PRId register ...............................................................82 programmable chip selects .......................................242 PWRCONREG1 ........................................................425 PWRCONREG2 ........................................................426 PWRRSETDRV.........................................................336
serial interface unit 1 ................................................ 360 serial interface unit 2 ................................................ 379 SHCLK ..................................................................... 405 shift clock ................................................................. 405 shutdown control ...................................................... 193 SIU1 ......................................................................... 360 SIU1 registers........................................................... 361 SIU2 ......................................................................... 379 SIU2 registers........................................................... 380 SIUACTMSK_1 ........................................................ 377 SIUACTMSK_2 ........................................................ 397 SIUACTTMR_1 ........................................................ 378 SIUACTTMR_2 ........................................................ 398 SIUCSEL_2 .............................................................. 396 SIUDLL_1................................................................. 362 SIUDLL_2................................................................. 381 SIUDLM_1................................................................ 364 SIUDLM_2................................................................ 383 SIUFC_1................................................................... 368 SIUFC_2................................................................... 387 SIUIE_1 .................................................................... 363 SIUIE_2 .................................................................... 382 SIUIID_1................................................................... 366 SIUIID_2................................................................... 385 SIUIRSEL_2 ............................................................. 395 SIULC_1................................................................... 371 SIULC_2................................................................... 390 SIULS_1 ................................................................... 373 SIULS_2 ................................................................... 392 SIUMC_1.................................................................. 372 SIUMC_2.................................................................. 391 SIUMS_1 .................................................................. 375 SIUMS_2 .................................................................. 394 SIURB_1 .................................................................. 362 SIURB_2 .................................................................. 381 SIURESET_1 ........................................................... 376 SIURESET_2 ........................................................... 396 SIUSC_1 .................................................................. 376 SIUSC_2 .................................................................. 395 SIUTH_1................................................................... 362 SIUTH_2................................................................... 381 SODATREG ............................................................. 306 Soft Reset................................................................. 105 SOFTINTREG .......................................................... 179 software shutdown ........................................... 100, 193 speaker ............................................................ 301, 315 SPKDMACFGREG ................................................... 152 SPKRCLENREG ...................................................... 150
R
Random register .........................................................69 realtime clock unit .....................................................216 receive FIFO .............................................160, 369, 388 receive operation ......................................................156 release detection ......................................................298 reset control ..............................................................191 reset function ..............................................................96 REVIDREG ...............................................................116 ROM interface...........................................................118 ROM space .................................................................93 RSTSW reset ......................................................98, 192 RTC...........................................................................216 RTC registers............................................................216 RTC reset............................................................97, 191 RTCINTREG .............................................................229 RTCL1CNTHREG .....................................................224 RTCL1CNTLREG......................................................223 RTCL1HREG ............................................................222 RTCL1LREG.............................................................221 RTCL2CNTHREG .....................................................228 RTCL2CNTLREG......................................................227 RTCL2HREG ............................................................226 RTCL2LREG.............................................................225 RTCLong timer..........................................................216
S
scan (KIU) .................................................................319 scan sequencer (KIU) .......................................320, 324 scan sequencer (PIU) .......................278, 283, 290, 295 SCK phase................................................................157 SCNTREG ................................................................307 SCNVC_END ............................................................308 SDCLK ................................................................47, 135 SDMADATREG.........................................................303 SDRAM .....................130, 192, 202, 204, 206, 207, 438 SDTIMINGREG.........................................................136 SEQREG...................................................................312 serial interface ..................................................239, 240 serial interface signals ................................................57
User's Manual U14272EJ3V0UM
443
APPENDIX B INDEX
SPKRSRC1REG1 .................................................... 147 SPKRSRC1REG2 .................................................... 147 SPKRSRC2REG1 .................................................... 148 SPKRSRC2REG2 .................................................... 148 Standby mode .................................................... 45, 190 state (PIU) ........................................................ 279, 297 Status register ............................................................ 76 STN .................................................................... 34, 399 Suspend mode ................................................... 45, 190 entering ........................................................ 205, 206 exiting ................................................................... 207 SYSCLK ............................................................. 47, 141 SYSINT1REG........................................................... 174 SYSINT2REG........................................................... 180 SYSMEMELnREG (n = 0 to 4) ................................. 345 SYSMEMSLnREG (n = 0 to 4) ................................. 344 system bus interface signals ...................................... 52 system control coprocessor ....................................... 67
touch panel interface unit ......................................... 275 transmit FIFO............................................ 160, 370, 389 transmit operation..................................................... 156
U
UMA.................................................................... 34, 399
V
VDD signals................................................................ 59 vertical blank .................................................... 402, 405 view rectangle........................................................... 402 VOLTSELREG.......................................................... 349 VOLTSENREG ......................................................... 348 VRTOTALREG ......................................................... 416 VRVISIBREG............................................................ 416
W
wait ........................................................................... 352 wake-up event .................................................... 35, 243 WatchHi register ......................................................... 85 WatchLo register ........................................................ 85 Wired register ............................................................. 73 word............................................................................ 42
T
TagHi register............................................................. 88 TagLo register ............................................................ 88 TClock .................................................... 31, 47, 57, 117 timing parameter ...................................................... 411 TLB............................................................................. 44 touch detection......................................................... 298 touch panel............................................................... 276 touch panel interface signals ..................................... 56
X
XContext register........................................................ 86 XISACTL................................................................... 140
444
User's Manual U14272EJ3V0UM

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