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TLE 6361 G Multi-Voltage Processor Power Supply
Data Sheet 1 1.1 * * * * * * * * Overview Features
* * * * * * * *
High efficiency regulator system Wide input voltage range, up to 60V Stand-by mode with low current consumption Suitable for standard 12V, 24V and 42V PowerNets Step down converter as pre-regulator: 5.5V / 1.5A Step down slope control for lowest EME Switching loss minimization Three high current linear post-regulators with selectable output voltages: 5V / 800mA 3.3V or 2.6V / 500mA 5V or 3.3V / 350mA Six independent voltage trackers (followers): 5V / 17mA each Stand-by regulator with 1mA current capability Three independent undervoltage detection circuits (e.g. reset, early warning) for each linear post-regulator Power on reset functionality Window watchdog triggered by SPI Tracker control and diagnosis by SPI All outputs protected against short-circuit Power-DSO-36 package Ordering Code Q 67007-A9466 Package
P-DSO-36-12
Type TLE 6361 G
SMD = Surface Mounted Device
P-DSO-36-12
Data Sheet, Rev. 1.31
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TLE 6361 G
1.2
Short functional description
The TLE 6361 G is a multi voltage power supply system especially designed for automotive applications using a standard 12V or 24V battery as well as the new 42V powernet. The device is intended to supply 32 bit micro-controller systems which require different supply voltage rails such as 5V, 3.3V and 2.6V. The regulators for external sensors are also provided. The TLE 6361 G cascades a Buck converter block with a linear regulator and tracker block on a single chip to achieve lowest power dissipation thus being able to power the application even at very high ambient temperatures. The step-down converter delivers a pre-regulated voltage of 5.5V with a minimum current capability of 1.5A. Supplied by this step down converter three low drop linear post-regulators offer 5V, 3.3V, or 2.6V of output voltages depending on the configuration of the device with current capabilities of 800mA, 500mA and 350mA. In addition the inputs of six voltage trackers are connected to the 5.5V bus voltage. Their outputs follow the main 5V linear regulator (Q_LDO1) with high accuracy and are able to drive a current of 17mA each. The trackers can be turned on and off individually by a 16 bit serial peripheral interface (SPI). Through this interface also the status information of each tracker (i.e. short circuit) can be read out. To monitor the output voltage levels of each of the linear regulators three independent undervoltage detection circuits are available which can be used to implement the reset or an early warning function. The supervision of the C is managed by the SPI-triggered window watchdog. For energy saving reasons while the motor is turned off, the TLE 6361 G offers a standby mode, where the quiescent current does not exceed 30A typically. In this stand-by mode just the stand-by regulator remains active. The TLE 6361 G is based on Infineon Power technology SPT which allows bipolar , CMOS and Power DMOS circuitry to be integrated on the same monolithic circuitry.
Data Sheet, Rev. 1.31
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TLE 6361 G
1.3
Pin configuration P-DSO-36-12
GND CLK CS DI DO ERR Q_STB Q_T1 Q_T2 Q_T3 Q_T4 Q_T5 Q_T6 Q_LDO3 R3 R2 R1 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
GND SLEW WAKE BOOST IN SW IN SW Bootstrap Q_LDO1 FB/L_IN FB/L_IN Q_LDO2 SEL CCP C+ CGND
Figure 1 Pin Configuration (Top View), bottom heatslug and GND corner pins are connected
Data Sheet, Rev. 1.31
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1.4 Pin No. 1,18,19, 36 2
Pin definitions and functions Symbol GND Function Ground; to reduce thermal resistance place cooling areas on PCB close to this pins. Those pins are connected internally to the heatslug at the bottom. SPI Interface Clock input; clocks the shiftregister; CLK has an internal active pull down and requires CMOS logic level inputs;see also chapter SPI SPI Interface chip select input; CS is an active low input; serial communication is enabled by pulling the CS terminal low; CS input should only be switched when CLK is low; CS has an internal active pull up and requires CMOS logic level inputs ;see also chapter SPI SPI Interface Date input; receives serial data from the control device; serial data transmitted to DI is a 16 bit control word with the Least Significant Bit (LSB) being transferred first; the input has an active pull down and requires CMOS logic level inputs; DI will accept data on the falling edge of CLK-signal; see also chapter SPI SPI Interface Data output; this tristate output transfers diagnosis data to the controlling device; the output will remain 3stated unless the device is selected by a low on Chip-Select CS; see also the chapter SPI Error output; push-pull output. Monitors failures in parallel to the SPI diagnosis word, reset via SPI. ERR is a latched output. Standby Regulator Output; the output is active even when the buck regulator and all other circuitry is in off mode Voltage Tracker Output T1 tracked to Q_LDO1; bypass with a 1F ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed. Voltage Tracker Output T2 tracked to Q_LDO1; bypass with a 1F ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed. Voltage Tracker Output T3 tracked to Q_LDO1; bypass with a 1F ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed.
CLK
3
CS
4
DI
5
DO
6 7 8
ERR Q_STB Q_T1
9
Q_T2
10
Q_T3
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1.4 Pin No. 11
Pin definitions and functions (cont'd) Symbol Q_T4 Function Voltage Tracker Output T4 tracked to Q_LDO1; bypass with a 1F ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed. Voltage Tracker Output T5 tracked to Q_LDO1; bypass with a 1F ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed. Voltage Tracker Output T6 tracked to Q_LDO1; bypass with a 1F ceramic capacitor for stability. It is switched on and off by SPI command. Keep open, if not needed. Voltage Regulator Output 3; 5V or 3.3V output; ouput voltage is selected by pin SEL (see also 3.4.2); For stability a ceramic capacitor of 470nF to GND is sufficient. Reset output 3, undervoltage detection for output Q_LDO3; open collector output; an external pullup resistor of 10k is required Reset output 2, undervoltage detection for output Q_LDO2; open collector output; an external pullup resistor of 10k is required Reset output 1, undervoltage detection for output Q_LDO1 and watchdog failure reset; open collector output ; an external pullup resistor of 10k is required Charge pump capacitor connection; Add the fly-capacitor of 100nF between C+ and CCharge pump capacitor connection; Add the fly-capacitor of 100nF between C+ and CCharge Pump Storage Capacitor Output; Add the storage capacitor of 220nF between pin CCP and GND. Select Pin for output voltage adjust of Q_LDO2 and Q_LDO3 (see also 2.2.2) Voltage Regulator Output 2; 3.3V or 2.6V output; output voltage is selected by pin SEL (see also 3.4.2); For stability a ceramic capacitor of 470nF to GND is sufficient. Feedback and Linear Regulator Input; input connection for the Buck converter output
12
Q_T5
13
Q_T6
14
Q_LDO3
15
R3
16
R2
17
R1
20 21 22 23 24
CC+ CCP SEL Q_LDO2
25, 26
FB/L_IN
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1.4 Pin No. 27
Pin definitions and functions (cont'd) Symbol Q_LDO1 Function Voltage Regulator Output 1; 5V output; acts as the reference for the voltage trackers.The SPI and window watchdog logic is supplied from this voltage. For stability a ceramic capacitor of 470nF to GND is sufficient.
28
Bootstrap Bootstrap Input; add the bootstrap capacitor between pin SW and pin Bootstrap, the capcitance value should be not lower than 2% of the Buck converter output capacitance SW Switch Output; connect both pins externally through short lines directly to the cathode of the catch diode and the Buck circuit inductance. Supply Voltage Input; connect both pins externally through short lines to the input filter/the input capacitors. Boost Input; for switching loss minimization connect a diode (cathode directly to boost pin) in series with a 100nF ceramic capacitor to the IN pin and from the anode of the diode to the buck converter output a 22 resistor. Recommended for 42V applications, in 12/24V applications connect boost directly to IN Wake Up Input; a positive voltage applied to this pin turns on the device Slew control Input; a resistor to GND defines the current slope in the buck switch for reduced EME
29, 31
30, 32 33
IN BOOST
34 35
WAKE SLEW
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TLE 6361 G
1.5
Basic block diagram
TLE 6361
Standby Regulator 2.5V Q_STB
Boost SW 2* IN 2*
BUCK REGULATOR
Driver Bootstrap
Slew
OSZ
PWM
ErrorAmplifier
Internal Reference feedback
FB/L_IN
2*
C+
Charge Pump
C-
Protection
CCP
Wake
Power Down Logic SEL
R1
Linear Reg. 1 Reset Logic Linear Reg. 2 Linear Reg. 3
Q_LDO1
R2
Q_LDO2
-controller / memory supply
R3
Q_LDO3
ref
Window Watchdog
ref
Tracker 5V Tracker 5V Tracker 5V
Q_T1
Q_T2
CLK
ref
Q_T3
CS SPI 16 bit DI
ref
Tracker 5V Tracker 5V Tracker 5V
Q_T4
Sensor supplies (off board supplies)
ref
Q_T5
DO
ref
Q_T6
ERR
GND
4*
Figure 2 Block Diagram
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2
Detailed circuit description
In the following major buck regulator blocks, the linear voltage regulators and trackers, the undervoltage reset function, the watchdog and the SPI are described in more detail. For applications information e.g. choice of external components, please refer to section . 2.1 Buck Regulator
The diagram below shows the internal implemented circuit of the Buck converter, i. e. the internal DMOS devices, the regulation loop and the other major blocks.
IN
5V
Int. voltage regulator Int. charge pump
14V 150A to current sense amplifier
8 to 10V
FB/L_IN
C+
CCP
Main switch ON/OFF
Gate driver
Main DMOS
undervoltage lockout
IN
CBOOTSTRAP SW
Divider
switching frequency 330kHz
Slope switch charge signal Slope DMOS
BOOST
Oscillator 1.4MHz
Slope compensation
Slope switch discharge signal Gate off signal from overtemp or sleep command
Lowpass Voltage feedback amplifier
Trigger for gate on
PWM logic Slope logic Zero cross detection
SW
Current comparator
Vref=6V
Lowpass
Trigger for gate off
from current sensing
Current sense amplifier
+
Delay unit
Slope control
SLEW
external components pins
Figure 3 Detailed Buck regulator diagram The 1.5A Buck regulator consists of two internal DMOS power stages including a current mode regulation scheme to avoid external compensation components plus additional blocks for low EME and reduced switching loss. Figure 3 indicates also the principle how
Data Sheet, Rev. 1.31
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the gate driver supply is managed by the combination of internal charge pump, external charge pump and bootstrap capacitor. 2.1.1 Current mode control scheme
The regulation loop is located at the left lower corner in the schematic, there you find the voltage feedback amplifier which gives the actual information of the actual output voltage level and the current sense amplifier for the load current information to form finally the regulation signal. To avoid subharmonic oscillations at duty cycles higher than 50% the slope compensation block is necessary. The control signal formed out of those three blocks is finally the input of the PWM regulator for the DMOS gate turn off command, which means this signal determines the duty cycle. The gate turn on signal is set by the oscillator periodically every 3s which leads to a Buck converter switching frequency around 330kHz. With decreasing input voltage the device changes to the so called pulse skipping mode which means basically that some of the oscillator gate turn off signals are ignored. When the input voltage is still reduced the DMOS is turned on statically (100% duty cycle) and its gate is supplied by the internal charge pump. Below typical 4.5V at the feedback pin the device is turned off.During normal switching operation the gate driver is supplied by the bootstrap capacitor. 2.1.2 Start-up procedure
To guarantee a device startup even under full load condition at the linear regulator outputs a special start up procedure is implemented. At first the bootstrap capacitor is charged by the internal charge pump. Afterwards the outpuput capacitor is charged where the driver supply in that case is maintained only by the bootstrap capacitor. Once the output capacitor of the buck converter is charged the external charge pump is activated being able to supply the linear regulators and finally the linear regulators are released to supply the loads. 2.1.3 Reduction of electromagnetic emission
In figure 3 it is recognized that two internal DMOS switches are used, a main switch and an auxiliary switch. The second implemented switch is used to adjust the current slope of the switching current. The slope adjustment is done by a controlled charge and discharge of the gate of this DMOS. By choosing the external slew resistor appropriate the current transition time can be adjusted between 20ns and 100ns. 2.1.4 Reducing the switching losses
The second purpose of the slope DMOS is to minimise the switching losses. Once being in freewheeling mode of the buck regulator the output voltage level is sufficient to force the load current to flow, the input voltage level is not needed in the first moment. By a feedback network consisting of a resistor and a diode to the boost pin (connection see
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section ) the output voltage level is present at the drain of the switch. As soon as the voltage at the SW pin passes zero volts the handover to the main switch occurs and the traditional switching behaviour of the Buck switch can be observed. 2.2 Linear Voltage Regulators
The Linear regulators offer voltage rails of 5V, 3.3V and 2.6V which can be determined by a hardware connection (see table at 2.2.2) for proper power up procedure. Being supplied by the output of the Buck pre-regulator the power loss within the three linear regulators is minimized. All voltage regulators are short circuit protected which means that each regulator provides a maximum current according to its current limit when shorted. Together with the external charge pump the NPN pass elements of the regulators allow low dropout voltage operation. By using this structure the linear regulators work stable even with a minimum of 470nF ceramic capacitors at their output. Q_LDO1 has 5V nominal output voltage, Q_LDO2 has a hardware programmable output voltage of 3.3V or 2.6V and Q_LDO3 is programmable to 5V or 3.3V (see 2.2.2). All three regulators are on all the time, if one regulator is not needed a base load resistor in parallel to the output capacitance for controlled power down is recommended.
2.2.1
Startup Sequence Linear Regulators
When acting as 32 bit C supply the so-called power sequencing (the dependency of the different voltage reails to each other) is important. Within the TLE 6361 G the following Startup-Sequence is defined (see also figure 4): VQ_LDO2 VQ_LDO1; VQ_LDO3 VQ_LDO1 with VQ_LDO1=5V, VQ_LDO2 = 2.6V and VQ_LDO3 = 3.3V and VQ_LDO2 VQ_LDO1 with VQ_LDO1=5V, VQ_LDO2 = 2.6V/3.3V and VQ_LDO3 = 5V The power sequencing refers to the regulator itself, externally voltages applied at Q_LDO2 and Q_LDO3 are not pulled down actively by the device if Q_LDO1 is lower than those outputs. That means for the power down sequencing if different output capacitors and different loads at the three outputs of the linear regulators are used the voltages at Q_LDO2 and Q_LDO3 might be higher than at Q_LDO1 due to slower discharging. To avoid this behaviour three Schottky diodes have to be connected between the three outputs of the linear regulators in that way that the cathodes of the diodes are always connected to the higher nominal rail.
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Power Sequencing
VFB/L_IN
VLDO_EN
t
VQ_LDO1
5V VRth5 3.3V 2.6V
t
VQ_LDO2 (2.6V Mode)
0.7V 2.6V VRth2.6 5V LDO 5V LDO 0.7V
t
VQ_LDO3 (3.3V Mode)
5V LDO 3.3V VRth3.3 +/- 50mV 5V LDO +/- 50mV
t
Figure 4 Power-up and -down sequencing of the regulators
2.2.2
Q_LDO2 and Q_LDO3 output voltage selection*
To determine the output voltage levels of the three linear regulators, the selection pin (SEL, pin 23) has to be connected according to the matrix given in the table below. Definition of Output voltage Q_LDO2 and Q_LDO3 Select Pin SEL connected to GND Q_LDO1 Q_LDO2 Q_LDO2 Q_LDO3 output voltage output voltage 3.3 V 2.6 V 2.6 V 5V 3.3 V 5V
* for different output voltages please refer to the multi voltage supply TLE6368
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2.3
Voltage Trackers
For off board supplies i.e. sensors six voltage trackers Q_T1 to Q_T6 with 17mA output current capability each are available. The output voltages match Q_LDO1 within +5 / -15mV. They can be individually turned on and off by the appropriate SPI command word sent by the microcontroller. A ceramic capacitor with the value of 1F at the output of each tracker is sufficient for stable operation without oscillation. The tracker outputs can be connected in parallel to obtain a higher output current capability, no matter if only two or up to all six trackers are tied together. For uniformly distributed current density in each tracker internal balance resistors at each output are foreseen internally. By connecting twice three trackers in parallel two sensors with more than 50mA each can be supplied, all six in parallel give more than 100mA. The tracker outputs can withstand short circuits to GND or battery in a range from -5 to +60V. A short circuit to GND at is detected and indicated individually for each tracker in the SPI status word. Also an open load condition might be recognised and indicated as a failure condition in the SPI status word. A minimum load current of 2mA is required to avoid open load failure indication. In case of connecting several trackers to a common branch balancing currents can prevent proper operation of the failure indication. 2.4 Standby Regulator
The standby regulator is an ultra low power 2.5V linear voltage regulator with 1mA output current which is on all the time. It is intended to supply the microcontroller in stop mode and requires then only a minimum of quiescent current (<30A) to extend the battery lifetime. 2.5 Charge Pump
The 1.6 MHz charge pump with the two external capacitors will serve to supply the base of the NPN linear regulators Q_LDO1 and Q_LDO3 as well as the gate of the Buck DMOS transistor in 100% duty cycle operation at low battery condition. The charge pump voltage in the range of 8 to 10V can be measured at pin 22 (CCP) but is not intended to be used as a supply for additional circuitry. 2.6 Power On Reset
A power on reset is available for each linear voltage regulator output. The reset output lines R1, R2 and R3 are active (low) during start up and turn inactive with a reset delay time after Q_LDO1, Q_LDO2 and Q_LDO3 have reached their reset threshold. The reset outputs are open collector, three pull up resistors of 10k each have to be connected to the I/O rail (e.g. Q_LDO1) of the C. All three reset outputs can be linked in parallel to obtain a wired-OR. The reset delay time is 64 ms by default and can be set to lower values as 8 ms, 16 ms or 32 ms by SPI command. At each power up of the device when the output voltage at
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Q_LDO1 has decreased below 3.3V (max.) the default settings are valid, means the 64ms delay time. If the voltage on Q_LDO1 during sleep or power off mode was kept above 3.3V the delay time set by the last SPI command is valid.
VFB/L_IN
VQ_LDOx
trr tRES tRES
< trr
t
VRTH,Q_LDOx
t
tRES tRES
VRx
t
thermal shutdown under voltage over load
Figure 5 Undervoltage reset timing 2.7 RAM good flag
A RAM good flag will be set within the SPI status word when the Q_LDO1 voltage drops below 2.3V. A second one will be set if Q_LDO2 drops below typical 1.4V. Both RAM good flags can be read after power up to determine if a cold or warm start needs to be processed. Both RAM good flags will be reset after each SPI cycle. 2.8 ERR Pin
An hardware error pin indicates any fault conditions on the chip. It should be connected to an interrupt input of the microcontroller. A low signal indicates an error condition. The microcontroller can read the root cause of the error by reading the SPI register. 2.9 Window Watchdog
The on board window watchdog for supervision of the C works in combination with the SPI. The window watchdog logic is triggered when CS is low and Bit WD-Trig in the SPI command word is set to "1". The watchdog trigger is recognized with the low to high transition of the CS signal. To allow reading the SPI at any time without getting a reset due to misinterpretation the WD-Trig bit has to be set to "0" to avoid false trigger conditions. To disable the window watchdog the WD-OFF bits need to be set to "010".
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tSR = tOW/2 tCW=tCW definition
closed window
tWDR = tRES (not the same scale)
tOW=tCW
open window
(not the same scale)
reset delay time without trigger
definition tECW fOSC=fOSCmax t EOW, w.c.= ( tCW+tOW )(1-) worst cases fOSC=fOSCmin t ECW, w.c.= tCW (1+)
reset start delay time after window watchdog timeout
reset duration time after window watchdog time-out
t EOW = end of open window Example with: tCW=128ms =25% (oscillator deviation) tECW, w.c. = 128(1.25) = 160ms tEOW, w.c = (128+128)(0.75) = 192ms t OWmin towmin = 32ms
Minimum open window time: t OWmin= tOW - * ( tOW + 2* tCW )
Figure 6 Window watchdog timing definition Figure 6 shows some guidelines for designing the watchdog trigger timing taking the oscillator deviation of different devices into account. Of importance is the maximum (w.c.) of the closed window and the minimum of the open window in which the trigger has to occur. The length of the OW and CW can be modified by SPI command. If a change of the window length is desired during the Watchdog function is operating please send the SPI command with the new timing with a 'Watchdog trigger Bit' D15=1.In this case the next CW will directly start with the new length. A minimum time gap of > 1/48 of the actual OW/CW time between a 'Watchdog disable' and 'Watchdog enable' SPI-command should be maintained. This allows the internal Watchdog counters to be resetted. Thus after the enable command the Watchdog will start properly with a full CW of the adjusted length.
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Perfect triggering after Power on Reset
VQ_LDO1
VRth1 1V
t
R1
tRES
t
Watchdog window
tCW
tSR
CW
OW
CW
OW
CW
CW
OW t
CS
with WDtrig=1
t
ERR t
Incorrect triggering
Watchdog window
CW
OW
t
CS
with WDtrig=1 1) 2)
t
1) Pretrigger 2) Missing trigger Legend: OW = Open window CW = Closed window
Figure 7 Window watchdog timing Figure 7 gives some timing information about the window watchdog. Looking at the upper signals the perfect triggering of the watchdog is shown. When the 5V linear regulator Q_LDO1 reaches its reset threshold, the reset delay time has to run off before
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the closed window (CW) starts. Then three valid watchdog triggers are shown, no effect on the reset line and/or error pin is observed. With the missing watchdog trigger signal the error signal turns low immediately where the reset is asserted after another delay of half the closed window time. Also shown in the figure are two typical failure modes, one pretrigger and one missing signal. In both cases the error signal will go low immediately the failure is detected with the reset following after the half closed window time. 2.10 Overtemperature Protection
At a chip temperature of more than 130 an error and temperature flag is set and can be read through the SPI. The device is switched off if the device reaches the overtemperature threshold of 170C. The overtemperature shutdown has a hysteresis to avoid thermal pumping. 2.11 Power Down Mode
The TLE 6361 G is started by a static high signal at the wake input or a high pulse with a minimum of 50s duration at the Wake input (pin 34). In order to avoid instabilities of the device voltages applied to the Wake pin (pin 34) have to have a certain slope, i.e. 1V/3s. Voltages in the range between the turn on and turn off thresholds for a few 100s must be avoided! By SPI command ("Sleep"-bit, D8, equals zero) all voltage regulators including the switching regulator except the standby regulator can be turned off completely only if the wake input is low. In the case the Wake input is permanently connected to battery the device cannot be turned off by SPI command, it will always turn on again. For stable "on" operation of the device the "Sleep"-bit, D8 has to be set to high at each SPI cycle! When powering the device again after power down the status of the SPI controlled devices (e.g. trackers, watchdog etc.) depends on the output voltage on Q_LDO1. Did the voltage at Q_LDO1 decrease below 3.3V the default status (given in the next section) is set otherwise the last SPI command defines the status. 2.12 Serial Peripheral Interface
A standard 16bit SPI is available for control and diagnostics. It is capable to operate in a daisy chain. It can be written or read by a 16 bit SPI interface as well as by an 8 bit SPI interface. The 16-bit control word (write bit assignment, see figure 8) is read in via the data input DI, synchronous to the clock input CLK supplied by the C. The diagnosis word appears in the same way synchronously at the data output DO (read bit assignment, see figure 9), so with the first bit shifted on the DI line the first bit appears on the DO line.
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The transmission cycle begins when the TLE 6361 G is selected by the "not chip select" input CS (H to L). After the CS input returns from L to H, the word that has been read in at the DI line becomes the new control word. The DO output switches to tristate status at this point, thereby releasing the DO bus circuit for other uses. For details of the SPI timing please refer to figures 10 to 13. The SPI will be reset to default values given in the following table "write bit meaning" if the RAM good flag of Q_LDO1 indicates a cold start (lower output voltage than 3.3V). The reset will be active as long as the power on reset is present so during the reset delay time at power up no SPI commands are acceptable. The register content of the SPI - including watchdog timings and reset delay timings - is maintained if the RAM good flag of Q_LDO1 indicates a warm start (i.e. Q_LDO1 did not decrease below 3.3V). 2.12.1 Write mode
The following tables show the bit assignment to the different control functions, how to change settings with the right bit combination and also the default status at power up. 2.12.2
BIT Name Default
Write mode bit assignment
DO
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D 15
WD_OF NOT F1 assigned
T1control
T2control
T6control
T4control
T5control
T6control
sleep
WD_OF F2
reset 1
reset 2
WD 1
WD 2
WD_OF WD-Trig F3
1
X
0
0
0
0
0
0
1
1
0
0
0
0
1
0
Figure 8 Write Bit assignment
Write Bit meaning Function Not assigned Tracker 1 to 6 - control: turn on/off the individual trackers Bit D1 D2 D3 D4 D5 D6 D7 D8 Combination X 0: OFF 1: ON Default X 0
Power down: send device to sleep
Data Sheet, Rev. 1.31 17
0: SLEEP 1: NORMAL
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Write Bit meaning Function Reset timing: Reset delay time tRES valid at warm start Bit D10D11 Combination 00: 64ms 10: 32ms 01: 16ms 11: 8ms 00: 128ms 10: 64ms 01: 32ms 11: 16ms 010: OFF 1xx: ON x0x: ON xx1: ON Default 00
Window watchdog timing: Open window time tOW and closed window time tCW valid at warm start Window watchdog function: Enable /disable window watchdog
D12D13
00
D0D9D14
111
Window watchdog trigger: Enable / disable window watchdog trigger
D15
0: not triggered 1 1: triggered
2.12.3 Read mode Below the status information word and the bit assignments for diagnosis are shown. 2.12.3.1 Read mode bit assignment
BIT Name Default
DO
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D 15
ERROR
temp_ warn
T1status
T2status
T3status
T4status
T5status
T6status
RAM Good 1
RAM Good 2
WD Window
R-Error1 R-Error2 R-Error3
WD Error
DC/DC status
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Figure 9 Read Bit assignment
Error bit D0: The error bit indicates fail function and turns high if the temperature prewarning, the watchdog error is active, further if one RAM good indicates a cold start or if a voltage tracker does not settle within 1ms when it is turned on. In addition to the error indication by software the ERR pin atcs as a hardware error flag.
Data Sheet, Rev. 1.31 18 2004-10-12
TLE 6361 G
Read Bit meaning Function Error indication, explanation see below this table Overtemperature warning Status of Tracker Output Q_T[1:6],only if output is ON Type Latched Bit D0 Combination Default 0: normal operation 0 1: fail function 0: normal operation 0 1: prewarning 1: settled output voltage 0:Tracker turned off or shorted output. Also open load may possibly be indicated as 0.1) 0: cold start 1: warm start 0: cold start 1: warm start 0: open window 1: closed window 0
Not latched D1 Not latched D2 D3 D4 D5 D6 D7
Indication of cold start/ warm start, Q_LDO1 Indication of cold start/ warm start, Q_LDO2 Indication for open or closed window Reset condition at output Q_LDO1 Reset condition at output Q_LDO2 Reset condition at output Q_LDO3 Watchdog Error DC/DC converter status
1)
Latched Latched
D8 D9
0 0 0
Not latched D10 Not latched D11 Not latched D12 Not latched D13
0: normal operation 0 1: Reset R1 0: normal operation 0 1: Reset R2 0: normal operation 0 1: Reset R3 0: normal operation 1: WD error 0: off 1: on 0 1
Latched
D14
Not latched D15
Min. load current to avoid '0' signal caused by open load is 2mA.
Data Sheet, Rev. 1.31
19
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TLE 6361 G
2.12.4 SPI Timings
CS High to Low & rising edge of CLK: DO is enabled. Status information is transferred to Output Shift Register
CS
CS Low to High: Data from Register are transferred to e.g. Trackers
time
CLK
0
1
2
3
13 14 15
0
1
Data In (N) DI
D0 D1 D2 D3 D13 D14 D15
Data In (N+1)
D0
+
D1
+
DI: Data will be accepted on the falling edge of CLK-Signal Data Out (N-1) DO
D0 D1 D2 D3 D13 D14 D15
Data Out (N)
D0 D1
DO: State will change on the rising edge of CLK-Signal
e.g.
Trackercontrol
Setting (N-1)
Setting (N)
e.g.
Trackerstatus
Status (N-1)
Status (N)
Figure 10 SPI Data Transfer Timing
Data Sheet, Rev. 1.31 20 2004-10-12
TLE 6361 G
Figure 11 SPI-Input Timing
trIN
tfIN <10ns 0.7 VQ_LDO1 50% 0.2 VQ_LDO1 trDO 90%
CLK
DO
(low to high) 10% tVADO tfDO 90%
DO
(high to low) 10%
Figure 12 DO Valid Data Delay Time and Valid Time
Data Sheet, Rev. 1.31
21
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TLE 6361 G
tfIN
trIN <10ns 0.7 VQ_LDO1 50% 0.2 VQ_LDO1
CS
DO
tENDO tDISDO
10k 50% Pullup to VQ_LDO1
DO
Figure 13 DO Enable and Disable Time
10k Pulldown 50% to GND
Data Sheet, Rev. 1.31
22
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TLE 6361 G
3 3.1 Item
Characteristics Absolute Maximum Ratings Parameter Symbol Limit Values Min. Max. 60 - VS+0.5 - 8 - Unit Test Condition
3.1.1 Supply Voltage Input IN Voltage Current Voltage Current Voltage Current Voltage Voltage Current 3.1.5 Boost Input Voltage Current Voltage Current Voltage Current
VVS IVS VSW ISW VFB/L_IN IFB/L_IN VBootstrap VBootstrap IBootstrap VBoost IBoost VSlew ISlew VCL ICL
-0.5 - -2 - -0.5 -
V
-
-
3.1.2 Buck-Switch Output SW
V
-
-
3.1.3 Feedback and Linear Voltage Regulator Input
V
-
-
3.1.4 Bootstrap Connector Bootstrap
VSW0.5V -0.5 - -0.5 - -0.5 - -0.5 -150
VSW+
10V 70 - 60 - 6 - VFB/L_IN +0.5 +150
V V
- Internally Limited - Internally Limited - Internally Limited
V
-
3.1.6 Slope Control Input Slew
V
-
3.1.7 Charge Pump Capacitor Connector C-
V
mA
Data Sheet, Rev. 1.31
23
2004-10-12
TLE 6361 G
3.1.8 Charge Pump Capacitor Connector C+ Voltage Current
VCH ICH
-0.5 -150
13 +150
V
mA
3.1.9 Charge Pump Storage Capacitor CCP Voltage Current Voltage Current Voltage Current Voltage Current Voltage Current Voltage Current Voltage Current Voltage Current Voltage Current
Data Sheet, Rev. 1.31
VCCP ICCP VQ_Stb IQ_Stb VQ_LDO1 IQ_LDO1 VQ_LDO2 IQ_LDO2 VQ_LDO3 IQ_LDO3 VQ_T1 IQ_T1 VQ_T2 IQ_T2 VQ_T3 IQ_T3 VQ_T4 IQ_T4
-0.5 -150 -0.5 - -0.5 - -0.5 - -0.5 - -5 - -5 - -5 - -5 -
12 - 6 - 6 - 6 - 6 - 60 - 60 - 60 - 60 -
24
V
mA
3.1.10 Standby Voltage Regulator output Q_STB
V
-
- Internally limited - Internally limited - Internally limited - Internally limited - Internally limited - Internally limited - Internally limited - Internally limited
2004-10-12
3.1.11 Voltage Regulator output voltage Q_LDO1
V
-
3.1.12 Voltage Regulator output voltage Q_LDO2
V
-
3.1.13 Voltage Regulator output voltage Q_LDO3
V
-
3.1.14 Voltage Tracker output voltage Q_T1
V
mA
3.1.15 Voltage Tracker output voltage Q_T2
V
mA
3.1.16 Voltage Tracker output voltage Q_T3
V
mA
3.1.17 Voltage Tracker output voltage Q_T4
V
mA
TLE 6361 G
3.1.18 Voltage Tracker output voltage Q_T5 Voltage Current Voltage Current Voltage Current Voltage Current Voltage Current Voltage Current Voltage Current Voltage Current Voltage Current Voltage Current
Data Sheet, Rev. 1.31
VQ_T5 IQ_T5 VQ_T6 IQ_T6 VSEL ISEL VWake IWake VR1 IR1 VR2 IR2 VR3 IR3 VDI IDI VDO IDO VCLK ICLK
-5 - -5 - -0.5 - -0.5 - -0.5 - -0.5 - -0.5 - -0.5 - -0.5 - -0.5 -
60 - 60 - 6 - 60 - 6 - 6 - 6 - 6 - 6 - 6 -
25
V
mA
- Internally limited - Internally limited - Internally limited -
3.1.19 Voltage Tracker output voltage Q_T6
V
mA
3.1.20 Select Input SEL
V
-
3.1.21 Wake Up Input Wake
V
-
3.1.22 Reset Output R1
V
-
-
3.1.23 Reset Output R2
V
-
-
3.1.24 Reset Output R3
V
-
-
3.1.25 SPI Data Input DI
V
-
-
3.1.26 SPI Data Output DO
V
-
- Internally limited -
3.1.27 SPI Clock Input CLK
V
-
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TLE 6361 G
3.1.28 SPI Chip Select Not Input CS Voltage Current Voltage Current Junctionambient Junctionambient Junctioncase 3.1.31 Temperature Junction temperature Junction temperature transient Storage temperature Tj Tjt -40 150 175 C C lifetime=TBD
VCS ICS VError IError Rthja Rthja Rthjc
-0.5 - -0.5 -
6 - 6 - 37 29
V
-
-
3.1.29 Error Output Pin
V
- K/W K/W K/W
- Internally limited
1)
3.1.30 Thermal Resistance PCB heat sink area 300mm2
1)
PCB heat sink area 600mm2
-
2
Tstg
-50
150
C
3.1.32 ESD - Protection (Human Body Model; 1.5k; C=100pF) Electrostatic discharge voltage VESD -1 1 kV All pins
1) Package mounted on FR4 47x50x1.5mm3; 70 Cu, zero airflow
Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit.
Data Sheet, Rev. 1.31
26
2004-10-12
TLE 6361 G
3.2
Functional Range Symbol VIN 5.5 Limit Values min. Supply Voltage Supply Voltage Ripple at FB/L_IN max. V To achieve VIN,min an initial startup with VIN >8V is required; Unit Condition
-40C < Tj < 150 C Item Parameter
VIN VFB/L_IN
ripple
60 0 150
V mVPP
Note: Within the functional range the IC can be operated . The electrical characteristics, however, are not guaranteed over this full functional range
Data Sheet, Rev. 1.31
27
2004-10-12
TLE 6361 G
3.3
Recommended Operation Range Symbol min. Buck Inductor Buck Capacitor LB CB 18 10 Limit Values typ. max. 100 H F
1)
-40C < Tj < 150 C Item Parameter Unit Condition
ESR <0.15 , ceramic capacitor (X7R) recommended1)
Bootstrap Capacitor SLEW resistor Linear regulator capacitors Tracker bypass capacitors SPI rise and fall timings, CS, DI, CLK
1)
CBTP RSLEW
2 0 20
% of CB k nF ceramic capacitor (X7R) ceramic capacitor (X7R)
CQ_LDO1-3 470
CQ_T1-6
1
F
tr,f
200
ns
CB, min needs a Buck inductance LB=47H to avoid instabilities
Data Sheet, Rev. 1.31
28
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TLE 6361 G
3.4
Electrical Characteristics
The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. Typical values represent the median values at room temperature, which are related to production processes. -40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter Symbol min. Buck regulator 3.4.1 Switching frequency 3.4.2 Current transition time, min., rising edge 3.4.3 Current transition time, max., rising edge 3.4.4 Current transition time, min., falling edge 3.4.5 Current transition time, max., falling edge fSW tr_I_SW 280 370 20 425 kHz ns RSL=0 1) Limit Values typ. max. Unit Test Conditions
tr_I_SW
100
ns
RSL=20k 1)
tf_I_SW
20
ns
RSL=0 1)
tf_I_SW
100
ns
RSL=20k 1)
3.4.6 Voltage rise / tf_V_SW fall time 3.4.7 Static on resistance 3.4.8 Static on resistance 3.4.9 Current limit 3.4.10 Output voltage 3.4.11 Output voltage
Data Sheet, Rev. 1.31
25 160 280 1.5 5.4 5.4 400 3.2 6.3 6.05
ns m m A V V
1)
RON RON IMAX VOUT VOUT
Tj=25C in static operation Tj=150C in static operation VFB/L_IN=5.4V IOUT=0.1A VIN=13.5 V IOUT=1.5A VIN=13.5 V
2004-10-12
29
TLE 6361 G
-40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter 3.4.12 Bootstrap charging current at start-up 3.4.13 Bootstrap voltage (internal charge pump) Symbol min. IBTSTR 80 Limit Values typ. 160 max. 220 A Unit Test Conditions
VBTSTR
10
17
V
VFB/L_IN=6.5V, Buck converter off
VBTSTR, 3.4.14 Bootstrap undervoltage turn on lockout, Buck turn on threshold 3.4.15 Bootstrap VBTSTR, undervoltage turn on lockout, VBTSTR, hysteresis turn off 3.4.16 Charge pump voltage 3.4.17 Max. Duty Cycle 3.4.18 Min. Duty Cycle 3.4.19 Output voltage 3.4.20 Output voltage 3.4.21 Load Regulation 3.4.22 Current limit
Data Sheet, Rev. 1.31
5
9
V
2.5
V
VCCP
7.9
11.0
V
IQ_LDO1 = 800mA, VFB/L_IN=6.0V, CFLY=100nF, CCCP=220nF Switching operation Static-off operation 100mA < IQ_LDO1 < 800mA IQ_LDO1 = 800mA 100mA< IQ_LDO1 <800mA; VFB/L_IN=5,5V VQ_LDO1=4V
2004-10-12
dutymax dutymin
95 0
% %
Voltage Regulator Q_LDO1 VQ1 VQ1 VQ_LDO1 4.9 5.0 40 5.1 V V mV
IQ_LDO1limit 800
1050
30
1400
mA
TLE 6361 G
-40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter 3.4.23 Ripple rejection 3.4.24 Output Capacitor 3.4.25 Output voltage 3.3V 3.4.26 Output voltage 3.3V 3.4.27 Output voltage 2.6V 3.4.28 Output voltage 2.6V 3.4.29 Load Regulation Symbol min. PSRR1 CQ_LDO1 26 470 Limit Values typ. 40 max. dB nF f=330kHz; 1) Ceramic type, value for stability 50mA < IQ_LDO2 < 400mA; 3.3V mode IQ_LDO2 =400mA; 3.3V mode 50mA < IQ_LDO2 < 400mA; 2.6V mode IQ_LDO2 =400mA; 2.6V mode 50mA< IQ_LDO3 <400mA; VFB/L_IN=5.5V 3.3V mode 50mA< IQ_LDO2 <400mA; VFB/L_IN=5.5V 2.6V mode VQ_LDO2= 2.8V; 3.3V mode VQ_LDO2= 2V; 2.6V mode f=330kHz; 1) Ceramic type, value for stability Unit Test Conditions
Voltage Regulator Q_LDO2 VQ_LDO2 3.14 3.46 V
VQ_LDO2 VQ_LDO2 2.500
3.32 2.750
V V
VQ_LDO2 VQ_LDO2
2.62 50
V mV
3.4.30 Load Regulation
VQ_LDO2
50
mV
3.4.31 Current limit 3.4.32 Current limit 3.4.33 Ripple rejection 3.4.34 Output Capacitor
IQ_LDO2limit 500 IQ_LDO2limit 500 PSRR2 CQ_LDO2 26 470
650 650 40
850 850
mA mA dB nF
Voltage Regulator Q_LDO3
Data Sheet, Rev. 1.31
31
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TLE 6361 G
-40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter 3.4.35 Output voltage 5V 3.4.36 Output voltage 5V 3.4.37 Output voltage 3.3V 3.4.38 Output voltage 3.3V 3.4.39 Load Regulation Symbol min. VQ_LDO3 4.8 Limit Values typ. max. 5.2 V 20mA < IQ_LDO3 < 300mA; 5V mode IQ_LDO3 =300mA; 5V mode 20mA < IQ_LDO3 < 300mA; 3.3V mode IQ_LDO3 =300mA; 3.3V mode 20mA< IQ_LDO3 <300mA; VFB/L_IN=5,5V 5V mode 20mA< IQ_LDO3 <300mA; VFB/L_IN=5,5V 3.3V mode VQ_LDO3=4V; 5V mode VQ_LDO3=2.8V; 3.3V mode f=330kHz; 1) Ceramic type, value for stability VQ_T1-VQ_LDO1; 1mA < IQ_T1 < 17mA VQ_T1-VQ_LDO1; IQ_T1 = 17mA Unit Test Conditions
VQ_LDO3 VQ_LDO3 3.14
5.0 3.46
V V
VQ_LDO3 VQ_LDO3
3.32 100
V mV
3.4.40 Load Regulation
VQ_LDO3
50
mV
3.4.41 Current limit 3.4.42 Current limit 3.4.43 Ripple rejection 3.4.44 Output Capacitor 3.4.45 Output voltage tracking accuracy 3.4.46 Output voltage tracking accuracy
Data Sheet, Rev. 1.31
IQ_LDO3
limit
350 350 26 470
500 500 40
600 600
mA mA dB nF
IQ_LDO3
limit
PSRR3 CQ_LDO3
Voltage Tracker Q_T1 VQ_T1 -15 5 mV
VQ_T1
-10
mV
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-40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter 3.4.47 Overvoltage threshold Symbol min. VOVQ_T1 Limit Values typ. VQ_T1,
nom
Unit mV mV
Test Conditions IQ_T1 = 0mA; 1)
1)
max.
3.4.48 Undervoltage VUVQ_T1 threshold 3.4.49 Current limit 3.4.50 Ripple rejection IQ_T1 limit PSRR 17 26 1
VQ_T115mV 30
mA dB F
VQ_T1=4V f=330kHz; 1) Ceramic type, minimum for stability VQ_T2-VQ_LDO1; 1mA < IQ_T2 < 17mA VQ_T2-VQ_LDO2; IQ_T2 = 17mA
3.4.51 Tracker load CQ_T1 capacitor Voltage Tracker Q_T2 3.4.52 Output voltage tracking accuracy 3.4.53 Output voltage tracking accuracy 3.4.54 Overvoltage threshold VQ_T2
-15
5
mV
VQ_T2
-10
mV
VOVQ_T2
VQ_T2,
nom
mV mV 30 mA dB F
IQ_T2 = 0mA;1)
1)
3.4.55 Undervoltage VUVQ_T2 threshold 3.4.56 Current limit 3.4.57 Ripple rejection IQ_T2 limit PSRR 17 26 1
VQ_T215mV
VQ_T2=4V f=330kHz; 1) Ceramic type, minimum for stability
3.4.58 Tracker load CQ_T2 capacitor
Voltage Tracker Q_T3
Data Sheet, Rev. 1.31
33
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-40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter 3.4.59 Output voltage tracking accuracy 3.4.60 Output voltage tracking accuracy 3.4.61 Overvoltage threshold Symbol min. VQ_T3 -15 Limit Values typ. max. 5 mV VQ_T3-VQ_LDO1; 1mA < IQ_T3 < 17mA VQ_T3-VQ_LDO3; IQ_T3 = 17mA Unit Test Conditions
VQ_T3
-10
mV
VOVQ_T3
VQ_T3,
nom
mV mV 30 mA dB F
IQ_T3 = 0mA; 1)
1)
3.4.62 Undervoltage VUVQ_T3 threshold 3.4.63 Current limit 3.4.64 Ripple rejection IQ_T3 limit PSRR 17 26 1
VQ_T315mV
VQ_T3=4V f=330kHz; 1) Ceramic type, minimum for stability VQ_T4-VQ_LDO1; 1mA < IQ_T4 < 17mA VQ_T4-VQ_LDO4; IQ_T4 = 17mA
3.4.65 Tracker load CQ_T3 capacitor Voltage Tracker Q_T4 3.4.66 Output voltage tracking accuracy 3.4.67 Output voltage tracking accuracy 3.4.68 Overvoltage threshold VQ_T4
-15
5
mV
VQ_T4
-10
mV
VOVQ_T4
VQ_T4,
nom
mV mV 30 mA dB
IQ_T4 = 0mA; 1)
1)
3.4.69 Undervoltage VUVQ_T4 threshold 3.4.70 Current limit 3.4.71 Ripple rejection
Data Sheet, Rev. 1.31
VQ_T415mV 17 26
IQ_T4 limit PSSR
VQ_T4=4V f=330kHz; 1)
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-40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter Symbol min. 3.4.72 Tracker load CQ_T4 capacitor Voltage Tracker Q_T5 3.4.73 Output voltage tracking accuracy 3.4.74 Output voltage tracking accuracy 3.4.75 Overvoltage threshold VQ_T5 -15 5 mV VQ_T5-VQ_LDO1; 1mA < IQ_T5 < 17mA VQ_T5-VQ_LDO5; IQ_T5 = 17mA 1 Limit Values typ. max. F Ceramic type, minimum for stability Unit Test Conditions
VQ_T5
-10
mV
VOVQ_T5
VQ_T5,
nom
mV mV 30 mA dB F
IQ_T5 = 0mA; 1)
1)
3.4.76 Undervoltage VUVQ_T5 threshold 3.4.77 Current limit 3.4.78 Ripple rejection IQ_T5 limit PSRR 17 26 1
VQ_T515mV
VQ_T5=4V f=330kHz; 1) Ceramic type, minimum for stability VQ_T6-VQ_LDO1; 1mA < IQ_T6 < 17mA VQ_T6-VQ_LDO6; IQ_T6 = 17mA
3.4.79 Tracker load CQ_T5 capacitor Voltage Tracker Q_T6 3.4.80 Output voltage tracking accuracy 3.4.81 Output voltage tracking accuracy 3.4.82 Overvoltage threshold VQ_T6
-15
5
mV
VQ_T6
-10
mV
VOVQ_T6
VQ_T6,
nom
mV
IQ_T6 = 0mA; 1)
Data Sheet, Rev. 1.31
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-40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter Symbol min. 3.4.83 Undervoltage VUVQ_T6 threshold 3.4.84 Current limit 3.4.85 Ripple rejection IQ_T6 limit PSRR 17 26 1 Limit Values typ. VQ_T615mV 30 max. mV mA dB F
1)
Unit
Test Conditions
VQ_T6=4V f=330kHz; 1) Ceramic type, minimum for stability 0A 3.4.86 Tracker load CQ_T6 capacitor Standby Regulator 3.4.87 Output voltage 3.4.88 Current limit 3.4.89 Standby load capacitor Off-Mode 3.4.90 Supply current from battery 3.4.91 Supply current from battery 3.4.92 Turn on Wake-up threshold 3.4.93 Turn off Wake-up threshold 3.4.94 Wake-up input current Iq,off VQ_STB
2.2
2.4
2.6
V
IQ_STB limit 1 CQ_STB 100
3
6
mA nF
10
30
A
Iq,off
10
30
A
Vwake th, on
2.4
2.8
V
Vwake th, off 1.8
2.35
V
Vwake decreasing
Iwake 4
50 10
150 50
A s
Vwake=5V Vwake > Vwake th, on max; 1)
3.4.95 Wake up twake,min input on time Reset R1
Data Sheet, Rev. 1.31
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-40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter 3.4.96 Reset threshold Q_LDO1 3.4.97 Reset threshold Q_LDO1 Symbol min. VRTH
Q_LDO1, de
Limit Values typ. 4.65 max. 4.8 4.5
Unit V
Test Conditions VQ_LDO1 decreasing VQ_LDO1 increasing IR1=1.6mA; VQ_LDO1 =5V IR1=0.3mA; VQ_LDO1 =1V
VRTH
Q_LDO1, in
4.55
4.70
4.9
V
3.4.98 Reset output VR1 L low voltage 3.4.99 Reset output VR1 L low voltage 3.4.100 Reset High leakage current Reset R2 3.4.101 Reset threshold Q_LDO2 3.4.102 Reset threshold hysteresis Q_LDO2 3.4.103 Reset threshold Q_LDO2 3.4.104 Reset threshold hysteresis Q_LDO2 VRTH
Q_LDO2, de
0.4 0.3 1
V V A
IR1 H
2.6
2.8
3.0
V
3.3V mode; VQ_LDO2 decreasing 3.3V mode
VRTH
Q_LDO2, in
40 -
mV
VRTH
Q_LDO2, de
VRTH
Q_LDO2, de
2.3
2.4
2.5
V
2.6V mode; VQ_LDO2 decreasing 2.6V mode
VRTH
Q_LDO2, in
40 -
mV
VRTH
Q_LDO2, de
3.4.105 Reset output VR2 L low voltage 3.4.106 Reset output VR2 L low voltage 3.4.107 Reset High leakage current
Data Sheet, Rev. 1.31
0.4 0.3 1
V V A
IR2=1.6mA; VQ_LDO2 =2.5V IR2=0.3mA; VQ_LDO2 =1V
IR2 H
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-40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter Reset R3 3.4.108 Reset threshold Q_LDO3 3.4.109 Reset threshold hysteresis Q_LDO3 3.4.110 Reset threshold Q_LDO3 3.4.111 Reset threshold hysteresis Q_LDO3 VRTH
Q_LDO3, de
Symbol min. 2.7
Limit Values typ. 2.85 max. 3.0
Unit
Test Conditions
V
3.3V mode; VQ_LDO3 decreasing 3.3V mode
VRTH
Q_LDO3, in
40 -
mV
VRTH
Q_LDO3, de
VRTH
Q_LDO3, de
4.0
4.2
4.5
V
5V mode; VQ_LDO3 decreasing 5V mode
VRTH
Q_LDO3, in
40 -
mV
VRTH
Q_LDO3, de
3.4.112 Reset output VR3 L low voltage 3.4.113 Reset output VR3 L low voltage 3.4.114 Reset High leakage current IR3 H
0.4 0.3 1
V V A
IR3=1.6mA; VQ_LDO3 =3.3V IR3=0.3mA; VQ_LDO3 =1V
3.4.115 Reset trr reaction time 3.4.116 Reset Delay Norm factor 3.4.117 Reset Delay time
1
2
10
s
1)
Valid for R1, R2 and R3 1 1 1.25 1.25 1 tRES(SPI) Valid for R1, R2 and R3; tRES (SPI) is defined by the SPI word (see section 2.12) V
tNORM,RES 0.75 tRES 0.75
RAM Good 3.4.118 VQ1 threshold VTh Q1 2.3 2.8 3.3
Data Sheet, Rev. 1.31
38
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-40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter Symbol min. 3.4.119 VQ2 threshold VTh Q2 3.4.120 VQ2 threshold VTh Q2 Window Watchdog 3.4.121 Closed window time tolerance tCW_tol 0.75 1 1.25 Multiply with watchdog window time set by SPI to obtain the limits (2.12) Multiply with watchdog window time set by SPI to obtain the limits (2.12) 1.2 1.2 Limit Values typ. 1.4 1.4 max. 1.7 1.7 V V 3.3V mode 2.6V mode; 1) Unit Test Conditions
3.4.122 Open window time tolerance
tOW_tol
0.75
1
1.25
3.4.123 Watchdog reset low time 3.4.124 Watchdog reset delay time 3.4.125 H-output voltage level 3.4.126 L-output voltage level
tWRL
tRES
tSR
tCW/2
Error Output ERR
VERR,H VERR,L
VQ_LDO1
- 2.0 -
VQ_LDO1
- 0.7 0.3
- 0.5
V V
IERR, H = 1 mA IERR, L = - 1.6 mA
SPI 3.4.127 SPI clock frequency SPI Input DI fCLK 0 2.5 MHz Production test up to 1MHz; 2.5MHz 1)
Data Sheet, Rev. 1.31
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2004-10-12
TLE 6361 G
-40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter 3.4.128 H-input voltage threshold 3.4.129 L-input voltage threshold Symbol min. Limit Values typ. 40 max. 70 % of
-
Unit
Test Conditions
VIH
-
VQ_LDO1 VIL
20 36 - % of
-
VQ_LDO1
50 5 - - - 200 25 10 - - 500 100 15 200 200 mV A pF ns ns
1)
3.4.130 Hysteresis of VIHY input voltage 3.4.131 Pull down current 3.4.132 Input capacitance 3.4.133 Input signal rise time 3.4.134 Input signal fall time 3.4.135 H-input voltage threshold 3.4.136 L-input voltage threshold
II CI tr tf
VDI = 0.2 * VQ_LDO1 0 V < VQ_LDO1 < 5.25 V
1)
1)
SPI Clock Input CLK
VIH
-
40
70
% of
-
VQ_LDO1 VIL
20 36 - % of
-
VQ_LDO1
50 5 - - - 200 25 10 - - 500 100 15 200 200 mV A pF ns ns
1)
3.4.137 Hysteresis of VIHY input voltage 3.4.138 Pull down current 3.4.139 Input capacitance 3.4.140 Input signal rise time 3.4.141 Input signal fall time
II CI tr tf
VCLK = 0.2 * VQ_LDO1 0 V < VQ_LDO1 < 5.25 V
1)
1)
SPI Chip Select Input CS
Data Sheet, Rev. 1.31 40 2004-10-12
TLE 6361 G
-40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter 3.4.142 H-input voltage threshold 3.4.143 L-input voltage threshold Symbol min. Limit Values typ. 39 max. 70 % of
-
Unit
Test Conditions
VIH
-
VQ_LDO1 VIL
20 35 - % of
-
VQ_LDO1
50 - 100 200 - 25 500 -5 mV A
1)
3.4.144 Hysteresis of VIHY input voltage 3.4.145 Pull up II, CS current at pin CS 3.4.146 Input capacitance 3.4.147 Input signal rise time 3.4.148 Input signal fall time
VCS = 0.2 * VQ_LDO1 0 V < VQ_LDO1 < 5.25 V
1)
CI tr tf
- - -
10 - -
15 200 200
pF ns ns
1)
Logic Output DO 3.4.149 H-output voltage level 3.4.150 L-output voltage level 3.4.151 Tri-state leakage current 3.4.152 Tri-state input capacitance
VDOH VDOL IDO_TRI
VQ_LDO1
- 1.0 - - 10
VQ_LDO1
- 0.8 0.2 -
- 0.4 10
V V A
IDOH = 1 mA IDOL = - 1.6 mA VCS = VQ_LDO1; 0 V < VDO < VQ_LDO1 VCS = VQ_LDO1 0 V < VQ_LDO1 < 5.25 V
CDO
-
10
15
pF
Data Input Timing 3.4.153 Clock period
tpCLK
1000
-
-
ns
1)
Data Sheet, Rev. 1.31
41
2004-10-12
TLE 6361 G
-40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter 3.4.154 Clock high time 3.4.155 Clock low time 3.4.156 Clock low before CS low 3.4.157 CS setup time 3.4.158 CLK setup time Symbol min. Limit Values typ. - - - max. - - - ns ns ns
1)
Unit
Test Conditions
tCLKH tCLKL tbef
500 500 500
1)
1)
tlead tlag
500 500 500 250 250
- - - - -
- - - - -
ns ns ns ns ns
1)
1)
3.4.159 Clock low tbeh after CS high 3.4.160 DI setup time tDISU 3.4.161 DI hold time
1)
1) 1)
tDIHO
Data Output Timing 3.4.162 DO rise time trDO 3.4.163 DO fall time 3.4.164 DO enable time 3.4.165 DO disable time - - - - - 50 50 - - 100 100 100 250 250 250 ns ns ns ns ns
CL = 100 pF CL = 100 pF low impedance
tfDO tENDO tDISDO
high impedance
3.4.166 DO valid time tVADO
VDO < 10% VDO > 90% CL = 100 pF
General 3.4.167 Temperature TJ,Flag warning flag TJ,Shutdown 150 3.4.168 Over Temperature shutdown 140 170 200 C C
2)
Data Sheet, Rev. 1.31
42
2004-10-12
TLE 6361 G
-40 < Tj <150 C; VIN=13.5V unless otherwise specified Item Parameter Symbol min. 3.4.169 OverTsd_hys Temperature shutdown Hysteresis 3.4.170 DeltaTW to TSD
1)
Limit Values typ. 30 max.
Unit K
Test Conditions
TJ,Shutdown - TJ,Flag
20
K
Specified by design, not subject to production test Simulated at wafer test only, not absolutely measured
2)
4
Typical performance charcteristics
Buck converter switching frequency vs. junction temperature
fSW kHz 420
400
380
360
340
320
300
280 -50
-20
10
40
70
100
130
Tj C
160
Data Sheet, Rev. 1.31
43
2004-10-12
TLE 6361 G
Buck converter output voltage at 1.5A load Buck converter current limit vs. junction temperature vs. junction temperature
VFB/L_IN V 6.0 IMAX A 4.0
5.9
3.5
5.8
3.0
5.7
2.5
5.6
2.0
5.5
1.5
5.4
1.0
5.3 -50
-20
10
40
70
100
130
Tj C
160
0.5 -50
-20
10
40
70
100
130
Tj C
160
Buck converter DMOS on-resistance vs. junction temperature
RON m 400
Start-up bootstrap charging current vs. junction temperature
IBTSTR A 280
350
240
300
200
250
160
200
120
150
80
100
40
50 -50
-20
10
40
70
100
130
Tj C
160
0
-50
-20
10
40
70
100
130
Tj C
160
Data Sheet, Rev. 1.31
44
2004-10-12
TLE 6361 G
Bootstrap UV lockout, turn on threshold vs. junction temperature
VBTSTR, 8.5
turn on
Q_LDO1 output voltage at 800mA load vs. junction temperature
VQ_LDO1 V 5.20
V
8.0
5.15
7.5
5.10
7.0
5.05
6.5
5.00
6.0
4.95
5.5
4.90
5.0 -50
-20
10
40
70
100
130
Tj C
160
4.85 -50
-20
10
40
70
100
130
Tj C
160
Device wake up thresholds vs. junction temperature
Vwake th V 2.8
Reset1 threshold at drecreasing V_LDO1 vs. junction temperature
VRTH V 4.80
Q_LDO1, de
2.7
4.75
2.6
4.70
2.5 V wake th, on 2.4
4.65
4.60
2.3 Vwake th, off 2.2
4.55
4.50
2.1 -50
-20
10
40
70
100
130
Tj C
160
4.45 -50
-20
10
40
70
100
130
Tj C
160
Data Sheet, Rev. 1.31
45
2004-10-12
TLE 6361 G
Q_LDO1 current limit vs. junction temperature
IQ_LDO1 V 1400
Q_LDO2 current limit (2.6V mode) vs. junction temperature
IQ_LDO2 V 850
1300
800
1200
750
1100
700
1000
650
900
600
800
550
700 -50
-20
10
40
70
100
130
Tj C
160
500 -50
-20
10
40
70
100
130
Tj C
160
Q_LDO2 output voltage at 400mA load (2.6V mode) vs. junction temperature
VQ_LDO2 V 2.80
Q_LDO3 output voltage at 300mA load (3.3V mode) vs. junction temperature
VQ_LDO3 3.50 V
2.75
3.45
2.70
3.40
2.65
3.35
2.60
3.30
2.55
3.25
2.50
3.20
2.45 -50
-20
10
40
70
100
130
Tj C
160
3.15 -50
-20
10
40
70
100
130
Tj C
160
Data Sheet, Rev. 1.31
46
2004-10-12
TLE 6361 G
Reset2 threshold at decreasing V_LDO2 (2.6V mode) vs. junction temperature
VRTH V 2.60
Q_LDO2, de
Reset3 threshold at decreasing V_LDO3 (3.3V mode) vs. junction temperature
VRTH V 3.00
Q_LDO3, de
2.55
2.95
2.50
2.90
2.45
2.85
2.40
2.80
2.35
2.75
2.30
2.70
2.25 -50
-20
10
40
70
100
130
Tj C
160
2.65 -50
-20
10
40
70
100
130
Tj C
160
Q_LDO3 current limit (3.3V mode) vs. junction temperature
IQ_LDO3 V 600
Tracker current limit vs. junction temperature
IQ_Tx mA 32
550
30
500
28
450
26
400
24
350
22
300
20
250 -50
-20
10
40
70
100
130
Tj C
160
18
-50
-20
10
40
70
100
130
Tj C
160
Data Sheet, Rev. 1.31
47
2004-10-12
TLE 6361 G
Tracker accuracy with respect to V_LDO1 vs. junction temperature
dVQ_Tx mV 4
Q_STB current limit vs. junction temperature
IQ_STB mA 4.0
2
3.5
0
3.0
-2
2.5
-4
2.0
-6
1.5
-8
1.0
-10 -50
-20
10
40
70
100
130
Tj C
160
0.5 -50
-20
10
40
70
100
130
Tj C
160
Q_STB output voltage at 500A load vs. junction temperature
VQ_STB V 2.8
Device current consumption in off mode vs. junction temperature
Iq, off A 35
2.7
30
2.6
25
2.5
20
2.4
15
2.3
10
2.2
5
2.1 -50
-20
10
40
70
100
130
Tj C
160
0
-50
-20
10
40
70
100
130
Tj C
160
Data Sheet, Rev. 1.31
48
2004-10-12
TLE 6361 G
5 5.1
Application Information Application Diagram
RBoost
22 DBOOST TLE 6361 Standby Regulator 2.5 V Q_STB
CSTB
SW 2*
LI
Battery
CBOOST
100 nF BOOST 2* IN
Up to 47 H
100 nF
LB CBTSTR
47 H + DB 3 A, 60 V
Buck Output > 10 F ceramic or > 20 F low ESR tantalum
CI1
+
100 nF
CI2
CI3
47 F
10 to 100 nF SLEW
Buck Regulator Driver ErrorAmplifier OSZ PWM BOOTSTRAP
CB
680 nF
RSlew
0 to 20 k
Internal Reference
Feedback To IGN Protection Charge Pump WAKE 10 k 10 k 10 k R1 Power Down Logic Lin. Reg. 5V Reset Logic Lin. Reg. 3.3/2.6 V Lin. Reg. 5/3.3 V Ref Window Watchdog CCCP FB/L_IN 2* C+ 10 k Q_LDO1
CFLY
100 nF
CCCP
SEL Q_LDO1
220 nF
CLDO1,1 +
Q_LDO2 470 nF
CLDO1,2
4.7 F
To C
R2
CLDO2,1 +
Q_LDO3 470 nF
CLDO2,2
4.7 F
R3
-Controller/ Memory Supply
CLDO3,1 +
470 nF Q_T1
CLDO3,2
4.7 F
Tracker 5V Tracker 5V Tracker 5V Tracker 5V Tracker 5V Tracker 5V
CT1
Q_T2
Ref
1 F
CT2
Q_T3
10 k
CLK
Ref
1 F
CT3
Q_T4
10 k
CS SPI 16 Bit
Ref
1 F
CT4
Q_T5
To C
10 k
DI
Ref
1 F
Sensor Supplies (off board supplies)
CT5
Q_T6
1 k
DO ERR GND 4*
Ref
1 F
CT6
1 F
AEA03380_6361ZR.VSD
Figure 14 Application Diagram
Data Sheet, Rev. 1.31 49 2004-10-12
TLE 6361 G
5.2
Buck converter circuit
A typical choice of external components for the buck converter is given in figure 14. For basic operation of the buck converter the input capacitor CI2, the bootstrap capacitor CBTP, the catch diode DB, the induuctance LB, the output capacitor CB and the charge pump capacitors CFLY and CCCP are necessary. The additional components shown on top of the circuit lower the electromagnetic emission (LI, CI1, CI3, RSlew) and the switching losses (RBoost, CBoost, DBoost). For 12V battery systems the switching loss minimization feature might not be used. In that case the Boost pin (33) is connected directly to the IN pins (32, 30) and the components RBoost, CBoost and DBoost are left away 5.2.1 Buck inductance (LB) selection:
The inductance value determines together with the input voltage, the output voltage and the switching frequency the current ripple which occurs during normal operation of the step down converter. This current ripple is important for the all over ripple at the output of the switching converter. As a rule of thumb this current ripple I is chosen between 10% and 50% of the load current. ( V I - V OUT ) V OUT L = -------------------------------------------------f SW V I I
For optimum operation of the control loop of the Buck converter the inductance value should be in the range indicated in section 3.3, recommended operation range. When picking finally the inductance of a certain supplier (Epcos, Coilcraft etc.) the saturation current has to be considered. With a maximum current limit of the Buck converter of 3.2A an inductance with a minimum saturation current of 3.2A has to be chosen.
Data Sheet, Rev. 1.31
50
2004-10-12
TLE 6361 G
5.2.2
Buck output capacitor (CB) selection:
The choice of the output capacitor effects straight to the minimum achievable ripple which is seen at the output of the buck converter. In continuous conduction mode the ripple of the output voltage equals:
1 V Ripple = I R ESRCB + ---------------------------- C 8f
SW B
From the formula it is recognized that the ESR has a big influence in the total ripple at the output, so ceramic types or low ESR tantalum capacitors are recommended for the application. One other important thing to note are the requirements for the resonant frequency of the output LC-combination. The choice of the components L and C have to meet also the specified range given in section 3.3 otherwise instabilities of the regulation loop might occur. 5.2.3 Input capacitor (CI2) selection:
At high load currents, where the current through the inductance flows continuously, the input capacitor is exposed to a square wave current with its duty cycle VOUT/VI. To prevent a high ripple to the battery line a capacitor with low ESR should be used. The maximum RMS current which the capacitor has to withstand is calculated to:
2 V OUT I 1 IRMS = I LOAD -------------- 1 + -- ---------------------- 3 2 I LOAD V IN
5.2.4
Freewheeling diode / catch diode (DB)
For lowest power loss in the freewheeling path Schottky diodes are recommended. With those types the reverse recovery charge is negligible and a fast handover from freewheeling to forward conduction mode is possible. Depending on the application (12V battery systems) 40V types could be also used instead of the 60V diodes. A fast recovery diode with recovery times in the range of 30ns can be also used if smaller junction capacitance values (smaller spikes) are desired, the slew resistor should be set in this case between 10 and 20k.
Data Sheet, Rev. 1.31
51
2004-10-12
TLE 6361 G
5.2.5
Bootstrap capacitor (CBTP)
The voltage at the Bootstrap capacitor does not exceed 15V, a ceramic type with a minimum of 2% of the buck output capacitance and voltage class 16V would be sufficient. 5.2.6 External charge pump capacitors (CFLY, CCCP)
Out of the feedback voltage the charge pump generates a voltage between 8 and 10V. The fly capacitor connected between C+ and C- is charged with the feedback voltage level and discharged to achieve the (almost) double voltage level at CCP. CFLY is chosen to 100nF and CCCP to 220nF, both ceramic types. The connection of CCP to a voltage source of e.g. 7V (take care of the maximum ratings!) via a diode improves the start-up behavior at very low battery voltage. The diode with the cathode on CCP has to be used in order to avoid any influence of the voltage source to the device's operation and vice versa. 5.2.7 Input filter components for reduced EME (CI1, CI2, CI3, LI, RSlew)
At the input of Buck converters a square wave current is observed causing electromagnetical interference on the battery line. The emission to the battery line consists on one hand of components of the switching frequency (fundamental wave) and its harmonics and on the other hand of the high frequency components derived from the current slope. For proper attenuation of those interferers a -type input filter structure is recommended which is built up with inductive (LI) and capacitive components (CI1, CI2, CI3). The inductance can be chosen up to the value of the Buck converter inductance, higher values might not be necessary, CI1 and CI3 should be ceramic types and for CI2 an input capacitance with very low ESR should be chosen and placed as close to the input of the Buck converter as possible. Inexpensive input filters show due to their parasitrics a notch filter characteristic, which means basically that the lowpass filter acts from a certain frequency as a highpass filter and means further that the high frequency components are not attenuated properly. For that reason the TLE 6361 G offers the possibility of current slope adjustment. The current transistion time can be set by the external slew resistor to times between 20ns and 80ns by varying the resistor value bewteen 0 (fastest transition) and 20k (slowest transistion). 5.2.8 Feedback circuit for minimum switching loss (RBoost, CBoost, DBoost)
To decrease the switching losses to a mininum the external components RBoost, CBoost and DBoost are needed. The current through the feedback resistor RBoost is about a few mA where the Diode DBoost and the capacitor CBoost run a part of the load current. If this feature is not needed the three components are not needed and the Boost pin (33) can be connected directly to the IN pins(32, 30).
Data Sheet, Rev. 1.31 52 2004-10-12
TLE 6361 G
5.3
Reverse polarity protection
The Buck converter is due to the parasitic source drain diode of the DMOS not reverse polarity protected. Therefore, as an example, the reverse polarity diode is shown in the application circuit, in general the reverse polarity protection can be done in different ways. 5.4 Linear voltage regulators (CLDO1, 2, 3)
As indicated before the linear regulators show stable operation with a minimum of 470nF ceramic capacitors. To avoid a high ripple at the output due to load steps this output cap might have to be increased to some few F capacitors. 5.5 Linear voltage trackers (CT1,2,3,4,5,6)
The voltage trackers require at their outputs 1F ceramic capacitors each to avoid some oscillation at the output. If needed the tracker outputs can be connected in parallel, in that the output capacitor increases linear according to the number of parallel outputs. 5.6 Reset outputs (R1,2,3)
The undervoltage/watchdog reset outputs are open drain structures and require external pull up resistors in the range of 10k to the C I/O voltage rail.
Data Sheet, Rev. 1.31
53
2004-10-12
TLE 6361 G
5.7 Device LI
Components recommendation - overview Type B82479 series B82464-A4 series DO3340P series DO5022P series DS5022P series SLF1275T-330M3R2 Supplier EPCOS EPCOS Coilcraft Coilcraft Coilcraft TDK various various various various EPCOS EPCOS Coilcraft Coilcraft Coilcraft various Motorola Motorola various EPCOS Taiyo Yuden TDK AVX various various 10-1000H; 4.3-0.56A 1-1000H; 6.8-0.3A 10-1000H; 8.0-0.8A 1-1000H; 20.0-1.0A 10-1000H; 8.0-0.8A 100nF, 10V Schottky, 60V, 3A Schottky, 40V, 3A Schottky, 40V, 3A Low ESR Tantalum, 22F, 10V, C-case Ceramic X7R, 4.7F, 10V Ceramic X7R, 10F, 16V Low ESR Tantalum, 47F, 10V, C-case 470nF, 10V 1F, 60V Remark 10-1000H; 4.3-0.56A 1-1000H; 6.8-0.3A 10-1000H; 8.0-0.8A 1-1000H; 20.0-1.0A 10-1000H; 8.0-0.8A 33H, 3.2A 100nF, 60V 47F, 60V 10nF to 100nF, 60V
CI1 CI2 CI3 DBoost LB
Ceramic Low ESR tantalum Ceramic S3B B82479 series B82464-A4 series DO3340P series DO5022P series DS5022P series
CBTP DB
Ceramic MBRD360 MBRD340 SS34
CB
B45197-A2226 2 * LMK316BJ475ML C3216X7R1C106M TPSC476K010R350
CLDOx CTx
Ceramic Ceramic
Data Sheet, Rev. 1.31
54
2004-10-12
TLE 6361 G
5.8
Layout recommendation
The most sensitive points for Buck converters - when considering the layout - are the nodes at the input and the output of the Buck switch, the DMOS transistor. For proper operation the external catch diode and Buck inductance have to be connected as close as possible to the SW pins (29, 31). Best suitable for the connection of the cathode of the Schottky diode and one terminal of the inductance would be a small plain located next to the SW pins. The GND connection of the catch diode must be also as short as possible. In general the GND level should be implemented as surface area over the whole PCB as second layer, if necessary as third layer. The pin FB/L_IN is sensitive to noise. With an appropriate layout the Buck output capacitor helps to avoid noise coupling to this pin. Also filtering of steep edges at the supply voltage pin e.g. as shown in the application diagram is mandatory. CI2 may either be a low ESR Tantalum capacitor or a ceramic capacitor. A minimum capacitance of 10F is recommended for CI2. To obtain the optimum filter capability of the input -filter it has to be located also as close as possible to the IN pins, at least the ceramic capacitor CI3 should be next to those pins.
Data Sheet, Rev. 1.31
55
2004-10-12
TLE 6361 G
Package Outlines P-DSO-36-12
SMD = Surface Mounted Device
Dimensions in mm
3.5 MAX.
3.25 0.1
11 0.15 1)
B
0.25
+0.07 -0.02
0 +0.1
1.1 0.1
2.8
0.65
15.74 0.1 (Heatslug) 36x 0.25 M A B C
1.3
6.3 (Mold)
14.2 0.3
0.1 C
Heatslug 0.95 0.15 0.25 B
0.25 +0.13
Bottom View
3.2 0.1 (Metal)
36
19
19
36
Index Marking
1 x 45
1
18
10
15.9 0.1 1) (Mold)
1)
A
13.7 -0.2 (Metal)
1
Heatslug
Does not include plastic or metal protrusion of 0.15 max. per side
see also: http://www.infineon.com -> Products -> Packages
Data Sheet, Rev. 1.31
56
5.9 0.1 (Metal)
5 3
2004-10-12
TLE 6361 G
Published by Infineon Technologies AG , Bereichs Kommunikation, St.-Martin-Strasse 53 D-81541 Munchen
(c) Infineon Technologies AG 2003
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologiesis an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Data Sheet, Rev. 1.31
57
2004-10-12

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