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SSD1339
Advance Information
132RGB x 132 with 2 smart Icon lines Dot Matrix OLED/PLED Segment/Common Driver with Controller
This document contains information on a new product. Specifications and information herein are subject to change without notice. http://www.solomon-systech.com SSD1339 Rev 1.1 P 1/59 Jul 2005 Copyright 2005 Solomon Systech Limited
TABLE OF CONTENTS 1. GERENAL DESCRIPTION...................................................................................................................................5 2. FEATURES..............................................................................................................................................................5 3. ORDERING INFORMATION...............................................................................................................................6 4. BLOCK DIAGRAM................................................................................................................................................7 5. DIE PAD FLOOR PLAN........................................................................................................................................8 6. PIN DESCRIPTION..............................................................................................................................................15 7. FUNCTIONAL BLOCK DISCRIPTIONS .........................................................................................................19 OSCILLATOR CIRCUIT AND DISPLAY TIME GENERATOR...........................................................................................19 RESET CIRCUIT.........................................................................................................................................................19 COMMAND DECODER AND COMMAND INTERFACE...................................................................................................20 MPU PARALLEL 6800-SERIES INTERFACE................................................................................................................20 MPU PARALLEL 8080-SERIES INTERFACE................................................................................................................20 MPU SERIAL INTERFACE .........................................................................................................................................21 GRAPHIC DISPLAY DATA RAM (GDDRAM) ..........................................................................................................22 GRAY SCALE AND GRAY SCALE TABLE ...................................................................................................................26 CURRENT CONTROL AND VOLTAGE CONTROL .........................................................................................................27 SEGMENT DRIVERS/COMMON DRIVERS ...................................................................................................................27 DC-DC VOLTAGE CONVERTER................................................................................................................................28 8. COMMAND TABLE ............................................................................................................................................29 9. COMMAND DESCRIPTIONS ............................................................................................................................34 10. MAXIMUM RATINGS.......................................................................................................................................47 11. DC CHARACTERISTICS..................................................................................................................................48 12. AC CHARACTERISTICS..................................................................................................................................49 13. APPLICATION EXAMPLE ..............................................................................................................................53 14. PACKAGE INFORMATION.............................................................................................................................54 SSD1339U3 PIN ASSIGNMENT.................................................................................................................................54 SSD1339U3 COF DETAILS DIMENSIONS..................................................................................................................56
Solomon Systech
Jul 2005
P 2/59
Rev 1.1
SSD1339
TABLE OF FIGURES FIGURE 1 - BLOCK DIAGRAM ........................................................................................................................................7 FIGURE 2 - SSD1339Z PIN ASSIGNMENT .......................................................................................................................8 FIGURE 3 - SSD1339Z ALIGNMENT MARK DIMENSIONS ..............................................................................................13 FIGURE 4 - DIE TRAY INFORMATION ............................................................................................................................14 FIGURE 5 - OSCILLATOR CIRCUIT ................................................................................................................................19 FIGURE 6 - DISPLAY DATA READ BACK PROCEDURE - INSERTION OF DUMMY READ.....................................................20 FIGURE 7 - DISPLAY DATA WRITE PROCEDURE IN SPI MODE .......................................................................................21 FIGURE 8 - GRAPHIC DISPLAY DATA RAM STRUCTURE .............................................................................................22 FIGURE 9 - 262K COLOR DEPTH DATA WRITING SEQUENCE IN 18-BIT MCU INTERFACE ..............................................22 FIGURE 10 - 262K COLOR DEPTH DATA WRITING SEQUENCE IN 16-BIT MCU INTERFACE IN OPTION 1 ........................23 FIGURE 11 - 262K COLOR DEPTH DATA WRITING SEQUENCE IN 16-BIT MCU INTERFACE IN OPTION 2 ........................23 FIGURE 12 - 262K COLOR DEPTH GRAPHIC DISPLAY DATA WRITING SEQUENCE IN 9-BIT MCU INTERFACE .................23 FIGURE 13 - 262K COLOR DEPTH GRAPHIC DISPLAY DATA WRITING SEQUENCE IN 8-BIT MCU INTERFACE .................23 FIGURE 14 - 65K COLOR DEPTH GRAPHIC DISPLAY DATA WRITING SEQUENCE IN 16-BIT MCU INTERFACE .................23 FIGURE 15 - 65K COLOR DEPTH GRAPHIC DISPLAY DATA WRITING SEQUENCE IN 8-BIT MCU INTERFACE ...................24 FIGURE 16 - DISPLAY DATA RAM WRITING POSITION FOR COLOR A, B AND C DATA INPUT IN 65K COLOR MODE ......24 FIGURE 17 - DISPLAY DATA RAM WRITING POSITION FOR COLOR A, B AND C DATA INPUT IN 256 COLOR MODE ......25 FIGURE 18 - RELATION BETWEEN GRAPHIC DATA RAM VALUE AND GRAY SCALE TABLE ENTRY FOR THREE COLORS 26 FIGURE 19 - ILLUSTRATION OF RELATION BETWEEN GRAPHIC DISPLAY RAM VALUE AND GRAY SCALE CONTROL .....27 FIGURE 20 - EXAMPLE OF COLUMN AND ROW ADDRESS POINTER MOVEMENT .............................................................34 FIGURE 21 - ADDRESS POINTER MOVEMENT OF HORIZONTAL ADDRESS INCREMENT MODE .........................................35 FIGURE 22 - ADDRESS POINTER MOVEMENT OF VERTICAL ADDRESS INCREMENT MODE ..............................................35 FIGURE 23 - EXAMPLE OF SET DISPLAY START LINE WITH NO REMAP ..........................................................................37 FIGURE 24 - EXAMPLE OF SET DISPLAY OFFSET WITH NO REMAP .................................................................................37 FIGURE 25 - EXAMPLE OF GAMMA CORRECTION BY GRAY SCALE TABLE SETTING.......................................................39 FIGURE 26 - SEGMENT OUTPUT CURRENT FOR DIFFERENT CONTRAST CONTROL AND MASTER CURRENT SETTING.......41 FIGURE 27 - EXAMPLE OF DRAW LINE COMMAND........................................................................................................42 FIGURE 28 - EXAMPLE OF DRAW RECTANGLE COMMAND ............................................................................................42 FIGURE 29 - EXAMPLE OF DRAW CIRCLE COMMAND....................................................................................................43 FIGURE 30 - EXAMPLE OF COPY COMMAND .................................................................................................................44 FIGURE 31 - EXAMPLE OF COPY + CLEAR = MOVE COMMAND....................................................................................45 FIGURE 32 - 6800-SERIES MPU PARALLEL INTERFACE CHARACTERISTICS ..................................................................50 FIGURE 33 - 8080-SERIES MPU PARALLEL INTERFACE CHARACTERISTICS ..................................................................51 FIGURE 34 - SERIAL INTERFACE CHARACTERISTICS.....................................................................................................52 FIGURE 35 - APPLICATION EXAMPLE FOR 8-BIT 6800-PARALLEL INTERFACE MODE ....................................................53 FIGURE 36 - SSD1339U3 PIN ASSIGNMENT..................................................................................................................54 FIGURE 37 - SSD1339U3 DETAIL DIMENSIONS ............................................................................................................56
SSD1339
Rev 1.1
P 3/59
Jul 2005
Solomon Systech
LIST OF TABLES TABLE 1 - ORDERING INFORMATION .............................................................................................................................6 TABLE 2 - SSD1339Z DIE PAD COORDINATES..............................................................................................................9 TABLE 3 - COMMAND TABLE .......................................................................................................................................29 TABLE 4 - GRAPHIC ACCELERATION COMMAND ..........................................................................................................32 TABLE 5 - RESULT OF CHANGE OF BRIGHTNESS BY DIM WINDOW COMMAND ..............................................................44 TABLE 6 - MAXIMUM RATINGS ....................................................................................................................................47 TABLE 7 - DC CHARACTERISTICS ................................................................................................................................48 TABLE 8 - AC CHARACTERISTICS ................................................................................................................................49 TABLE 9 - 6800-SERIES MPU PARALLEL INTERFACE TIMING CHARACTERISTICS.........................................................50 TABLE 10 - 8080-SERIES MPU PARALLEL INTERFACE TIMING CHARACTERISTICS ......................................................51 TABLE 11 - SERIAL INTERFACE TIMING CHARACTERISTICS ..........................................................................................52 TABLE 12 - SSD1339U3 PIN ASSIGNMENT...................................................................................................................55
Solomon Systech
Jul 2005
P 4/59
Rev 1.1
SSD1339
1. GERENAL DESCRIPTION
The SSD1339 is a single-chip CMOS OLED/PLED driver with controller for organic/polymer light emitting diode dot-matrix graphic display system. It consists of 396 segments (132RGB), 132 commons and 2 smart icon lines. This IC is designed for Common Cathode type OLED panel. The SSD1339 displays data directly from its internal 132x133x18 bits Graphic Data RAM (GDDRAM). Data/Commands are sent from general MCU through the hardware selectable 6800/8000 series compatible Parallel Interface or Serial Peripheral Interface. It has a 256 steps contrast control and 262k color control
2. FEATURES
! ! ! ! ! ! ! ! ! ! ! ! ! ! Support max. 132RGB x 132 matrix panel + icon line Power supply: VDD=2.4-3.5V VDDIO=1.5V - 3.5V VCC=7.0V - 18.0V OLED driving output voltage, 16V maximum DC-DC voltage booster controller Segment maximum source current: 200uA Common maximum sink current: 80mA Embedded 132x133x18 bit SRAM display buffer 16 step master current control, and 256 step current control for the three color components Smart Icon mode Programmable color mode of 256, 65k, 262k Programmable Frame Rate Graphic Acceleration Command Set (GAC) 8/9/16/18-bit 6800-series Parallel Interface, 8/9/16/18-bit 8080-series Parallel Interface and Serial Peripheral Interface. Wide range of operating temperature: -40 to 90 C
SSD1339
Rev 1.1
P 5/59
Jul 2005
Solomon Systech
3. ORDERING INFORMATION
Table 1 - Ordering Information
Ordering Part Number SEG COM Package Form Reference * * Remark Min SEG pad pitch: 41.2 m Min COM pad pitch: 41.2 m
SSD1339Z
132RGB
132
COG
Page 8
Punched COF SSD1339U3 128RGB 128 COF Page 54
Solomon Systech
Jul 2005
P 6/59
Rev 1.1
SSD1339
4. BLOCK DIAGRAM
Grey Scale Decoder
D17 - D0
MCU Interface
GDDRAM
RES# CS# D/C# E (RD#) R/W#(WR#) BS2 BS1 BS0
. . . . . . . . . . .
Common Drivers(even)
COM130 COM128
| COM2 COM0 COMX
VDDIO VDD VSS
. . . . . . . . . . .
Segment Drivers
SA0 SB0 SC0 SA1 SB1 SC1 |
SA131 SB131 SC131
Common Drivers (odd)
. . . . . . . . . . .
Seg/Com OLED
DC-DC voltage
Driving block
Command Decoder
Oscillator
Display Timing Generator
converter
COM1 COM3
| COM129 COM131 COMX
BGGND VDDB VSSB GDR RESE FB VBref VCC VCOMH VREF VPA VPB VPC IREF
CL CLS
Figure 1 - Block Diagram
SSD1339
Rev 1.1
P 7/59
Jul 2005
VSL VCL
Solomon Systech
5. DIE PAD FLOOR PLAN
Pad #1
+ represents the centre of the alignment mark
X-pos (m) -8176.0 8176.0 -9140.0 9140.0 All alignment keys have size 75 m x 75 m
Y-pos (m) 307.0 307.0 -941.0 -941.0
Die Size: 20989um x 2250um Die Thickness: 457um +/- 25um Min I/O pad pitch: 76.2 m Min SEG pad pitch: 41.2 m Min COM pad pitch: 41.2 m Bump Height: Nominal 15 m
Figure 2 - SSD1339Z pin assignment
Solomon Systech
Jul 2005
P 8/59
Rev 1.1
SSD1339
Table 2 - SSD1339Z Die Pad Coordinates
Pad # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pad Name NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCC VCC VCC VCC VCC VCC VCC VCC VCOMH VCOMH VCOMH VSL VSL VSL VSL VSL VSL VSL VSL VSL VDD VDD VDD VDD VDD VDD VDD VDD VCL VCL VCL VCL VCL VCL VCL VCL VCL VSS VSS VSS VSS VSS VSS VSSB VSSB VSSB VSSB TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 X-Axis -10160.275 -10084.075 -10007.875 -9931.675 -9737.3 -9661.1 -9584.9 -9508.7 -9432.5 -9356.3 -9280.1 -9203.9 -9127.7 -9051.5 -8975.3 -8899.1 -8822.9 -8746.7 -8670.5 -8594.3 -8518.1 -8441.9 -8305.8 -8229.6 -8153.4 -8077.2 -8001 -7924.8 -7848.6 -7772.4 -7696.2 -7620 -7543.8 -7467.6 -7391.4 -7315.2 -7239 -7162.8 -7086.6 -7010.4 -6934.2 -6858 -6781.8 -6705.6 -6629.4 -6553.2 -6477 -6400.8 -6324.6 -6248.4 -6172.2 -6096 -6019.8 -5943.6 -5867.4 -5791.2 -5715 -5638.8 -5562.6 -5486.4 -5410.2 -5334 -5257.8 -5181.6 -5105.4 -5029.2 -4953 -4876.8 -4800.6 -4724.4 -4648.2 -4572 -4495.8 -4419.6 -4343.4 -4267.2 -4191 -4114.8 -4038.6 -3962.4 Y-Axis -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 Pad # 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Pad Name TR0 VSS VSSB VSSB VSSB VSSB GDR GDR GDR GDR GDR GDR GDR GDR GDR GDR GDR GDR GDR GDR GDR GDR GDR GDR GDR GDR VDDB VDDB VDDB VDDB VDD VDD VDD VDD FB VSS RESE VBREF VSS BGGND NC VPA VPB VPC VSS NC VSS GPIO0 GPIO1 VDDIO ICASC ICASB ICASA VSS VREF VCC VMONA VMONA VCC VCC VCC VCC VCC VSS IREF M CL DOF# RES# VSS D/C# VDDIO CS# VSS BS2 VDDIO BS1 VSS BS0 VDDIO X-Axis -3886.2 -3810 -3733.8 -3657.6 -3581.4 -3505.2 -3429 -3352.8 -3276.6 -3200.4 -3124.2 -3048 -2971.8 -2895.6 -2819.4 -2743.2 -2667 -2590.8 -2514.6 -2438.4 -2362.2 -2286 -2209.8 -2133.6 -2057.4 -1981.2 -1905 -1828.8 -1752.6 -1676.4 -1600.2 -1524 -1447.8 -1371.6 -1295.4 -1219.2 -1143 -1066.8 -990.6 -914.4 -838.2 -762 -685.8 -609.6 -533.4 -457.2 -381 -304.8 -228.6 -152.4 -76.2 0 76.2 152.4 228.6 304.8 381 457.2 533.4 609.6 685.8 762 838.2 914.4 990.6 1066.8 1143 1219.2 1295.4 1371.6 1447.8 1524 1600.2 1676.4 1752.6 1828.8 1905 1981.2 2057.4 2133.6 Y-Axis -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 Pad # Pad Name 161 VSS 162 R/W#(WR#) 163 E(RD#) 164 VDDIO 165 D0 166 D1 167 D2 168 D3 169 D4 170 D5 171 D6 172 D7 173 D8 174 D9 175 D10 176 D11 177 D12 178 D13 179 D14 180 D15 181 VDDIO 182 MS 183 CLS 184 D16 185 D17 186 VSS 187 VSS 188 VSS 189 VSS 190 VSS 191 VSS 192 VCL 193 VCL 194 VCL 195 VCL 196 VCL 197 VCL 198 VCL 199 VCL 200 VCL 201 VCL 202 VCL 203 VCL 204 VDD 205 VDD 206 VDD 207 VDD 208 VDD 209 VDD 210 VDD 211 VDD 212 VSL 213 VSL 214 VSL 215 VSL 216 VSL 217 VSL 218 VSL 219 VSL 220 VSL 221 VSL 222 VSL 223 VSL 224 VDDIO 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 VDDIO VCOMH VCOMH VCOMH VCOMH VCOMH VCC VCC VCC VCC VCC VCC VCC VCC NC NC X-Axis 2209.8 2286 2362.2 2438.4 2514.6 2590.8 2667 2743.2 2819.4 2895.6 2971.8 3048 3124.2 3200.4 3276.6 3352.8 3429 3505.2 3581.4 3657.6 3733.8 3810 3886.2 3962.4 4038.6 4114.8 4191 4267.2 4343.4 4419.6 4495.8 4572 4648.2 4724.4 4800.6 4876.8 4953 5029.2 5105.4 5181.6 5257.8 5334 5410.2 5486.4 5562.6 5638.8 5715 5791.2 5867.4 5943.6 6019.8 6096 6172.2 6248.4 6324.6 6400.8 6477 6553.2 6629.4 6705.6 6781.8 6858 6934.2 7010.4 7086.6 7162.8 7239 7315.2 7391.4 7467.6 7543.8 7620 7696.2 7772.4 7848.6 7924.8 8001 8077.2 8153.4 8229.6 Y-Axis -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043
SSD1339
Rev 1.1
P 9/59
Jul 2005
Solomon Systech
Pad # 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320
Pad Name NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC COM65 COM64 COM63 COM62 COM61 COM60 COM59 COM58 COM57 COM56 COM55 COM54 COM53 COM52 COM51 COM50 COM49 COM48 COM47 COM46 COM45 COM44 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC COM43 COM42 COM41 COM40 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM31
X-Axis 8305.8 8441.9 8518.1 8594.3 8670.5 8746.7 8822.9 8899.1 8975.3 9051.5 9127.7 9203.9 9280.1 9356.3 9432.5 9508.7 9584.9 9661.1 9737.3 9931.675 10007.875 10084.075 10160.275 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10359.7 10389.7 10318.5 10258.8 10217.6 10176.4 10135.2 10094 10052.8 10011.6 9970.4 9929.2 9888 9846.8 9805.6 9764.4
Y-Axis -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1043 -1060 -967 -925.8 -884.6 -843.4 -802.2 -761 -719.8 -678.6 -637.4 -596.2 -555 -513.8 -472.6 -431.4 -390.2 -349 -307.8 -266.6 -225.4 -184.2 -143 -101.8 -60.6 -19.4 21.8 63 104.2 145.4 186.6 227.8 269 310.2 351.4 404.1 562.95 615.65 656.85 698.05 739.25 780.45 833.15 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030
Pad # 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400
Pad Name COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMX NC NC NC SA0 SB0 SC0 SA1 SB1 SC1 SA2 SB2 SC2 SA3 SB3 SC3 SA4 SB4 SC4 SA5 SB5 SC5 SA6 SB6 SC6 SA7 SB7 SC7 SA8 SB8 SC8 SA9 SB9 SC9 SA10 SB10 SC10 SA11 SB11 SC11 SA12 SB12 SC12 SA13 SB13 SC13 SA14 SB14 SC14
X-Axis 9723.2 9682 9640.8 9599.6 9558.4 9517.2 9476 9434.8 9393.6 9352.4 9311.2 9270 9228.8 9187.6 9146.4 9105.2 9064 9022.8 8981.6 8940.4 8899.2 8858 8816.8 8775.6 8734.4 8693.2 8652 8610.8 8569.6 8528.4 8487.2 8446 8404.8 8363.6 8240 8198.8 8157.6 8116.4 8075.2 8034 7992.8 7951.6 7910.4 7869.2 7828 7786.8 7745.6 7704.4 7663.2 7622 7580.8 7539.6 7498.4 7457.2 7416 7374.8 7333.6 7292.4 7251.2 7210 7168.8 7127.6 7086.4 7045.2 7004 6962.8 6921.6 6880.4 6839.2 6798 6756.8 6715.6 6674.4 6633.2 6592 6550.8 6509.6 6468.4 6427.2 6386
Y-Axis 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030
Pad # 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480
Pad Name SA15 SB15 SC15 SA16 SB16 SC16 SA17 SB17 SC17 SA18 SB18 SC18 SA19 SB19 SC19 SA20 SB20 SC20 SA21 SB21 SC21 SA22 SB22 SC22 SA23 SB23 SC23 SA24 SB24 SC24 SA25 SB25 SC25 SA26 SB26 SC26 SA27 SB27 SC27 SA28 SB28 SC28 SA29 SB29 SC29 SA30 SB30 SC30 SA31 SB31 SC31 SA32 SB32 SC32 SA33 SB33 SC33 SA34 SB34 SC34 SA35 SB35 SC35 SA36 SB36 SC36 SA37 SB37 SC37 SA38 SB38 SC38 SA39 SB39 SC39 SA40 SB40 SC40 SA41 SB41
X-Axis 6344.8 6303.6 6262.4 6221.2 6180 6138.8 6097.6 6056.4 6015.2 5974 5932.8 5891.6 5850.4 5809.2 5768 5726.8 5685.6 5644.4 5603.2 5562 5520.8 5479.6 5438.4 5397.2 5356 5314.8 5273.6 5232.4 5191.2 5150 5108.8 5067.6 5026.4 4985.2 4944 4902.8 4861.6 4820.4 4779.2 4738 4696.8 4655.6 4614.4 4573.2 4532 4490.8 4449.6 4408.4 4367.2 4326 4284.8 4243.6 4202.4 4161.2 4120 4078.8 4037.6 3996.4 3955.2 3914 3872.8 3831.6 3790.4 3749.2 3708 3666.8 3625.6 3584.4 3543.2 3502 3460.8 3419.6 3378.4 3337.2 3296 3254.8 3213.6 3172.4 3131.2 3090
Y-Axis 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030
Solomon Systech
Jul 2005
P 10/59
Rev 1.1
SSD1339
Pad # 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560
Pad Name SC41 SA42 SB42 SC42 SA43 SB43 SC43 SA44 SB44 SC44 SA45 SB45 SC45 SA46 SB46 SC46 SA47 SB47 SC47 SA48 SB48 SC48 SA49 SB49 SC49 SA50 SB50 SC50 SA51 SB51 SC51 SA52 SB52 SC52 SA53 SB53 SC53 SA54 SB54 SC54 SA55 SB55 SC55 SA56 SB56 SC56 SA57 SB57 SC57 SA58 SB58 SC58 SA59 SB59 SC59 SA60 SB60 SC60 SA61 SB61 SC61 SA62 SB62 SC62 SA63 SB63 SC63 SA64 SB64 SC64 SA65 SB65 SC65 SA66 SB66 SC66 SA67 SB67 SC67 SA68
X-Axis 3048.8 3007.6 2966.4 2925.2 2884 2842.8 2801.6 2760.4 2719.2 2678 2636.8 2595.6 2554.4 2513.2 2472 2430.8 2389.6 2348.4 2307.2 2266 2224.8 2183.6 2142.4 2101.2 2060 2018.8 1977.6 1936.4 1895.2 1854 1812.8 1771.6 1730.4 1689.2 1648 1606.8 1565.6 1524.4 1483.2 1442 1400.8 1359.6 1318.4 1277.2 1236 1194.8 1153.6 1112.4 1071.2 1030 988.8 947.6 906.4 865.2 824 782.8 741.6 700.4 659.2 618 576.8 535.6 494.4 453.2 412 370.8 329.6 288.4 247.2 206 164.8 123.6 82.4 41.2 0 -41.2 -82.4 -123.6 -164.8 -206
Y-Axis 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030
Pad # 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640
Pad Name SB68 SC68 SA69 SB69 SC69 SA70 SB70 SC70 SA71 SB71 SC71 SA72 SB72 SC72 SA73 SB73 SC73 SA74 SB74 SC74 SA75 SB75 SC75 SA76 SB76 SC76 SA77 SB77 SC77 SA78 SB78 SC78 SA79 SB79 SC79 SA80 SB80 SC80 SA81 SB81 SC81 SA82 SB82 SC82 SA83 SB83 SC83 SA84 SB84 SC84 SA85 SB85 SC85 SA86 SB86 SC86 SA87 SB87 SC87 SA88 SB88 SC88 SA89 SB89 SC89 SA90 SB90 SC90 SA91 SB91 SC91 SA92 SB92 SC92 SA93 SB93 SC93 SA94 SB94 SC94
X-Axis -247.2 -288.4 -329.6 -370.8 -412 -453.2 -494.4 -535.6 -576.8 -618 -659.2 -824 -865.2 -906.4 -947.6 -988.8 -1030 -1071.2 -1112.4 -1153.6 -1194.8 -1236 -1277.2 -1318.4 -1359.6 -1400.8 -1442 -1483.2 -1524.4 -1565.6 -1606.8 -1648 -1689.2 -1730.4 -1771.6 -1812.8 -1854 -1895.2 -1936.4 -1977.6 -2018.8 -2060 -2101.2 -2142.4 -2183.6 -2224.8 -2266 -2307.2 -2348.4 -2389.6 -2430.8 -2472 -2513.2 -2554.4 -2595.6 -2636.8 -2678 -2719.2 -2760.4 -2801.6 -2842.8 -2884 -2925.2 -2966.4 -3007.6 -3048.8 -3090 -3131.2 -3172.4 -3213.6 -3254.8 -3296 -3337.2 -3378.4 -3419.6 -3460.8 -3502 -3543.2 -3584.4 -3625.6
Y-Axis 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030
Pad # 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720
Pad Name SA95 SB95 SC95 SA96 SB96 SC96 SA97 SB97 SC97 SA98 SB98 SC98 SA99 SB99 SC99 SA100 SB100 SC100 SA101 SB101 SC101 SA102 SB102 SC102 SA103 SB103 SC103 SA104 SB104 SC104 SA105 SB105 SC105 SA106 SB106 SC106 SA107 SB107 SC107 SA108 SB108 SC108 SA109 SB109 SC109 SA110 SB110 SC110 SA111 SB111 SC111 SA112 SB112 SC112 SA113 SB113 SC113 SA114 SB114 SC114 SA115 SB115 SC115 SA116 SB116 SC116 SA117 SB117 SC117 SA118 SB118 SC118 SA119 SB119 SC119 SA120 SB120 SC120 SA121 SB121
X-Axis -3666.8 -3708 -3749.2 -3790.4 -3831.6 -3872.8 -3914 -3955.2 -3996.4 -4037.6 -4078.8 -4120 -4161.2 -4202.4 -4243.6 -4284.8 -4326 -4367.2 -4408.4 -4449.6 -4490.8 -4532 -4573.2 -4614.4 -4655.6 -4696.8 -4738 -4779.2 -4820.4 -4861.6 -4902.8 -4944 -4985.2 -5026.4 -5067.6 -5108.8 -5150 -5191.2 -5232.4 -5273.6 -5314.8 -5356 -5397.2 -5438.4 -5479.6 -5520.8 -5562 -5603.2 -5644.4 -5685.6 -5726.8 -5768 -5809.2 -5850.4 -5891.6 -5932.8 -5974 -6015.2 -6056.4 -6097.6 -6138.8 -6180 -6221.2 -6262.4 -6303.6 -6344.8 -6386 -6427.2 -6468.4 -6509.6 -6550.8 -6592 -6633.2 -6674.4 -6715.6 -6756.8 -6798 -6839.2 -6880.4 -6921.6
Y-Axis 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030
SSD1339
Rev 1.1
P 11/59
Jul 2005
Solomon Systech
Pad # 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800
Pad Name SC121 SA122 SB122 SC122 SA123 SB123 SC123 SA124 SB124 SC124 SA125 SB125 SC125 SA126 SB126 SC126 SA127 SB127 SC127 SA128 SB128 SC128 SA129 SB129 SC129 SA130 SB130 SC130 SA131 SB131 SC131 NC NC NC COM66 COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COM80 COM81 COM82 COM83 COM84 COM85 COM86 COM87 COM88 COM89 COM90 COM91 COM92 COM93 COM94 COM95 COM96 COM97 COM98 COM99 COM100 COM101 COM102 COM103 COM104 COM105 COM106 COM107 COM108 COM109 COM110 NC
X-Axis -6962.8 -7004 -7045.2 -7086.4 -7127.6 -7168.8 -7210 -7251.2 -7292.4 -7333.6 -7374.8 -7416 -7457.2 -7498.4 -7539.6 -7580.8 -7622 -7663.2 -7704.4 -7745.6 -7786.8 -7828 -7869.2 -7910.4 -7951.6 -7992.8 -8034 -8075.2 -8116.4 -8157.6 -8198.8 -8240 -8363.6 -8404.8 -8446 -8487.2 -8528.4 -8569.6 -8610.8 -8652 -8693.2 -8734.4 -8775.6 -8816.8 -8858 -8899.2 -8940.4 -8981.6 -9022.8 -9064 -9105.2 -9146.4 -9187.6 -9228.8 -9270 -9311.2 -9352.4 -9393.6 -9434.8 -9476 -9517.2 -9558.4 -9599.6 -9640.8 -9682 -9723.2 -9764.4 -9805.6 -9846.8 -9888 -9929.2 -9970.4 -10011.6 -10052.8 -10094 -10135.2 -10176.4 -10217.6 -10258.8 -10318.5
Y-Axis 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030 1030
Pad # 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843
Pad Name NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC COM111 COM112 COM113 COM114 COM115 COM116 COM117 COM118 COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127 COM128 COM129 COM130 COM131 COMX NC
X-Axis -10389.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7 -10359.7
Y-Axis 1030 833.15 780.45 739.25 698.05 656.85 615.65 562.95 404.1 351.4 310.2 269 227.8 186.6 145.4 104.2 63 21.8 -19.4 -60.6 -101.8 -143 -184.2 -225.4 -266.6 -307.8 -349 -390.2 -431.4 -472.6 -513.8 -555 -596.2 -637.4 -678.6 -719.8 -761 -802.2 -843.4 -884.6 -925.8 -967 -1060
Die Size:
20989um x 2250um
Gold Bump Face Up Pad 1, 2 ,3, ... -->
Pad # 1 - 263 264, 298-299, 305, 802, 808-809, 843 265-297, 300-304, 803-807, 810-842 306-307, 800-801 308-799
X-Dimension 54um 110um 110um 50um 27um
Y-Dimension 84um 50um 27um 110um 110um
Marks
X-Axis
Y-Axis
KEY_O 9140.000 KEY_O -9140.000 KEY_T -8176.000 KEY_X 8176.000
-941.000 -941.000 307.000 307.000
Solomon Systech
Jul 2005
P 12/59
Rev 1.1
SSD1339
T shape
+ shape
Circle
*All units are in um
Figure 3 - SSD1339Z alignment mark dimensions
SSD1339
Rev 1.1
P 13/59
Jul 2005
Solomon Systech
W1 W2 W3 X1 Y1 Px Py X Y Z N
Spec mm 76.00 +/-0.1 68.00 +/-0.1 68.30 +/-0.1 4.00 +/-0.1 1.55 +/-0.1 22.30 +/-0.05 4.20 +/-0.1 21.14 +/-0.05 2.40 +/-0.05 0.61 +/-0.05 45
(mil) (2992) (2677) (2689) (157) (61) (878) (165) (832) (94) (24)
Remark 1. Depth of text is 0.1mm 2. Tray material: ABS 3. Tray color code: Black 9 11 4. Surface resistance 10 ~ 10 - cm 5. Tray warpage: Max 0.15mm 6. Unspecifier dim's tolerance: +/- 0.15mm 7. Pocket size: 21.14 x 2.40 x 0.61mm
Figure 4 - Die tray information
Solomon Systech
Jul 2005
P 14/59
Rev 1.1
SSD1339
6. PIN DESCRIPTION
RES# This pin is reset signal input. When the pin is low, initialization of the chip is executed.
CS# This pin is the chip select input. The chip is enabled for MCU communication only when CS# is pulled low. D/C# This pin is Data/Command control pin. When the pin is pulled high, the data at D7-D0 is treated as display data. When the pin is pulled low, the data at D7-D0 will be transferred to the command register. For detail relationship to MCU interface signals, please refer to the Timing Characteristics Diagrams.
E (RD#) This pin is MCU interface input. When interfacing to a 6800-series microprocessor, this pin will be used as the Enable (E) signal. Read/write operation is initiated when this pin is pulled high and the chip is selected. When connecting to an 8080-microprocessor, this pin receives the Read (RD#) signal. Data read operation is initiated when this pin is pulled low and the chip is selected.
R/W# (WR#) This pin is MCU interface input. When interfacing to a 6800-series microprocessor, this pin will be used as Read/Write (R/W#) selection input. Read mode will be carried out when this pin is pulled high and write mode will be carried out when this pin is pulled low. When 8080 interface mode is selected, this pin will be the Write (WR#) input. Data write operation is initiated when this pin is pulled low and the chip is selected.
BS0, BS1, BS2 These pins are MCU interface selection input. See the following table:
6800-parallel interface (8 bit) 0 0 1 0 6800-parallel interface (9 bit) 0 0 1 1 8080-parallel interface (8 bit) 0 1 1 0 8080-parallel interface (9 bit) 0 1 1 1 6800-parallel interface (16 bit) 1 0 1 0 6800-parallel interface (18 bit) 1 0 1 1 8080-parallel interface (16 bit) 1 1 1 0 8080-parallel interface (18 bit) 1 1 1 1 Serial interface 0 0 0 0
BS0 BS1 BS2 BS3
BS0 BS1 BS2 BS3
Note: Unlike BS0, BS1 and BS2 are controlled by hardware connection, BS3 is controlled by software command, A0.
SSD1339
Rev 1.1
P 15/59
Jul 2005
Solomon Systech
D17-D0 These pins are 18-bit bi-directional data bus to be connected to the microprocessor's data bus.
VDDIO This pin is a power supply pin of I/O buffer. It should be connected to VDD or external source. All I/O signal should have VIH reference to VDDIO. When I/O signal pins (BS012, M/S, CLS, D0-D17, control signals...) pull high, they should be connected to VDDIO.
VDD Power Supply pin. It must be connected to external source.
VSS Ground. It also acts as a reference for the logic pins. It must be connected to external ground.
CL This pin is the system clock input. When internal clock is enabled, this pin should be left open. Nothing should be connected to this pin. When internal oscillator is disabled, this pin receives display clock signal from external clock source. MS This pin must be connected to VDD to enable the chip. CLS This pin is internal clock enable. When this pin is pulled high, internal oscillator is selected. The internal clock will be disabled when it is pulled low, an external clock source must be connected to CL pin for normal operation.
VDDB This is the power supply pin for the internal buffer of the DC-DC voltage converter. It must be connected to VDD when the converter is used. It is also recommended to connect this pin to VDD when the converter is not used to avoid floating node.
VSSB This is the GND pin for the internal buffer of the DC-DC voltage converter. It must be connected to VSS when the converter is used. It is also recommended to connect this pin to VSS when the converter is not used to avoid floating node.
GDR This output pin drives the gate of the external NMOS of the booster circuit. This pin can be left open when the converter is not used.
RESE This pin connects to the source current pin of the external NMOS of the booster circuit. This pin can be left open when the converter is not used.
Solomon Systech
Jul 2005
P 16/59
Rev 1.1
SSD1339
FB This pin is the feedback resistor input of the booster circuit. It is used to adjust the booster output voltage level (Vcc). This pin can be left open when the converter is not used. BGGND This is a ground pin for analog circuits. It must be connected to external ground.
VBREF This pin is the internal voltage reference of booster circuit. A stabilization capacitor, typ. 1uF, should be connected to Vss. This pin can be left open when the converter is not used.
VCC This is the most positive voltage supply pin of the chip. It is supplied either by external high voltage source or internal booster
VCOMH This pin is the input pin for the voltage output high level for COM signals. It can be supplied externally or internally. When VCOMH is generated internally, a capacitor should be connected between this pin and VSS. VREF This pin is the reference for OLED driving voltages like VPA, VPB, VPC and VCOMH. It can be either supplied externally or connected to VCC (VREF VCC). VPA, VPB, VPC These pins are the driving voltages for OLED driving segment pins SA0-SA131, SB0-SB131 and SC0SC131 respectively. They can be supplied externally or internally generated by VP circuit. When internal VP is used, VPA, VPB, VPC pins should be left open. IREF This pin is the segment output current reference pin. ISEG of each color is derived from IREF ISEG = (Contrast / 256) * IREF * scale factor Contrast is set by command C1h Scale factor = master current control register setting (C7h) + 1, i.e., with value from 1~16. A resistor should be connected between this pin and VSS to maintain the current around 10uA. VSL This is segment voltage reference pin. This pin should be left open.
VCL This is common voltage reference pin. This pin should be connected to VSS externally. COM0-COM131 These pins provide the Common switch signals to the OLED panel. These pins are in high impedance state when display is off.
SSD1339
Rev 1.1
P 17/59
Jul 2005
Solomon Systech
SA0-SA131, SB0-SB131, SC0-SC131 These pins provide the OLED segment driving signals. These pins are in high impedance state when display is off. The 396 segment pins are divided into 3 groups, SA, SB and SC. Each group can have different color settings for color A, B and C.
COMX These two pins provide the Common switch signals for soft icon line to the OLED panel. These pins are in high impedance state when display is off.
TR0 - TR8, VMONA, ICASA, ICASB, ICASC, GPIO0, GPIO1, M, DOF# These are reserved pins. No connection is necessary and should be left open individually.
NC No connection pins. They should be left open individually.
Solomon Systech
Jul 2005
P 18/59
Rev 1.1
SSD1339
7. FUNCTIONAL BLOCK DISCRIPTIONS
Oscillator Circuit and Display Time Generator
Internal Oscillator Fosc CL
M U X CLK Divider DCLK Display Clock
CLS
Figure 5 - Oscillator Circuit This module is an On-Chip low power RC oscillator circuitry. The operation clock (CLK) can be generated either from internal oscillator or external source CL pin. This selection is done by CLS pin. If CLS pin is pulled high, internal oscillator is chosen. Pulling CLS pin low disables internal oscillator and external clock must be connected to CL pins for proper operation. When the internal oscillator is selected, its output frequency Fosc can be changed by command B3h. In some COF packages of SSD1339, CLS pin is tied to high internally and the internal oscillator is selected in these packages. The display clock (DCLK) for the Display Timing Generator is derived from CLK. The division factor can be programmed from 1 to 16 by command B3h.
Reset Circuit
When RES# input is low, the chip is initialized with the following status: 1. Display is OFF 2. 132x132 Display Mode 3. Normal segment and display data column address and row address mapping (SEG0 mapped to address 00H and COM0 mapped to address 00H) 4. Shift register data clear in serial interface 5. Display start line is set at display RAM address 0 6. Column address counter is set at 0 7. Normal scan direction of the COM outputs 8. Contrast control register is set at 80H
SSD1339
Rev 1.1
P 19/59
Jul 2005
Solomon Systech
Command Decoder and Command Interface
This module determines whether the input data is interpreted as data or command. Data is interpreted based upon the input of the D/C# pin. If D/C# pin is high, data is written to Graphic Display Data RAM (GDDRAM). If it is low, the input at D7-D0 is interpreted as a Command and it will be decoded and be written to the corresponding command register.
MPU Parallel 6800-series Interface
The parallel interface consists of 18 bi-directional data pins (D17-D0) or 8 bi-directional data pins (D7-D0), R/W#(WR#), D/C#, E (RD#) and CS#. R/W#(WR#) input High indicates a read operation from the Graphic Display Data RAM (GDDRAM) or the status register. RW#/(WR#) input Low indicates a write operation to Display Data RAM or Internal Command Registers depending on the status of D/C# input. The E(RD#) input serves as data latch signal (clock) when high provided that CS# is low and high respectively. Refer to . Figure 32 of parallel timing characteristics for Parallel Interface Timing Diagram of 6800-series microprocessors. In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 6 below.
R/ W#(WR#)
E(RD#)
Data bus N Write column address Dummy read n Data read1
n+1 Data read2
n+2 Data read3
Figure 6 - Display data read back procedure - insertion of dummy read
MPU Parallel 8080-series Interface
The parallel interface consists of 18 bi-directional data pins (D17-D0) or 8 bi-directional data pins (D7-D0), E (RD#), R/W#(WR#), D/C# and CS#. The E(RD#) input serves as data read latch signal (clock) when low, provided that CS# is low and high respectively. Display data or status register read is controlled by D/C#. R/W#(WR#) input serves as data write latch signal (clock) when high provided that CS# is low and high respectively. Display data or command register write is controlled by D/C#. Refer to * when 8 bit used: D0 ~ D7 instead; when 9 bit used: D0 ~ D8 instead; when 16 bit used: D0 ~ D15 instead; when 18 bit used: D0 ~ D17 instead. Figure 33 of parallel timing characteristics for Parallel Interface Timing Diagram of 8080-series microprocessor. Similar to 6800-series interface, a dummy read is also required before the first actual display data read.
Solomon Systech
Jul 2005
P 20/59
Rev 1.1
SSD1339
MPU Serial Interface
The serial interface consists of serial clock SCLK, serial data SDIN, D/C#, CS#. In this mode, D0 acts as SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open. D3 to D7, E and R/W pins can be connected to external ground. SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6, ... D0. D/C is sampled on every eighth clock and the data byte in the shift register is written to the Display Data RAM or command register in the same clock. During data writing, an additional NOP command should be inserted before the CS# goes high (Refer to Figure 7. Figure 7 - Display data write procedure in SPI mode
CS#
D/C
SDIN/ SCLK
DB1
DB2
DBn
NOP COMMAND
SCLK(D0)
SDIN(D1)
D7
D6
D5
D4
D3
D2
D1
D0
SSD1339
Rev 1.1
P 21/59
Jul 2005
Solomon Systech
Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 132 x 133 x 18bits. For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by software. For vertical scrolling of the display, an internal register storing display start line can be set to control the portion of the RAM data to be mapped to the display. Each pixel has 18-bit data. Each sub-pixels for color A, B and C have 6 bits. The arrangement of data pixel in graphic display data RAM is shown below.
Column Address Normal Remap A5 A4 A3 A2 A1 A0 6 0 131 B5 B4 B3 B2 B1 B0 6 C5 C4 C3 C2 C1 C0 6 A5 A4 A3 A2 A1 A0 6 1 130 B5 B4 B3 B2 B1 B0 6 C5 C4 C3 C2 C1 C0 6 2 129 A5 B5 A4 B4 A3 B3 A2 B2 A1 B1 B0 A0 6 6 C5 C4 C3 C2 C1 C0 6 : : : A5 A4 A3 A2 A1 A0 6 129 2 B5 B4 B3 B2 B1 B0 6 C5 C4 C3 C2 C1 C0 6 A5 A4 A3 A2 A1 A0 6 130 1 B5 B4 B3 B2 B1 B0 6 C5 C4 C3 C2 C1 C0 6 A5 A4 A3 A2 A1 A0 6 131 0 B5 B4 B3 B2 B1 B0 6 C5 C4 C3 C2 C1 C0 6
Data Format
:
Row Address Normal 0 1 2 : 130 131 132 Remap 132 131 130 : 2 1 0
COM OUTPUT COM0 COM1 COM2 : COM130 COM131 COM132
no. of bits of data in this cell
:
SEG OUTPUT
SA0 SB0 SC0 SA1 SB1 SC1 SA2 SB2 SC2
:
SA129 SB129 SC129 SA130 SB130 SC130 SA131 SB131 SC131
Figure 8 - Graphic Display Data RAM Structure
Data access in 262k colors mode In 262k colors depth mode, there are different MCU interface communication modes to access graphic display data RAM in OLED driver. For 18 bits mode, the communication is made up of one session of 18 data bits. MCU transmits all bits to write one 18-bit pixel data into OLED driver. This 18-bit mode can be selected by setting the A[3] bit in command A0 to 1. Bit Data bits 17 C5 16 C4 15 C3 14 C2 13 C1 12 C0 11 B5 10 B4 9 B3 8 B2 7 B1 6 B0 5 A5 4 A4 3 A3 2 A2 1 A1 0 A0
Figure 9 - 262k color depth data writing sequence in 18-bit MCU interface
For the 1 option of the two 16-bit modes, the communication is divided into two sessions of 16 data bits. MCU transmits two 16-bit words to write one 18-bit pixel data into OLED driver. Mode 1 is selected by setting A0h register A[7:6] bits to 10b. In below, A1, B1, C1 are pixel bits for color A, B and C, and "X" stands for don't care value.
st
Solomon Systech
Jul 2005
P 22/59
Rev 1.1
SSD1339
Bit st 1 word nd 2 word
15 X X
14 X X
13 X B15
12 X B14
11 X B13
10 X B12
9 X B11
8 X B10
7 X X
6 X X
5 C15 A15
4 C14 A14
3 C13 A13
2 C12 A12
1 C11 A11
0 C10 A10
Figure 10 - 262k color depth data writing sequence in 16-bit MCU interface in Option 1
For the 2 option of the 16-bit modes, the communication is divided into three sessions of 16 data bits. MCU transmits three 16-bit words to write two 18-bit pixels data into OLED driver. Option 2 is selected by setting A0h register A[7:6] bits to 11b. In below, A1, B1, C1 are first data pixel bits, and A2, B2, C2 are second data pixel bits. Bit st 1 word nd 2 word th 3 word 15 X X X 14 X X X 13 C15 A15 B25 12 C14 A14 B24 11 C13 A13 B23 10 C12 A12 B22 9 C11 A11 B21 8 C10 A10 B20 7 X X X 6 X X X 5 B15 C25 A25 4 B14 C24 A24 3 B13 C23 A23 2 B12 C22 A22 1 B11 C21 A21 0 B10 C20 A20
nd
Figure 11 - 262k color depth data writing sequence in 16-bit MCU interface in Option 2
For 9-bit modes, the communication is divided into two sessions of 9 data bits. MCU transmits two 9 data bits to write one 18-bit pixel data into OLED driver. This 9-bit mode can be selected by setting the A[3] bit in command A0 to 1. Bit st 1 9 Data bits nd 2 9 Data bits 8 C5 B2 7 C4 B1 6 C3 B0 5 C2 A5 4 C1 A4 3 C0 A3 2 B5 A2 1 B4 A1 0 B3 A0
Figure 12 - 262k color depth graphic display data writing sequence in 9-bit MCU interface
In 8-bit MCU interface, the communication session is divided into three times. MCU transmit three 8-bit bytes to write one 18-bit pixel data into OLED driver. Bit st 1 byte nd 2 byte rd 3 byte 7 X X X 6 X X X 5 C15 B15 A15 4 C14 B14 A14 3 C13 B13 A13 2 C12 B12 A12 1 C11 B11 A11 0 C10 B10 A10
Figure 13 - 262k color depth graphic display data writing sequence in 8-bit MCU interface
Data access in 65k colors mode Writing a 65K pixel in 16-bit MCU interface involves one session as follows. Bit st 1 word 15 C14 14 C13 13 C12 12 C11 11 C10 10 B15 9 B14 8 B13 7 B12 6 B11 5 B10 4 A14 3 A13 2 A12 1 A11 0 A10
Figure 14 - 65k color depth graphic display data writing sequence in 16-bit MCU interface
SSD1339
Rev 1.1
P 23/59
Jul 2005
Solomon Systech
The sequence of sending 65K color depth pixel in 8-bit MCU interface is divided into two 8-bit sessions as shown below. Bit st 1 byte nd 2 byte 7 C14 B12 6 C13 B11 5 C12 B10 4 C11 A14 3 C10 A13 2 B15 A12 1 B14 A11 0 B13 A10
Figure 15 - 65k color depth graphic display data writing sequence in 8-bit MCU interface
With reference to Figure 8 conventions, in writing the data into graphic display data RAM, the bit positions filled by the input data for each color is shown below. Color A Bit Position Input Data Color B Bit Position Input Data Color C Bit Position Input Data A5 A14 B5 B15 A4 A13 B4 B14 A3 A12 B3 B13 A2 A11 B2 B12 A1 A10 B1 B11 A0 A14 B0 B10
C5 C14
C4 C13
C3 C12
C2 C11
C1 C10
C0 C14
Figure 16 - Display data RAM writing position for color A, B and C data input in 65k color mode
In data RAM, each data occupies 6-bit. However, color A and C have 5-bit length only in 65k color mode. Therefore, RAM positions A0 and C0 are empty originally. These emptied positions are filled as shown above to increase color A and C to 6-bit length in display data RAM.
Data access in 256 colors mode In 256-color mode, each pixel is composed of 8-bit. Only 8-bit MCU interface is available to access display data RAM. The communication session is done in 1 time by writing 8-bit data into RAM. Bit st 1 byte 7 C12 6 C11 5 C10 4 B12 3 B11 2 B10 1 A11 0 A10
Figure 11 - 256 Color Depth Graphic Display Data Writing Sequence in 8-bit MCU Interface
With reference to Figure 8 conventions, in writing the data into graphic display data RAM, the bit positions filled by the input data for each color is shown below. Color A Bit Position Input Data A5 A11 A4 A10 A3 A11 A2 A11 A1 A11 A0 A11
Solomon Systech
Jul 2005
P 24/59
Rev 1.1
SSD1339
Color B Bit Position Input Data Color C Bit Position Input Data
B5 B12 C5 C12
B4 B11 C4 C11
B3 B10 C3 C10
B2 B12 C2 C12
B1 B12 C1 C12
B0 B12 C0 C12
Figure 17 - Display data RAM writing position for color A, B and C data input in 256 color mode
In data RAM, each data occupies 6-bit. However, color B and C have 3-bit length and color A has 2-bit only in 256 color mode. Therefore, RAM positions B2~B0, C2~C0 and A3~A0 are empty originally. These emptied positions are filled as shown above to increase color A, B and C to 6-bit length in display data RAM.
SSD1339
Rev 1.1
P 25/59
Jul 2005
Solomon Systech
Gray Scale and Gray Scale Table
Controlling the current pulse widths from the segment driver in the current drive phase produces the gray scale display. The gray scale table stores the corresponding pulse widths (PW0 ~ PW63) of the 64 gray scale levels (GS0~GS63). The wider the pulse width, the brighter the pixel will be. Therefore, the brightness of each pixel is defined in the graphic display data RAM in term of pulse width in gray scale table. This single gray scale table supports all the three colors A, B and C. The pulse widths are entered by software commands. In graphic display data RAM, each color occupies 6-bit length. So color A, B and C each has 64 gray scale levels. Color A, B, C RAM data (6 bits) 0 1 2 3 4 : : : 60 61 62 63 Gray Scale GS 0 GS 1 GS 2 GS 3 GS 4 : : : GS 60 GS 61 GS 62 GS 63
Figure 18 - Relation between graphic data RAM value and gray scale table entry for three colors In 65k and 256 color modes, the length color data are less than 6 bits. They are expanded to 6-bit length as shown in Figure 16 and Figure 17 respectively.
Solomon Systech
Jul 2005
P 26/59
Rev 1.1
SSD1339
The meaning of values inside data RAM with respect to the gray scale level is best to be illustrated in an example below. Gray Scale (Pulse Width) PW0 PW1 PW2 : PW62 PW63 Value/DCLKs 0 2 5 : 120 125
Gray Scale Table
Segment Voltage
Color B RAM data = 000001b PW1 pulse width = 2 DCLKs
Color B RAM data = 111110b PW62 pulse width = 120 DCLKs
VSS
Time
Figure 19 - Illustration of relation between graphic display RAM value and gray scale control
Current Control and Voltage Control
This block is used to derive the incoming power sources into the different levels of internal use voltage and current. VCC and VDD are external power supplies. VREF is reference voltage, which is used to derive driving voltage for segments and commons. IREF is a reference current source for segment current drivers.
Segment Drivers/Common Drivers
Segment drivers deliver 396 current sources to drive OLED panel. The driving current can be adjusted from 0 to 200uA with 256 steps. Common drivers generate voltage scanning pulse.
SSD1339
Rev 1.1
P 27/59
Jul 2005
Solomon Systech
DC-DC Voltage Converter
It is a switching voltage generator circuit, designed for handheld applications. In SSD1339, internal DCDC voltage converter accompanying with an external application circuit (shown in below figure) can generate a high voltage supply VCC from a low voltage supply input VDD. VCC is the voltage supply to the OLED driver block. Below application circuit is an example for the input voltage of 3V VDD to generate VCC of 12V @20mA ~ 30mA application.
L1 VDD
+
D1
VCC
C5
AGND
Q1
VDDB GDR
+
R1
+
+
+
C6
+
VBREF
RESE
C7 R3
C2
C3
C1
AGND
VSSB
FB
+
AGND
C4
R2
DGND
*ALL PATHS TO AGND SHOULD BE CONNECTED AS SHORT AS POSSIBLE
Passive components selection: Components Typical Value L1 Inductor, 22H D1 Schottky diode Q1 MOSFET R1, R2 R3 C1 C2 C3 C4 C5 C6 C7 Resistor Resistor, 1.5 Capacitor, 1F Capacitor, 22F Capacitor, 1F Capacitor, 10nF Capacitor, 1 ~ 10 F Capacitor, 0.1 ~ 1F Capacitor, 15nF
Remark 2A 2A, 25V e.g. 1N5822 N-FET with low RDS(on) and low Vth voltage. e.g. MGSF1N02LT1 [ON SEMICONDUCTOR] 1%,1/10W 1%, 1/2W 16V Low ESR, 25V 16V 16V 16V 16V 16V
The VCC output voltage level can be adjusted by changing the R1 and R2 resistor values, the reference formula is: VCC = 1.2 x (R1+R2) / R2
Solomon Systech
Jul 2005
P 28/59
Rev 1.1
SSD1339
8. COMMAND TABLE
Table 3 - Command table ( D/C = 0, R/ W ( WR ) = 0, E( RD ) = 1) unless specific setting is stated Single byte command ( D/C = 0), Multiple byte command ( D/C = 0 for first byte, D/C = 1 for other bytes)
D/C
0 1 1 0 1 1 0
Hex
15 A[7:0] B[7:0] 75 A[7:0] B[7:0] 5C
D7 D6 D5 D4 D3 D2 D2 D0
0 A7 B7 0 A7 B7 0 0 A6 B6 1 A6 B6 1 0 A5 B5 1 A5 B5 0 1 A4 B4 1 A4 B4 1 0 A3 B3 0 A3 B3 1 1 A2 B2 1 A2 B2 1 0 A1 B1 0 A1 B1 0 1 A0 B0 1 A0 B0 0
Command
Set Column Address
Description
A[7:0]: Start Address, reset=0d B[7:0]: End Address, reset=131d Range from 0d to 131d A[7:0]: Start Address, reset=0d
Set Row Address B[7:0]: End Address, reset=131d Range from 0d to 131d Write RAM Command Read RAM Command Enable MCU to write Data into RAM Enable MCU to read Data from RAM
0
5D
0
1
0
1
1
1
0
1
0 1
A0 A[7:0]
1 A7
0 A6
1 A5
0 A4
0 A3
0 A2
0 A1
0 A0
A[0]=0, Horizontal address increment (POR) A[0]=1, Vertical address increment
A[1]=0, Column address 0 is mapped to SEG0 (POR) A[1]=1, Column address 131 is mapped to SEG0
A[2]=0, Color sequence: A # B # C (POR) A[2]=1, Color sequence is swapped: C # B # A
A[3]=0, Disable 9/18-bit bus interface (POR) Set Re-map / Color Depth(Display RAM to Panel) A[3]=1, Enable 9/18-bit bus interface
A[4]=0, Scan from COM 0 to COM [N -1] (POR) A[4]=1, Scan from COM [N-1] to COM0. Where N is the Multiplex ratio.
A[5]=0, Disable COM Split Odd Even (POR) A[5]=1, Enable COM Split Odd Even A[7:6] Set Color Depth, 00 256 color 01 65K color, (POR) 10 262k color, 8/9/18-bit,16 bit (1st option) MCU interface 11 262k color, 16 - bit MCU interface (2nd option) 0 1 A1 A[7:0] 1 A7 0 A6 1 A5 0 A4 0 A3 0 A2 0 A1 1 A0 Set Display Start Set vertical scroll by RAM from 0~131 Line [reset=00d]
SSD1339
Rev 1.1
P 29/59
Jul 2005
Solomon Systech
D/C
0 1
Hex
A2 A[7:0]
D7 D6 D5 D4 D3 D2 D2 D0
1 A7 0 A6 1 A5 0 A4 0 A3 0 A2 1 A1 0 A0
Command
Set Display Offset
Description
Set vertical scroll by Row from 0-131. [reset=00b]
0
A4~A7
1
0
1
0
0
1
X1
X0
A4: All Off A5: All On (All pixels have GS15) Set Display Mode A6 : Reset to normal display (POR) A7: Inverse Display (GS0 -> GS63, GS1 -> GS62, ....)
0 1
AD A[7:0]
1 1
0 0
1 0
0 0
1 1
1 A2
0 A1
1 A0
A[7:0] should be set as 100011A[1]A[0]b A[0]= 0 Select external VCC supply at master ON A[0] = 1 Select internal booster at master ON [reset] Master Configuration A[1]= 0 Select external VCOMH voltage supply at master ON A[1] = 1 Select internal VCOMH regulator at master ON [reset] A[2] = 0 Select external pre-charge voltage source A[2] = 1 Select internal pre-charge voltage source [reset]
0
AE~AF
1
0
1
0
1
1
1
X0
Set Sleep mode AE = Sleep mode On (Display off) On/Off AF = Sleep mode Off (Display on) A[4:0]: Power Saving Mode 00000b = Normal 10010b = Power Saving 00101b = Reserved
0
B0
1 0
0 0
1 0
1 A4
0 A3
0 A2
0 A1
0 A0
0 1
B1 A[7:0]
1 A7
0 A6
1 A5
1 A4
0 A3
0 A2
0 A1
1 A0
Set Reset (Phase A[3:0] Phase 1 period of 1~16 dclk clocks [reset=4h] 1) /Pre-charge A[7:4] Phase 2 period of 1~16 dclk clocks [reset=7h] (Phase 2) period A[3:0] [reset=0], divide by DIVSET+1 (i.e. 1 to 16) Front Clock Divider A[7:4] Osc frequency, frequency increase as level (DivSet)/ Oscillator increase [reset=1001b] Frequency The next 32 bytes of command set the current drive pulse width of gray scale level GS1, GS3, GS5 ...GS63 as below in unit of DCLK. Look Up Table for A[7:0] : PW1, POR =1 DCLK Gray Scale Pulse B[7:0] : PW3, POR = 5 DCLK width C[7:0] : PW5, POR = 9 DCLK . . AE[7:0] : PW61, POR = 121 DCLK AF[7:0] : PW63, POR = 123 DCLK where PW1 must > 0 PW3 must > PW1+1
0 1
B3 A[7:0]
1 A7
0 A6
1 A5
1 A4
0 A3
0 A2
1 A1
1 A0
0 1 1 1 1 1 1 1
B8 A[7:0] B[7:0] . . .
1 A7 B7 . . .
0 A6 B6 . . .
1 A5 B5 . . .
1 A4 B4 . . .
1 A3 B3 . . .
0 A2 B2 . . .
0 A1 B1 . . .
0 A0 B0 . . .
.AE[7:0] AE7 AE6 AE5 AE4 AE3 AE2 AE1 AE0 AF[7:0] AF7 AF6 AF5 AF4 AF3 AF2 AF1 AF0
Solomon Systech
Jul 2005
P 30/59
Rev 1.1
SSD1339
D/C
Hex
D7 D6 D5 D4 D3 D2 D2 D0
Command
Description
PW5 must > PW3+1 Note: GS0 has no pre-charge and current drive stages. For GS2 GS4...GS62, they are derived by driver itself with: PWn = (PWn-1+PWn+1)/2 Max pulse width is 125
0
B9
1
0
1
1
1
0
0
1
Reset to default Look Up Table: PW1 = 1 PW2 = 3 Use Built-in Linear LUT (reset= linear) PW3 = 5 PW4 = 7 ... PW62 = 123 PW63 = 125
0 1 1 1
BB A[7:0] B[7:0] C[7:0]
1 A7
0 A6
1 A5
1 A4
1 A3
0 A2
1 A1
1 A0
A[7:0] Pre-charge Color A [reset = 00011100] B[7:0] Pre-charge Color B [reset = 00011100] C[7:0] Pre-charge Color C [reset = 00011100] Set Pre-charge voltage of Color A BC 00000000 0.51*Vref ..... 00011111 0.84*Vref 1xxxxxxx connects to VCOMH
0 1
BE A[6:0]
1 *
0 A6
1 A5
1 A4
1 A3
1 A2
1 A1
0 A0 Set VCOMH
A[6:0] 0000000 0.51*Vref ..... 0011111 0.84*Vref [VCOMHSET, reset]
0 1 1 1
C1 A[7:0] B[7:0] C[7:0]
1 A7 B7 C7
1 A6 B6 C6
0 A5 B5 C5
0 A4 B4 C4
0 A3 B3 C3
0 A2 B2 C2
0 A1 B1 C1
1 A0 B0 C0
A[7:0] Contrast Value Color A Contrast Current B[7:0] Contrast Value Color B for Color A,B,C C[7:0] Contrast Value Color C
[reset=1000000b] [reset=1000000b] [reset=1000000b]
0 1
C7 A[3:0]
1 *
1 *
0 *
0 *
0 A3
1 A2
1 A1
1 A0
A[3:0] : 0000 reduce output currents for all colors to 1/16 0001 reduce output currents for all colors to 2/16 Master Contrast Current Control .... 1110 reduce output currents for all colors to 15/16 1111 no change [reset = 1111b]
SSD1339
Rev 1.1
P 31/59
Jul 2005
Solomon Systech
D/C
0 1 0
Hex
CA A[7:0] E3
D7 D6 D5 D4 D3 D2 D2 D0
1 A7 1 1 A6 1 0 A5 1 0 A4 0 1 A3 0 0 A2 0 1 A1 1 0 A0 1
Command
Set Mux Ratio NOP
Description
A[7:0] mux ratio 16MUX ~ 132MUX, [reset=131d], (Range from 15d to 131d) Command for No Operation
Table 4 - Graphic acceleration command Set (GAC) ( D/C = 0, R/ W ( WR ) = 0, E( RD ) = 1) unless specific setting is stated Single byte command ( D/C = 0), Multiple byte command ( D/C = 0 for first byte, D/C = 1 for other bytes)
D/C
0 1 1 1 1 1 1
Hex
83 A[7:0] B[7:0] C[7:0] D[7:0] E[7:0] F[7:0]
D7 D6 D5 D4 D3 D2 D2 D0
1 A7 B7 C7 D7 E7 F7 0 A6 B6 C6 D6 E6 F6 0 A5 B5 C5 D5 E5 F5 0 A4 B4 C4 D4 E4 F4 0 A3 B3 C3 D3 E3 F3 0 A2 B2 C2 D2 E2 F2 1 A1 B1 C1 D1 E1 F1 1 A0 B0 C0 D0 E0 F0
Command
Description
A[7:0] : Column Address of Start B[7:0] : Row Address of Start C[7:0] : Column Address of End
Draw Line
D[7:0] : Row Address of End E[7:0] : Line Color - CCCCCBBB F[7:0] : Line Color - BBBAAAAA * A < C < 132 * B < D < 132
0 1 1 1 1 1 1 1 1
84 A[7:0] B[7:0] C[7:0] D[7:0] E[7:0] F[7:0] G[7:0] H[7:0]
1 A7 B7 C7 D7 E7 F7 G7 H7
0 A6 B6 C6 D6 E6 F6 G6 H6
0 A5 B5 C5 D5 E5 F5 G5 H5
0 A4 B4 C4 D4 E4 F4 G4 H4
0 A3 B3 C3 D3 E3 F3 G3 H3
1 A2 B2 C2 D2 E2 F2 G2 H2
0 A1 B1 C1 D1 E1 F1 G1 H1
0 A0 B0 C0 D0 E0 F0 G0 H0 Draw Rectangle
A[7:0] : Column Address of Start B[7:0] : Row Address of Start C[7:0] : Column Address of End D[7:0] : Row Address of End E[7:0] : Line Color - CCCCCBBB F[7:0] : Line Color - BBBAAAAA G[7:0] : Fill Color - CCCCCBBB H[7:0] : Fill Color - BBBAAAAA
* A < C < 132 * B < D < 132 0 1 1 1 1 1 1 1 0 1 1 1 1 86 A[7:0] B[7:0] C[7:0] D[7:0] E[7:0] F[7:0] G[7:0] 8A A[7:0] B[7:0] C[7:0] D[7:0] 1 A7 B7 C7 D7 E7 F7 G7 1 A7 B7 C7 D7 0 A6 B6 C6 D6 E6 F6 G6 0 A6 B6 C6 D6 0 A5 B5 C5 D5 E5 F5 G5 0 A5 B5 C5 D5 0 A4 B4 C4 D4 E4 F4 G4 0 A4 B4 C4 D4 0 A3 B3 C3 D3 E3 F3 G3 1 A3 B3 C3 D3 1 A2 B2 C2 D2 E2 F2 G2 0 A2 B2 C2 D2 1 A1 B1 C1 D1 E1 F1 G1 1 A1 B1 C1 D1 0 A0 B0 C0 D0 E0 F0 G0 0 A0 B0 C0 D0 Copy A[7:0] : Column Address of Start B[7:0] : Row Address of Start C[7:0] : Column Address of End D[7:0] : Row Address of End E[7:0] : Column Address of New Start Draw Circle A[7:0] : Column Address of Centre B[7:0] : Row Address of Centre C[7:0] : Radius D[7:0] : Line Color - CCCCCBBB E[7:0] : Line Color - BBBAAAAA F[7:0] : Fill Color - CCCCCBBB G[7:0] : Fill Color - BBBAAAAA
Solomon Systech
Jul 2005
P 32/59
Rev 1.1
SSD1339
D/C
1 1
Hex
E[7:0] F[7:0]
D7 D6 D5 D4 D3 D2 D2 D0
E7 F7 E6 F6 E5 F5 E4 F4 E3 F3 E2 F2 E1 F1 E0 F0
Command
* A < C < 132 * B < D < 132
Description
F[7:0] : Row Address of New Start
0 1 1 1 1
8C A[7:0] B[7:0] C[7:0] D[7:0]
1 A7 B7 C7 D7
0 A6 B6 C6 D6
0 A5 B5 C5 D5
0 A4 B4 C4 D4
1 A3 B3 C3 D3
1 A2 B2 C2 D2
0 A1 B1 C1 D1
0 A0 B0 C0 D0 Dim Window
A[7:0] : Column Address of Start B[7:0] : Row Address of Start C[7:0] : Column Address of End D[7:0] : Row Address of End * A < C < 132 * B < D < 132
0 1 1 1 1
8E A[7:0] B[7:0] C[7:0] D[7:0]
1 A7 B7 C7 D7
0 A6 B6 C6 D6
0 A5 B5 C5 D5
0 A4 B4 C4 D4
1 A3 B3 C3 D3
1 A2 B2 C2 D2
1 A1 B1 C1 D1
0 A0 B0 C0 D0 Clear Window
A[7:0] : Column Address of Start B[7:0] : Row Address of Start C[7:0] : Column Address of End D[7:0] : Row Address of End * A < C < 132 * B < D < 132
0 1
92 A[5:0]
1 *
0 *
0 A5
1 A4
0 A3
0 A2
1 A1
0 A0
A0 0 : Disable Fill for Draw Rectangle/Circle Command [reset] 1 : Enable Fill for Draw Rectangle/Circle Command Fill Enable / Disable A4 A5 copying 0 : Disable reverse copy, reset] 1 : Enable reverse during copying. 0 : Disable x-wrap, [reset] 1 : Enable wrap around in x-direction during A[7:0] : 1~124 horizontal offset in number of Column Invalid entry for value larger than 124 0 no horizontal scroll B[7:0] : start row address C[7:0] : number of rows to be H-scrolled B+C <= 132 Horizontal Scroll D[7:0] : Reserved E[1:0] : scrolling time interval 0 1 2 3 test mode normal slow slowest
0 1 1 1 1 1
96 A[7:0] B[7:0] C[7:0] D[7:0] E[1:0]
1 A7 B7 C7 D7 *
0 A6 B6 C6 D6 *
0 A5 B5 C5 D5 *
1 A4 B4 C4 D4 *
0 A3 B3 C3 D3 *
1 A2 B2 C2 D2 *
1 A1 B1 C1 D1 E1
0 A0 B0 C0 D0 E0
Note : operates during display on. 0 0 9E 9F 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 1 Stop Moving Start Moving
SSD1339
Rev 1.1
P 33/59
Jul 2005
Solomon Systech
9. COMMAND DESCRIPTIONS
Set Column Address (15h) This command specifies column start address and end address of the display data RAM. This command also sets the column address pointer to column start address. This pointer is used to define the current read/write column address in graphic display data RAM. If horizontal address increment mode is enabled by command A0h, after finishing read/write one column data, it is incremented automatically to the next column address. Whenever the column address pointer finishes accessing the end column address, it is reset back to start column address.
Set Row Address (75h) This command specifies row start address and end address of the display data RAM. This command also sets the row address pointer to row start address. This pointer is used to define the current read/write row address in graphic display data RAM. If vertical address increment mode is enabled by command A0h, after finishing read/write one row data, it is incremented automatically to the next row address. Whenever the row address pointer finishes accessing the end row address, it is reset back to start row address. For example, column start address is set to 2 and column end address is set to 129, row start address is set to 1 and row end address is set to 130. Horizontal address increment mode is enabled by command A0h. In this case, the graphic display data RAM column accessible range is from column 2 to column 129 and from row 1 to row 130 only. In addition, the column address pointer is set to 2 and row address pointer is set to 1. After finishing read/write one pixel of data, the column address is increased automatically by 1 to access the next RAM location for next read/write operation. Whenever the column address pointer finishes accessing the end column 129, it is reset back to column 2 and row address is automatically increased by 1. While the end row 130 and end column 129 RAM location is accessed, the row address is reset back to 1. The diagram below shows the way of column and row address pointer movement for this example. Col 0 Row 0 Row 1 Row 2 : : : Row 129 Row 130 Row 131 : : : Col 1 Col 2 ..... ....... Col129 Col130 Col131
Figure 20 - Example of column and row address pointer movement
Solomon Systech
Jul 2005
P 34/59
Rev 1.1
SSD1339
Write RAM Command (5Ch) After this single byte command, data entries will be written into the display RAM until another command is written. Address pointer is increased accordingly. This command must be sent before write data into RAM.
Read RAM Command (5Dh) After this single byte command, data is read from display RAM until another command is written. Address pointer is increased accordingly. This command must be sent before read data from RAM.
Set Re-map & Color Depth (A0h) This command has multiple configurations and each bit setting is described as follows. * Address increment mode (A[0]) When it is set to 0, the driver is set as horizontal address increment mode. After the display RAM is read/written, the column address pointer is increased automatically by 1. If the column address pointer reaches column end address, the column address pointer is reset to column start address and row address pointer is increased by 1. The sequence of movement of the row and column address point for horizontal address increment mode is shown in Figure 21. Col 0 Row 0 Row 1 : Row 130 Row 131 : Col 1 : ..... : Col 130 : Col 131 :
Figure 21 - Address pointer movement of horizontal address increment mode When A[0] is set to 1, the driver is set to vertical address increment mode. After the display RAM is read/written, the row address pointer is increased automatically by 1. if the row address pointer reaches the row end address, the row address pointer is reset to row start address and column address pointer is increased by 1. The sequence of movement of the row and column address point for vertical address increment mode is shown in Figure 22. Col 0 Row 0 Row 1 : Row 130 Row 131 Col 1 ..... ..... ..... : ..... ..... Col 130 Col 131
Figure 22 - Address pointer movement of vertical address increment mode * Column Address Mapping (A[1]) This command bit is made for flexible layout of segment signals in OLED module with segment arranged from left to right or vice versa. Color Remap (A[2]) This command bit is made for flexible layout of color sequence A # B # C or C # B # and A.
*
SSD1339
Rev 1.1
P 35/59
Jul 2005
Solomon Systech
*
MCU interface selection (A[3]) This command bit is made for setting the 6800 or 8080 parallel bus interface for to either 8/16-bit or 9/18-bit. COM Remap (A[4]) This bit determines the scanning direction of the common for flexible layout of common signals in OLED module either from up to down or vice versa. Odd even split of COM pins (A[5]) This bit can set the odd even arrangement of COM pins. A[5] = 0: Disable COM split odd even, pin assignment of common is in sequential as COM131 COM129 .... COM 33 COM32..SC131..SA0..COM0 COM1.... COM30 COM31 A[5] = 1: Enable COM split odd even, pin assignment of common is in odd even split as COM131 COM129.... COM3 COM1..SC131..SA0..COM0 COM2.... COM60 COM62 Display color mode (A[7:6]) Select either 262k, 65k or 256 color mode. In 262k colors mode, if 16-bit MCU interface is selected, there are two communication modes. In mode 1, one pixel data in transmitted in two 16-bit words. In mode 2, one communication session is consisted of three 16-bit words to transmit two pixel data. Please refer to section "Data access in 262k colors mode" for details. In all other 8/9/18-bit parallel or SPI MCU interfaces, there is no difference between mode 1 and mode 2 selections. The display RAM data format in different mode is described in section "Graphic Display Data RAM (GDDRAM)".
*
*
*
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Set Display Start Line (A1h) This command is to set Display Start Line register to determine starting address of display RAM to be displayed by selecting a value from 0 to 131. The figure below shows an example of this command. In there, "Row" means the graphic display data RAM row. COM Pin COM0 COM1 COM2 COM3 : : COM125 COM126 COM127 COM128 COM129 COM130 COM131 132 0 Row0 Row1 Row2 Row3 : : Row125 Row126 Row127 Row128 Row129 Row130 Row131 132 4 Row4 Row5 Row6 Row7 : : Row129 Row130 Row131 Row0 Row1 Row2 Row3 130 0 Row0 Row1 Row2 Row3 : : Row125 Row126 Row127 Row128 Row129 130 4 Row4 Row5 Row6 Row7 : : Row129 Row130 Row131 Row0 Row1 Mux ratio Display start line
Figure 23 - Example of set display start line with no remap Set Display Offset (A2h) This command specifies the mapping of display start line (it is assumed that COM0 is the display start line, display start line register equals to 0) to one of COM0-131. The figure below shows an example of this command. In there, "Row" means the graphic display data RAM row. COM Pin COM0 COM1 COM2 COM3 : : COM125 COM126 COM127 COM128 COM129 COM130 COM131 132 0 Row0 Row1 Row2 Row3 : : Row125 Row126 Row127 Row128 Row129 Row130 Row131 132 4 Row4 Row5 Row6 Row7 : : Row129 Row130 Row131 Row0 Row1 Row2 Row3 130 0 Row0 Row1 Row2 Row3 : : Row125 Row126 Row127 Row128 Row129 130 4 Row4 Row5 Row6 Row7 : : Row129 Row0 Row1 Row2 Row3 Mux ratio Display offset
Figure 24 - Example of set display offset with no remap
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Set Display Mode (A4h ~ A7h) These are single byte command and they are used to set Normal Display, Entire Display On, Entire Display Off and Inverse Display. * Set Entire Display On (A5h) Forces the entire display to be at "GS63" regardless of the contents of the display data RAM. * Set Entire Display Off (A4h) Forces the entire display to be at gray level "GS0" regardless of the contents of the display data RAM. * Inverse Display (A7h) The gray level of display data are swapped such that "GS0" <-> "GS63", "GS1" <-> "GS62", .... * Normal Display (A6h) Reset the above effect and turn the data to ON at the corresponding gray level.
Master Configuration (ADh) This command contains multiple bits to control several functionalities of the driver. * Select DC-DC converter (A[0]) 0 = Disable selection of DC-DC converter and VCC is supplied externally. 1 (POR) = Enable selection of DC-DC converter to supply high voltage to VCC. The output voltage of the converter is set by values of external resistors. Please refer to section "DC-DC Voltage Converter" for details. * Select VCOMH supply (A[1]) 0 = Select external VCOMH voltage from VCOMH pin for the common waveform high voltage level supply. It is recommended to set the voltage of VCOMH such that the OLED pixel diode is not turned on (prefer in reverse bias state) when the segment pin is either driven to VPA, VPB or VPC level. 1 = Select internal VCOMH voltage generated by regulator from VREF. The level of VCOMH can be programmed by command BEh. * Select pre-charge voltage supply (A[2]) 0 = Select pre-charge voltage sources from external pins VPA, VPB, VPC for color A, B and C respectively. 1 = Select pre-charge voltage supply internally. The level of VPA, VPB, VPC can be set by command BBh for color A, B and C respectively.
Set Sleep mode On/Off (AEh/AFh) These single byte commands are used to turn the OLED panel display on or off. When the display is on, the selected circuits by Set Master Configuration command will be turned on. When the display is off, those circuits will be turned off and the segment and common output are in high impedance state.
Power Saving Mode (B0h) This command sets the driver IC either in normal power mode and power saving mode.
Set Reset (Phase 1)/ Pre-charge (Phase 2) period (B1h) This command sets the length of phase 1 and 2 of segment waveform of the driver. * Phase 1 (A[3:0]): Set the period from 1 to 16 in the unit of DCLKs. A larger capacitance of the OLED pixel may require longer period to discharge the previous data charge completely. * Phase 2 (A[7:4]): Set the period from 1 to 16 in the unit of DCLKs. A longer period is needed to charge up a larger capacitance of the OLED pixel to the target voltage VPA, VPB, VPC for color A, B and C respectively.
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Front Clock Divider (DivSet)/ Oscillator Frequency (B3h) This command consists of two functions: * Display Clock Divide Ratio (A[3:0]) Set the divide ratio to generate DCLK (Display Clock) from CLK. The divide ratio is from 1 to 16, with power on reset value = 1. Please refer to section "Oscillator Circuit and Display Time Generator" for the details of DCLK and CLK. * Oscillator Frequency (A[7:4]) Program the oscillator frequency Fosc which is the source of CLK if CLS pin is pulled high. The 4-bit value results in 16 different frequency setting available as shown below. The default value is 1101b.
Look Up Table for Gray Scale Pulse width (B8h) This command is used to set the gray scale table for the display. Except gray scale entry 0, which is zero as it has no pre-charge and current drive, each odd entry gray scale level is programmed in the length of current drive stage pulse width with unit of DCLK. The longer the length of the pulse width, the brighter is the OLED pixel when it's turned on. Please refer to section "Graphic Display Data RAM (GDDRAM)" for more detailed explanation of relation of display data RAM, gray scale table and the pixel brightness. Following the command B8h, the user has to set the pulse width from PW1, PW3, PW5, ..., PW59, PW61, PW63 one by one in sequence and complies the following conditions. PW1 > 0; PW3 > PW1 + 1; PW5 > PW3 + 1; ...... Afterwards, the driver automatically derives the pulse width of even entry of gray scale table PW2, PW4, ..., PW62 with the formula like below. PWn = (PWn-1 + PWn+1) / 2 For example, if PW1 = 3 DCLKs and PW3 = 7 DCLKs, PW2 = (3+7)/2 = 5 DCLKs The setting of gray scale table entry can perform gamma correction on OLED panel display. Normally, it is desired that the brightness response of the panel is linearly proportional to the image data value in display data RAM. However, the OLED panel is somehow responded in non-linear way. Appropriate gray scale table setting like example below can compensate this effect. Brightness Pulse Width Gray scale table setting Brightness
Panel response
Result in linear response Gray Scale
Gray Scale
Pulse width
Figure 25 - Example of gamma correction by gray scale table setting
Use Built-in Linear LUT (B9h) This command reloads the preset linear gray scale table as PW1 = 1, PW2 = 3, PW3 = 5, ...., PW62 = 123, PW63 = 125 DCLKs.
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Set Pre-charge voltage of Color A, B and C (BBh) This command is used to set VPA, VPB and VPC phase 2 voltage level for color A, B and C respectively. The command is valid in condition that these voltages are selected to generate internally by command ADh. It can be programmed to set the pre-charge voltage reference to VREF or VCOMH. Voltage level increases linearly when set value increases.
Set VCOMH (BEh) This command sets the high voltage level of common pins, VCOMH, when it is selected to generate internally by command ADh. The level of VCOMH is programmed with reference to VREF. Voltage level increases linearly when set value increases.
Contrast Current for Color A, B, C (C1h) This command is to set Contrast Current of each color A, B and C. The chip has three contrast control circuits for color A, B and C. Each contrast circuit has 256 contrast steps from 00h to FFh. The segment output current ISEG increases linearly with the contrast step, which results in brighter of the color. This relation is shown in Figure 26. In many situations, the output brightness of color A, B and C pixels are different under the same segment current condition. The contrasts of color A, B and C are set such that the brightness of each color are the same on the OLED panel
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Master Contrast Current Control (C7h) This command is to control the segment output current by a scale factor. This factor is common to color A, B and C. The chip has 16 master control steps. The factor is ranged from 1 [0000] to 16 [1111]. POR is 16 [1111]. The smaller the master current value, the dimmer the OLED panel display is set. For example, if original segment output current of a color is 160uA at scale factor = 16, setting scale factor to 8 to reduce the current to 80uA. Please see Figure 26.
Segment output current
200
Master current setting
150
Change contrast control moves along the contrast curve with constant slope
100
50
0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00
9F AF BF CF DF EF FF
Output current Iseg (uA)
0 00 0F 1F 2F 3F 4F 5F 6F 7F 8F
Contrast setting
Change master current selects different contrast slope.
Figure 26 - Segment output current for different contrast control and master current setting
Set Multiplex Ratio (CAh) This command switches default 1:132 multiplex mode to any multiplex mode from 16 to 132. For example, when multiplex ratio is set to 16, only 16 common pins are enabled. The starting and the ending of the enabled common pins are depended on the setting of "Display Offset" register programmed by command A2h.
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Graphic Acceleration command set description Draw Line (83h) This command draws a line by the given start, end column and row coordinates and the color of the line. Line Color Row 2, Column 2
Row 1, Column 1 Figure 27 - Example of draw line command For example, the line above can be drawn by the following command sequence. 1. Enter into draw line mode by command 21h 2. Send column start address of line, column1, for example = 1h 3. Send row start address of line, row 1, for example = 10h 4. Send column end address of line, column 2, for example = 28h 5. Send row end address of line, row 2, for example = 4h 6. Send color C, B and A of line, for example = 35d, 0d, 0d for blue color
Draw Rectangle (84h) Given the starting point (Row 1, Column 1) and the ending point (Row 2, Column 2), specify the outline and fill area colors, a rectangle that will be drawn with the color specified. Remarks: If fill color option is disabled, the enclosed area will not be filled. Row 1, Column 1 Outline Color Row 2, Column 2 Figure 28 - Example of draw rectangle command The following example illustrates the rectangle drawing command sequence. 1. Enter the "draw rectangle mode" by execute the command 22h 2. Set the starting column coordinates, Column 1. e.g., 03h. 3. Set the starting row coordinates, Row 1. e.g., 02h. 4. Set the finishing column coordinates, Column 2. e.g., 12h 5. Set the finishing row coordinates, Row 2. e.g., 15h 6. Set the outline color C, B and A. e.g., (28d, 0d, 0d) for blue color 7. Set the filled color C, B and A. e.g., (0d, 0d, 40d) for red color Filled Color
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Draw Circle (86h) By providing the center coordination (column and row address) and radius length, specify the outline and fill area colors, a circle will be drawn with the colors specified.
Outline Color
Radius
Filled Color
Center column & row address Figure 29 - Example of draw circle command The following example illustrates the circle drawing command sequence. 1. Enter the "draw circle mode" by execute the command 86h 2. Set the circle center column coordinates, e.g., 03h. 3. Set the circle center row coordinates. e.g., 10h. 4. Set the radius of circle. e.g., 12h 5. Set the outline color C, B and A. e.g., (0d, 0d, 40d) for red color 6. Set the filled color C, B and A. e.g., (28d, 0d, 0d) for blue color
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Copy (8Ah) Copy the rectangular region defined by the starting point (Row 1, Column 1) and the ending point (Row 2, Column 2) to location (Row 3, Column 3). If the new coordinates are smaller than the ending points, the new image will overlap the original one. The following example illustrates the copy procedure. 1. Enter the "copy mode" by execute the command 23h 2. Set the starting column coordinates, Column 1. E.g., 00h. 3. Set the starting row coordinates, Row 1. E.g., 00h. 4. Set the finishing column coordinates, Column 2. E.g., 05h 5. Set the finishing row coordinates, Row 2. E.g., 05h 6. Set the new column coordinates, Column 3. E.g., 03h 7. Set the new row coordinates, Row 3. E.g., 03h Original Image
Row 1, Column 1
Row 3, Column 3 New Copied Image Row 3 + Row 2, Column 3 + Column 2
Figure 30 - Example of copy command
Dim Window (8Ch) This command will dim the window area specify by starting point (Row 1, Column 1) and the ending point (Row 2, Column 2). After the execution of this command, the selected window area will become darker as follow.
Table 5 - Result of change of brightness by dim window command Original gray scale GS0 ~ GS15 GS16 ~ GS19 GS20 ~ GS23 : GS60 ~ GS63 New gray scale after dim window command No change GS4 GS5 : GS15
Additional execution of this command over the same window area will not change the data content.
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Clear Window (8Eh) This command sets the window area specify by starting point (Row 1, Column 1) and the ending point (Row 2, Column 2) to clear the window display. The graphic display data RAM content of the specified window area will be set to zero. This command can be combined with Copy command to make as a "move" result. The following example illustrates the copy plus clear procedure and results in moving the window object. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. Enter the "copy mode" by execute the command 23h Set the starting column coordinates, Column 1. E.g., 00h. Set the starting row coordinates, Row 1. E.g., 00h. Set the finishing column coordinates, Column 2. E.g., 05h Set the finishing row coordinates, Row 2. E.g., 05h Set the new column coordinates, Column 3. E.g., 06h Set the new row coordinates, Row 3. E.g., 06h Enter the "clear mode" by execute the command 24h Set the starting column coordinates, Column 1. E.g., 00h. Set the starting row coordinates, Row 1. E.g., 00h. Set the finishing column coordinates, Column 2. E.g., 05h Set the finishing row coordinates, Row 2. E.g., 05h Original Image
Row 1, Column 1
New Copied Image
Clear Command
Row 3, Column 3 Row 3 + Row 2, Column 3 + Column 2
Figure 31 - Example of copy + clear = Move command
Fill Enable/Disable (92h) This command has two functions. * Enable/Disable fill (A[0]) 0 = Disable filling of color into rectangle in draw rectangle command. (POR) 1 = Enable filling of color into rectangle in draw rectangle command. * Enable/Disable reverse copy (A[4]) 0 = Disable reverse copy (POR) 1 = During copy command, the new image colors are swapped such that "GS0" <-> "GS63", "GS1" <-> "GS62", ....
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Horizontal Scroll (96h) This command consists of 5 consecutive bytes to set up the horizontal scroll parameters. It determined the scrolling start page, end page and the scrolling speed. Before issuing this command, the horizontal scroll must be deactivated (9Eh). Otherwise, RAM content may be corrupted.
Stop Moving (9Eh) Stop motion of horizontal scrolling.
Start Moving (9Fh) Start motion of horizontal scrolling. This command should only be issued after Horizontal scroll setup parameters are defined. The following actions are prohibited after the horizontal scroll is activated 1. RAM access (Data write or read) 2. Changing horizontal scroll setup parameters The SSD1339 horizontal scroll is designed for 132 columns scrolling
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10. MAXIMUM RATINGS
Table 6 - Maximum ratings (Voltage Reference to VSS)
Symbol VDD VCC VREF VCOMH Vin TA Tstg Parameter Supply Voltage Supply Voltage/Output voltage SEG/COM output voltage Input voltage Operating Temperature Storage Temperature Range Value -0.3 to +4 0 to 18 0 to 18 0 to 16 0 to 16 Vss-0.3 to Vdd+0.3 -40 to +90 -65 to +150 Unit V V V V V V C C
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description.
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11. DC CHARACTERISTICS
Table 7 - DC characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to 3.5V, TA = 25C)
Symbol
Vcc VDD VDDIO VOH VOL VIH VIL ISLEEP ICC IDD
Parameter
Operating Voltage Logic Supply Voltage Power Supply for I/O pins High Logic Output Level Low Logic Output Level High Logic Input Level Low Logic Input Level Sleep mode Current VCC Supply Current VDD Supply Current Segment Output Current Setting VDD=2.7V, VCC=11V, IREF=10uA, All one pattern, Display on, Segment pin under test is connected with a 20K resistive load to Vcc.
Test Condition
Min
7 2.4 1.5 0.9*VDDIO 0 0.8*VDDIO 0 -
Typ
11 2.7 2.7 1.3 0.4 160 110 60 0
Max
18 3.5 3.5 VDDIO 0.1*VDDI
O
Unit
V V V V V V V uA mA mA uA uA
Iout =100uA, 3.3MHz Iout =100uA, 3.3MHz Iout =100uA, 3.3MHz Iout =100uA, 3.3MHz VDD=2.7V, Display OFF, No panel attached VDD=3.0V, VCC=18V, Display ON Contrast =FF, No panel attached VDD=3.0V, VCC=18V, Display ON Contrast =FF, No panel attached Contrast = FF Contrast = AF Contrast = 5F Contrast = 00 Dev = (ISEG - IMID)/IMID IMID = (IMAX + IMIN)/2 ISEG[0:395] = Segment current at contrast = FF
VDDIO 0.2*VDDI
O
5 -
ISEG
-
uA uA
Segment output current uniformity Dev
-
-
3
%
Adj. Dev VCC
Adjacent pin output current uniformity (contrast = FF) Booster output voltage (Vcc)
Adj Dev = (I[n]-I[n+1]) / (I[n]+I[n+1]) Vin=3V, L=22uH; R1=450Kohm; R2=50Kohm; Icc = 30mA(soaking)
-
2.0 12
--
% V
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12. AC CHARACTERISTICS
Table 8 - AC characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 2.4 to 3.5V, TA = 25C.)
Symbol
FOSC FFRM
Parameter
Oscillation Frequency of Display Timing Generator Frame Frequency for 132 MUX Mode
Test Condition
Vdd = 2.7V 132RGB x 132 Graphic Display Mode, Display ON, Internal Oscillator Enabled
Min
-
Typ
2.0 FOSC X 1/(D*K*132)
Max
-
Unit
MHz Hz
D: divide ratio (POR =1) K: number of display clocks (POR=136, i.e. phase1 dclk+phase2 dclk+ phase3 dclk=4+7+125) Refer to command table for detail description
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Table 9 - 6800-Series MPU parallel interface timing characteristics (VDD - VSS = 2.4 to 3.5V, TA = 25C)
Symbol
tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF
Parameter
Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time Chip Select Low Pulse Width (read) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time
Min
300 0 0 40 15 20 120 60 60 60 -
Typ
-
Max
70 140 15 15
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
D/C# tAS R/W# tAH
E tcycle CS# tF D0~D7(WRITE) * tACC D0~D7(READ) * Valid Data tOH PW CSL PW CSH
tR
tDSW Valid Data tDHR tDHW
* when 9 bit used: D0 ~ D8 instead; when 16 bit used: D0 ~ D15 instead; when 18 bit used: D0 ~ D17 instead. Figure 32 - 6800-series MPU parallel interface characteristics
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Table 10 - 8080-Series MPU parallel interface timing characteristics (VDD - VSS = 2.4 to 3.5V, TA = 25C)
Symbol
tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF
Parameter
Clock Cycle Time Address Setup Time Address Hold Time Write Data Setup Time Write Data Hold Time Read Data Hold Time Output Disable Time Access Time Chip Select Low Pulse Width (read) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time
Min
300 0 0 40 15 20 120 60 60 60 -
Typ
-
Max
70 140 15 15
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
D/C tAS CS# tF PW CSL tcycle tR PW CSH t AH
RD#
WR#
tDSW D0-D17 * (Write data to driver) D0-D17 * (Read data from driver) Valid Data
tDHW
tACC Valid Data
tDHR
t * when 8 bit used: D0 ~ D7 instead; when 9 bit used: D0 ~ D8 instead; when 16 bit used: D0 ~ D15 instead; when 18 bit used: D0 ~ D17 instead. Figure 33 - 8080-series MPU parallel interface characteristics
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Table 11 - Serial interface timing characteristics (VDD - VSS = 2.4 to 3.5V, TA = 25C)
Symbol
tcycle tAS tAH tCSS tCSH tDSW tDHW tCLKL tCLKH Clock Cycle Time Address Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Data Setup Time Write Data Hold Time Clock Low Time Clock High Time Rise Time Fall Time
Parameter
Min
250 150 150 120 60 100 100 100 100 -
Typ
-
Max
15 15
Unit
ns ns ns ns ns ns ns ns ns ns ns
tR
tF
D/C# tAS CS# tCSS tCLK SCLK(D0) tF tDSW SDIN(D1) Valid Data tR tDHW tcycle tAH tCSH tCLKH
CS#
SCLK(D0) D7 D6 D5 D4 D3 D2 D1 D0
SDIN(D1)
Figure 34 - Serial interface characteristics
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13. APPLICATION EXAMPLE
The configuration for 8-bit 6800-parallel interface mode, externally VCC is shown in the following diagram: (VDD = VDDIO = 3.0V, external VCC = 12V, IREF = 10uA)
Color OLED Panel 132RGB x 132
COM130 . COM0
SSD1339Z
NC VCC VCOMH NC D7~D0 E RW# DC# RES# CS# IREF BS2 BS1 VDD VDDIO VP_C VP_B VP_A VBREF RESE FB VDDB GDR VSS NC
COM1 . COM131
SA0 SB0 SC0 . . . . . . . . . . SA131 SB131 SC131
R1
C1 C2 C3
D7~D0
E
RW# DC# RES# CS#
VSS [GND]
Pin connected to MCU interface: D0~D7, E, R/W#, D/C#, RES#, CS# Pin internally connected to VDD: M/S#, CLS Pin internally connected to VSS: VSSB, BGGND Pin internally connected to VCC: VREF Pin externally connected to VDD: BS0,1 Pin externally connected to VSS: BS2 Pin floated: VP_C, VP_B, VP_A, VBREF, RESE, FB, VDDB, GDR C1~C3: 4.7uF Voltage at IREF = VCC - 3V R1 = (Voltage at IREF - VSS) / IREF = 910K
Figure 35 - Application example for 8-bit 6800-parallel interface mode
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14. PACKAGE INFORMATION
SSD1339U3 Pin Assignment
Figure 36 - SSD1339U3 pin assignment
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Table 12 - SSD1339U3 pin assignment
Name NC VCC COMH VDDIO VSL D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 E R/W# BS0 BS1 BS2 CS# D/C# RES# IREF VBREF RESE FB VDDIO GDR VSS NC Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Name NC NC NC NC COM129 COM128 COM127 COM126 COM125 COM124 COM123 COM122 COM121 COM120 COM119 COM118 COM117 COM116 COM115 COM114 COM113 COM112 COM111 COM110 COM109 COM108 COM107 COM106 COM105 COM104 COM103 COM102 COM101 COM100 COM99 COM98 COM97 COM96 COM95 COM94 COM93 COM92 COM91 COM90 COM89 COM88 COM87 COM86 COM85 COM84 COM83 COM82 COM81 COM80 COM79 COM78 COM77 COM76 COM75 COM74 COM73 COM72 COM71 COM70 COM69 COM68 COM67 COM66 NC NC NC NC NC NC NC NC NC NC NC NC NC Pin # 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Name NC NC NC SA127 SC126 SB126 SA126 SC125 SB125 SA125 SC124 SB124 SA124 SC123 SB123 SA123 SC122 SB122 SA122 SC121 SB121 SA121 SC120 SB120 SA120 SC119 SB119 SA119 SC118 SB118 SA118 SC117 SB117 SA117 SC116 SB116 SA116 SC115 SB115 SA115 SC114 SB114 SA114 SC113 SB113 SA113 SC112 SB112 SA112 SC111 SB111 SA111 SC110 SB110 SA110 SC109 SB109 SA109 SC108 SB108 SA108 SC107 SB107 SA107 SC106 SB106 SA106 SC105 SB105 SA105 SC104 SB104 SA104 SC103 SB103 SA103 SC102 SB102 SA102 SC101 SB101 Pin # 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 Name SA101 SC100 SB100 SA100 SC99 SB99 SA99 SC98 SB98 SA98 SC97 SB97 SA97 SC96 SB96 SA96 SC95 SB95 SA95 SC94 SB94 SA94 SC93 SB93 SA93 SC92 SB92 SA92 SC91 SB91 SA91 SC90 SB90 SA90 SC89 SB89 SA89 SC88 SB88 SA88 SC87 SB87 SA87 SC86 SB86 SA86 SC85 SB85 SA85 SC84 SB84 SA84 SC83 SB83 SA83 SC82 SB82 SA82 SC81 SB81 SA81 SC80 SB80 SA80 SC79 SB79 SA79 SC78 SB78 SA78 SC77 SB77 SA77 SC76 SB76 SA76 SC75 SB75 SA75 SC74 SB74 Pin # 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 Name SA74 SC73 SB73 SA73 SC72 SB72 SA72 SC71 SB71 SA71 SC70 SB70 SA70 SC69 SB69 SA69 SC68 SB68 SA68 SC67 SB67 SA67 SC66 SB66 SA66 SC65 SB65 SA65 SC64 SB64 SA64 NC SC63 SB63 SA63 SC62 SB62 SA62 SC61 SB61 SA61 SC60 SB60 SA60 SC59 SB59 SA59 SC58 SB58 SA58 SC57 SB57 SA57 SC56 SB56 SA56 SC55 SB55 SA55 SC54 SB54 SA54 SC53 SB53 SA53 SC52 SB52 SA52 SC51 SB51 SA51 SC50 SB50 SA50 SC49 SB49 SA49 SC48 SB48 SA48 SC47 Pin # 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 Name SB47 SA47 SC46 SB46 SA46 SC45 SB45 SA45 SC44 SB44 SA44 SC43 SB43 SA43 SC42 SB42 SA42 SC41 SB41 SA41 SC40 SB40 SA40 SC39 SB39 SA39 SC38 SB38 SA38 SC37 SB37 SA37 SC36 SB36 SA36 SC35 SB35 SA35 SC34 SB34 SA34 SC33 SB33 SA33 SC32 SB32 SA32 SC31 SB31 SA31 SC30 SB30 SA30 SC29 SB29 SA29 SC28 SB28 SA28 SC27 SB27 SA27 SC26 SB26 SA26 SC25 SB25 SA25 SC24 SB24 SA24 SC23 SB23 SA23 SC22 SB22 SA22 SC21 SB21 SA21 SC20 Pin # 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 Name SB20 SA20 SC19 SB19 SA19 SC18 SB18 SA18 SC17 SB17 SA17 SC16 SB16 SA16 SC15 SB15 SA15 SC14 SB14 SA14 SC13 SB13 SA13 SC12 SB12 SA12 SC11 SB11 SA11 SC10 SB10 SA10 SC9 SB9 SA9 SC8 SB8 SA8 SC7 SB7 SA7 SC6 SB6 SA6 SC5 SB5 SA5 SC4 SB4 SA4 SC3 SB3 SA3 SC2 SB2 SA2 SC1 SB1 SA1 SC0 SB0 SA0 Pin # 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 Name NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 NC NC NC NC Pin # 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589
SSD1339
Rev 1.1
P 55/59
Jul 2005
Solomon Systech
SSD1339U3 COF details dimensions
Figure 37 - SSD1339U3 detail dimensions
1
2
38
39
Solomon Systech
Jul 2005
P 56/59
Rev 1.1
SSD1339
Contact Side
JAE JACS-10142
SSD1339
Rev 1.1
P 57/59
Jul 2005
Solomon Systech
Solomon Systech
Jul 2005
P 58/59
Rev 1.1
SSD1339
Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part.
http://www.solomon-systech.com
SSD1339
Rev 1.1
P 59/59
Jul 2005
Solomon Systech

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