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TM
UCT UCT D ROD TE P TE PRO E SOL STITU 2 OB SUB G44 Data SheetIBLE G445, D March 2000 SS D PO
IH5053
File Number 3131.3
Quad CMOS Analog Switch [ /Title (IH505 3) /Subject (Quad CMOS Analog Switch es) /Autho r () /Keywords (Intersil Corporation, semiconductor, Quad CMOS Analog Switch es) /Creator () /DOCI NFO pdfmark [ /PageMode
The IH5053 analog switch uses an improved, high voltage CMOS technology, which provides performance advantages not previously available from solid state switches. Key performance advantages are TTL compatibility and ultra lowpower operation. The quiescent current requirement is less than 10A. The IH5053 also guarantees Break-Before-Make switching. This is accomplished by extending the tON time (1000ns) such that it exceeds the tOFF time (500ns). This insures that an ON channel will be turned OFF before an OFF channel can turn ON, and eliminates the need for external logic required to avoid channel to channel shorting during switching.
Features
* Switches Greater Than 20VP-P Signals with 15V Supplies * Quiescent Current . . . . . . . . . . . . . . . . . . . . . . . . . <10A * Break-Before-Make Switching - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns * TTL, CMOS Compatible * 4 Normally Open Switches * Low rDS(ON) (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Part Number Information
PART NUMBER TEMP. RANGE (oC) 0 to 70 PACKAGE 16 Ld SBDIP PKG. NO. D16.3
Pinout
IH5053 (SBDIP) TOP VIEW
IN1 1 D1 2 S1 3 V- 4 GND 5 S2 6 D2 7 IN2 8 16 IN4 15 D4 14 S4 13 V+ 12 VL 11 S3 10 D3 9 IN3
IH5053CDE
Schematic Diagram
( 1/4 AS SHOWN)
V+
Q3 5K Q4 Q1
SWITCH STATES SHOWN FOR LOGIC "1" INPUT
2K GND IN VL Q2 FLOATS 400 1K 10K Q6 Q5 400 Q7 Q8 Q12 Q11
TRUTH TABLE LOGIC 0 1 SWITCHES Off On
V-
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation Copyright (c) Intersil Corporation 2000
IH5053
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <36V V+ to VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V VD to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V VD to VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <22V VL to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <33V VL to VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V Continuous Current (S-D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current IN or OUT (Pulsed 1ms, 10% Duty Cycle, Max) . . . 70mA
Thermal Information
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . .175oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
V+ = +15V, V- = -15V, VL = +5V (NOTES 1, 2)
PER CHANNEL PARAMETER DYNAMIC CHARACTERISTICS Turn ON Time, tON Turn OFF Time, tOFF Charge Injection, Q OFF Isolation, OIRR Crosstalk, CCRR DIGITAL INPUT CHARACTERISTICS Input Logic Current, IIN(ON) Input Logic Current, IIN(OFF) ANALOG SWITCH CHARACTERISTICS Drain-Source ON Resistance, rDS(ON) Channel-to-Channel, rDS(ON) Match Minimum Analog Signal Handling Capability, VANALOG Switch OFF Leakage Current, ID(OFF) , IS(OFF) Switch ON Leakage Current, ID(ON) + IS(ON) POWER SUPPLY CHARACTERISTICS + Power Supply Quiescent Current, I+ - Power Supply Quiescent Current, I+5V Supply Quiescent Current, IL NOTES: VlN = 2.4V VlN = 0.8V Figure 7
TEST CONDITIONS
0 oC
25oC
70oC
UNITS
RL = 1k, VANALOG = -10V to +10V (Figure 6)
-
1000 500 20 (Typ) 50 (Typ) 50 (Typ)
-
ns ns mV dB dB
f = 1MHz, RL = 100, CL 5pF (Figure 4) One Channel Off (Figure 3)
-
10 10
-
A A
IS = 10mA, VANALOG = -10V to +10V
80 -
80 30 (Typ) 10 (Typ) 5 10
100 -
V
VANALOG = -10V to +10V VD = VS = -10V to +10V
-
100 100
nA nA
10 10 10
10 10 10
100 100 100
A A A
1. Typical values are for Design Aid only, not guaranteed nor production tested. 2. Min or Max value unless otherwise specified.
2
IH5053 Test Circuits and Waveforms
100 IS = 1mA VS = 15V 80 120 rDS(ON) () rDS(ON) () 125oC 60 25oC 40 -55oC 100 80 60 40 20 20 0 -10.0 0 -10.0 VS = 12V VS = 15V VS = 10V 160 140
-7.5
-5.0
-2.5
0
2.5
5.0
7.5
10.0
-7.5
-5.0
-2.5
0
2.5
5.0
7.5
10.0
VANALOG (V)
VANALOG (V)
FIGURE 1. rDS(ON) vs ANALOG INPUT VOLTAGE
-120 CCRR = 20LOG -100 CROSSTALK (dB)
FIGURE 2. rDS(ON) vs POWER SUPPLY VOLTAGE
VOUT (VP-P) 2VP-P OFF STATE VOUT
-80
-60
100
-40 ON STATE 2VP-P AT 1MHz 51 0 1 10 100 1K 10K 100K 1M FREQUENCY (Hz) 100
-20
FIGURE 3A. CROSSTALK vs FREQUENCY FIGURE 3. CROSSTALK
120 OIRR = 20LOG 100 OFF ISOLATION (dB) 80
FIGURE 3B. TEST CIRCUIT
2VP-P VOUT (VP-P)
60 2VP-P AT 1MHz 40 OFF STATE VOUT 0 1 10 100 1K 10K 100K 1M FREQUENCY (Hz) 100 51
20
FIGURE 4A. OFF ISOLATION vs FREQUENCY FIGURE 4. OFF ISOLATION
FIGURE 4B. TEST CIRCUIT
3
IH5053 Test Circuits and Waveforms (Continued)
TTL LEVEL 0.1T T IQUIESCENT (EITHER + OR - SUPPLY) (A) 1000 LOGIC INPUT
100 ANALOG INPUT 10V 3V 10 0V TTL LOGIC INPUT 10pF 1 1 10 100 1K 10K 100K LOGIC FREQUENCY AT 10% DUTY CYCLE (Hz) VOUT 1k
FIGURE 5. SUPPLY CURRENT vs LOGIC FREQUENCY
FIGURE 6. tON AND tOFF TEST CIRCUIT
45 40 35 QINJECT (mVP-P) 30 ANALOG INPUT 25 20 15 10 0 -10.0 0V TTL LOGIC INPUT 10nF VOUT 3V
-7.5
-5.0
-2.5
0
2.5
5.0
7.5
10.0
VANALOG (V)
FIGURE 7A. CHARGE INJECTION vs ANALOG INPUT VOLTAGE, CL = 10nF FIGURE 7. CHARGE INJECTION
FIGURE 7B. TEST CIRCUIT
4
IH5053 Typical Applications
10k 15V REXT (1k TO 20k) TTL LOGIC INPUT IN GND
LOGIC INPUT
VL
V+ +15V
15V TTL GATE
20k
FIGURE 8. +15V OPEN COLLECTOR TTL INTERFACE
+15V 13 IH5053 VIN1 3 CH1 1 VIN2 14 CH2 16 VIN3 11 CH3 9 VIN4 6 CH4 8 4 -15V 12 +5V 10 GAIN3 9 7 GAIN4 8 4 -15V 12 +5V 6 100 11 100 1000X 7 2 GAIN1 1 10X 15 GAIN2 16 100X 14 2k 100k 9.9k 10 +15V 13 IH5053 5 1X 3 18k 15 2 2 3 + LM101A 5 +15V 7 -15V 4 1 30pF
6
VOUT
-
FIGURE 9. ACTIVE LOW PASS FILTER WITH DIGITALLY SELECTED BREAK FREQUENCY
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com 5

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