View TPS51116_362910.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TPS51116
www.ti.com
SLUS609A - MAY 2004 - REVISED JUNE 2004
COMPLETE DDR AND DDR2 MEMORY POWER SOLUTION SYNCHRONOUS BUCK CONTROLLER, 3-A LDO, BUFFERED REFERENCE
FEATURES
* Synchronous Buck Controller (VDDQ) - Wide-Input Voltage Range: 3.0-V to 28-V - D-CAPTM Mode with 100-ns Load Step Response - Current Mode Option Supports Ceramic Output Capacitors - Supports Soft-Off in S4/S5 States - Current Sensing from RDS(on) or Resistor - 2.5-V (DDR), 1.8-V (DDR2) or Adjustable Output (1.5-V to 3.0-V) - Equipped with Powergood, Overvoltage Protection and Undervoltage Protection 3-A LDO (VTT), Buffered Reference (VREF) - Capable to Sink and Source 3 A - LDO Input Available to Optimize Power Losses - Requires only 20-F Ceramic Output Capacitor - Buffered Low Noise 10-mA Output - Accuracy 20 mV for both VREF and VTT - Supports High-Z in S3 and Soft-Off in S4/S5 - Thermal Shutdown
DESCRIPTION
The TPS51116 provides a complete power supply for both DDR/SSTL-2 and DDR2/SSTL-18 memory systems. It integrates a synchronous buck controller with a 3-A sink/source tracking linear regulator and buffered low noise reference. The TPS51116 offers the lowest total solution cost in systems where space is at a premium. The TPS51116 synchronous controller runs fixed 400kHz pseudo-constant frequency PWM with an adaptive on-time control that can be configured in D-CAPTM Mode for ease of use and fastest transient response or in current mode to support ceramic output capacitors. The 3-A sink/source LDO maintains fast transient response only requiring 20-F (2 x 10 F) of ceramic output capacitance. In addition, the LDO supply input is available externally to significantly reduce the total power losses. The TPS51116 supports all of the sleep state controls placing VTT at high-Z in S3 (suspend to RAM) and discharging VDDQ, VTT and VTTREF (soft-off) in S4/S5 (suspend to disk). The TPS51116 has all of the protection features including thermal shutdown and is in a 20-pin HTSSOP PowerPADTM package.
*
APPLICATIONS
* * DDR/DDR2 Memory Power Supplies SSTL-2 SSTL-18 and HSTL Termination
C1 Ceramic 0.1 F DRVH 19 LL 18 DRVL 17 C8 SP-CAP 2 x 150 F R1 L1 1 H VIN C5 Ceramic 2 x 10 F VDDQ 1.8 V 10 A
TYPICAL APPLICATION (DDR2)
VTT 0.9 V 2A GND
TPS51116PWP 1 VLDOIN 2 VTT 3 VTTGND 4 VTTSNS VBST 20
C3 Ceramic 2 x 10 F
5 GND C4 Ceramic 0.033 F 6 MODE 7 VTTREF 8 COMP
PGND 16 CS 15 V5IN 14 R2 PGOOD 13 S5 12 S3 11 PGOOD S5 S3
UDG-04058
VREF 0.9 V 10 mA GND
5V_IN C2 Ceramic 4.7 F
9 VDDQSNS 10 VDDQSET
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2004, Texas Instruments Incorporated
TPS51116
SLUS609A - MAY 2004 - REVISED JUNE 2004
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION
TA -40C to 85C (1) PLASTIC HTTSOP PowerPAD (PWP) (1) TPS51116PWP
The PWP package is also available taped and reeled. Add an R suffix to the device type (TPS51116PWPR)
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range unless otherwise noted
TPS51116 VBST VIN Input voltage range VBST wrt LL CS, MODE, S3, S5, VTTSNS, VDDQSNS, V5IN, VLDOIN, VDDQSET PGND, VTTGND DRVH VOUT TA Tstg (1) Output voltage range LL COMP, DRVL, PGOOD, VTT, VTTREF Operating ambient temperature range Storage temperature -0.3 to 36 -0.3 to 6 -0.3 to 6 -0.3 to 0.3 -1.0 to 36 -1.0 to 30 -0.3 to 6 -40 to 85 -55 to 150 C V V UNITS
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted.
DISSIPATION RATINGS
PACKAGE 20-pin TA < 25C 2.53 W DERATING FACTOR ABOVE TA = 25C 25.3 mW/C TA = 85C 1.01 W
RECOMMENDED OPERATING CONDITIONS
MIN Supply voltage, V5IN VBST, DRVH LL VLDOIN, VTT, VTTSNS, VDDQSNS Voltage range VTTREF PGND, VTTGND S3, S5, MODE, VDDQSET, CS, COMP, PGOOD, DRVL Operating free-air temperature, TA 4.75 -0.1 -0.6 -0.1 -0.1 -0.1 -0.1 -40 MAX 5.25 34 28 3.6 1.8 0.1 5.25 85 C V UNIT V
2
TPS51116
www.ti.com
SLUS609A - MAY 2004 - REVISED JUNE 2004
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)
PARAMETER SUPPLY CURRENT IV5IN1 IV5IN2 IV5IN3 IV5INSDN IVLDOIN1 IVLDOIN2 IVLDOINSDN VVTTREF Supply current 1, V5IN Supply current 2, V5IN Supply current 3, V5IN Shutdown current, V5IN Supply current 1, VLDOIN Supply current 2, VLDOIN Standby current, VLDOIN Output voltage, VTTREF -10 mA < IVTTREF < 10 mA, VVDDQSNS/2= 2.5 V, Tolerance to VVDDQSNS/2 VVTTREFTOL Output voltage tolerance -10 mA < IVTTREF < 10 mA, VVDDQSNS/2 = 1.8 V, Tolerance to VVDDQSNS/2 VVDDQSNS = 2.5 V, VVTTREF = 0 V VVDDQSNS = 2.5 V, VVTTREF = 2.5 V VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 2.5 V VS3 = VS5 = 5 V, VVLDOIN = VVDDQSNS = 1.8 V -20 -30 -40 -20 -30 -40 3.0 1.5 3.0 1.5 -10 -1 -1 10 17 -0.1 3.8 2.2 3.6 2.2 -20 -18 -20 20 -40 40 1.25 0.9 20 30 40 20 30 40 6.0 3.0 6.0 3.0 10 1 1 mA A A mV TA = 25C, No load, VS3 = VS5 = 5 V, COMP connected to capacitor TA = 25C, No load, VS3 = 0 V, VS5 = 5 V, COMP connected to capacitor TA = 25C, No load, VS3 = 0 V, VS5 = 5 V, VCOMP = 5 V TA = 25C, No load, VS3 = VS5 = 0 V TA = 25C, No load, VS3 = VS5 = 5 V TA = 25C, No load, VS3 = 5 V, VS5 = 0 V, TA = 25C, No load, VS3 = VS5 = 0 V 0.8 300 240 0.1 1 0.1 0.1 VVDDQSNS/2 20 mV 18 -80 80 2 600 500 1.0 10 10 1.0 V A mA TEST CONDITIONS MIN TYP MAX UNIT
VTTREF OUTPUT
VVTTREFSRC VVTTREFSNK VTT OUTPUT VVTTSNS
Source current Sink current
mA
Output voltage, VTT
V
VVTTTOL25
VS3 = VS5 = 5 V, IVTT = 0 A VTT output voltage tolerance VS3 = VS5 = 5 V, |IVTT| = 0 A < 1.5 A to VTTREF VS3 = VS5 = 5 V, |IVTT| = 0 A < 3 A VTT output voltage tolerance VS3 = VS5 = 5 V, |IVTT| = 0 A < 1 A to VTTREF VS3 = VS5 = 5 V, |IVTT| = 0 A < 2 A Source current limit, VTT VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS = 1.19 V, PGOOD = HI VVLDOIN = VVDDQSNS = 2.5 V, VVTT = 0 V VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVTTSNS = 1.31 V, PGOOD = HI VVLDOIN = VVDDQSNS = 2.5 V, VVTT = VVDDQ VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2 VS3 = 5 V, VVTTSNS = VVDDQSNS /2 VS3 = 0 V, VS5 = 5 V, VVTT = VVDDQSNS /2 TA = 25C, VS3 = VS5 = VVDDQSNS = 0 V, VVTT = 0.5 V TA = 25C, VVDDQSET = 0 V, No load 0C TA 85C, VVDDQSET = 0 V, No load (1) -40C TA 85C, VVDDQSET = 0 V, No load
(1)
VS3 = VS5 = 5 V, IVTT = 0 A
VVTTTOL18
IVTTTOCLSRC
IVTTTOCLSNK IVTTLK IVTTBIAS IVTTSNSLK IVTTDisch
Sink current limit, VTT Leakage current, VTT Input bias current, VTTSNS Leakage current, VTTSNS Discharge current, VTT
VDDQ OUTPUT 2.465 2.457 2.440 1.776 1.769 1.764 1.5 2.500 2.500 2.500 1.800 1.800 1.800 2.535 2.543 2.550 1.824 1.831 1.836 3.0 V
VVDDQ
Output voltage, VDDQ
TA = 25C, VVDDQSET = 5 V, No load (1) 0C TA 85C, VVDDQSET = 5V, No load (1) -40C TA 85C, VVDDQSET = 5V, No load (1) -40C TA 85C, Adjustable mode, No load (1)
(1)
Ensured by design. Not production tested. 3
TPS51116
SLUS609A - MAY 2004 - REVISED JUNE 2004
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)
PARAMETER VVDDQSET TEST CONDITIONS TA = 25C, Adjustable mode VDDQSET regulation voltage 0C TA 85C, Adjustable mode -40C TA 85C, Adjustable mode VVDDQSET = 0 V RVDDQSNS Input impedance, VDDQSNS VVDDQSET = 5 V Adjustable mode IVDDQSET IVDDQDisch IVDDOINDisch Input current, VDDQSET Discharge current, VDDQ Discharge current, VLDOIN VVDDQSET = 0.78 V, COMP = Open VVDDQSET = 0.78 V, COMP = 5 V VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V, VMODE = 0 V VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V, VMODE = 0.5 V TA = 25C VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.7 V, VCOMP = 1.28 V 240 10 MIN 742.5 740.2 738.0 TYP 750.0 750.0 750.0 215 180 460 -0.04 -0.06 40 mA 700 A k MAX 757.5 759.8 762.0 mV UNIT
TRANSCONDUCTANCE AMPLIFIER gM ICOMPSNK ICOMPSRC VCOMPHI VCOMPLO Gain COMP maximum sink current 300 13 A -13 1.31 1.18 1.34 1.21 1.37 V 1.24 360 S
COMP maximum source cur- VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, rent VVDDQSNS = 2.3 V, VCOMP = 1.28 V COMP high clamp voltage COMP low clamp voltage VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.3 V, VCS = 0 V VS3 = 0 V, VS5 = 5 V, VVDDQSET = 0 V, VVDDQSNS = 2.7 V, VCS = 0 V VIN = 12 V, VVDDQSET = 0 V VIN = 12 V, VVDDQSNS = 0 V TA = 25C TA = 25C Source, IDRVH = -100 mA Sink, IDRVH = 100 mA Source, IDRVL = -100 mA Sink, IDRVL = 100 mA LL-low to DRVL-on
(2)
DUTY CONTROL TON TON0 TON(min) TOFF(min) Operating on-time Startup on-time Minimum on-time Minimum off-time 520 125 100 300 3 0.9 3 0.9 10 20 0.7 0.8 0.1 0.9 1.0 6 3 6 3 ns ns
OUTPUT DRIVERS RDRVH RDRVL TD DRVH resistance DRVL resistance Dead time
DRVL-off to DRVH-on (2) VV5IN-VBST , IF = 10 mA, TA = 25C VVBST = 34 V, VLL = 28 V, VVDDQ = 2.6 V, TA = 25C VPGND-CS , PGOOD = HI, VCS < 0.5 V VPGND-CS , PGOOD = LO, VCS < 0.5 V TA = 25C, VCS > 4.5 V, PGOOD = HI TA = 25C, VCS > 4.5 V, PGOOD = LO 50 20 9 4
INTERNAL BST DIODE VFBST IVBSTLK Forward voltage VBST leakage current V A
PROTECTIONS VOCL ITRIP Current limit threshold Current sense sink current 60 30 10 5 4500 70 40 11 6 mV A ppm/C
TCITRIP
TRIP current temperature co- RDS(on) sense scheme, On the basis efficient of TA = 25C
(2) 4
Ensured by design. Not production tested.
TPS51116
www.ti.com
SLUS609A - MAY 2004 - REVISED JUNE 2004
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output (unless otherwise noted)
PARAMETER VOCL(off) VR(trip) Overcurrent protection COMP offset TEST CONDITIONS (VV5IN-CS - VPGND-LL), VV5IN-CS = 60 mV, VCS > 4.5 V
(2)
MIN -5 30
TYP 0
MAX 5
UNIT
Current limit threshold setting VV5IN-CS range
mV 150
POWERGOOD COMPARATOR PG in from lower VTVDDQPG IPG(max) TPG(del) VDDQ powergood threshold PGOOD sink current PGOOD delay time PG in from higher PG hysteresis VVTT = 0 V, VPGOOD = 0.5 V Delay for PG in Wake up Hysteresis No discharge Non-tracking discharge 2.5 V output 1.8 V output S3, S5 S3, S5 S3, S5 S3, S5, MODE VDDQSET OVP detect Hysteresis -1 -1 110% 115% 5% 1.5 UVP detect Hysteresis 70% 10% 32 1007 Shutdown temperature Hysteresis 160 10 clks s 0.2 1 1 120% A 0.08 3.5 2.2 0.3 0.15 4.0 2.5 80 3.7 0.2 4.7 0.1 0.25 4.5 V 93% 103% 95% 105% 5% 7.5 130 4.0 0.3 200 4.3 0.4 mA s 97% 107%
UNDERVOLTAGE LOCKOUT/LOGIC THRESHOLD VUVV5IN VTHMODE VTHVDDQSET VIH VIL VIHYST VINLEAK VINVDDQSET V5IN UVLO threshold voltage MODE threshold VDDQSET threshold voltage High-level input voltage Low-level input voltage Hysteresis voltage Logic input leakage current Input leakage/ bias current
UNDERVOLTAGE AND OVERVOLTAGE PROTECTION VOVP TOVPDEL VUVP TUVPDEL TUVPEN VDDQ OVP trip threshold voltage VDDQ OVP propagation delay (3) Output UVP trip threshold Output UVP propagation delay Output UVP enable delay
THERMAL SHUTDOWN TSDN Thermal SDN threshold
(3)
C
(3)
Ensured by design. Not production tested.
5
TPS51116
SLUS609A - MAY 2004 - REVISED JUNE 2004
www.ti.com
DEVICE INFORMATION
PWP PACKAGE (TOP VIEW)
VLDOIN VTT VTTGND VTTSNS GND MODE VTTREF COMP VDDQSNS VDDQSET
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VBST DRVH LL DRVL PGND CS V5IN PGOOD S5 S3
TERMINAL FUNCTIONS
TERMINAL NAME COMP CS DRVH DRVL GND LL MODE PGND PGOOD S3 S5 V5IN VBST VDDQSET VDDQSNS VLDOIN VTT VTTGND VTTREF VTTSNS NO. 8 15 19 17 5 18 6 16 13 11 12 14 20 10 9 1 2 3 7 4 I/O I/O I/O O O I/O I O I I I I/O I I/O I O O I DESCRIPTION Output of the transconductance amplifier for phase compensation. Connect to V5IN to disable gM amplifier and use D-CAPTM mode. Current sense comparator input (-) for resistor current sense scheme. Or over current trip voltage setting input for RDS(on) current sense scheme if connected to V5IN through the voltage setting resistor. Switching (top) MOSFET gate drive output. Rectifying (bottom) MOSFET gate drive output. Signal ground. Connect to minus terminal of the VTT LDO output capacitor. Switching (top) MOSFET gate driver return. Current sense comparator input (-) for RDS(on) current sense. Discharge mode setting pin. See VDDQ and VTT Discharge Control section. Ground for rectifying (bottom) MOSFET gate driver. Also current sense comparator input (+). Powergood signal open drain output, In HIGH state when VDDQ output voltage is within the target range. S3 signal input. S5 signal input. 5-V power supply input for internal circuits. Switching (top) MOSFET driver bootstrap voltage input. VDDQ output voltage setting pin. See VDDQ Output Voltage Selection section. VDDQ reference input for VTT and VTTREF. Power supply for the VTTREF. Discharge current sinking terminal for VDDQ Non-tracking discharge. Output voltage feedback input for VDDQ output if VDDQSET pin is connected to V5IN or GND. Power supply for the VTT LDO. Power output for the VTT LDO. Power ground output for the VTT LDO. VTTREF buffered reference output. Voltage sense input for the VTT LDO. Connect to plus terminal of the VTT LDO output capacitor.
6
TPS51116
www.ti.com
SLUS609A - MAY 2004 - REVISED JUNE 2004
FUNCTIONAL BLOCK DIAGRAM
7
TPS51116
SLUS609A - MAY 2004 - REVISED JUNE 2004
www.ti.com
DETAILED DESCRIPTION
The TPS51116 is an integrated power management solution which combines a synchronous buck controller, a 10-mA buffered reference and a high-current sink/source low-dropout linear regulator (LDO) in a small 20-pin HTSSOP package. Each of these rails generates VDDQ, VTTREF and VTT that required with DDR/DDR2 memory systems. The switch mode power supply (SMPS) portion employs external N-channel MOSFETs to support high current for DDR/DDR2 memory's VDD/VDDQ. The output voltage is preset and selectable from 2.5 V or 1.8 V. User defined output voltage is also possible and can be adjustable from 1.5 V to 3 V. Input voltage range of the SMPS is 3 V to 28 V. The SMPS runs an adaptive on-time PWM operation at high-load condition and automatically reduces frequency to keep excellent efficiency down to several mA. Current sensing scheme uses either RDS(on) of the external rectifying MOSFET for a low-cost, loss-less solution, or an optional sense resistor placed in series to the rectifying MOSFET for more accurate current limit. The output of the switcher is sensed by VDDQSNS pin to generate one-half VDDQ for the 10-mA buffered reference (VTTREF) and the VTT active termination supply. The VTT LDO can source and sink up to 3-A peak current with only 20-F (two 10 F in parallel) ceramic output capacitors. VTTREF tracks VDDQ/2 within 20 mV. VTT output tracks VTTREF within 20 mV at no load condition while 40 mV at full load. The LDO input can be separated from VDDQ and optionally connected to a lower voltage by using VLDOIN pin. This helps reducing power dissipation in sourcing phase. TheTPS51116 is fully compatible to JEDEC DDR/DDR2 specifications at S3/S5 sleep state (see Table 2). The part has two options of output discharge function when both VTT and VDDQ are disabled. The tracking discharge mode discharges VDDQ and VTT outputs through the internal LDO transistors and then VTT output tracks half of VDDQ voltage during discharge. The non-tracking discharge mode discharges outputs using internal discharge MOSFETs which are connected to VDDQSNS and VTT. The current capability of these discharge FETs are limited and discharge occurs more slowly than the tracking discharge. These discharge functions can be disabled by selecting non-discharge mode.
VDDQ SMPS, Dual PWM Operation Modes
The main control loop of the SMPS is designed as an adaptive on-time pulse width modulation (PWM) controller. It supports two control schemes which are a current mode and a proprietary D-CAPTM mode. D-CAPTM mode uses internal compensation circuit and is suitable for low external component count configuration with an appropriate amount of ESR at the output capacitor(s). Current mode control has more flexibility, using external compensation network, and can be used to achieve stable operation with very low ESR capacitor(s) such as ceramic or specialty polymer capacitors. These control modes are selected by the COMP terminal connection. If the COMP pin is connected to V5IN, TPS51116 works in the D-CAPTM mode, otherwise it works in the current mode. VDDQ output voltage is monitored at a feedback point voltage. If VDDQSET is connected to V5IN or GND, this feedback point is the output of the internal resistor divider inside VDDQSNS pin. If an external resistor divider is connected to VDDQSET pin, VDDQSET pin itself becomes the feedback point (see VDDQ Output Voltage Selection section). At the beginning of each cycle, the synchronous top MOSFET is turned on, or becomes ON state. This MOSFET is turned off, or becomes OFF state, after internal one shot timer expires. This one shot is determined by VIN and VOUT to keep frequency fairly constant over input voltage range, hence it is called adaptive on-time control (see PWM Frequency and Adaptive On-Time Control section). The MOSFET is turned on again when feedback information indicates insufficient output voltage and inductor current information indicates below the over current limit. Repeating operation in this manner, the controller regulates the output voltage. The synchronous bottom or the rectifying MOSFET is turned on each OFF state to keep the conduction loss minimum. The rectifying MOSFET is turned off when inductor current information detects zero level. This enables seamless transition to the reduced frequency operation at light load condition so that high efficiency is kept over broad range of load current. In the current mode control scheme, the transconductance amplifier generates a target current level corresponding to the voltage difference between the feedback point and the internal 750 mV reference. During the OFF state, the PWM comparator monitors the inductor current signal as well as this target current level, and when the inductor current signal comes lower than the target current level, the comparator provides SET signal to initiate the next ON state. The voltage feedback gain is adjustable outside the controller device to support various types of output MOSFETs and capacitors. In the D-CAPTM mode, the transconductance amplifier is disabled and the PWM comparator compares the feedback point voltage and the internal 750 mV reference during the OFF state. When the feedback point comes lower than the reference voltage, the comparator provides SET signal to initiate the next ON state.
8
TPS51116
www.ti.com
SLUS609A - MAY 2004 - REVISED JUNE 2004
DETAILED DESCRIPTION (continued) VDDQ SMPS, Light Load Condition
TPS51116 automatically reduces switching frequency at light load condition to maintain high efficiency. This reduction of frequency is achieved smoothly and without increase of VOUTripple or load regulation. Detail operation is described as follows. As the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to the point that its valley touches zero current, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when this zero inductor current is detected. As the load current further decreased, the converter runs in discontinuous conduction mode and it takes longer and longer to discharge the output capacitor to the level that requires next ON cycle. The ON-time is kept the same as that in the heavy load condition. In reverse, when the output current increase from light load to heavy load, switching frequency increases to the constant 400 kHz as the inductor current reaches to the continuous conduction. The transition load point to the light load operation IOUT(LL) (i.e. the threshold between continuous and discontinuous conduction mode) can be calculated in Equation 1: (V IN * V OUT) V OUT 1 I OUT(LL) + 2Lf V IN (1) where * f is the PWM switching frequency (400 kHz) Switching frequency versus output current in the light load condition is a function of L, f, VIN and VOUT, but it decreases almost proportional to the output current from the IOUT(LL) given above. For example, it is 40 kHz at IOUT(LL)/10 and 4 kHz at IOUT(LL)/100.
Low-Side Driver
The low-side driver is designed to drive high-current, low-RDS(on), N-channel MOSFET(s). The drive capability is represented by its internal resistance, which are 3 for V5IN to DRVL and 0.9 for DRVL to PGND. A dead-time to prevent shoot through is internally generated between top MOSFET off to bottom MOSFET on, and bottom MOSFET off to top MOSFET on. 5-V bias voltage is delivered from V5IN supply. The instantaneous drive current is supplied by an input capacitor connected between V5IN and GND. The average drive current is equal to the gate charge at VGS = 5 V times switching frequency. This gate drive current as well as the high-side gate drive current times 5 V makes the driving power which needs to be dissipated from TPS51116 package.
High-Side Driver
The high-side driver is designed to drive high-current, low-RDS(on) N-channel MOSFET(s). When configured as a floating driver, 5-V bias voltage is delivered from V5IN supply. The average drive current is also calculated by the gate charge at VGS = 5V times switching frequency. The instantaneous drive current is supplied by the flying capacitor between VBST and LL pins. The drive capability is represented by its internal resistance, which are 3 for VBST to DRVH and 0.9 for DRVH to LL.
Current Sensing Scheme
In order to provide both good accuracy and cost effective solution, TPS51116 supports both of external resistor sensing and MOSFET RDS(on) sensing. For resistor sensing scheme, an appropriate current sensing resistor should be connected between the source terminal of the bottom MOSFET and PGND. CS pin is connected to the MOSFET source terminal node. The inductor current is monitored by the voltage between PGND pin and CS pin. For RDS(on) sensing scheme, CS pin should be connected to V5IN through the trip voltage setting resistor, RTRIP. In this scheme, CS terminal sinks 10-A ITRIP current and the trip level is set to the voltage across the RTRIP. The inductor current is monitored by the voltage between PGND pin and LL pin so that LL pin should be connected to the drain terminal of the bottom MOSFET. ITRIP has 4500ppm/C temperature slope to compensate the temperature dependency of the RDS(on). In either scheme, PGND is used as the positive current sensing node so that PGND should be connected to the proper current sensing device, i.e. the sense resistor or the source terminal of the bottom MOSFET.
9
TPS51116
SLUS609A - MAY 2004 - REVISED JUNE 2004
www.ti.com
DETAILED DESCRIPTION (continued) PWM Frequency and Adaptive On-Time Control
TPS51116 employs adaptive on-time control scheme and does not have a dedicated oscillator on board. However, the device runs with fixed 400-kHz pseudo-constant frequency by feed-forwarding the input and output voltage into the on-time one-shot timer. The on-time is controlled inverse proportional to the input voltage and proportional to the output voltage so that the duty ratio is kept as VOUT/VIN technically with the same cycle time. Although the TPS51116 does not have a pin connected to VIN, the input voltage is monitored at LL pin during the ON state. This helps pin count reduction to make the part compact without sacrificing its performance. In order to secure minimum ON-time during startup, feed-forward from the output voltage is enabled after the output becomes 750 mV or larger.
VDDQ Output Voltage Selection
TPS51116 can be used for both of DDR (VVDDQ = 2.5 V) and DDR2 (VVDDQ = 1.8 V) power supply and adjustable output voltage (1.5 V < VVDDQ < 3 V) by connecting VDDQSET pin as shown in Table 1. Table 1. VDDQSET and Output Voltages
VDDQSET GND V5IN FB Resistors VDDQ (V) 2.5 1.8 Adjustable VTTREF and VTT VVDDQSNS/2 VVDDQSNS/2 VVDDQSNS/2 NOTE DDR DDR2 1.5 V < VVDDQ < 3 V
VTT Linear Regulator and VTTREF
TPS51116 integrates high performance low-dropout linear regulator that is capable of sourcing and sinking current up to 3 A. This VTT linear regulator employs ultimate fast response feedback loop so that small ceramic capacitors are enough to keep tracking the VTTREF within 40 mV at all conditions including fast load transient. To achieve tight regulation with minimum effect of wiring resistance, a remote sensing terminal, VTTSNS, should be connected to the positive node of VTT output capacitor(s) as a separate trace from VTT pin. For stable operation, total capacitance of the VTT output terminal can be equal to or greater than 20 F. It is recommended to attach two 10-F ceramic capacitors in parallel to minimize the effect of ESR and ESL. If ESR of the output capacitor is greater than 2 m, insert an RC filter between the output and the VTTSNS input to achieve loop stability. The RC filter time constant should be almost the same or slightly lower than the time constant made by the output capacitor and its ESR. VTTREF block consists of on-chip 1/2 divider, LPF and buffer. This regulator also has sink and source capability up to 10 mA. Bypass VTTREF to GND by a 0.033-F ceramic capacitor for stable operation.
Outputs Management by S3, S5 Control
In the DDR/DDR2 memory applications, it is important to keep VDDQ always higher than VTT/VTTREF including both start-up and shutdown. TPS51116 provides this management by simply connecting both S3 and S5 terminals to the sleep-mode signals such as SLP_S3 and SLP_S5 in the notebook PC system. All of VDDQ, VTTREF and VTT are turned on at S0 state (S3 = S5 = high). In S3 state (S3 = low, S5 = high), VDDQ and VTTREF voltages are kept on while VTT is turned off and left at high impedance (high-Z) state. The VTT output is floated and does not sink or source current in this state. In S4/S5 states (S3 = S5 = low), all of the three outputs are disabled. Outputs are discharged to ground according to the discharge mode selected by MODE pin (see VDDQ and VTT Discharge Control section). Each state code represents as follow; S0 = full ON, S3 = suspend to RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF. (See Table 2) Table 2. S3 and S5 Control
STATE S0 S3 S4/S5 S3 HI LO LO S5 HI HI LO VDDQ On On Off (Discharge) VTTREF On On Off (Discharge) VTT On Off (Hi-Z) Off (Discharge)
10
TPS51116
www.ti.com
SLUS609A - MAY 2004 - REVISED JUNE 2004
DETAILED DESCRIPTION (continued) Soft-Start and Powergood
The soft start function of the SMPS is achieved by ramping up reference voltage and two-stage current clamp. At the starting point, the reference voltage is set to 650 mV (87% of its target value) and the overcurrent threshold is set half of the nominal value. When UVP comparator detects VDDQ become greater than 80% of the target, the reference voltage is raised toward 750 mV using internal 4-bit DAC. This takes approximately 85 s. The overcurrent threshold is released to nominal value at the end of this period. The powergood signal waits another 45 s after the reference voltage reaches 750 mV and the VDDQ voltage becomes good (above 95% of the target voltage), then turns off powergood open-drain MOSFET. The soft-start function of the VTT LDO is achieved by current clamp. The current limit threshold is also changed in two stages using an internal powergood signal dedicated for LDO. During VTT is below the powergood threshold, the current limit level is cut into 60% (2.2 A).This allows the output capacitors to be charged with low and constant current that gives linear ramp up of the output. When the output comes up to the good state, the overcurrent limit level is released to normal value (3.8 A). TPS51116 has an independent counter for each output, but the PGOOD signal indicates only the status of VDDQ and does not indicate VTT powergood externally. See Figure 1.
100% 87% 80%
VVDDQ
VOCL
VPGOOD
VS5 85 s 45 s
UDG-04066
Figure 1. VDDQ Soft-Start and Powergood Timing Soft-start duration, TVDDQSS, TVTTSS are functions of output capacitances. 2 C VDDQ V VDDQ 0.8 T VDDQSS + ) 85 ms I VDDQOCP where IVDDQOCP is the current limit value for VDDQ switcher calculated by Equation 5. C VVTT T VTTSS + VTT I VTTOCL
(2)
(3)
where, IVTTOCL = 2.2 A (typ). In each of the two previous calculations, no load current during start-up are assumed. Note that both switchers and the LDO do not start up with full load condition.
VDDQ and VTT Discharge Control
TPS51116 discharges VDDQ, VTTREF and VTT outputs during S3 and S5 are both low. There are two different discharge modes. The discharge mode can be set by connecting MODE pin as shown in Table 3.
11
TPS51116
SLUS609A - MAY 2004 - REVISED JUNE 2004
www.ti.com
DETAILED DESCRIPTION (continued)
Table 3. Discharge Selection
MODE V5IN VDDQ S4/GND DISCHARGE MODE No discharge Tracking discharge Non-tracking discharge
When in tracking-discharge mode, TPS51116 discharges outputs through the internal VTT regulator transistors and VTT output tracks half of VDDQ voltage during this discharge. Note that VDDQ discharge current flows via VLDOIN to LDOGND thus VLDOIN must be connected to VDDQ output in this mode. The internal LDO can handle up to 3 A and discharge quickly. After VDDQ is discharged down to 0.2 V, the internal LDO is turned off and the operation mode is changed to the non-tracking-discharge mode. When in non-tracking-discharge mode, TPS51116 discharges outputs using internal MOSFETs which are connected to VDDQSNS and VTT. The current capability of these MOSFETs are limited to discharge slowly. Note that VDDQ discharge current flows from VDDQSNS to PGND in this mode. In case of non-tracking mode, TPS51116 does not discharge output charge at all.
Current Protection for VDDQ
The SMPS has cycle-by-cycle over current limiting control. The inductor current is monitored during the OFF state and the controller keeps the OFF state during the inductor current is larger than the over current trip level. The trip level and current sense scheme are determined by CS pin connection (see Current Sensing Scheme section). For resistor sensing scheme, the trip level, VTRIP, is fixed value of 60 mV. For RDS(on) sensing scheme, CS terminal sinks 10 A and the trip level is set to the voltage across this RTRIP resistor. V TRIP (mV) + RTRIP (kW) 10 (mA) (4) As the comparison is done during the OFF state, VTRIP sets valley level of the inductor current. Thus, the load current at over current threshold, IOCP, can be calculated as shown in Equation 5. V OUT V IN * V OUT V I V 1 I OCP + TRIP ) RIPPLE + TRIP ) 2 RDS(on) R DS(on) 2 L f V IN
(5)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor thus the output voltage tends to fall down. If the output voltage becomes less than Powergood level, the VTRIP is cut into half and the output voltage tends to be even lower. Eventually, it crosses the undervoltage protection threshold and shutdown.
Current Protection for VTT
The LDO has an internally fixed constant over current limiting of 3.8 A while operating at normal condition. This trip point is reduced to 2.2 A before the output voltage comes within 5% of the target voltage or goes outside of 10% of the target voltage.
Overvoltage and Undervoltage Protection for VDDQ
TPS51116 monitors a resistor divided feedback voltage to detect overvoltage and undervoltage. If VDDQSET is connected to V5IN or GND, the feedback voltage is made by an internal resistor divider inside VDDQSNS pin. If an external resistor divider is connected to VDDQSET pin, the feedback voltage is VDDQSET voltage itself. When the feedback voltage becomes higher than 115% of the target voltage, the OVP comparator output goes high and the circuit latches as the top MOSFET driver OFF and the bottom MOSFET driver ON. Also, TPS51116 monitors VDDQSNS voltage directly and if it becomes greater than 4 V TPS51116 turns off the top MOSFET driver. When the feedback voltage becomes lower than 70% of the target voltage, the UVP comparator output goes high and an internal UVP delay counter begins counting. After 32 cycles, TPS51116 latches OFF both top and bottom MOSFETs. This function is enabled after 1007 cycles of SMPS operation to ensure startup.
12
TPS51116
www.ti.com
SLUS609A - MAY 2004 - REVISED JUNE 2004
DETAILED DESCRIPTION (continued) V5IN Undervoltage Lockout (UVLO) Protection
TPS51116 has V5IN undervoltage lock out protection (UVLO). When the V5IN voltage is lower than UVLO threshold voltage, SMPS, VTTLDO and VTTREF are shut off. This is a non-latch protection.
V5IN Input Capacitor
Add a ceramic capacitor with a value between 1.0 F and 4.7 F placed close to the V5IN pin to stabilize 5 V from any parasitic impedance from the supply.
Thermal Shutdown
TPS51116 monitors the temperature of itself. If the temperature exceeds the threshold value, 160C (typ), SMPS, VTTLDO and VTTREF are shut off. This is a non-latch protection and the operation is resumed when the device is cooled down by about 10C.
13
TPS51116
SLUS609A - MAY 2004 - REVISED JUNE 2004
www.ti.com
APPLICATION INFORMATION Loop Compensation and External Parts Selection
Current Mode Operation A buck converter using TPS51116 current mode operation can be partitioned into three portions, a voltage divider, an error amplifier and a switching modulator. By linearizing the switching modulator, we can derive the transfer function of the whole system. Since current mode scheme directly controls the inductor current, the modulator can be linearized as shown in Figure 2.
Figure 2. Linearizing the Modulator Here, the inductor is located inside the local feedback loop and its inductance does not appear in the small signal model. As a result, a modulated current source including the power inductor can be modeled as a current source with its transconductance of 1/RS and the output capacitor represent the modulator portion. This simplified model is applicable in the frequency space up to approximately a half of the switching frequency. One note is, although the inductance has no influence to small signal model, it has influence to the large signal model as it limits slew rate of the current source. This means the buck converter's load transient response, one of the large signal behaviors, can be improved by using smaller inductance without affecting the loop stability. Total open loop transfer function of the whole system is given by Equation 6. H(s) + H 1(s) H 2(s) H 3(s)
(6)
Assuming RL>>ESR, RO>>RC and CC>>CC2, each transfer function of the three blocks is shown starting with Equation 7. R2 H 1(s) + (R2 ) R1) (7)
H 2(s) + * g M H 3(s) + (1 ) s 1)s RO 1 ) s 1)s CO CO CC ESR) RL CC RC CC2 RC
(8)
RO 1 ) s RL RS
(9)
There are three poles and two zeros in H(s). Each pole and zero is given by the following five equations.
14
TPS51116
www.ti.com
SLUS609A - MAY 2004 - REVISED JUNE 2004
APPLICATION INFORMATION (continued)
w P1 + w P2 + w P3 + w Z1 + w Z2 + 1 CC 1 CO 1 CC2 1 CC 1 CO ESR
(14)
RO RL RC RC
(10)
(11)
(12)
(13)
Usually, each frequency of those poles and zeros is lower than the 0 dB frequency, f0. However, the f0 should be kept under 1/3 of the switching frequency to avoid effect of switching circuit delay. The f0 is given by Equation 15. RC gM RC gM 0.75 R1 f0 + 1 +1 2p R1 ) R2 C O R S 2p V OUT C O RS (15) Based on small signal analysis above, the external components can be selected by following manner. 1. Choose the inductor. The inductance value should be determined to give the ripple current of approximately 1/4 to 1/3 of maximum output current.
L+ 1 I IND(ripple) f VIN(max) * VOUT VIN(max) VOUT + 3 I OUT(max) f V IN(max) * V OUT V IN(max) V OUT
(16)
The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak inductor current before saturation. The peak inductor current can be estimated as shown in Equation 17.
I IND(peak) + V TRIP )1 RDS(on) L f VIN(max) * VOUT VIN(max) V OUT
(17)
2. Choose rectifying (bottom) MOSFET. When RDS(on) sensing scheme is selected, the rectifying MOSFET's on-resistance is used as this RS so that lower RDS(on) does not always promise better performance. In order to clearly detect inductor current, minimum RS recommended is to give 15 mV or larger ripple voltage with the inductor ripple current. This promises smooth transition from CCM to DCM or vice versa. Upper side of the RDS(on) is of course restricted by the efficiency requirement, and usually this resistance affects efficiency more at high-load conditions. When using external resistor current sensing, there is no restriction for low RDS(on). However, the current sensing resistance RS itself affects the efficiency 3. Choose output capacitor(s). In cases of organic semiconductor capacitors (OS-CON) or specialty polymer capacitors (SP-CAP), ESR to achieve required ripple value at stable state or transient load conditions determines the amount of capacitor(s) need, and capacitance is then enough to satisfy stable operation. The peak-to-peak ripple value can be estimated by ESR times the inductor ripple current for stable state, or ESR times the load current step for a fast transient load response. In case of ceramic capacitor(s), usually ESR is small enough to meet ripple requirement. On the other hand, transient undershoot and overshoot driven by output capacitance becomes the key factor to determine the capacitor(s). 4. Determine f0 and calculate RC using Equation 18. Note that higher RC shows faster transient response in cost of unstableness. If the transient response is not enough even with high RC value, try increasing the out put capacitance. Recommended f0 is fOSC/4. Then RC can be derived by Equation 19.
15
TPS51116
SLUS609A - MAY 2004 - REVISED JUNE 2004
www.ti.com
APPLICATION INFORMATION (continued)
R C v 2p R C + 2.8 f0 V OUT 0.75 CO gM RS R S [mW]
(18) (19)
V OUT
C O [mF]
5. Calculate CC2. Purpose of this capacitance is to cancel zero caused by ESR of the output capacitor. In case of ceramic capacitor(s) is used, no need for CC2. 1 1 w z2 + + wp3 + CO ESR C C2 RC
C C2 + CO ESR RC
(20)
(21)
6. Calculate CC. The purpose of CC is to cut DC component to obtain high DC feedback gain. However, as it causes phase delay, another zero to cancel this effect at f0 frequency is need. This zero, z1, is determined by Cc and Rc. Recommended z1 is 10 times lower to the f0 frequency. f 1 f z1 + +0 10 2p C C R C (22) 7. When using adjustable mode, determine the value of R1 and R2. Recommended R2 value is from 100 k to 300 k. Determine R1 using Equation 23. V * 0.75 R1 + OUT R2 0.75 (23)
D-CAPTM Mode Operation
A buck converter system using D-CAPTM Mode can be simplified as below.
Figure 3. Linearizing the Modulator The VDDQSNS voltage is compare with internal reference voltage after divider resistors. The PWM comparator determines the timing to turn on top MOSFET. The gain and speed of the comparator is high enough to keep the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The DC output voltage may have line regulation due to ripple amplitude that slightly increases as the input voltage increase. For the loop stability, the 0-dB frequency, f0, defined below need to be lower than 1/3 of the switching frequency.
16
TPS51116
www.ti.com
SLUS609A - MAY 2004 - REVISED JUNE 2004
APPLICATION INFORMATION (continued)
f0 + 2p 1 ESR CO v f SW 3
(24)
As f0 is determined solely by the output capacitor's characteristics, loop stability of D-CAPTM mode is determined by the capacitor's chemistry. For example, specialty polymer capacitors (SP-CAP) have CO in the order of several 100 F and ESR in range of 10 m. These makes f0 in the order of 100 kHz or less and the loop is then stable. However, ceramic capacitors have f0 at more than 700 kHz, which is not suitable for this operational mode. Although D-CAPTM mode provides many advantages such as ease-of-use, minimum external components configuration and extremely short response time, due to not employing an error amplifier in the loop, sufficient amount of feedback signal needs to be provided by external circuit to reduce jitter level. The required signal level is approximately 15 mV at comparing point. This gives VRIPPLE = (VOUT/0.75) x 15 (mV) at the output node. The output capacitor's ESR should meet this requirement. The external components selection is much simple in D-CAPTM mode. 1. Choose inductor. This section is the same as the current mode. Please refer to the instructions in the Current Mode Operation section. 2. Choose output capacitor(s).Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. Determine ESR to meet required ripple voltage above. A quick approximation is shown in Equation 25. V 0.015 ESR + OUT [ VOUT 60 [mW] I RIPPLE 0.75 I OUT(max)
(25)
Thermal Design
Primary power dissipation of TPS51116 is generated from VTT regulator. VTT current flow in both source and sink directions generate power dissipation from the part. In the source phase, potential difference between VLDOIN and VTT times VTT current becomes the power dissipation, WDSRC. W DSRC + VVLDOIN * VVTT I VTT
(26)
In this case, if VLDOIN is connected to an alternative power supply lower than VDDQ voltage, power loss can be decreased. For the sink phase, VTT voltage is applied across the internal LDO regulator, and the power dissipation, WDSNK, is calculated by Equation 27: W DSNK + VVTT I VTT (27) Since this device does not sink AND source the current at the same time and IVTT varies rapidly with time, actual power dissipation need to be considered for thermal design is an average of above value. Another power consumption is the current used for internal control circuitry from V5IN supply and VLDOIN supply. V5IN supports both the internal circuit and external MOSFETs drive current. The former current is in the VLDOIN supply can be estimated as 1.5 mA or less at normal operational conditions. These powers need to be effectively dissipated from the package. Maximum power dissipation allowed to the package is calculated by Equation 28, T J(max) * T A(max) W PKG + q JA (28) where * TJ(max) is 125C * TA(max) is the maximum ambient temperature in the system * JA is the thermal resistance from the silicon junction to the ambient
17
TPS51116
SLUS609A - MAY 2004 - REVISED JUNE 2004
www.ti.com
APPLICATION INFORMATION (continued)
This thermal resistance strongly depends on the board layout. TPS51116 is assembled in a thermally enhanced PowerPADTM package that has exposed die pad underneath the body. For improved thermal performance, this die pad needs to be attached to ground trace via thermal land on the PCB. This ground trace acts as a heat sink/spread. The typical thermal resistance, 39.6C/W, is achieved based on a 6.5 mm x 3.4 mm thermal land with eight vias without air flow. It can be improved by using larger thermal land and/or increasing vias number. Further information about PowerPADTM and its recommended board layout is described in (SLMA002). This document is available at .
Layout Considerations
Certain points must be considered before designing a layout using the TPS51116. * PCB trace defined as LL node, which connects to source of switching MOSFET, drain of rectifying MOSFET and high-voltage side of the inductor, should be as short and wide as possible. * Consider adding a small snubber circuit, consists of 3 and 1 nF, between LL and PGND in case a high-frequency surge is observed on the LL voltage waveform. * All sensitive analog traces such as VDDQSNS, VTTSNS and CS should placed away from high-voltage switching nodes such as LL, DRVL or DRVH nodes to avoid coupling. * VLDOIN should be connected to VDDQ output with short and wide trace. If different power source is used for VLDOIN, an input bypass capacitor should be placed to the pin as close as possible with short and wide connection. * The output capacitor for VTT should be placed close to the pin with short and wide connection in order to avoid additional ESR and/or ESL of the trace. * VTTSNS should be connected to the positive node of VTT output capacitor(s) as a separate trace from the high current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed to sense the voltage of the point of the load, it is recommended to attach the output capacitor(s) at that point. Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin and the output capacitor(s). * Consider adding LPF at VTTSNS in case ESR of the VTT output capacitor(s) is larger than 2 m. * VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the reference voltage of VTTREF. Avoid any noise generative lines. * Negative node of VTT output capacitor(s) and VTTREF capacitor should be tied together by avoiding common impedance to the high current path of the VTT source/sink current. * GND (Signal GND) pin node represents the reference potential for VTTREF and VTT outputs. Connect GND to negative nodes of VTT capacitor(s), VTTREF capacitor and VDDQ capacitor(s) with care to avoid additional ESR and/or ESL. GND and PGND (power ground) should be connected together at a single point. * In order to effectively remove heat from the package, prepare thermal land and solder to the package's thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps heat spreading. Numerous vias with a 0.33-mm diameter connected from the thermal land to the internal/solder-side ground plane(s) should be used to help dissipation. Do NOT connect PGND to this thermal land underneath the package.
18
TPS51116
www.ti.com
SLUS609A - MAY 2004 - REVISED JUNE 2004
APPLICATION INFORMATION (continued)
Figure 4. D-CAPTM Mode Table 4. D-CAPTM Mode Schematic Components
SYMBOL R1 R2 R3 R4 M1 M2 SPECIFICATION 5.1 k 100 k (100 xVVDDQ - 75) k 75 k 30 V, 13 m 30 V, 5 m MANUFACTURER International Rectifier International Rectifier IRF7821 IRF7832 PART NUMBER
19
TPS51116
SLUS609A - MAY 2004 - REVISED JUNE 2004
www.ti.com
Figure 5. Current Mode Table 5. Current Mode
SYMBOL R0 R2 M0 M1 SPECIFICATION 6 m, 1% 100 k 30 V, 13 m 30 V, 5 m MANUFACTURER Vishay International Rectifier International Rectifier PART NUMBER WSL-2521 0.006 IRF7821 IRF7832
20
TPS51116
www.ti.com
SLUS609A - MAY 2004 - REVISED JUNE 2004
TYPICAL CHARACTERISTICS
V5IN SUPPLY CURRENT vs JUNCTION TEMPERATURE
2.0 1.8 IV5IN1 - V5IN Shutdown Current - mA IV5IN1 - V5IN Supply Current - mA 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50
V5IN SHUTDOWN CURRENT vs JUNCTION TEMPERATURE
0
50
100
150
0
50
100
150
TJ - Junction Temperature - C
TJ - Junction Temperature - C
Figure 6. V5IN SUPPLY CURRENT vs LOAD CURRENT
10 9 IV5IN - V5IN Supply Current - mA 8 7 6 5 4 3 2 1 0 -2 -1 0 IVTT - VTT Current - A 1 2 DDR2 VVTT = 0.9 V IVLDOIN - VLDOIN Supply Current - A 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50
Figure 7. VLDOIN SUPPLY CURRENT vs TEMPERATURE
0
50
100
150
TJ - Junction Temperature - C
Figure 8.
Figure 9.
21
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers Data Converters DSP Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless

▲Up To Search▲

Price & Availability of TPS51116

	To Download TPS51116 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .